Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Maxim/TARGET_MAX32610/rtc_regs.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #ifndef _MXC_RTC_REGS_H
<> 144:ef7eb2e8f9f7 35 #define _MXC_RTC_REGS_H
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 38 extern "C" {
<> 144:ef7eb2e8f9f7 39 #endif
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #include <stdint.h>
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /**
<> 144:ef7eb2e8f9f7 44 * @file rtc_regs.h
<> 144:ef7eb2e8f9f7 45 * @addtogroup rtc RTCTMR
<> 144:ef7eb2e8f9f7 46 * @{
<> 144:ef7eb2e8f9f7 47 */
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /**
<> 144:ef7eb2e8f9f7 50 * @brief Defines clock divider for 4096Hz input clock.
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52 typedef enum {
<> 144:ef7eb2e8f9f7 53 /** (4kHz) divide input clock by 2^0 = 1 */
<> 144:ef7eb2e8f9f7 54 MXC_E_RTC_PRESCALE_DIV_2_0 = 0,
<> 144:ef7eb2e8f9f7 55 /** (2kHz) divide input clock by 2^1 = 2 */
<> 144:ef7eb2e8f9f7 56 MXC_E_RTC_PRESCALE_DIV_2_1,
<> 144:ef7eb2e8f9f7 57 /** (1kHz) divide input clock by 2^2 = 4 */
<> 144:ef7eb2e8f9f7 58 MXC_E_RTC_PRESCALE_DIV_2_2,
<> 144:ef7eb2e8f9f7 59 /** (512Hz) divide input clock by 2^3 = 8 */
<> 144:ef7eb2e8f9f7 60 MXC_E_RTC_PRESCALE_DIV_2_3,
<> 144:ef7eb2e8f9f7 61 /** (256Hz) divide input clock by 2^4 = 16 */
<> 144:ef7eb2e8f9f7 62 MXC_E_RTC_PRESCALE_DIV_2_4,
<> 144:ef7eb2e8f9f7 63 /** (128Hz) divide input clock by 2^5 = 32 */
<> 144:ef7eb2e8f9f7 64 MXC_E_RTC_PRESCALE_DIV_2_5,
<> 144:ef7eb2e8f9f7 65 /** (64Hz) divide input clock by 2^6 = 64 */
<> 144:ef7eb2e8f9f7 66 MXC_E_RTC_PRESCALE_DIV_2_6,
<> 144:ef7eb2e8f9f7 67 /** (32Hz) divide input clock by 2^7 = 128 */
<> 144:ef7eb2e8f9f7 68 MXC_E_RTC_PRESCALE_DIV_2_7,
<> 144:ef7eb2e8f9f7 69 /** (16Hz) divide input clock by 2^8 = 256 */
<> 144:ef7eb2e8f9f7 70 MXC_E_RTC_PRESCALE_DIV_2_8,
<> 144:ef7eb2e8f9f7 71 /** (8Hz) divide input clock by 2^9 = 512 */
<> 144:ef7eb2e8f9f7 72 MXC_E_RTC_PRESCALE_DIV_2_9,
<> 144:ef7eb2e8f9f7 73 /** (4Hz) divide input clock by 2^10 = 1024 */
<> 144:ef7eb2e8f9f7 74 MXC_E_RTC_PRESCALE_DIV_2_10,
<> 144:ef7eb2e8f9f7 75 /** (2Hz) divide input clock by 2^11 = 2048 */
<> 144:ef7eb2e8f9f7 76 MXC_E_RTC_PRESCALE_DIV_2_11,
<> 144:ef7eb2e8f9f7 77 /** (1Hz) divide input clock by 2^12 = 4096 */
<> 144:ef7eb2e8f9f7 78 MXC_E_RTC_PRESCALE_DIV_2_12,
<> 144:ef7eb2e8f9f7 79 } mxc_rtc_prescale_t;
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 /* Offset Register Description
<> 144:ef7eb2e8f9f7 82 ====== ========================================= */
<> 144:ef7eb2e8f9f7 83 typedef struct {
<> 144:ef7eb2e8f9f7 84 __IO uint32_t ctrl; /* 0x0000 RTC Timer Control */
<> 144:ef7eb2e8f9f7 85 __IO uint32_t timer; /* 0x0004 RTC Timer Count Value */
<> 144:ef7eb2e8f9f7 86 __IO uint32_t comp[2]; /* 0x0008 RTC Alarm (0..1) Compare Registers */
<> 144:ef7eb2e8f9f7 87 __IO uint32_t flags; /* 0x0010 CPU Interrupt and RTC Domain Flags */
<> 144:ef7eb2e8f9f7 88 __I uint32_t rsv0014; /* 0x0014 */
<> 144:ef7eb2e8f9f7 89 __IO uint32_t inten; /* 0x0018 Interrupt Enable Controls */
<> 144:ef7eb2e8f9f7 90 __IO uint32_t prescale; /* 0x001C RTC Timer Prescale Setting */
<> 144:ef7eb2e8f9f7 91 __I uint32_t rsv0020; /* 0x0020 */
<> 144:ef7eb2e8f9f7 92 __IO uint32_t prescale_mask; /* 0x0024 RTC Timer Prescale Compare Mask */
<> 144:ef7eb2e8f9f7 93 __IO uint32_t trim_ctrl; /* 0x0028 RTC Timer Trim Controls */
<> 144:ef7eb2e8f9f7 94 __IO uint32_t trim_value; /* 0x002C RTC Timer Trim Adjustment Interval */
<> 144:ef7eb2e8f9f7 95 } mxc_rtctmr_regs_t;
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 /*
<> 144:ef7eb2e8f9f7 98 Register offsets for module RTCTMR.
<> 144:ef7eb2e8f9f7 99 */
<> 144:ef7eb2e8f9f7 100 #define MXC_R_RTCTMR_OFFS_CTRL ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 101 #define MXC_R_RTCTMR_OFFS_TIMER ((uint32_t)0x00000004UL)
<> 144:ef7eb2e8f9f7 102 #define MXC_R_RTCTMR_OFFS_COMP_0 ((uint32_t)0x00000008UL)
<> 144:ef7eb2e8f9f7 103 #define MXC_R_RTCTMR_OFFS_COMP_1 ((uint32_t)0x0000000CUL)
<> 144:ef7eb2e8f9f7 104 #define MXC_R_RTCTMR_OFFS_FLAGS ((uint32_t)0x00000010UL)
<> 144:ef7eb2e8f9f7 105 #define MXC_R_RTCTMR_OFFS_INTEN ((uint32_t)0x00000018UL)
<> 144:ef7eb2e8f9f7 106 #define MXC_R_RTCTMR_OFFS_PRESCALE ((uint32_t)0x0000001CUL)
<> 144:ef7eb2e8f9f7 107 #define MXC_R_RTCTMR_OFFS_PRESCALE_MASK ((uint32_t)0x00000024UL)
<> 144:ef7eb2e8f9f7 108 #define MXC_R_RTCTMR_OFFS_TRIM_CTRL ((uint32_t)0x00000028UL)
<> 144:ef7eb2e8f9f7 109 #define MXC_R_RTCTMR_OFFS_TRIM_VALUE ((uint32_t)0x0000002CUL)
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /*
<> 144:ef7eb2e8f9f7 112 Field positions and masks for module RTCTMR.
<> 144:ef7eb2e8f9f7 113 */
<> 144:ef7eb2e8f9f7 114 #define MXC_F_RTC_CTRL_ENABLE_POS 0
<> 144:ef7eb2e8f9f7 115 #define MXC_F_RTC_CTRL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ENABLE_POS))
<> 144:ef7eb2e8f9f7 116 #define MXC_F_RTC_CTRL_CLEAR_POS 1
<> 144:ef7eb2e8f9f7 117 #define MXC_F_RTC_CTRL_CLEAR ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLEAR_POS))
<> 144:ef7eb2e8f9f7 118 #define MXC_F_RTC_CTRL_PENDING_POS 2
<> 144:ef7eb2e8f9f7 119 #define MXC_F_RTC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PENDING_POS))
<> 144:ef7eb2e8f9f7 120 #define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS 3
<> 144:ef7eb2e8f9f7 121 #define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS))
<> 144:ef7eb2e8f9f7 122 #define MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS 4
<> 144:ef7eb2e8f9f7 123 #define MXC_F_RTC_CTRL_AGGRESSIVE_RST ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS))
<> 144:ef7eb2e8f9f7 124 #define MXC_F_RTC_CTRL_EN_ACTIVE_POS 16
<> 144:ef7eb2e8f9f7 125 #define MXC_F_RTC_CTRL_EN_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_EN_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 126 #define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS 17
<> 144:ef7eb2e8f9f7 127 #define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 128 #define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS 18
<> 144:ef7eb2e8f9f7 129 #define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 130 #define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS 19
<> 144:ef7eb2e8f9f7 131 #define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 132 #define MXC_F_RTC_CTRL_SET_ACTIVE_POS 20
<> 144:ef7eb2e8f9f7 133 #define MXC_F_RTC_CTRL_SET_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_SET_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 134 #define MXC_F_RTC_CTRL_CLR_ACTIVE_POS 21
<> 144:ef7eb2e8f9f7 135 #define MXC_F_RTC_CTRL_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLR_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 136 #define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS 22
<> 144:ef7eb2e8f9f7 137 #define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 138 #define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS 23
<> 144:ef7eb2e8f9f7 139 #define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 140 #define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS 24
<> 144:ef7eb2e8f9f7 141 #define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 142 #define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS 25
<> 144:ef7eb2e8f9f7 143 #define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 144 #define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS 26
<> 144:ef7eb2e8f9f7 145 #define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS))
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 #define MXC_F_RTC_FLAGS_COMP0_POS 0
<> 144:ef7eb2e8f9f7 148 #define MXC_F_RTC_FLAGS_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_POS))
<> 144:ef7eb2e8f9f7 149 #define MXC_F_RTC_FLAGS_COMP1_POS 1
<> 144:ef7eb2e8f9f7 150 #define MXC_F_RTC_FLAGS_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_POS))
<> 144:ef7eb2e8f9f7 151 #define MXC_F_RTC_FLAGS_PRESCALE_COMP_POS 2
<> 144:ef7eb2e8f9f7 152 #define MXC_F_RTC_FLAGS_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCALE_COMP_POS))
<> 144:ef7eb2e8f9f7 153 #define MXC_F_RTC_FLAGS_OVERFLOW_POS 3
<> 144:ef7eb2e8f9f7 154 #define MXC_F_RTC_FLAGS_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_POS))
<> 144:ef7eb2e8f9f7 155 #define MXC_F_RTC_FLAGS_TRIM_POS 4
<> 144:ef7eb2e8f9f7 156 #define MXC_F_RTC_FLAGS_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_POS))
<> 144:ef7eb2e8f9f7 157 #define MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS 8
<> 144:ef7eb2e8f9f7 158 #define MXC_F_RTC_FLAGS_COMP0_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS))
<> 144:ef7eb2e8f9f7 159 #define MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS 9
<> 144:ef7eb2e8f9f7 160 #define MXC_F_RTC_FLAGS_COMP1_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS))
<> 144:ef7eb2e8f9f7 161 #define MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS 10
<> 144:ef7eb2e8f9f7 162 #define MXC_F_RTC_FLAGS_PRESCL_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS))
<> 144:ef7eb2e8f9f7 163 #define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS 11
<> 144:ef7eb2e8f9f7 164 #define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS))
<> 144:ef7eb2e8f9f7 165 #define MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS 12
<> 144:ef7eb2e8f9f7 166 #define MXC_F_RTC_FLAGS_TRIM_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS))
<> 144:ef7eb2e8f9f7 167 #define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS 31
<> 144:ef7eb2e8f9f7 168 #define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS))
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 #define MXC_F_RTC_INTEN_COMP0_POS 0
<> 144:ef7eb2e8f9f7 171 #define MXC_F_RTC_INTEN_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP0_POS))
<> 144:ef7eb2e8f9f7 172 #define MXC_F_RTC_INTEN_COMP1_POS 1
<> 144:ef7eb2e8f9f7 173 #define MXC_F_RTC_INTEN_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP1_POS))
<> 144:ef7eb2e8f9f7 174 #define MXC_F_RTC_INTEN_PRESCALE_COMP_POS 2
<> 144:ef7eb2e8f9f7 175 #define MXC_F_RTC_INTEN_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_PRESCALE_COMP_POS))
<> 144:ef7eb2e8f9f7 176 #define MXC_F_RTC_INTEN_OVERFLOW_POS 3
<> 144:ef7eb2e8f9f7 177 #define MXC_F_RTC_INTEN_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_OVERFLOW_POS))
<> 144:ef7eb2e8f9f7 178 #define MXC_F_RTC_INTEN_TRIM_POS 4
<> 144:ef7eb2e8f9f7 179 #define MXC_F_RTC_INTEN_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_TRIM_POS))
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 #define MXC_F_RTC_PRESCALE_WIDTH_SELECTION_POS 0
<> 144:ef7eb2e8f9f7 182 #define MXC_F_RTC_PRESCALE_WIDTH_SELECTION ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_WIDTH_SELECTION_POS))
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 #define MXC_F_RTC_PRESCALE_MASK_COMP_MASK_POS 0
<> 144:ef7eb2e8f9f7 185 #define MXC_F_RTC_PRESCALE_MASK_COMP_MASK ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_MASK_COMP_MASK_POS))
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 #define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS 0
<> 144:ef7eb2e8f9f7 188 #define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS))
<> 144:ef7eb2e8f9f7 189 #define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS 1
<> 144:ef7eb2e8f9f7 190 #define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS))
<> 144:ef7eb2e8f9f7 191 #define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS 2
<> 144:ef7eb2e8f9f7 192 #define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS))
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 #define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS 0
<> 144:ef7eb2e8f9f7 195 #define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE ((uint32_t)(0x0003FFFFUL << MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS))
<> 144:ef7eb2e8f9f7 196 #define MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL_POS 18
<> 144:ef7eb2e8f9f7 197 #define MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL_POS))
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 #define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS 0
<> 144:ef7eb2e8f9f7 200 #define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER ((uint32_t)(0x0000FFFFUL << MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS))
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 #define MXC_F_RTC_CLK_CTRL_OSC1_EN_POS 0
<> 144:ef7eb2e8f9f7 203 #define MXC_F_RTC_CLK_CTRL_OSC1_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC1_EN_POS))
<> 144:ef7eb2e8f9f7 204 #define MXC_F_RTC_CLK_CTRL_OSC2_EN_POS 1
<> 144:ef7eb2e8f9f7 205 #define MXC_F_RTC_CLK_CTRL_OSC2_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC2_EN_POS))
<> 144:ef7eb2e8f9f7 206 #define MXC_F_RTC_CLK_CTRL_NANO_EN_POS 2
<> 144:ef7eb2e8f9f7 207 #define MXC_F_RTC_CLK_CTRL_NANO_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_NANO_EN_POS))
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 #define MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE_POS 0
<> 144:ef7eb2e8f9f7 210 #define MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE_POS))
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 #define MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS 0
<> 144:ef7eb2e8f9f7 213 #define MXC_F_RTC_OSC_CTRL_OSC_BYPASS ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS))
<> 144:ef7eb2e8f9f7 214 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS 1
<> 144:ef7eb2e8f9f7 215 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS))
<> 144:ef7eb2e8f9f7 216 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS 2
<> 144:ef7eb2e8f9f7 217 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS))
<> 144:ef7eb2e8f9f7 218 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS 3
<> 144:ef7eb2e8f9f7 219 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS))
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /* Offset Register Description
<> 144:ef7eb2e8f9f7 222 ====== ===================================================================== */
<> 144:ef7eb2e8f9f7 223 typedef struct {
<> 144:ef7eb2e8f9f7 224 __IO uint32_t nano_counter; /* 0x0000 Nanoring Counter Read Register */
<> 144:ef7eb2e8f9f7 225 __IO uint32_t clk_ctrl; /* 0x0004 RTC Clock Control Settings */
<> 144:ef7eb2e8f9f7 226 __IO uint32_t dsen_ctrl; /* 0x0008 Dynamic Tamper Sensor Control */
<> 144:ef7eb2e8f9f7 227 __IO uint32_t osc_ctrl; /* 0x000C RTC Oscillator Control */
<> 144:ef7eb2e8f9f7 228 } mxc_rtccfg_regs_t;
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 /*
<> 144:ef7eb2e8f9f7 231 Register offsets for module RTCCFG.
<> 144:ef7eb2e8f9f7 232 */
<> 144:ef7eb2e8f9f7 233 #define MXC_R_RTCCFG_OFFS_NANO_COUNTER ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 234 #define MXC_R_RTCCFG_OFFS_CLK_CTRL ((uint32_t)0x00000004UL)
<> 144:ef7eb2e8f9f7 235 #define MXC_R_RTCCFG_OFFS_DSEN_CTRL ((uint32_t)0x00000008UL)
<> 144:ef7eb2e8f9f7 236 #define MXC_R_RTCCFG_OFFS_OSC_CTRL ((uint32_t)0x0000000CUL)
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 239 }
<> 144:ef7eb2e8f9f7 240 #endif
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /**
<> 144:ef7eb2e8f9f7 243 * @}
<> 144:ef7eb2e8f9f7 244 */
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 #endif /* _MXC_RTC_REGS_H */