Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pmu_regs.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #ifndef _MXC_PMU_REGS_H_
<> 144:ef7eb2e8f9f7 35 #define _MXC_PMU_REGS_H_
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 38 extern "C" {
<> 144:ef7eb2e8f9f7 39 #endif
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #include <stdint.h>
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /**
<> 144:ef7eb2e8f9f7 44 * @file pmu_regs.h
<> 144:ef7eb2e8f9f7 45 * @addtogroup pmu PMU
<> 144:ef7eb2e8f9f7 46 * @{
<> 144:ef7eb2e8f9f7 47 */
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /* Offset Register Description
<> 144:ef7eb2e8f9f7 50 ====== ======================================================== */
<> 144:ef7eb2e8f9f7 51 typedef struct {
<> 144:ef7eb2e8f9f7 52 __IO uint32_t dscadr; /* 0x0000 Starting Descriptor Address */
<> 144:ef7eb2e8f9f7 53 __IO uint32_t cfg; /* 0x0004 Channel Configuration */
<> 144:ef7eb2e8f9f7 54 __IO uint32_t loop; /* 0x0008 Channel Loop Counters */
<> 144:ef7eb2e8f9f7 55 __IO uint32_t op; /* 0x000C Current Descriptor DWORD 0 (OP) */
<> 144:ef7eb2e8f9f7 56 __IO uint32_t dsc1; /* 0x0010 Current Descriptor DWORD 1 */
<> 144:ef7eb2e8f9f7 57 __IO uint32_t dsc2; /* 0x0014 Current Descriptor DWORD 2 */
<> 144:ef7eb2e8f9f7 58 __IO uint32_t dsc3; /* 0x0018 Current Descriptor DWORD 3 */
<> 144:ef7eb2e8f9f7 59 __IO uint32_t dsc4; /* 0x001C Current Descriptor DWORD 4 */
<> 144:ef7eb2e8f9f7 60 } mxc_pmu_regs_t;
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /*
<> 144:ef7eb2e8f9f7 63 Register offsets for module PMU.
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65 #define MXC_R_PMU_OFFS_DSCADR ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 66 #define MXC_R_PMU_OFFS_CFG ((uint32_t)0x00000004UL)
<> 144:ef7eb2e8f9f7 67 #define MXC_R_PMU_OFFS_LOOP ((uint32_t)0x00000008UL)
<> 144:ef7eb2e8f9f7 68 #define MXC_R_PMU_OFFS_OP ((uint32_t)0x0000000CUL)
<> 144:ef7eb2e8f9f7 69 #define MXC_R_PMU_OFFS_DSC1 ((uint32_t)0x00000010UL)
<> 144:ef7eb2e8f9f7 70 #define MXC_R_PMU_OFFS_DSC2 ((uint32_t)0x00000014UL)
<> 144:ef7eb2e8f9f7 71 #define MXC_R_PMU_OFFS_DSC3 ((uint32_t)0x00000018UL)
<> 144:ef7eb2e8f9f7 72 #define MXC_R_PMU_OFFS_DSC4 ((uint32_t)0x0000001CUL)
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /*
<> 144:ef7eb2e8f9f7 75 Field positions and masks for module PMU.
<> 144:ef7eb2e8f9f7 76 */
<> 144:ef7eb2e8f9f7 77 #define MXC_F_PMU_CFG_ENABLE_POS 0
<> 144:ef7eb2e8f9f7 78 #define MXC_F_PMU_CFG_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_ENABLE_POS))
<> 144:ef7eb2e8f9f7 79 #define MXC_F_PMU_CFG_LL_STOPPED_POS 2
<> 144:ef7eb2e8f9f7 80 #define MXC_F_PMU_CFG_LL_STOPPED ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_LL_STOPPED_POS))
<> 144:ef7eb2e8f9f7 81 #define MXC_F_PMU_CFG_MANUAL_POS 3
<> 144:ef7eb2e8f9f7 82 #define MXC_F_PMU_CFG_MANUAL ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_MANUAL_POS))
<> 144:ef7eb2e8f9f7 83 #define MXC_F_PMU_CFG_BUS_ERROR_POS 4
<> 144:ef7eb2e8f9f7 84 #define MXC_F_PMU_CFG_BUS_ERROR ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_BUS_ERROR_POS))
<> 144:ef7eb2e8f9f7 85 #define MXC_F_PMU_CFG_TO_STAT_POS 6
<> 144:ef7eb2e8f9f7 86 #define MXC_F_PMU_CFG_TO_STAT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_TO_STAT_POS))
<> 144:ef7eb2e8f9f7 87 #define MXC_F_PMU_CFG_TO_SEL_POS 11
<> 144:ef7eb2e8f9f7 88 #define MXC_F_PMU_CFG_TO_SEL ((uint32_t)(0x00000007UL << MXC_F_PMU_CFG_TO_SEL_POS))
<> 144:ef7eb2e8f9f7 89 #define MXC_F_PMU_CFG_PS_SEL_POS 14
<> 144:ef7eb2e8f9f7 90 #define MXC_F_PMU_CFG_PS_SEL ((uint32_t)(0x00000003UL << MXC_F_PMU_CFG_PS_SEL_POS))
<> 144:ef7eb2e8f9f7 91 #define MXC_F_PMU_CFG_INTERRUPT_POS 16
<> 144:ef7eb2e8f9f7 92 #define MXC_F_PMU_CFG_INTERRUPT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INTERRUPT_POS))
<> 144:ef7eb2e8f9f7 93 #define MXC_F_PMU_CFG_INT_EN_POS 17
<> 144:ef7eb2e8f9f7 94 #define MXC_F_PMU_CFG_INT_EN ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INT_EN_POS))
<> 144:ef7eb2e8f9f7 95 #define MXC_F_PMU_CFG_BURST_SIZE_POS 24
<> 144:ef7eb2e8f9f7 96 #define MXC_F_PMU_CFG_BURST_SIZE ((uint32_t)(0x0000001FUL << MXC_F_PMU_CFG_BURST_SIZE_POS))
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 #define MXC_F_PMU_LOOP_COUNTER_0_POS 0
<> 144:ef7eb2e8f9f7 99 #define MXC_F_PMU_LOOP_COUNTER_0 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_0_POS))
<> 144:ef7eb2e8f9f7 100 #define MXC_F_PMU_LOOP_COUNTER_1_POS 16
<> 144:ef7eb2e8f9f7 101 #define MXC_F_PMU_LOOP_COUNTER_1 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_1_POS))
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 104 }
<> 144:ef7eb2e8f9f7 105 #endif
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 /**
<> 144:ef7eb2e8f9f7 108 * @}
<> 144:ef7eb2e8f9f7 109 */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 #endif /* _MXC_PMU_REGS_H_ */