Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Maxim/TARGET_MAX32610/max32610.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #ifndef _MAX32610_H_
<> 144:ef7eb2e8f9f7 35 #define _MAX32610_H_
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #include <stdint.h>
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 typedef enum IRQn_Type {
<> 144:ef7eb2e8f9f7 40 NonMaskableInt_IRQn = -14,
<> 144:ef7eb2e8f9f7 41 HardFault_IRQn = -13,
<> 144:ef7eb2e8f9f7 42 MemoryManagement_IRQn = -12,
<> 144:ef7eb2e8f9f7 43 BusFault_IRQn = -11,
<> 144:ef7eb2e8f9f7 44 UsageFault_IRQn = -10,
<> 144:ef7eb2e8f9f7 45 SVCall_IRQn = -5,
<> 144:ef7eb2e8f9f7 46 DebugMonitor_IRQn = -4,
<> 144:ef7eb2e8f9f7 47 PendSV_IRQn = -2,
<> 144:ef7eb2e8f9f7 48 SysTick_IRQn = -1,
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /* Externals interrupts */
<> 144:ef7eb2e8f9f7 51 UART0_IRQn = 0, /* 16:01 UART0 */
<> 144:ef7eb2e8f9f7 52 UART1_IRQn, /* 17: 2 UART1 */
<> 144:ef7eb2e8f9f7 53 I2CM0_IRQn, /* 18: 3 I2C Master 0 */
<> 144:ef7eb2e8f9f7 54 I2CS_IRQn, /* 19: 4 I2C Slave */
<> 144:ef7eb2e8f9f7 55 USB_IRQn, /* 20: 5 USB */
<> 144:ef7eb2e8f9f7 56 PMU_IRQn, /* 21: 6 DMA */
<> 144:ef7eb2e8f9f7 57 AFE_IRQn, /* 22: 7 AFE */
<> 144:ef7eb2e8f9f7 58 MAA_IRQn, /* 23: 8 MAA */
<> 144:ef7eb2e8f9f7 59 AES_IRQn, /* 24: 9 AES */
<> 144:ef7eb2e8f9f7 60 SPI0_IRQn, /* 25:10 SPI0 */
<> 144:ef7eb2e8f9f7 61 SPI1_IRQn, /* 26:11 SPI1 */
<> 144:ef7eb2e8f9f7 62 SPI2_IRQn, /* 27:12 SPI2 */
<> 144:ef7eb2e8f9f7 63 TMR0_IRQn, /* 28:13 Timer32-0 */
<> 144:ef7eb2e8f9f7 64 TMR1_IRQn, /* 29:14 Timer32-1 */
<> 144:ef7eb2e8f9f7 65 TMR2_IRQn, /* 30:15 Timer32-1 */
<> 144:ef7eb2e8f9f7 66 TMR3_IRQn, /* 31:16 Timer32-2 */
<> 144:ef7eb2e8f9f7 67 RSVD0_IRQn, /* 32:17 RSVD */
<> 144:ef7eb2e8f9f7 68 RSVD1_IRQn, /* 33:18 RSVD */
<> 144:ef7eb2e8f9f7 69 DAC0_IRQn, /* 34:19 DAC0 (12-bit DAC) */
<> 144:ef7eb2e8f9f7 70 DAC1_IRQn, /* 35:20 DAC1 (12-bit DAC) */
<> 144:ef7eb2e8f9f7 71 DAC2_IRQn, /* 36:21 DAC2 (8-bit DAC) */
<> 144:ef7eb2e8f9f7 72 DAC3_IRQn, /* 37:22 DAC3 (8-bit DAC) */
<> 144:ef7eb2e8f9f7 73 ADC_IRQn, /* 38:23 ADC */
<> 144:ef7eb2e8f9f7 74 FLC_IRQn, /* 39:24 Flash Controller */
<> 144:ef7eb2e8f9f7 75 PWRMAN_IRQn, /* 40:25 PWRMAN */
<> 144:ef7eb2e8f9f7 76 CLKMAN_IRQn, /* 41:26 CLKMAN */
<> 144:ef7eb2e8f9f7 77 RTC0_IRQn, /* 42:27 RTC INT0 */
<> 144:ef7eb2e8f9f7 78 RTC1_IRQn, /* 43:28 RTC INT1 */
<> 144:ef7eb2e8f9f7 79 RTC2_IRQn, /* 44:29 RTC INT2 */
<> 144:ef7eb2e8f9f7 80 RTC3_IRQn, /* 45:30 RTC INT3 */
<> 144:ef7eb2e8f9f7 81 WDT0_IRQn, /* 46:31 WATCHDOG0 */
<> 144:ef7eb2e8f9f7 82 WDT0_P_IRQn, /* 47:32 WATCHDOG0 PRE-WINDOW */
<> 144:ef7eb2e8f9f7 83 WDT1_IRQn, /* 48:33 WATCHDOG1 */
<> 144:ef7eb2e8f9f7 84 WDT1_P_IRQn, /* 49:34 WATCHDOG1 PRE-WINDOW */
<> 144:ef7eb2e8f9f7 85 GPIO_P0_IRQn, /* 50:35 GPIO Port 0 */
<> 144:ef7eb2e8f9f7 86 GPIO_P1_IRQn, /* 51:36 GPIO Port 1 */
<> 144:ef7eb2e8f9f7 87 GPIO_P2_IRQn, /* 52:37 GPIO Port 2 */
<> 144:ef7eb2e8f9f7 88 GPIO_P3_IRQn, /* 53:38 GPIO Port 3 */
<> 144:ef7eb2e8f9f7 89 GPIO_P4_IRQn, /* 54:39 GPIO Port 4 */
<> 144:ef7eb2e8f9f7 90 GPIO_P5_IRQn, /* 55:40 GPIO Port 5 */
<> 144:ef7eb2e8f9f7 91 GPIO_P6_IRQn, /* 56:41 GPIO Port 6 */
<> 144:ef7eb2e8f9f7 92 GPIO_P7_IRQn, /* 57:42 GPIO Port 7 */
<> 144:ef7eb2e8f9f7 93 TMR16_0_IRQn, /* 58:43 Timer16-s0 */
<> 144:ef7eb2e8f9f7 94 TMR16_1_IRQn, /* 59:44 Timer16-s1 */
<> 144:ef7eb2e8f9f7 95 TMR16_2_IRQn, /* 60:45 Timer16-s2 */
<> 144:ef7eb2e8f9f7 96 TMR16_3_IRQn, /* 61:46 Timer16-s3 */
<> 144:ef7eb2e8f9f7 97 I2CM1_IRQn, /* 62:47 I2C Master 1 */
<> 144:ef7eb2e8f9f7 98 MXC_IRQ_EXT_COUNT,
<> 144:ef7eb2e8f9f7 99 } IRQn_Type;
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 104 /* ================ Processor and Core Peripheral Section ================ */
<> 144:ef7eb2e8f9f7 105 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 #include <core_cm3.h> /* Processor and core peripherals */
<> 144:ef7eb2e8f9f7 110 #include "system_max32610.h" /* System Header */
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 113 /* ================== Device Specific Memory Section ================== */
<> 144:ef7eb2e8f9f7 114 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 #define MXC_FLASH_MEM_BASE 0x00000000UL
<> 144:ef7eb2e8f9f7 117 #define MXC_FLASH_PAGE_SIZE 0x1000 // 256 x 128b = 4KB
<> 144:ef7eb2e8f9f7 118 #define MXC_FLASH_MEM_SIZE 0x00040000UL
<> 144:ef7eb2e8f9f7 119 #define MXC_SYS_MEM_BASE 0x20000000UL
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 122 /* ================ Device Specific Peripheral Section ================ */
<> 144:ef7eb2e8f9f7 123 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 126 /* General Purpose I/O Ports (GPIO) */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 #define MXC_BASE_GPIO ((uint32_t)0x40000000UL)
<> 144:ef7eb2e8f9f7 129 #define MXC_GPIO ((mxc_gpio_regs_t *)MXC_BASE_GPIO)
<> 144:ef7eb2e8f9f7 130 #define MXC_BASE_GPIO_BITBAND ((uint32_t)0x42000000UL)
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 #define MXC_GPIO_GET_IRQ(i) (((unsigned int)i) + GPIO_P0_IRQn)
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 136 /* Pulse Train Generation */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 #define MXC_CFG_PT_INSTANCES (13)
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 #define MXC_BASE_PTG ((uint32_t)0x40001000UL)
<> 144:ef7eb2e8f9f7 141 #define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG)
<> 144:ef7eb2e8f9f7 142 #define MXC_BASE_PT ((uint32_t)0x40001008UL)
<> 144:ef7eb2e8f9f7 143 #define MXC_PT ((mxc_pt_regs_t *)MXC_BASE_PT)
<> 144:ef7eb2e8f9f7 144 #define MXC_BASE_PT0 ((uint32_t)0x40001008UL)
<> 144:ef7eb2e8f9f7 145 #define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0)
<> 144:ef7eb2e8f9f7 146 #define MXC_BASE_PT1 ((uint32_t)0x40001010UL)
<> 144:ef7eb2e8f9f7 147 #define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1)
<> 144:ef7eb2e8f9f7 148 #define MXC_BASE_PT2 ((uint32_t)0x40001018UL)
<> 144:ef7eb2e8f9f7 149 #define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2)
<> 144:ef7eb2e8f9f7 150 #define MXC_BASE_PT3 ((uint32_t)0x40001020UL)
<> 144:ef7eb2e8f9f7 151 #define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3)
<> 144:ef7eb2e8f9f7 152 #define MXC_BASE_PT4 ((uint32_t)0x40001028UL)
<> 144:ef7eb2e8f9f7 153 #define MXC_PT4 ((mxc_pt_regs_t *)MXC_BASE_PT4)
<> 144:ef7eb2e8f9f7 154 #define MXC_BASE_PT5 ((uint32_t)0x40001030UL)
<> 144:ef7eb2e8f9f7 155 #define MXC_PT5 ((mxc_pt_regs_t *)MXC_BASE_PT5)
<> 144:ef7eb2e8f9f7 156 #define MXC_BASE_PT6 ((uint32_t)0x40001038UL)
<> 144:ef7eb2e8f9f7 157 #define MXC_PT6 ((mxc_pt_regs_t *)MXC_BASE_PT6)
<> 144:ef7eb2e8f9f7 158 #define MXC_BASE_PT7 ((uint32_t)0x40001040UL)
<> 144:ef7eb2e8f9f7 159 #define MXC_PT7 ((mxc_pt_regs_t *)MXC_BASE_PT7)
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /* PT12, PT13, PT14 are not used */
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 164 /* CRC-16/CRC-32 Engine */
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 #define MXC_BASE_CRC ((uint32_t)0x40010000UL)
<> 144:ef7eb2e8f9f7 167 #define MXC_CRC_REGS ((mxc_crc_regs_t *)MXC_BASE_CRC)
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 #define MXC_BASE_CRC_DATA ((uint32_t)0x4010B000UL)
<> 144:ef7eb2e8f9f7 170 #define MXC_CRC_DATA ((mxc_crc_data_regs_t *)MXC_BASE_CRC_DATA)
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 173 /* Trust Protection Unit (TPU) */
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 #define MXC_BASE_TPU ((uint32_t)0x40011000UL)
<> 144:ef7eb2e8f9f7 176 #define MXC_TPU ((mxc_tpu_regs_t *)MXC_BASE_TPU)
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 #define MXC_BASE_TPU_TSR ((uint32_t)0x40011C00UL)
<> 144:ef7eb2e8f9f7 179 #define MXC_TPU_TSR ((mxc_tpu_tsr_regs_t *)MXC_BASE_TPU_TSR)
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 182 /* AES Cryptographic Engine */
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 #define MXC_BASE_AES ((uint32_t)0x40011400UL)
<> 144:ef7eb2e8f9f7 185 #define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES)
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 #define MXC_BASE_AES_MEM ((uint32_t)0x4010A000UL)
<> 144:ef7eb2e8f9f7 188 #define MXC_AES_MEM ((mxc_aes_mem_regs_t *)MXC_BASE_AES_MEM)
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 192 /* MAA Cryptographic Engine */
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 #define MXC_BASE_MAA ((uint32_t)0x40011800UL)
<> 144:ef7eb2e8f9f7 195 #define MXC_MAA ((mxc_maa_regs_t *)MXC_BASE_MAA)
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 #define MXC_BASE_MAA_MEM ((uint32_t)0x4010A800UL)
<> 144:ef7eb2e8f9f7 198 #define MXC_MAA_MEM ((mxc_maa_mem_regs_t *)MXC_BASE_MAA_MEM)
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 201 /* 32-Bit PWM Timer/Counter */
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 #define MXC_CFG_TMR_INSTANCES (4)
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 #define MXC_BASE_TMR0 ((uint32_t)0x40012000UL)
<> 144:ef7eb2e8f9f7 206 #define MXC_BASE_TMR0_BITBAND ((uint32_t)0x42240000UL)
<> 144:ef7eb2e8f9f7 207 #define MXC_TMR0 ((mxc_tmr_regs_t *) MXC_BASE_TMR0)
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 #define MXC_BASE_TMR1 ((uint32_t)0x40013000UL)
<> 144:ef7eb2e8f9f7 210 #define MXC_BASE_TMR1_BITBAND ((uint32_t)0x42260000UL)
<> 144:ef7eb2e8f9f7 211 #define MXC_TMR1 ((mxc_tmr_regs_t *) MXC_BASE_TMR1)
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 #define MXC_BASE_TMR2 ((uint32_t)0x40014000UL)
<> 144:ef7eb2e8f9f7 214 #define MXC_BASE_TMR2_BITBAND ((uint32_t)0x42280000UL)
<> 144:ef7eb2e8f9f7 215 #define MXC_TMR2 ((mxc_tmr_regs_t *) MXC_BASE_TMR2)
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 #define MXC_BASE_TMR3 ((uint32_t)0x40015000UL)
<> 144:ef7eb2e8f9f7 218 #define MXC_BASE_TMR3_BITBAND ((uint32_t)0x422A0000UL)
<> 144:ef7eb2e8f9f7 219 #define MXC_TMR3 ((mxc_tmr_regs_t *) MXC_BASE_TMR3)
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 #define MXC_TMR_GET_IRQ_32(i) ((i) == 0 ? TMR0_IRQn : \
<> 144:ef7eb2e8f9f7 223 (i) == 1 ? TMR1_IRQn : \
<> 144:ef7eb2e8f9f7 224 (i) == 2 ? TMR2_IRQn : \
<> 144:ef7eb2e8f9f7 225 (i) == 3 ? TMR3_IRQn : 0)
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 #define MXC_TMR_GET_IRQ_16(i) ((i) == 0 ? TMR0_IRQn : \
<> 144:ef7eb2e8f9f7 228 (i) == 1 ? TMR1_IRQn : \
<> 144:ef7eb2e8f9f7 229 (i) == 2 ? TMR2_IRQn : \
<> 144:ef7eb2e8f9f7 230 (i) == 3 ? TMR3_IRQn : \
<> 144:ef7eb2e8f9f7 231 (i) == 4 ? TMR16_0_IRQn : \
<> 144:ef7eb2e8f9f7 232 (i) == 5 ? TMR16_1_IRQn : \
<> 144:ef7eb2e8f9f7 233 (i) == 6 ? TMR16_2_IRQn : \
<> 144:ef7eb2e8f9f7 234 (i) == 7 ? TMR16_3_IRQn : 0)
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 #define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \
<> 144:ef7eb2e8f9f7 237 (i) == 1 ? MXC_BASE_TMR1 : \
<> 144:ef7eb2e8f9f7 238 (i) == 2 ? MXC_BASE_TMR2 : \
<> 144:ef7eb2e8f9f7 239 (i) == 3 ? MXC_BASE_TMR3 : 0)
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 #define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \
<> 144:ef7eb2e8f9f7 242 (i) == 1 ? MXC_TMR1 : \
<> 144:ef7eb2e8f9f7 243 (i) == 2 ? MXC_TMR2 : \
<> 144:ef7eb2e8f9f7 244 (i) == 3 ? MXC_TMR3 : 0)
<> 144:ef7eb2e8f9f7 245 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 246 /* Watchdog Timer */
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 #define MXC_CFG_WDT_INSTANCES (2)
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 #define MXC_BASE_WDT0 ((uint32_t)0x40021000UL)
<> 144:ef7eb2e8f9f7 251 #define MXC_BASE_WDT0_BITBAND ((uint32_t)0x42420000UL)
<> 144:ef7eb2e8f9f7 252 #define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0)
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 #define MXC_BASE_WDT1 ((uint32_t)0x40022000UL)
<> 144:ef7eb2e8f9f7 255 #define MXC_BASE_WDT1_BITBAND ((uint32_t)0x42440000UL)
<> 144:ef7eb2e8f9f7 256 #define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1)
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 #define MXC_WDT_GET_IRQ(i) ((i) == 0 ? WDT0_IRQn : \
<> 144:ef7eb2e8f9f7 259 (i) == 1 ? WDT1_IRQn : 0)
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 #define MXC_WDT_GET_IRQ_P(i) ((i) == 0 ? WDT0_P_IRQn : \
<> 144:ef7eb2e8f9f7 262 (i) == 1 ? WDT1_P_IRQn : 0)
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 #define MXC_WDT_GET_BASE(i) ((i) == 0 ? MXC_BASE_WDT0 : \
<> 144:ef7eb2e8f9f7 265 (i) == 1 ? MXC_BASE_WDT1 : 0)
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 #define MXC_WDT_GET_WDT(i) ((i) == 0 ? MXC_WDT0 : \
<> 144:ef7eb2e8f9f7 268 (i) == 1 ? MXC_WDT1 : 0)
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 271 /* SPI Interface */
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 #define MXC_CFG_SPI_INSTANCES (3)
<> 144:ef7eb2e8f9f7 274 #define MXC_CFG_SPI_FIFO_DEPTH (16)
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 #define MXC_BASE_SPI0 ((uint32_t)0x40030000UL)
<> 144:ef7eb2e8f9f7 277 #define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI0)
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 #define MXC_BASE_SPI0_TXFIFO ((uint32_t)0x40100000UL)
<> 144:ef7eb2e8f9f7 280 #define MXC_SPI0_TXFIFO ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI0_TXFIFO)
<> 144:ef7eb2e8f9f7 281 #define MXC_BASE_SPI0_RXFIFO ((uint32_t)0x40100800UL)
<> 144:ef7eb2e8f9f7 282 #define MXC_SPI0_RXFIFO ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI0_RXFIFO)
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 #define MXC_BASE_SPI1 ((uint32_t)0x40031000UL)
<> 144:ef7eb2e8f9f7 285 #define MXC_SPI1 ((mxc_spi_regs_t *)MXC_BASE_SPI1)
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 #define MXC_BASE_SPI1_TXFIFO ((uint32_t)0x40101000UL)
<> 144:ef7eb2e8f9f7 288 #define MXC_SPI1_TXFIFO ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI1_TXFIFO)
<> 144:ef7eb2e8f9f7 289 #define MXC_BASE_SPI1_RXFIFO ((uint32_t)0x40101800UL)
<> 144:ef7eb2e8f9f7 290 #define MXC_SPI1_RXFIFO ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI1_RXFIFO)
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 #define MXC_BASE_SPI2 ((uint32_t)0x40032000UL)
<> 144:ef7eb2e8f9f7 293 #define MXC_SPI2 ((mxc_spi_regs_t *)MXC_BASE_SPI2)
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 #define MXC_BASE_SPI2_TXFIFO ((uint32_t)0x40102000UL)
<> 144:ef7eb2e8f9f7 296 #define MXC_SPI2_TXFIFO ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI2_TXFIFO)
<> 144:ef7eb2e8f9f7 297 #define MXC_BASE_SPI2_RXFIFO ((uint32_t)0x40102800UL)
<> 144:ef7eb2e8f9f7 298 #define MXC_SPI2_RXFIFO ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI2_RXFIFO)
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 #define MXC_SPI_GET_IRQ(i) ((i) == 0 ? SPI0_IRQn : \
<> 144:ef7eb2e8f9f7 302 (i) == 1 ? SPI1_IRQn : \
<> 144:ef7eb2e8f9f7 303 (i) == 2 ? SPI2_IRQn : 0)
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 #define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI0 : \
<> 144:ef7eb2e8f9f7 306 (i) == 1 ? MXC_BASE_SPI1 : \
<> 144:ef7eb2e8f9f7 307 (i) == 2 ? MXC_BASE_SPI2 : 0)
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 #define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : \
<> 144:ef7eb2e8f9f7 310 (i) == 1 ? MXC_SPI1 : \
<> 144:ef7eb2e8f9f7 311 (i) == 2 ? MXC_SPI2 : 0)
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 #define MXC_SPI_GET_RXFIFO(i) ((i) == 0 ? MXC_SPI0_RXFIFO : \
<> 144:ef7eb2e8f9f7 314 (i) == 1 ? MXC_SPI1_RXFIFO : \
<> 144:ef7eb2e8f9f7 315 (i) == 2 ? MXC_SPI2_RXFIFO : 0)
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 #define MXC_SPI_GET_TXFIFO(i) ((i) == 0 ? MXC_SPI0_TXFIFO : \
<> 144:ef7eb2e8f9f7 318 (i) == 1 ? MXC_SPI1_TXFIFO : \
<> 144:ef7eb2e8f9f7 319 (i) == 2 ? MXC_SPI2_TXFIFO : 0)
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 #define MXC_SPI_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 12) + MXC_BASE_SPI0)
<> 144:ef7eb2e8f9f7 322 #define MXC_SPI_BASE_TO_INSTANCE(base) (((uint32_t)(base) & 0x00003000) >> 12)
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 326 /* UART Interface */
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 #define MXC_CFG_UART_INSTANCES (2)
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 #define MXC_BASE_UART0 ((uint32_t)0x40038000UL)
<> 144:ef7eb2e8f9f7 331 #define MXC_BASE_UART0_BITBAND ((uint32_t)0x42700000UL)
<> 144:ef7eb2e8f9f7 332 #define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0)
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 #define MXC_BASE_UART1 ((uint32_t)0x40039000UL)
<> 144:ef7eb2e8f9f7 335 #define MXC_BASE_UART1_BITBAND ((uint32_t)0x42720000UL)
<> 144:ef7eb2e8f9f7 336 #define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1)
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 #define MXC_UART_GET_IRQ(i) ((i) == 0 ? UART0_IRQn : \
<> 144:ef7eb2e8f9f7 340 (i) == 1 ? UART1_IRQn : 0)
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 #define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \
<> 144:ef7eb2e8f9f7 343 (i) == 1 ? MXC_BASE_UART1 : 0)
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 #define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \
<> 144:ef7eb2e8f9f7 346 (i) == 1 ? MXC_UART1 : 0)
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 #define MXC_UART_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 12) + MXC_BASE_UART0)
<> 144:ef7eb2e8f9f7 349 #define MXC_UART_BASE_TO_INSTANCE(base) (((uint32_t)(base) & 0x00001000) >> 12)
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 353 /* I2C Master Interface */
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 #define MXC_CFG_I2CM_INSTANCES (2)
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 #define MXC_BASE_I2CM0 ((uint32_t)0x40040000UL)
<> 144:ef7eb2e8f9f7 358 #define MXC_BASE_I2CM0_BITBAND ((uint32_t)0x42800000UL)
<> 144:ef7eb2e8f9f7 359 #define MXC_I2CM0 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM0)
<> 144:ef7eb2e8f9f7 360 #define MXC_BASE_I2CM0_TX_FIFO ((uint32_t)0x40103000UL)
<> 144:ef7eb2e8f9f7 361 #define MXC_BASE_I2CM0_RX_FIFO ((uint32_t)0x40103800UL)
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 #define MXC_BASE_I2CM1 ((uint32_t)0x40042000UL)
<> 144:ef7eb2e8f9f7 364 #define MXC_BASE_I2CM1_BITBAND ((uint32_t)0x42840000UL)
<> 144:ef7eb2e8f9f7 365 #define MXC_I2CM1 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM1)
<> 144:ef7eb2e8f9f7 366 #define MXC_BASE_I2CM1_TX_FIFO ((uint32_t)0x4010D000UL)
<> 144:ef7eb2e8f9f7 367 #define MXC_BASE_I2CM1_RX_FIFO ((uint32_t)0x4010D800UL)
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 #define MXC_I2CM_GET_IRQ(i) ((i) == 0 ? I2CM0_IRQn : \
<> 144:ef7eb2e8f9f7 370 (i) == 1 ? I2CM1_IRQn : 0)
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 #define MXC_I2CM_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CM0 : \
<> 144:ef7eb2e8f9f7 373 (i) == 1 ? MXC_BASE_I2CM1 : 0)
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 #define MXC_I2CM_GET_I2CM(i) ((i) == 0 ? MXC_I2CM0 : \
<> 144:ef7eb2e8f9f7 376 (i) == 1 ? MXC_I2CM1 : 0)
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 #define MXC_I2CM_GET_BASE_TX_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_TX_FIFO : \
<> 144:ef7eb2e8f9f7 379 (i) == 1 ? MXC_BASE_I2CM1_TX_FIFO : 0)
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 #define MXC_I2CM_GET_BASE_RX_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_RX_FIFO : \
<> 144:ef7eb2e8f9f7 382 (i) == 1 ? MXC_BASE_I2CM1_RX_FIFO : 0)
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 #define MXC_I2CM_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 13) + MXC_BASE_I2CM0)
<> 144:ef7eb2e8f9f7 385 #define MXC_I2CM_BASE_TO_INSTANCE(base) (((uint32_t)(base) & 0x00002000) >> 13)
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 389 /* I2C Slave Interface */
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 #define MXC_CFG_I2CS_INSTANCES (1)
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 #define MXC_BASE_I2CS0 ((uint32_t)0x40041000UL)
<> 144:ef7eb2e8f9f7 394 #define MXC_BASE_I2CS0_BITBAND ((uint32_t)0x42820000UL)
<> 144:ef7eb2e8f9f7 395 #define MXC_I2CS0 ((mxc_i2cs_regs_t *)MXC_BASE_I2CS0)
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 #define MXC_BASE_I2CS0_FIFO ((uint32_t)0x40104000UL)
<> 144:ef7eb2e8f9f7 398 #define MXC_I2CS0_FIFO ((mxc_i2cs_fifo_regs_t *)MXC_BASE_I2CS0)
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 403 /* DACs */
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 #define MXC_CFG_DAC_INSTANCES (4)
<> 144:ef7eb2e8f9f7 406 #define MXC_CFG_DAC_FIFO_DEPTH (32)
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 #define MXC_BASE_DAC0 ((uint32_t)0x40050000UL)
<> 144:ef7eb2e8f9f7 409 #define MXC_DAC0 ((mxc_dac_regs_t *)MXC_BASE_DAC0)
<> 144:ef7eb2e8f9f7 410 #define MXC_BASE_DAC0_FIFO ((uint32_t)0x40105000UL)
<> 144:ef7eb2e8f9f7 411 #define MXC_DAC0_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC0_FIFO)
<> 144:ef7eb2e8f9f7 412 #define MXC_DAC0_WIDTH ((uint8_t)(2))
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 #define MXC_BASE_DAC1 ((uint32_t)0x40051000UL)
<> 144:ef7eb2e8f9f7 415 #define MXC_DAC1 ((mxc_dac_regs_t *)MXC_BASE_DAC1)
<> 144:ef7eb2e8f9f7 416 #define MXC_BASE_DAC1_FIFO ((uint32_t)0x40106000UL)
<> 144:ef7eb2e8f9f7 417 #define MXC_DAC1_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC1_FIFO)
<> 144:ef7eb2e8f9f7 418 #define MXC_DAC1_WIDTH ((uint8_t)(2))
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 #define MXC_BASE_DAC2 ((uint32_t)0x40052000UL)
<> 144:ef7eb2e8f9f7 421 #define MXC_DAC2 ((mxc_dac_regs_t *)MXC_BASE_DAC2)
<> 144:ef7eb2e8f9f7 422 #define MXC_BASE_DAC2_FIFO ((uint32_t)0x40107000UL)
<> 144:ef7eb2e8f9f7 423 #define MXC_DAC2_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC2_FIFO)
<> 144:ef7eb2e8f9f7 424 #define MXC_DAC2_WIDTH ((uint8_t)(1))
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 #define MXC_BASE_DAC3 ((uint32_t)0x40053000UL)
<> 144:ef7eb2e8f9f7 427 #define MXC_DAC3 ((mxc_dac_regs_t *)MXC_BASE_DAC3)
<> 144:ef7eb2e8f9f7 428 #define MXC_BASE_DAC3_FIFO ((uint32_t)0x40108000UL)
<> 144:ef7eb2e8f9f7 429 #define MXC_DAC3_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC3_FIFO)
<> 144:ef7eb2e8f9f7 430 #define MXC_DAC3_WIDTH ((uint8_t)(1))
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 #define MXC_DAC_GET_IRQ(i) ((i) == 0 ? DAC0_IRQn : \
<> 144:ef7eb2e8f9f7 434 (i) == 1 ? DAC1_IRQn : \
<> 144:ef7eb2e8f9f7 435 (i) == 2 ? DAC2_IRQn : \
<> 144:ef7eb2e8f9f7 436 (i) == 3 ? DAC3_IRQn : 0)
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 #define MXC_DAC_GET_BASE(i) (i == 0 ? MXC_BASE_DAC0 : \
<> 144:ef7eb2e8f9f7 440 i == 1 ? MXC_BASE_DAC1 : \
<> 144:ef7eb2e8f9f7 441 i == 2 ? MXC_BASE_DAC2 : \
<> 144:ef7eb2e8f9f7 442 i == 3 ? MXC_BASE_DAC3 : 0)
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 #define MXC_DAC_GET_FIFO(i) (i == 0 ? MXC_BASE_DAC0_FIFO : \
<> 144:ef7eb2e8f9f7 445 i == 1 ? MXC_BASE_DAC1_FIFO : \
<> 144:ef7eb2e8f9f7 446 i == 2 ? MXC_BASE_DAC2_FIFO : \
<> 144:ef7eb2e8f9f7 447 i == 3 ? MXC_BASE_DAC3_FIFO : 0)
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 #define MXC_DAC_GET_PMU_FIFO_IRQ(i) (i == 0 ? PMU_IRQ_DAC0_FIFO_AE : \
<> 144:ef7eb2e8f9f7 450 i == 1 ? PMU_IRQ_DAC1_FIFO_AE : \
<> 144:ef7eb2e8f9f7 451 i == 2 ? PMU_IRQ_DAC2_FIFO_AE : \
<> 144:ef7eb2e8f9f7 452 i == 3 ? PMU_IRQ_DAC3_FIFO_AE : 0)
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 #define MXC_DAC_GET_DAC(i) (i == 0 ? MXC_DAC0 : \
<> 144:ef7eb2e8f9f7 455 i == 1 ? MXC_DAC1 : \
<> 144:ef7eb2e8f9f7 456 i == 2 ? MXC_DAC2 : \
<> 144:ef7eb2e8f9f7 457 i == 3 ? MXC_DAC3 : 0)
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 #define MXC_DAC_GET_WIDTH(i) (i == 0 ? MXC_DAC0_WIDTH : \
<> 144:ef7eb2e8f9f7 460 i == 1 ? MXC_DAC1_WIDTH : \
<> 144:ef7eb2e8f9f7 461 i == 2 ? MXC_DAC2_WIDTH : \
<> 144:ef7eb2e8f9f7 462 i == 3 ? MXC_DAC3_WIDTH : 0)
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 466 /* Analog Front End */
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468 #define MXC_BASE_AFE ((uint32_t)0x4005401CUL)
<> 144:ef7eb2e8f9f7 469 #define MXC_AFE ((mxc_afe_regs_t *)MXC_BASE_AFE)
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 474 /* ADC */
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 #define MXC_CFG_ADC_FIFO_DEPTH ((uint32_t)(32))
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 #define MXC_BASE_ADC ((uint32_t)0x40054000UL)
<> 144:ef7eb2e8f9f7 479 #define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC)
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 #define MXC_BASE_ADCCFG ((uint32_t)0x40054038UL)
<> 144:ef7eb2e8f9f7 482 #define MXC_ADCCFG ((mxc_adccfg_regs_t *)MXC_BASE_ADCCFG)
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 #define MXC_BASE_ADC_FIFO ((uint32_t)0x40109000UL)
<> 144:ef7eb2e8f9f7 485 #define MXC_ADC_FIFO ((mxc_adc_fifo_regs_t *)MXC_BASE_ADC_FIFO)
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 490 /* Peripheral Management Unit (PMU) - formerly DMA Controller */
<> 144:ef7eb2e8f9f7 491
<> 144:ef7eb2e8f9f7 492 #define MXC_CFG_PMU_CHANNELS (6)
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 #define MXC_BASE_PMU0 ((uint32_t)0x40070000UL)
<> 144:ef7eb2e8f9f7 495 #define MXC_PMU0 ((mxc_pmu_regs_t *)MXC_BASE_PMU0)
<> 144:ef7eb2e8f9f7 496 #define MXC_BASE_PMU1 ((uint32_t)0x40070020UL)
<> 144:ef7eb2e8f9f7 497 #define MXC_PMU1 ((mxc_pmu_regs_t *)MXC_BASE_PMU1)
<> 144:ef7eb2e8f9f7 498 #define MXC_BASE_PMU2 ((uint32_t)0x40070040UL)
<> 144:ef7eb2e8f9f7 499 #define MXC_PMU2 ((mxc_pmu_regs_t *)MXC_BASE_PMU2)
<> 144:ef7eb2e8f9f7 500 #define MXC_BASE_PMU3 ((uint32_t)0x40070060UL)
<> 144:ef7eb2e8f9f7 501 #define MXC_PMU3 ((mxc_pmu_regs_t *)MXC_BASE_PMU3)
<> 144:ef7eb2e8f9f7 502 #define MXC_BASE_PMU4 ((uint32_t)0x40070080UL)
<> 144:ef7eb2e8f9f7 503 #define MXC_PMU4 ((mxc_pmu_regs_t *)MXC_BASE_PMU4)
<> 144:ef7eb2e8f9f7 504 #define MXC_BASE_PMU5 ((uint32_t)0x400700A0UL)
<> 144:ef7eb2e8f9f7 505 #define MXC_PMU5 ((mxc_pmu_regs_t *)MXC_BASE_PMU5)
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 #define MXC_BASE_PMU_BITBAND ((uint32_t)0x42E00000UL)
<> 144:ef7eb2e8f9f7 508 #define MXC_BASE_PMU_BITBAND_CHOFFSET ((uint32_t)0x00000400UL)
<> 144:ef7eb2e8f9f7 509 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 typedef enum {
<> 144:ef7eb2e8f9f7 512 PMU_IRQ_DAC0_FIFO_AE,
<> 144:ef7eb2e8f9f7 513 PMU_IRQ_DAC1_FIFO_AE,
<> 144:ef7eb2e8f9f7 514 PMU_IRQ_DAC2_FIFO_AE,
<> 144:ef7eb2e8f9f7 515 PMU_IRQ_DAC3_FIFO_AE,
<> 144:ef7eb2e8f9f7 516 PMU_IRQ_DAC0_DONE,
<> 144:ef7eb2e8f9f7 517 PMU_IRQ_DAC1_DONE,
<> 144:ef7eb2e8f9f7 518 PMU_IRQ_DAC2_DONE,
<> 144:ef7eb2e8f9f7 519 PMU_IRQ_DAC3_DONE,
<> 144:ef7eb2e8f9f7 520 PMU_IRQ_ADC_FIFO_AF,
<> 144:ef7eb2e8f9f7 521 PMU_IRQ_ADC_DONE,
<> 144:ef7eb2e8f9f7 522 PMU_IRQ_I2C_MST0_DONE,
<> 144:ef7eb2e8f9f7 523 PMU_IRQ_I2C_MST1_DONE,
<> 144:ef7eb2e8f9f7 524 PMU_IRQ_SPI0_RSLTS_DONE,
<> 144:ef7eb2e8f9f7 525 PMU_IRQ_SPI1_RSLTS_DONE,
<> 144:ef7eb2e8f9f7 526 PMU_IRQ_SPI2_RSLTS_DONE,
<> 144:ef7eb2e8f9f7 527 PMU_IRQ_MAA_DONE,
<> 144:ef7eb2e8f9f7 528 PMU_IRQ_SPI0_TX_FIFO_AE,
<> 144:ef7eb2e8f9f7 529 PMU_IRQ_SPI0_RSLTS_FIFO_AF,
<> 144:ef7eb2e8f9f7 530 PMU_IRQ_SPI1_TX_FIFO_AE,
<> 144:ef7eb2e8f9f7 531 PMU_IRQ_SPI1_RSLTS_FIFO_AF,
<> 144:ef7eb2e8f9f7 532 PMU_IRQ_SPI2_TX_FIFO_AE,
<> 144:ef7eb2e8f9f7 533 PMU_IRQ_SPI3_RSLTS_FIFO_AF,
<> 144:ef7eb2e8f9f7 534 PMU_IRQ_I2C_MST0_TRANS_FIFO,
<> 144:ef7eb2e8f9f7 535 PMU_IRQ_I2C_MST0_RSLT_FIFO,
<> 144:ef7eb2e8f9f7 536 PMU_IRQ_I2C_MST1_TRANS_FIFO,
<> 144:ef7eb2e8f9f7 537 PMU_IRQ_I2C_MST2_RSLT_FIFO,
<> 144:ef7eb2e8f9f7 538 PMU_IRQ_I2C_SLV_TRANS_FIFO,
<> 144:ef7eb2e8f9f7 539 PMU_IRQ_I2C_SLV_RSLT_FIFO,
<> 144:ef7eb2e8f9f7 540 PMU_IRQ_UART0_TX_FIFO,
<> 144:ef7eb2e8f9f7 541 PMU_IRQ_UART0_RX_FIFO,
<> 144:ef7eb2e8f9f7 542 PMU_IRQ_UART1_TX_FIFO,
<> 144:ef7eb2e8f9f7 543 PMU_IRQ_UART1_RX_FIFO,
<> 144:ef7eb2e8f9f7 544 PMU_IRQ_SPI0_EXCP,
<> 144:ef7eb2e8f9f7 545 PMU_IRQ_SPI1_EXCP,
<> 144:ef7eb2e8f9f7 546 PMU_IRQ_SPI2_EXCP,
<> 144:ef7eb2e8f9f7 547 PMU_IRQ_RSVD0,
<> 144:ef7eb2e8f9f7 548 PMU_IRQ_I2C_MST0_EXCP,
<> 144:ef7eb2e8f9f7 549 PMU_IRQ_I2C_MST1_EXCP,
<> 144:ef7eb2e8f9f7 550 PMU_IRQ_I2C_SLV_EXCP,
<> 144:ef7eb2e8f9f7 551 PMU_IRQ_RSVD1,
<> 144:ef7eb2e8f9f7 552 PMU_IRQ_GPIO0,
<> 144:ef7eb2e8f9f7 553 PMU_IRQ_GPIO1,
<> 144:ef7eb2e8f9f7 554 PMU_IRQ_GPIO2,
<> 144:ef7eb2e8f9f7 555 PMU_IRQ_GPIO3,
<> 144:ef7eb2e8f9f7 556 PMU_IRQ_GPIO4,
<> 144:ef7eb2e8f9f7 557 PMU_IRQ_GPIO5,
<> 144:ef7eb2e8f9f7 558 PMU_IRQ_GPIO6,
<> 144:ef7eb2e8f9f7 559 PMU_IRQ_GPIO7,
<> 144:ef7eb2e8f9f7 560 PMU_IRQ_GPIO8,
<> 144:ef7eb2e8f9f7 561 PMU_IRQ_AFE_COMP_NMI,
<> 144:ef7eb2e8f9f7 562 PMU_IRQ_AES_ENGINE,
<> 144:ef7eb2e8f9f7 563 } pmu_int_mask_t;
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 566 /* USB */
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 #define MXC_BASE_USB ((uint32_t)0x4010C000UL)
<> 144:ef7eb2e8f9f7 569 #define MXC_USB ((mxc_usb_regs_t *)MXC_BASE_USB)
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 #define MXC_USB_MAX_PACKET (64)
<> 144:ef7eb2e8f9f7 572 #define MXC_USB_NUM_EP (8)
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 576 /* Instruction Cache Controller */
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 #define MXC_BASE_ICC ((uint32_t)0x40080000UL)
<> 144:ef7eb2e8f9f7 579 #define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC)
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 /* System Manager */
<> 144:ef7eb2e8f9f7 582
<> 144:ef7eb2e8f9f7 583 #define MXC_BASE_SYSMAN ((uint32_t)0x40090000UL)
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 586 /* Clock Manager */
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 #define MXC_BASE_CLKMAN ((uint32_t)0x40090400UL)
<> 144:ef7eb2e8f9f7 589 #define MXC_CLKMAN ((mxc_clkman_regs_t *)MXC_BASE_CLKMAN)
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 593 /* Power Manager */
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 #define MXC_BASE_PWRMAN ((uint32_t)0x40090800UL)
<> 144:ef7eb2e8f9f7 596 #define MXC_PWRMAN ((mxc_pwrman_regs_t *)MXC_BASE_PWRMAN)
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 599 /* I/O Manager */
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 #define MXC_BASE_IOMAN ((uint32_t)0x40090C00UL)
<> 144:ef7eb2e8f9f7 602 #define MXC_IOMAN ((mxc_ioman_regs_t *)MXC_BASE_IOMAN)
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 606 /* RTC: Timer/Alarms */
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 #define MXC_BASE_RTCTMR ((uint32_t)0x40090A00UL)
<> 144:ef7eb2e8f9f7 609 #define MXC_RTCTMR ((mxc_rtctmr_regs_t *)MXC_BASE_RTCTMR)
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 #define MXC_RTCTMR_GET_IRQ(i) (i == 0 ? RTC0_IRQn : \
<> 144:ef7eb2e8f9f7 612 i == 1 ? RTC1_IRQn : \
<> 144:ef7eb2e8f9f7 613 i == 2 ? RTC2_IRQn : \
<> 144:ef7eb2e8f9f7 614 i == 3 ? RTC3_IRQn : 0)
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 #define MXC_BASE_RTCCFG ((uint32_t)0x40090A70UL)
<> 144:ef7eb2e8f9f7 617 #define MXC_RTCCFG ((mxc_rtccfg_regs_t *)MXC_BASE_RTCCFG)
<> 144:ef7eb2e8f9f7 618 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 619 /* RTC: Power Sequencer */
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 #define MXC_BASE_PWRSEQ ((uint32_t)0x40090A30UL)
<> 144:ef7eb2e8f9f7 622 #define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 625 /* Trim Shadow Registers */
<> 144:ef7eb2e8f9f7 626
<> 144:ef7eb2e8f9f7 627 #define MXC_BASE_TRIM ((uint32_t)0x400E0000UL)
<> 144:ef7eb2e8f9f7 628 #define MXC_TRIM ((mxc_ftr_regs_t *)MXC_BASE_TRIM)
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 631 /* Flash Memory Controller / Security */
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 #define MXC_BASE_FLC ((uint32_t)0x400F0000UL)
<> 144:ef7eb2e8f9f7 634 #define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC)
<> 144:ef7eb2e8f9f7 635 #define MXC_BASE_FLC_BITBAND ((uint32_t)0x43E00000UL)
<> 144:ef7eb2e8f9f7 636 #define MXC_FLC_PAGE_SIZE_SHIFT 11
<> 144:ef7eb2e8f9f7 637 #define MXC_FLC_PAGE_SIZE (1 << MXC_FLC_PAGE_SIZE_SHIFT)
<> 144:ef7eb2e8f9f7 638 #define MXC_FLC_PAGE_ERASE_MSK ((~(1 << (MXC_FLC_PAGE_SIZE_SHIFT - 1))) >> MXC_FLC_PAGE_SIZE_SHIFT) << MXC_FLC_PAGE_SIZE_SHIFT
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642 #define MXC_SET_FIELD(reg, clr, set) (*(volatile uint32_t *)reg = ((*(volatile uint32_t *)reg & ~clr) | set))
<> 144:ef7eb2e8f9f7 643
<> 144:ef7eb2e8f9f7 644 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 #define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
<> 144:ef7eb2e8f9f7 647 #define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
<> 144:ef7eb2e8f9f7 648 #define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
<> 144:ef7eb2e8f9f7 649 #define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 /*******************************************************************************/
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 #endif /* _MAX32610_H_ */