Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Maxim/TARGET_MAX32610/flc_regs.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #ifndef _MXC_FLC_REGS_H
<> 144:ef7eb2e8f9f7 35 #define _MXC_FLC_REGS_H
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 38 extern "C" {
<> 144:ef7eb2e8f9f7 39 #endif
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #include <stdint.h>
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /**
<> 144:ef7eb2e8f9f7 44 * @file flc_regs.h
<> 144:ef7eb2e8f9f7 45 * @addtogroup flc FLC
<> 144:ef7eb2e8f9f7 46 * @{
<> 144:ef7eb2e8f9f7 47 */
<> 144:ef7eb2e8f9f7 48 /* Offset Register Description
<> 144:ef7eb2e8f9f7 49 ====== ======================================================= */
<> 144:ef7eb2e8f9f7 50 typedef struct {
<> 144:ef7eb2e8f9f7 51 __IO uint32_t faddr; /* 0x0000 Flash Operation Address */
<> 144:ef7eb2e8f9f7 52 __IO uint32_t fckdiv; /* 0x0004 Flash Clock Rate Divisor */
<> 144:ef7eb2e8f9f7 53 __IO uint32_t ctrl; /* 0x0008 Flash Control Register */
<> 144:ef7eb2e8f9f7 54 __I uint32_t rsv000C[6]; /* 0x000C */
<> 144:ef7eb2e8f9f7 55 __IO uint32_t intr; /* 0x0024 Flash Controller Interrupt Flags and Enable/Disable 0 */
<> 144:ef7eb2e8f9f7 56 __I uint32_t rsv0028[2]; /* 0x0028 */
<> 144:ef7eb2e8f9f7 57 __IO uint32_t fdata; /* 0x0030 Flash Operation Data Register */
<> 144:ef7eb2e8f9f7 58 __I uint32_t rsv0034[7]; /* 0x0034 */
<> 144:ef7eb2e8f9f7 59 __IO uint32_t perform; /* 0x0050 Flash Performance Settings */
<> 144:ef7eb2e8f9f7 60 __I uint32_t rsv0054[11]; /* 0x0054 */
<> 144:ef7eb2e8f9f7 61 __IO uint32_t status; /* 0x0080 Security Status Flags */
<> 144:ef7eb2e8f9f7 62 __I uint32_t rsv0084; /* 0x0084 */
<> 144:ef7eb2e8f9f7 63 __IO uint32_t security; /* 0x0088 Flash Controller Security Settings */
<> 144:ef7eb2e8f9f7 64 __I uint32_t rsv008C[4]; /* 0x008C */
<> 144:ef7eb2e8f9f7 65 __IO uint32_t bypass; /* 0x009C Status Flags for DSB Operations */
<> 144:ef7eb2e8f9f7 66 __IO uint32_t user_option; /* 0x0100 Used to set DSB Access code and Auto-Lock in info block */
<> 144:ef7eb2e8f9f7 67 __I uint32_t rsv0104[15]; /* 0x0104 */
<> 144:ef7eb2e8f9f7 68 __IO uint32_t ctrl2; /* 0x0140 Flash Control Register 2 */
<> 144:ef7eb2e8f9f7 69 __IO uint32_t intfl1; /* 0x0144 Interrupt Flags Register 1 */
<> 144:ef7eb2e8f9f7 70 __IO uint32_t inten1; /* 0x0148 Interrupt Enable/Disable Register 1 */
<> 144:ef7eb2e8f9f7 71 __I uint32_t rsv014C; /* 0x014C */
<> 144:ef7eb2e8f9f7 72 __IO uint32_t disable_xr0; /* 0x0150 Disable Flash Page Exec/Read Register 0 */
<> 144:ef7eb2e8f9f7 73 __IO uint32_t disable_xr1; /* 0x0154 Disable Flash Page Exec/Read Register 1 */
<> 144:ef7eb2e8f9f7 74 __IO uint32_t disable_xr2; /* 0x0158 Disable Flash Page Exec/Read Register 2 */
<> 144:ef7eb2e8f9f7 75 __IO uint32_t disable_xr3; /* 0x015C Disable Flash Page Exec/Read Register 3 */
<> 144:ef7eb2e8f9f7 76 __IO uint32_t disable_we0; /* 0x0160 Disable Flash Page Write/Erase Register 0 */
<> 144:ef7eb2e8f9f7 77 __IO uint32_t disable_we1; /* 0x0164 Disable Flash Page Write/Erase Register 1 */
<> 144:ef7eb2e8f9f7 78 __IO uint32_t disable_we2; /* 0x0168 Disable Flash Page Write/Erase Register 2 */
<> 144:ef7eb2e8f9f7 79 __IO uint32_t disable_we3; /* 0x016C Disable Flash Page Write/Erase Register 3 */
<> 144:ef7eb2e8f9f7 80 } mxc_flc_regs_t;
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 /*
<> 144:ef7eb2e8f9f7 83 Register offsets for module FLC.
<> 144:ef7eb2e8f9f7 84 */
<> 144:ef7eb2e8f9f7 85 #define MXC_R_FLC_OFFS_FADDR ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 86 #define MXC_R_FLC_OFFS_FCKDIV ((uint32_t)0x00000004UL)
<> 144:ef7eb2e8f9f7 87 #define MXC_R_FLC_OFFS_CTRL ((uint32_t)0x00000008UL)
<> 144:ef7eb2e8f9f7 88 #define MXC_R_FLC_OFFS_INTR ((uint32_t)0x00000024UL)
<> 144:ef7eb2e8f9f7 89 #define MXC_R_FLC_OFFS_FDATA ((uint32_t)0x00000030UL)
<> 144:ef7eb2e8f9f7 90 #define MXC_R_FLC_OFFS_PERFORM ((uint32_t)0x00000050UL)
<> 144:ef7eb2e8f9f7 91 #define MXC_R_FLC_OFFS_STATUS ((uint32_t)0x00000080UL)
<> 144:ef7eb2e8f9f7 92 #define MXC_R_FLC_OFFS_SECURITY ((uint32_t)0x00000088UL)
<> 144:ef7eb2e8f9f7 93 #define MXC_R_FLC_OFFS_BYPASS ((uint32_t)0x0000009CUL)
<> 144:ef7eb2e8f9f7 94 #define MXC_R_FLC_OFFS_USER_OPTION ((uint32_t)0x00000100UL)
<> 144:ef7eb2e8f9f7 95 #define MXC_R_FLC_OFFS_CTRL2 ((uint32_t)0x00000140UL)
<> 144:ef7eb2e8f9f7 96 #define MXC_R_FLC_OFFS_INTFL1 ((uint32_t)0x00000144UL)
<> 144:ef7eb2e8f9f7 97 #define MXC_R_FLC_OFFS_INTEN1 ((uint32_t)0x00000148UL)
<> 144:ef7eb2e8f9f7 98 #define MXC_R_FLC_OFFS_DISABLE_XR0 ((uint32_t)0x00000150UL)
<> 144:ef7eb2e8f9f7 99 #define MXC_R_FLC_OFFS_DISABLE_XR1 ((uint32_t)0x00000154UL)
<> 144:ef7eb2e8f9f7 100 #define MXC_R_FLC_OFFS_DISABLE_XR2 ((uint32_t)0x00000158UL)
<> 144:ef7eb2e8f9f7 101 #define MXC_R_FLC_OFFS_DISABLE_XR3 ((uint32_t)0x0000015CUL)
<> 144:ef7eb2e8f9f7 102 #define MXC_R_FLC_OFFS_DISABLE_WE0 ((uint32_t)0x00000160UL)
<> 144:ef7eb2e8f9f7 103 #define MXC_R_FLC_OFFS_DISABLE_WE1 ((uint32_t)0x00000164UL)
<> 144:ef7eb2e8f9f7 104 #define MXC_R_FLC_OFFS_DISABLE_WE2 ((uint32_t)0x00000168UL)
<> 144:ef7eb2e8f9f7 105 #define MXC_R_FLC_OFFS_DISABLE_WE3 ((uint32_t)0x0000016CUL)
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 #define MXC_V_FLC_ERASE_CODE_PAGE_ERASE ((uint8_t)0x55)
<> 144:ef7eb2e8f9f7 108 #define MXC_V_FLC_ERASE_CODE_MASS_ERASE ((uint8_t)0xAA)
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 #define MXC_V_FLC_FLSH_UNLOCK_KEY ((uint8_t)0x2)
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 /*
<> 144:ef7eb2e8f9f7 113 Field positions and masks for module FLC.
<> 144:ef7eb2e8f9f7 114 */
<> 144:ef7eb2e8f9f7 115 #define MXC_F_FLC_FADDR_FADDR_POS 0
<> 144:ef7eb2e8f9f7 116 #define MXC_F_FLC_FADDR_FADDR ((uint32_t)(0x0003FFFFUL << MXC_F_FLC_FADDR_FADDR_POS))
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 #define MXC_F_FLC_FCKDIV_FCKDIV_POS 0
<> 144:ef7eb2e8f9f7 119 #define MXC_F_FLC_FCKDIV_FCKDIV ((uint32_t)(0x0000001FUL << MXC_F_FLC_FCKDIV_FCKDIV_POS))
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 #define MXC_F_FLC_CTRL_WRITE_POS 0
<> 144:ef7eb2e8f9f7 122 #define MXC_F_FLC_CTRL_WRITE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_POS))
<> 144:ef7eb2e8f9f7 123 #define MXC_F_FLC_CTRL_MASS_ERASE_POS 1
<> 144:ef7eb2e8f9f7 124 #define MXC_F_FLC_CTRL_MASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_MASS_ERASE_POS))
<> 144:ef7eb2e8f9f7 125 #define MXC_F_FLC_CTRL_PAGE_ERASE_POS 2
<> 144:ef7eb2e8f9f7 126 #define MXC_F_FLC_CTRL_PAGE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS))
<> 144:ef7eb2e8f9f7 127 #define MXC_F_FLC_CTRL_ERASE_CODE_POS 8
<> 144:ef7eb2e8f9f7 128 #define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS))
<> 144:ef7eb2e8f9f7 129 #define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS 16
<> 144:ef7eb2e8f9f7 130 #define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS))
<> 144:ef7eb2e8f9f7 131 #define MXC_F_FLC_CTRL_WRITE_ENABLE_POS 17
<> 144:ef7eb2e8f9f7 132 #define MXC_F_FLC_CTRL_WRITE_ENABLE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_ENABLE_POS))
<> 144:ef7eb2e8f9f7 133 #define MXC_F_FLC_CTRL_PENDING_POS 24
<> 144:ef7eb2e8f9f7 134 #define MXC_F_FLC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PENDING_POS))
<> 144:ef7eb2e8f9f7 135 #define MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS 25
<> 144:ef7eb2e8f9f7 136 #define MXC_F_FLC_CTRL_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS))
<> 144:ef7eb2e8f9f7 137 #define MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS 27
<> 144:ef7eb2e8f9f7 138 #define MXC_F_FLC_CTRL_AUTO_INCRE_MODE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS))
<> 144:ef7eb2e8f9f7 139 #define MXC_F_FLC_CTRL_FLSH_UNLOCK_POS 28
<> 144:ef7eb2e8f9f7 140 #define MXC_F_FLC_CTRL_FLSH_UNLOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS))
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 #define MXC_F_FLC_INTR_FLASH_OP_DONE_IF_POS 0
<> 144:ef7eb2e8f9f7 143 #define MXC_F_FLC_INTR_FLASH_OP_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_DONE_IF_POS))
<> 144:ef7eb2e8f9f7 144 #define MXC_F_FLC_INTR_FLASH_OP_FAILED_IF_POS 1
<> 144:ef7eb2e8f9f7 145 #define MXC_F_FLC_INTR_FLASH_OP_FAILED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_FAILED_IF_POS))
<> 144:ef7eb2e8f9f7 146 #define MXC_F_FLC_INTR_FLASH_OP_DONE_IE_POS 9
<> 144:ef7eb2e8f9f7 147 #define MXC_F_FLC_INTR_FLASH_OP_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_DONE_IE_POS))
<> 144:ef7eb2e8f9f7 148 #define MXC_F_FLC_INTR_FLASH_OP_FAILED_IE_POS 10
<> 144:ef7eb2e8f9f7 149 #define MXC_F_FLC_INTR_FLASH_OP_FAILED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_FAILED_IE_POS))
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 #define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS 8
<> 144:ef7eb2e8f9f7 152 #define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS))
<> 144:ef7eb2e8f9f7 153 #define MXC_F_FLC_PERFORM_DELAY_SE_EN_POS 0
<> 144:ef7eb2e8f9f7 154 #define MXC_F_FLC_PERFORM_DELAY_SE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_DELAY_SE_EN_POS))
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 #define MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW_POS 0
<> 144:ef7eb2e8f9f7 157 #define MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW_POS))
<> 144:ef7eb2e8f9f7 158 #define MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC_POS 1
<> 144:ef7eb2e8f9f7 159 #define MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC_POS))
<> 144:ef7eb2e8f9f7 160 #define MXC_F_FLC_STATUS_AUTO_LOCK_POS 3
<> 144:ef7eb2e8f9f7 161 #define MXC_F_FLC_STATUS_AUTO_LOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_AUTO_LOCK_POS))
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 #define MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS 0
<> 144:ef7eb2e8f9f7 164 #define MXC_F_FLC_SECURITY_DEBUG_DISABLE ((uint32_t)(0x000000FFUL << MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS))
<> 144:ef7eb2e8f9f7 165 #define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS 8
<> 144:ef7eb2e8f9f7 166 #define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS))
<> 144:ef7eb2e8f9f7 167 #define MXC_F_FLC_SECURITY_SECURITY_LOCK_POS 31
<> 144:ef7eb2e8f9f7 168 #define MXC_F_FLC_SECURITY_SECURITY_LOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_SECURITY_SECURITY_LOCK_POS))
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS 0
<> 144:ef7eb2e8f9f7 171 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS))
<> 144:ef7eb2e8f9f7 172 #define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS 1
<> 144:ef7eb2e8f9f7 173 #define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS))
<> 144:ef7eb2e8f9f7 174 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS 2
<> 144:ef7eb2e8f9f7 175 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS))
<> 144:ef7eb2e8f9f7 176 #define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS 3
<> 144:ef7eb2e8f9f7 177 #define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS))
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 #define MXC_F_FLC_CTRL2_FLASH_LVE_POS 0
<> 144:ef7eb2e8f9f7 180 #define MXC_F_FLC_CTRL2_FLASH_LVE ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_FLASH_LVE_POS))
<> 144:ef7eb2e8f9f7 181 #define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS 8
<> 144:ef7eb2e8f9f7 182 #define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS))
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 #define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS 0
<> 144:ef7eb2e8f9f7 185 #define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS))
<> 144:ef7eb2e8f9f7 186 #define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS 1
<> 144:ef7eb2e8f9f7 187 #define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS))
<> 144:ef7eb2e8f9f7 188 #define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS 2
<> 144:ef7eb2e8f9f7 189 #define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS))
<> 144:ef7eb2e8f9f7 190 #define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS 3
<> 144:ef7eb2e8f9f7 191 #define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS))
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 #define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS 0
<> 144:ef7eb2e8f9f7 194 #define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS))
<> 144:ef7eb2e8f9f7 195 #define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS 1
<> 144:ef7eb2e8f9f7 196 #define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS))
<> 144:ef7eb2e8f9f7 197 #define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS 2
<> 144:ef7eb2e8f9f7 198 #define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS))
<> 144:ef7eb2e8f9f7 199 #define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS 3
<> 144:ef7eb2e8f9f7 200 #define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS))
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 203 }
<> 144:ef7eb2e8f9f7 204 #endif
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /**
<> 144:ef7eb2e8f9f7 207 * @}
<> 144:ef7eb2e8f9f7 208 */
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 #endif /* _MXC_FLC_REGS_H_ */