Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Maxim/TARGET_MAX32610/dac_regs.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #ifndef _MXC_DAC_REGS_H
<> 144:ef7eb2e8f9f7 35 #define _MXC_DAC_REGS_H
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 38 extern "C" {
<> 144:ef7eb2e8f9f7 39 #endif
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #include <stdint.h>
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /**
<> 144:ef7eb2e8f9f7 44 * @file dac_regs.h
<> 144:ef7eb2e8f9f7 45 * @addtogroup dac DAC
<> 144:ef7eb2e8f9f7 46 * @{
<> 144:ef7eb2e8f9f7 47 */
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /**
<> 144:ef7eb2e8f9f7 50 * @brief Defines the DAC Operational Modes.
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52 typedef enum {
<> 144:ef7eb2e8f9f7 53 /** DAC OpMode FIFO */
<> 144:ef7eb2e8f9f7 54 MXC_E_DAC_OP_MODE_FIFO = 0,
<> 144:ef7eb2e8f9f7 55 /** DAC OpMode Sample Count */
<> 144:ef7eb2e8f9f7 56 MXC_E_DAC_OP_MODE_DACSMPLCNT,
<> 144:ef7eb2e8f9f7 57 /** DAC OpMode DAC_REG Control */
<> 144:ef7eb2e8f9f7 58 MXC_E_DAC_OP_MODE_DAC_REG,
<> 144:ef7eb2e8f9f7 59 /** DAC OpMode Continuous */
<> 144:ef7eb2e8f9f7 60 MXC_E_DAC_OP_MODE_CONTINUOUS
<> 144:ef7eb2e8f9f7 61 } mxc_dac_op_mode_t;
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /**
<> 144:ef7eb2e8f9f7 64 * @brief Defines the DAC Interpolation Options.
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 typedef enum {
<> 144:ef7eb2e8f9f7 67 /** DAC Interpolation is Disabled */
<> 144:ef7eb2e8f9f7 68 MXC_E_DAC_INTERP_MODE_DISABLED = 0,
<> 144:ef7eb2e8f9f7 69 /** DAC Interpolation 2:1 */
<> 144:ef7eb2e8f9f7 70 MXC_E_DAC_INTERP_MODE_2_TO_1,
<> 144:ef7eb2e8f9f7 71 /** DAC Interpolation 4:1 */
<> 144:ef7eb2e8f9f7 72 MXC_E_DAC_INTERP_MODE_4_TO_1,
<> 144:ef7eb2e8f9f7 73 /** DAC Interpolation 8:1 */
<> 144:ef7eb2e8f9f7 74 MXC_E_DAC_INTERP_MODE_8_TO_1
<> 144:ef7eb2e8f9f7 75 } mxc_dac_interp_mode_t;
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 /**
<> 144:ef7eb2e8f9f7 78 * @brief Defines the DAC Start Modes.
<> 144:ef7eb2e8f9f7 79 */
<> 144:ef7eb2e8f9f7 80 typedef enum {
<> 144:ef7eb2e8f9f7 81 /** Start on FIFO Not Empty */
<> 144:ef7eb2e8f9f7 82 MXC_E_DAC_START_MODE_FIFO_NOT_EMPTY = 0,
<> 144:ef7eb2e8f9f7 83 /** Start on ADC generated Start Strobe */
<> 144:ef7eb2e8f9f7 84 MXC_E_DAC_START_MODE_ADC_STROBE,
<> 144:ef7eb2e8f9f7 85 /** Start on DAC generated Start Strobe */
<> 144:ef7eb2e8f9f7 86 MXC_E_DAC_START_MODE_DAC_STROBE
<> 144:ef7eb2e8f9f7 87 } mxc_dac_start_mode_t;
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 /* Offset Register Description
<> 144:ef7eb2e8f9f7 90 ====== ================================================== */
<> 144:ef7eb2e8f9f7 91 typedef struct {
<> 144:ef7eb2e8f9f7 92 __IO uint32_t ctrl0; /* 0x0000 DAC Control Register 0 */
<> 144:ef7eb2e8f9f7 93 __IO uint32_t rate; /* 0x0004 DAC Output Rate Control */
<> 144:ef7eb2e8f9f7 94 __IO uint32_t ctrl1_int; /* 0x0008 DAC Control Register 1, Interrupt Flags and Enable */
<> 144:ef7eb2e8f9f7 95 __IO uint32_t reg; /* 0x000C DAC Data Register */
<> 144:ef7eb2e8f9f7 96 __IO uint32_t trm; /* 0x0010 DAC Trim Register */
<> 144:ef7eb2e8f9f7 97 } mxc_dac_regs_t;
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 /* Offset Register Description
<> 144:ef7eb2e8f9f7 100 ====== ================================================== */
<> 144:ef7eb2e8f9f7 101 typedef struct {
<> 144:ef7eb2e8f9f7 102 union {
<> 144:ef7eb2e8f9f7 103 __IO uint8_t output_8; /* 0x0000 Write to push values to DAC output FIFO */
<> 144:ef7eb2e8f9f7 104 __IO uint16_t output_16; /* 0x0000 Write to push values to DAC output FIFO */
<> 144:ef7eb2e8f9f7 105 };
<> 144:ef7eb2e8f9f7 106 } mxc_dac_fifo_regs_t;
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 /*
<> 144:ef7eb2e8f9f7 109 Register offsets for module DAC12.
<> 144:ef7eb2e8f9f7 110 */
<> 144:ef7eb2e8f9f7 111 #define MXC_R_DAC_OFFS_CTRL0 ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 112 #define MXC_R_DAC_OFFS_RATE ((uint32_t)0x00000004UL)
<> 144:ef7eb2e8f9f7 113 #define MXC_R_DAC_OFFS_CTRL1_INT ((uint32_t)0x00000008UL)
<> 144:ef7eb2e8f9f7 114 #define MXC_R_DAC_FIFO_OFFS_OUTPUT ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /*
<> 144:ef7eb2e8f9f7 117 Field positions and masks for module DAC.
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119 #define MXC_F_DAC_CTRL0_FIFO_AE_CNT_POS 0
<> 144:ef7eb2e8f9f7 120 #define MXC_F_DAC_CTRL0_FIFO_AE_CNT ((uint32_t)(0x0000000FUL << MXC_F_DAC_CTRL0_FIFO_AE_CNT_POS))
<> 144:ef7eb2e8f9f7 121 #define MXC_F_DAC_CTRL0_FIFO_ALMOST_FULL_POS 5
<> 144:ef7eb2e8f9f7 122 #define MXC_F_DAC_CTRL0_FIFO_ALMOST_FULL ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_FIFO_ALMOST_FULL_POS))
<> 144:ef7eb2e8f9f7 123 #define MXC_F_DAC_CTRL0_FIFO_EMPTY_POS 6
<> 144:ef7eb2e8f9f7 124 #define MXC_F_DAC_CTRL0_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_FIFO_EMPTY_POS))
<> 144:ef7eb2e8f9f7 125 #define MXC_F_DAC_CTRL0_FIFO_ALMOST_EMPTY_POS 7
<> 144:ef7eb2e8f9f7 126 #define MXC_F_DAC_CTRL0_FIFO_ALMOST_EMPTY ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_FIFO_ALMOST_EMPTY_POS))
<> 144:ef7eb2e8f9f7 127 #define MXC_F_DAC_CTRL0_INTERP_MODE_POS 8
<> 144:ef7eb2e8f9f7 128 #define MXC_F_DAC_CTRL0_INTERP_MODE ((uint32_t)(0x00000007UL << MXC_F_DAC_CTRL0_INTERP_MODE_POS))
<> 144:ef7eb2e8f9f7 129 #define MXC_F_DAC_CTRL0_FIFO_AF_CNT_POS 12
<> 144:ef7eb2e8f9f7 130 #define MXC_F_DAC_CTRL0_FIFO_AF_CNT ((uint32_t)(0x0000000FUL << MXC_F_DAC_CTRL0_FIFO_AF_CNT_POS))
<> 144:ef7eb2e8f9f7 131 #define MXC_F_DAC_CTRL0_START_MODE_POS 16
<> 144:ef7eb2e8f9f7 132 #define MXC_F_DAC_CTRL0_START_MODE ((uint32_t)(0x00000003UL << MXC_F_DAC_CTRL0_START_MODE_POS))
<> 144:ef7eb2e8f9f7 133 #define MXC_F_DAC_CTRL0_CPU_START_POS 20
<> 144:ef7eb2e8f9f7 134 #define MXC_F_DAC_CTRL0_CPU_START ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_CPU_START_POS))
<> 144:ef7eb2e8f9f7 135 #define MXC_F_DAC_CTRL0_OP_MODE_POS 24
<> 144:ef7eb2e8f9f7 136 #define MXC_F_DAC_CTRL0_OP_MODE ((uint32_t)(0x00000003UL << MXC_F_DAC_CTRL0_OP_MODE_POS))
<> 144:ef7eb2e8f9f7 137 #define MXC_F_DAC_CTRL0_POWER_MODE_1_0_POS 26
<> 144:ef7eb2e8f9f7 138 #define MXC_F_DAC_CTRL0_POWER_MODE_1_0 ((uint32_t)(0x00000003UL << MXC_F_DAC_CTRL0_POWER_MODE_1_0_POS))
<> 144:ef7eb2e8f9f7 139 #define MXC_F_DAC_CTRL0_POWER_ON_POS 28
<> 144:ef7eb2e8f9f7 140 #define MXC_F_DAC_CTRL0_POWER_ON ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_POWER_ON_POS))
<> 144:ef7eb2e8f9f7 141 #define MXC_F_DAC_CTRL0_CLOCK_GATE_EN_POS 29
<> 144:ef7eb2e8f9f7 142 #define MXC_F_DAC_CTRL0_CLOCK_GATE_EN ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_CLOCK_GATE_EN_POS))
<> 144:ef7eb2e8f9f7 143 #define MXC_F_DAC_CTRL0_POWER_MODE_2_POS 30
<> 144:ef7eb2e8f9f7 144 #define MXC_F_DAC_CTRL0_POWER_MODE_2 ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_POWER_MODE_2_POS))
<> 144:ef7eb2e8f9f7 145 #define MXC_F_DAC_CTRL0_RESET_POS 31
<> 144:ef7eb2e8f9f7 146 #define MXC_F_DAC_CTRL0_RESET ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_RESET_POS))
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 #define MXC_F_DAC_RATE_RATE_CNT_POS 0
<> 144:ef7eb2e8f9f7 149 #define MXC_F_DAC_RATE_RATE_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_DAC_RATE_RATE_CNT_POS))
<> 144:ef7eb2e8f9f7 150 #define MXC_F_DAC_RATE_SAMPLE_CNT_POS 16
<> 144:ef7eb2e8f9f7 151 #define MXC_F_DAC_RATE_SAMPLE_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_DAC_RATE_SAMPLE_CNT_POS))
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 #define MXC_F_DAC_CTRL1_INT_OUT_DONE_IF_POS 0
<> 144:ef7eb2e8f9f7 154 #define MXC_F_DAC_CTRL1_INT_OUT_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_OUT_DONE_IF_POS))
<> 144:ef7eb2e8f9f7 155 #define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IF_POS 1
<> 144:ef7eb2e8f9f7 156 #define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IF ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_UNDERFLOW_IF_POS))
<> 144:ef7eb2e8f9f7 157 #define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IF_POS 2
<> 144:ef7eb2e8f9f7 158 #define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IF ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IF_POS))
<> 144:ef7eb2e8f9f7 159 #define MXC_F_DAC_CTRL1_INT_UNDERFLOW_POS 3
<> 144:ef7eb2e8f9f7 160 #define MXC_F_DAC_CTRL1_INT_UNDERFLOW ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_UNDERFLOW_POS))
<> 144:ef7eb2e8f9f7 161 #define MXC_F_DAC_CTRL1_INT_OUT_DONE_IE_POS 16
<> 144:ef7eb2e8f9f7 162 #define MXC_F_DAC_CTRL1_INT_OUT_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_OUT_DONE_IE_POS))
<> 144:ef7eb2e8f9f7 163 #define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IE_POS 17
<> 144:ef7eb2e8f9f7 164 #define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_UNDERFLOW_IE_POS))
<> 144:ef7eb2e8f9f7 165 #define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IE_POS 18
<> 144:ef7eb2e8f9f7 166 #define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IE_POS))
<> 144:ef7eb2e8f9f7 167 #define MXC_F_DAC_CTRL1_INT_AHB_CG_DISABLE_POS 28
<> 144:ef7eb2e8f9f7 168 #define MXC_F_DAC_CTRL1_INT_AHB_CG_DISABLE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_AHB_CG_DISABLE_POS))
<> 144:ef7eb2e8f9f7 169 #define MXC_F_DAC_CTRL1_INT_APB_CG_DISABLE_POS 29
<> 144:ef7eb2e8f9f7 170 #define MXC_F_DAC_CTRL1_INT_APB_CG_DISABLE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_APB_CG_DISABLE_POS))
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 173 }
<> 144:ef7eb2e8f9f7 174 #endif
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /**
<> 144:ef7eb2e8f9f7 177 * @}
<> 144:ef7eb2e8f9f7 178 */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 #endif /* _DAC12_REGS_H */