Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Maxim/TARGET_MAX32610/TOOLCHAIN_GCC_ARM/startup_max32610.S@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 .syntax unified
<> 144:ef7eb2e8f9f7 35 .arch armv7-m
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 /* Memory Model
<> 144:ef7eb2e8f9f7 38 The HEAP starts at the end of the DATA section and grows upward.
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 The STACK starts at the end of the RAM and grows downward.
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 The HEAP and stack STACK are only checked at compile time:
<> 144:ef7eb2e8f9f7 43 (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 This is just a check for the bare minimum for the Heap+Stack area before
<> 144:ef7eb2e8f9f7 46 aborting compilation, it is not the run time limit:
<> 144:ef7eb2e8f9f7 47 Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
<> 144:ef7eb2e8f9f7 48 */
<> 144:ef7eb2e8f9f7 49 .section .stack
<> 144:ef7eb2e8f9f7 50 .align 3
<> 144:ef7eb2e8f9f7 51 #ifdef __STACK_SIZE
<> 144:ef7eb2e8f9f7 52 .equ Stack_Size, __STACK_SIZE
<> 144:ef7eb2e8f9f7 53 #else
<> 144:ef7eb2e8f9f7 54 .equ Stack_Size, 0x00001000
<> 144:ef7eb2e8f9f7 55 #endif
<> 144:ef7eb2e8f9f7 56 .globl __StackTop
<> 144:ef7eb2e8f9f7 57 .globl __StackLimit
<> 144:ef7eb2e8f9f7 58 __StackLimit:
<> 144:ef7eb2e8f9f7 59 .space Stack_Size
<> 144:ef7eb2e8f9f7 60 .size __StackLimit, . - __StackLimit
<> 144:ef7eb2e8f9f7 61 __StackTop:
<> 144:ef7eb2e8f9f7 62 .size __StackTop, . - __StackTop
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 .section .heap
<> 144:ef7eb2e8f9f7 65 .align 3
<> 144:ef7eb2e8f9f7 66 #ifdef __HEAP_SIZE
<> 144:ef7eb2e8f9f7 67 .equ Heap_Size, __HEAP_SIZE
<> 144:ef7eb2e8f9f7 68 #else
<> 144:ef7eb2e8f9f7 69 .equ Heap_Size, 0x00000C00
<> 144:ef7eb2e8f9f7 70 #endif
<> 144:ef7eb2e8f9f7 71 .globl __HeapBase
<> 144:ef7eb2e8f9f7 72 .globl __HeapLimit
<> 144:ef7eb2e8f9f7 73 __HeapBase:
<> 144:ef7eb2e8f9f7 74 .space Heap_Size
<> 144:ef7eb2e8f9f7 75 .size __HeapBase, . - __HeapBase
<> 144:ef7eb2e8f9f7 76 __HeapLimit:
<> 144:ef7eb2e8f9f7 77 .size __HeapLimit, . - __HeapLimit
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 .section .isr_vector
<> 144:ef7eb2e8f9f7 80 .align 2
<> 144:ef7eb2e8f9f7 81 .globl __isr_vector
<> 144:ef7eb2e8f9f7 82 __isr_vector:
<> 144:ef7eb2e8f9f7 83 .long __StackTop /* Top of Stack */
<> 144:ef7eb2e8f9f7 84 .long Reset_Handler /* Reset Handler */
<> 144:ef7eb2e8f9f7 85 .long NMI_Handler /* NMI Handler */
<> 144:ef7eb2e8f9f7 86 .long HardFault_Handler /* Hard Fault Handler */
<> 144:ef7eb2e8f9f7 87 .long MemManage_Handler /* MPU Fault Handler */
<> 144:ef7eb2e8f9f7 88 .long BusFault_Handler /* Bus Fault Handler */
<> 144:ef7eb2e8f9f7 89 .long UsageFault_Handler /* Usage Fault Handler */
<> 144:ef7eb2e8f9f7 90 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 91 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 92 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 93 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 94 .long SVC_Handler /* SVCall Handler */
<> 144:ef7eb2e8f9f7 95 .long DebugMon_Handler /* Debug Monitor Handler */
<> 144:ef7eb2e8f9f7 96 .long 0 /* Reserved */
<> 144:ef7eb2e8f9f7 97 .long PendSV_Handler /* PendSV Handler */
<> 144:ef7eb2e8f9f7 98 .long SysTick_Handler /* SysTick Handler */
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /* Externals interrupts */
<> 144:ef7eb2e8f9f7 101 .long UART0_IRQHandler /* 16: 1 UART0 */
<> 144:ef7eb2e8f9f7 102 .long UART1_IRQHandler /* 17: 2 UART1 */
<> 144:ef7eb2e8f9f7 103 .long I2CM0_IRQHandler /* 18: 3 I2C Master 0 */
<> 144:ef7eb2e8f9f7 104 .long I2CS_IRQHandler /* 19: 4 I2C Slave */
<> 144:ef7eb2e8f9f7 105 .long USB_IRQHandler /* 20: 5 USB */
<> 144:ef7eb2e8f9f7 106 .long PMU_IRQHandler /* 21: 6 DMA */
<> 144:ef7eb2e8f9f7 107 .long AFE_IRQHandler /* 22: 7 AFE */
<> 144:ef7eb2e8f9f7 108 .long MAA_IRQHandler /* 23: 8 MAA */
<> 144:ef7eb2e8f9f7 109 .long AES_IRQHandler /* 24: 9 AES */
<> 144:ef7eb2e8f9f7 110 .long SPI0_IRQHandler /* 25:10 SPI0 */
<> 144:ef7eb2e8f9f7 111 .long SPI1_IRQHandler /* 26:11 SPI1 */
<> 144:ef7eb2e8f9f7 112 .long SPI2_IRQHandler /* 27:12 SPI2 */
<> 144:ef7eb2e8f9f7 113 .long TMR0_IRQHandler /* 28:13 Timer32-0 */
<> 144:ef7eb2e8f9f7 114 .long TMR1_IRQHandler /* 29:14 Timer32-1 */
<> 144:ef7eb2e8f9f7 115 .long TMR2_IRQHandler /* 30:15 Timer32-1 */
<> 144:ef7eb2e8f9f7 116 .long TMR3_IRQHandler /* 31:16 Timer32-2 */
<> 144:ef7eb2e8f9f7 117 .long RSVD0_IRQHandler /* 32:17 RSVD */
<> 144:ef7eb2e8f9f7 118 .long RSVD1_IRQHandler /* 33:18 RSVD */
<> 144:ef7eb2e8f9f7 119 .long DAC0_IRQHandler /* 34:19 DAC0 (12-bit DAC) */
<> 144:ef7eb2e8f9f7 120 .long DAC1_IRQHandler /* 35:20 DAC1 (12-bit DAC) */
<> 144:ef7eb2e8f9f7 121 .long DAC2_IRQHandler /* 36:21 DAC2 (8-bit DAC) */
<> 144:ef7eb2e8f9f7 122 .long DAC3_IRQHandler /* 37:22 DAC3 (8-bit DAC) */
<> 144:ef7eb2e8f9f7 123 .long ADC_IRQHandler /* 38:23 ADC */
<> 144:ef7eb2e8f9f7 124 .long FLC_IRQHandler /* 39:24 Flash Controller */
<> 144:ef7eb2e8f9f7 125 .long PWRMAN_IRQHandler /* 40:25 PWRMAN */
<> 144:ef7eb2e8f9f7 126 .long CLKMAN_IRQHandler /* 41:26 CLKMAN */
<> 144:ef7eb2e8f9f7 127 .long RTC0_IRQHandler /* 42:27 RTC INT0 */
<> 144:ef7eb2e8f9f7 128 .long RTC1_IRQHandler /* 43:28 RTC INT1 */
<> 144:ef7eb2e8f9f7 129 .long RTC2_IRQHandler /* 44:29 RTC INT2 */
<> 144:ef7eb2e8f9f7 130 .long RTC3_IRQHandler /* 45:30 RTC INT3 */
<> 144:ef7eb2e8f9f7 131 .long WDT0_IRQHandler /* 46:31 WATCHDOG0 */
<> 144:ef7eb2e8f9f7 132 .long WDT0_P_IRQHandler /* 47:32 WATCHDOG0 PRE-WINDOW */
<> 144:ef7eb2e8f9f7 133 .long WDT1_IRQHandler /* 48:33 WATCHDOG1 */
<> 144:ef7eb2e8f9f7 134 .long WDT1_P_IRQHandler /* 49:34 WATCHDOG1 PRE-WINDOW */
<> 144:ef7eb2e8f9f7 135 .long GPIO_P0_IRQHandler /* 50:35 GPIO Port 0 */
<> 144:ef7eb2e8f9f7 136 .long GPIO_P1_IRQHandler /* 51:36 GPIO Port 1 */
<> 144:ef7eb2e8f9f7 137 .long GPIO_P2_IRQHandler /* 52:37 GPIO Port 2 */
<> 144:ef7eb2e8f9f7 138 .long GPIO_P3_IRQHandler /* 53:38 GPIO Port 3 */
<> 144:ef7eb2e8f9f7 139 .long GPIO_P4_IRQHandler /* 54:39 GPIO Port 4 */
<> 144:ef7eb2e8f9f7 140 .long GPIO_P5_IRQHandler /* 55:40 GPIO Port 5 */
<> 144:ef7eb2e8f9f7 141 .long GPIO_P6_IRQHandler /* 56:41 GPIO Port 6 */
<> 144:ef7eb2e8f9f7 142 .long GPIO_P7_IRQHandler /* 57:42 GPIO Port 7 */
<> 144:ef7eb2e8f9f7 143 .long TMR16_0_IRQHandler /* 58:43 Timer16-s0 */
<> 144:ef7eb2e8f9f7 144 .long TMR16_1_IRQHandler /* 59:44 Timer16-s1 */
<> 144:ef7eb2e8f9f7 145 .long TMR16_2_IRQHandler /* 60:45 Timer16-s2 */
<> 144:ef7eb2e8f9f7 146 .long TMR16_3_IRQHandler /* 61:46 Timer16-s3 */
<> 144:ef7eb2e8f9f7 147 .long I2CM1_IRQHandler /* 62:47 I2C Master 1 */
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 .text
<> 144:ef7eb2e8f9f7 151 .thumb
<> 144:ef7eb2e8f9f7 152 .thumb_func
<> 144:ef7eb2e8f9f7 153 .align 2
<> 144:ef7eb2e8f9f7 154 .globl Reset_Handler
<> 144:ef7eb2e8f9f7 155 .type Reset_Handler, %function
<> 144:ef7eb2e8f9f7 156 Reset_Handler:
<> 144:ef7eb2e8f9f7 157 /* Loop to copy data from read only memory to RAM. The ranges
<> 144:ef7eb2e8f9f7 158 * of copy from/to are specified by following symbols evaluated in
<> 144:ef7eb2e8f9f7 159 * linker script.
<> 144:ef7eb2e8f9f7 160 * __etext: End of code section, i.e., begin of data sections to copy from.
<> 144:ef7eb2e8f9f7 161 * __data_start__/__data_end__: RAM address range that data should be
<> 144:ef7eb2e8f9f7 162 * copied to. Both must be aligned to 4 bytes boundary. */
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 ldr r1, =__etext
<> 144:ef7eb2e8f9f7 165 ldr r2, =__data_start__
<> 144:ef7eb2e8f9f7 166 ldr r3, =__data_end__
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 .Lflash_to_ram_loop:
<> 144:ef7eb2e8f9f7 169 cmp r2, r3
<> 144:ef7eb2e8f9f7 170 ittt lt
<> 144:ef7eb2e8f9f7 171 ldrlt r0, [r1], #4
<> 144:ef7eb2e8f9f7 172 strlt r0, [r2], #4
<> 144:ef7eb2e8f9f7 173 blt .Lflash_to_ram_loop
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 .Lflash_to_ram_loop_end:
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 ldr r0, =SystemInit
<> 144:ef7eb2e8f9f7 178 blx r0
<> 144:ef7eb2e8f9f7 179 ldr r0, =_start
<> 144:ef7eb2e8f9f7 180 bx r0
<> 144:ef7eb2e8f9f7 181 .pool
<> 144:ef7eb2e8f9f7 182 .size Reset_Handler, . - Reset_Handler
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 .text
<> 144:ef7eb2e8f9f7 185 /* Macro to define default handlers. Default handler
<> 144:ef7eb2e8f9f7 186 * will be weak symbol and just dead loops. They can be
<> 144:ef7eb2e8f9f7 187 * overwritten by other handlers */
<> 144:ef7eb2e8f9f7 188 .macro def_default_handler handler_name
<> 144:ef7eb2e8f9f7 189 .align 1
<> 144:ef7eb2e8f9f7 190 .thumb_func
<> 144:ef7eb2e8f9f7 191 .weak \handler_name
<> 144:ef7eb2e8f9f7 192 .type \handler_name, %function
<> 144:ef7eb2e8f9f7 193 \handler_name :
<> 144:ef7eb2e8f9f7 194 b .
<> 144:ef7eb2e8f9f7 195 .size \handler_name, . - \handler_name
<> 144:ef7eb2e8f9f7 196 .endm
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 def_default_handler NMI_Handler
<> 144:ef7eb2e8f9f7 199 def_default_handler HardFault_Handler
<> 144:ef7eb2e8f9f7 200 def_default_handler MemManage_Handler
<> 144:ef7eb2e8f9f7 201 def_default_handler BusFault_Handler
<> 144:ef7eb2e8f9f7 202 def_default_handler UsageFault_Handler
<> 144:ef7eb2e8f9f7 203 def_default_handler SVC_Handler
<> 144:ef7eb2e8f9f7 204 def_default_handler DebugMon_Handler
<> 144:ef7eb2e8f9f7 205 def_default_handler PendSV_Handler
<> 144:ef7eb2e8f9f7 206 def_default_handler SysTick_Handler
<> 144:ef7eb2e8f9f7 207 def_default_handler Default_Handler
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 .macro def_irq_default_handler handler_name
<> 144:ef7eb2e8f9f7 210 .weak \handler_name
<> 144:ef7eb2e8f9f7 211 .set \handler_name, Default_Handler
<> 144:ef7eb2e8f9f7 212 .endm
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 def_irq_default_handler UART0_IRQHandler /* 16: 1 UART0 */
<> 144:ef7eb2e8f9f7 215 def_irq_default_handler UART1_IRQHandler /* 17: 2 UART1 */
<> 144:ef7eb2e8f9f7 216 def_irq_default_handler I2CM0_IRQHandler /* 18: 3 I2C Master 0 */
<> 144:ef7eb2e8f9f7 217 def_irq_default_handler I2CS_IRQHandler /* 19: 4 I2C Slave */
<> 144:ef7eb2e8f9f7 218 def_irq_default_handler USB_IRQHandler /* 20: 5 USB */
<> 144:ef7eb2e8f9f7 219 def_irq_default_handler PMU_IRQHandler /* 21: 6 DMA */
<> 144:ef7eb2e8f9f7 220 def_irq_default_handler AFE_IRQHandler /* 22: 7 AFE */
<> 144:ef7eb2e8f9f7 221 def_irq_default_handler MAA_IRQHandler /* 23: 8 MAA */
<> 144:ef7eb2e8f9f7 222 def_irq_default_handler AES_IRQHandler /* 24: 9 AES */
<> 144:ef7eb2e8f9f7 223 def_irq_default_handler SPI0_IRQHandler /* 25:10 SPI0 */
<> 144:ef7eb2e8f9f7 224 def_irq_default_handler SPI1_IRQHandler /* 26:11 SPI1 */
<> 144:ef7eb2e8f9f7 225 def_irq_default_handler SPI2_IRQHandler /* 27:12 SPI2 */
<> 144:ef7eb2e8f9f7 226 def_irq_default_handler TMR0_IRQHandler /* 28:13 Timer32-0 */
<> 144:ef7eb2e8f9f7 227 def_irq_default_handler TMR1_IRQHandler /* 29:14 Timer32-1 */
<> 144:ef7eb2e8f9f7 228 def_irq_default_handler TMR2_IRQHandler /* 30:15 Timer32-1 */
<> 144:ef7eb2e8f9f7 229 def_irq_default_handler TMR3_IRQHandler /* 31:16 Timer32-2 */
<> 144:ef7eb2e8f9f7 230 def_irq_default_handler RSVD0_IRQHandler /* 32:17 RSVD */
<> 144:ef7eb2e8f9f7 231 def_irq_default_handler RSVD1_IRQHandler /* 33:18 RSVD */
<> 144:ef7eb2e8f9f7 232 def_irq_default_handler DAC0_IRQHandler /* 34:19 DAC0 (12-bit DAC) */
<> 144:ef7eb2e8f9f7 233 def_irq_default_handler DAC1_IRQHandler /* 35:20 DAC1 (12-bit DAC) */
<> 144:ef7eb2e8f9f7 234 def_irq_default_handler DAC2_IRQHandler /* 36:21 DAC2 (8-bit DAC) */
<> 144:ef7eb2e8f9f7 235 def_irq_default_handler DAC3_IRQHandler /* 37:22 DAC3 (8-bit DAC) */
<> 144:ef7eb2e8f9f7 236 def_irq_default_handler ADC_IRQHandler /* 38:23 ADC */
<> 144:ef7eb2e8f9f7 237 def_irq_default_handler FLC_IRQHandler /* 39:24 Flash Controller */
<> 144:ef7eb2e8f9f7 238 def_irq_default_handler PWRMAN_IRQHandler /* 40:25 PWRMAN */
<> 144:ef7eb2e8f9f7 239 def_irq_default_handler CLKMAN_IRQHandler /* 41:26 CLKMAN */
<> 144:ef7eb2e8f9f7 240 def_irq_default_handler RTC0_IRQHandler /* 42:27 RTC INT0 */
<> 144:ef7eb2e8f9f7 241 def_irq_default_handler RTC1_IRQHandler /* 43:28 RTC INT1 */
<> 144:ef7eb2e8f9f7 242 def_irq_default_handler RTC2_IRQHandler /* 44:29 RTC INT2 */
<> 144:ef7eb2e8f9f7 243 def_irq_default_handler RTC3_IRQHandler /* 45:30 RTC INT3 */
<> 144:ef7eb2e8f9f7 244 def_irq_default_handler WDT0_IRQHandler /* 46:31 WATCHDOG0 */
<> 144:ef7eb2e8f9f7 245 def_irq_default_handler WDT0_P_IRQHandler /* 47:32 WATCHDOG0 PRE-WINDOW */
<> 144:ef7eb2e8f9f7 246 def_irq_default_handler WDT1_IRQHandler /* 48:33 WATCHDOG1 */
<> 144:ef7eb2e8f9f7 247 def_irq_default_handler WDT1_P_IRQHandler /* 49:34 WATCHDOG1 PRE-WINDOW */
<> 144:ef7eb2e8f9f7 248 def_irq_default_handler GPIO_P0_IRQHandler /* 50:35 GPIO Port 0 */
<> 144:ef7eb2e8f9f7 249 def_irq_default_handler GPIO_P1_IRQHandler /* 51:36 GPIO Port 1 */
<> 144:ef7eb2e8f9f7 250 def_irq_default_handler GPIO_P2_IRQHandler /* 52:37 GPIO Port 2 */
<> 144:ef7eb2e8f9f7 251 def_irq_default_handler GPIO_P3_IRQHandler /* 53:38 GPIO Port 3 */
<> 144:ef7eb2e8f9f7 252 def_irq_default_handler GPIO_P4_IRQHandler /* 54:39 GPIO Port 4 */
<> 144:ef7eb2e8f9f7 253 def_irq_default_handler GPIO_P5_IRQHandler /* 55:40 GPIO Port 5 */
<> 144:ef7eb2e8f9f7 254 def_irq_default_handler GPIO_P6_IRQHandler /* 56:41 GPIO Port 6 */
<> 144:ef7eb2e8f9f7 255 def_irq_default_handler GPIO_P7_IRQHandler /* 57:42 GPIO Port 7 */
<> 144:ef7eb2e8f9f7 256 def_irq_default_handler TMR16_0_IRQHandler /* 58:43 Timer16-s0 */
<> 144:ef7eb2e8f9f7 257 def_irq_default_handler TMR16_1_IRQHandler /* 59:44 Timer16-s1 */
<> 144:ef7eb2e8f9f7 258 def_irq_default_handler TMR16_2_IRQHandler /* 60:45 Timer16-s2 */
<> 144:ef7eb2e8f9f7 259 def_irq_default_handler TMR16_3_IRQHandler /* 61:46 Timer16-s3 */
<> 144:ef7eb2e8f9f7 260 def_irq_default_handler I2CM1_IRQHandler /* 62:47 I2C Master 1 */
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 .end