Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Maxim/TARGET_MAX32600/aes_regs.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #ifndef _MXC_AES_REGS_H_
<> 144:ef7eb2e8f9f7 35 #define _MXC_AES_REGS_H_
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 38 extern "C" {
<> 144:ef7eb2e8f9f7 39 #endif
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #include <stdint.h>
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /**
<> 144:ef7eb2e8f9f7 44 * @file aes_regs.h
<> 144:ef7eb2e8f9f7 45 * @addtogroup aes AES
<> 144:ef7eb2e8f9f7 46 * @{
<> 144:ef7eb2e8f9f7 47 */
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /**
<> 144:ef7eb2e8f9f7 50 * @brief Settings for AES_CTRL.CRYPT_MODE
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52 typedef enum {
<> 144:ef7eb2e8f9f7 53 MXC_E_AES_CTRL_ENCRYPT_MODE = 0,
<> 144:ef7eb2e8f9f7 54 MXC_E_AES_CTRL_DECRYPT_MODE = 1
<> 144:ef7eb2e8f9f7 55 } mxc_aes_ctrl_crypt_mode_t;
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /**
<> 144:ef7eb2e8f9f7 58 * @brief Settings for AES_CTRL.EXP_KEY_MODE
<> 144:ef7eb2e8f9f7 59 */
<> 144:ef7eb2e8f9f7 60 typedef enum {
<> 144:ef7eb2e8f9f7 61 MXC_E_AES_CTRL_CALC_NEW_EXP_KEY = 0,
<> 144:ef7eb2e8f9f7 62 MXC_E_AES_CTRL_USE_LAST_EXP_KEY = 1
<> 144:ef7eb2e8f9f7 63 } mxc_aes_ctrl_exp_key_mode_t;
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 /**
<> 144:ef7eb2e8f9f7 66 * @brief Settings for AES_CTRL.KEY_SIZE
<> 144:ef7eb2e8f9f7 67 */
<> 144:ef7eb2e8f9f7 68 typedef enum {
<> 144:ef7eb2e8f9f7 69 MXC_E_AES_CTRL_KEY_SIZE_128 = 0,
<> 144:ef7eb2e8f9f7 70 MXC_E_AES_CTRL_KEY_SIZE_192 = 1,
<> 144:ef7eb2e8f9f7 71 MXC_E_AES_CTRL_KEY_SIZE_256 = 2
<> 144:ef7eb2e8f9f7 72 } mxc_aes_ctrl_key_size_t;
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /* Offset Register Description
<> 144:ef7eb2e8f9f7 75 ====== =========================================================== */
<> 144:ef7eb2e8f9f7 76 typedef struct {
<> 144:ef7eb2e8f9f7 77 __IO uint32_t ctrl; /* 0x0000 AES Control and Status */
<> 144:ef7eb2e8f9f7 78 __I uint32_t rsv004; /* 0x0004 */
<> 144:ef7eb2e8f9f7 79 __IO uint32_t erase_all; /* 0x0008 Write to Trigger AES Memory Erase */
<> 144:ef7eb2e8f9f7 80 } mxc_aes_regs_t;
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 /* Offset Register Description
<> 144:ef7eb2e8f9f7 83 ====== =========================================================== */
<> 144:ef7eb2e8f9f7 84 typedef struct {
<> 144:ef7eb2e8f9f7 85 __IO uint32_t inp[4]; /* 0x0000 AES Input 0..3 */
<> 144:ef7eb2e8f9f7 86 __IO uint32_t key[8]; /* 0x0010 AES Key 0..7 */
<> 144:ef7eb2e8f9f7 87 __IO uint32_t out[4]; /* 0x0030 AES Output 0..3 */
<> 144:ef7eb2e8f9f7 88 __IO uint32_t expkey[8]; /* 0x0040 AES Expanded Key Data 0..7 */
<> 144:ef7eb2e8f9f7 89 } mxc_aes_mem_regs_t;
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /*
<> 144:ef7eb2e8f9f7 92 Register offsets for module AES.
<> 144:ef7eb2e8f9f7 93 */
<> 144:ef7eb2e8f9f7 94 #define MXC_R_AES_OFFS_CTRL ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 95 #define MXC_R_AES_OFFS_ERASE_ALL ((uint32_t)0x00000008UL)
<> 144:ef7eb2e8f9f7 96 #define MXC_R_AES_MEM_OFFS_INP0 ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 97 #define MXC_R_AES_MEM_OFFS_INP1 ((uint32_t)0x00000004UL)
<> 144:ef7eb2e8f9f7 98 #define MXC_R_AES_MEM_OFFS_INP2 ((uint32_t)0x00000008UL)
<> 144:ef7eb2e8f9f7 99 #define MXC_R_AES_MEM_OFFS_INP3 ((uint32_t)0x0000000CUL)
<> 144:ef7eb2e8f9f7 100 #define MXC_R_AES_MEM_OFFS_KEY0 ((uint32_t)0x00000010UL)
<> 144:ef7eb2e8f9f7 101 #define MXC_R_AES_MEM_OFFS_KEY1 ((uint32_t)0x00000014UL)
<> 144:ef7eb2e8f9f7 102 #define MXC_R_AES_MEM_OFFS_KEY2 ((uint32_t)0x00000018UL)
<> 144:ef7eb2e8f9f7 103 #define MXC_R_AES_MEM_OFFS_KEY3 ((uint32_t)0x0000001CUL)
<> 144:ef7eb2e8f9f7 104 #define MXC_R_AES_MEM_OFFS_KEY4 ((uint32_t)0x00000020UL)
<> 144:ef7eb2e8f9f7 105 #define MXC_R_AES_MEM_OFFS_KEY5 ((uint32_t)0x00000024UL)
<> 144:ef7eb2e8f9f7 106 #define MXC_R_AES_MEM_OFFS_KEY6 ((uint32_t)0x00000028UL)
<> 144:ef7eb2e8f9f7 107 #define MXC_R_AES_MEM_OFFS_KEY7 ((uint32_t)0x0000002CUL)
<> 144:ef7eb2e8f9f7 108 #define MXC_R_AES_MEM_OFFS_OUT0 ((uint32_t)0x00000030UL)
<> 144:ef7eb2e8f9f7 109 #define MXC_R_AES_MEM_OFFS_OUT1 ((uint32_t)0x00000034UL)
<> 144:ef7eb2e8f9f7 110 #define MXC_R_AES_MEM_OFFS_OUT2 ((uint32_t)0x00000038UL)
<> 144:ef7eb2e8f9f7 111 #define MXC_R_AES_MEM_OFFS_OUT3 ((uint32_t)0x0000003CUL)
<> 144:ef7eb2e8f9f7 112 #define MXC_R_AES_MEM_OFFS_EXPKEY0 ((uint32_t)0x00000040UL)
<> 144:ef7eb2e8f9f7 113 #define MXC_R_AES_MEM_OFFS_EXPKEY1 ((uint32_t)0x00000044UL)
<> 144:ef7eb2e8f9f7 114 #define MXC_R_AES_MEM_OFFS_EXPKEY2 ((uint32_t)0x00000048UL)
<> 144:ef7eb2e8f9f7 115 #define MXC_R_AES_MEM_OFFS_EXPKEY3 ((uint32_t)0x0000004CUL)
<> 144:ef7eb2e8f9f7 116 #define MXC_R_AES_MEM_OFFS_EXPKEY4 ((uint32_t)0x00000050UL)
<> 144:ef7eb2e8f9f7 117 #define MXC_R_AES_MEM_OFFS_EXPKEY5 ((uint32_t)0x00000054UL)
<> 144:ef7eb2e8f9f7 118 #define MXC_R_AES_MEM_OFFS_EXPKEY6 ((uint32_t)0x00000058UL)
<> 144:ef7eb2e8f9f7 119 #define MXC_R_AES_MEM_OFFS_EXPKEY7 ((uint32_t)0x0000005CUL)
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 #define MXC_F_AES_CTRL_START_POS 0
<> 144:ef7eb2e8f9f7 122 #define MXC_F_AES_CTRL_START ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_START_POS))
<> 144:ef7eb2e8f9f7 123 #define MXC_F_AES_CTRL_CRYPT_MODE_POS 1
<> 144:ef7eb2e8f9f7 124 #define MXC_F_AES_CTRL_CRYPT_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_CRYPT_MODE_POS))
<> 144:ef7eb2e8f9f7 125 #define MXC_F_AES_CTRL_EXP_KEY_MODE_POS 2
<> 144:ef7eb2e8f9f7 126 #define MXC_F_AES_CTRL_EXP_KEY_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_EXP_KEY_MODE_POS))
<> 144:ef7eb2e8f9f7 127 #define MXC_F_AES_CTRL_KEY_SIZE_POS 3
<> 144:ef7eb2e8f9f7 128 #define MXC_F_AES_CTRL_KEY_SIZE ((uint32_t)(0x00000003UL << MXC_F_AES_CTRL_KEY_SIZE_POS))
<> 144:ef7eb2e8f9f7 129 #define MXC_F_AES_CTRL_INTEN_POS 5
<> 144:ef7eb2e8f9f7 130 #define MXC_F_AES_CTRL_INTEN ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTEN_POS))
<> 144:ef7eb2e8f9f7 131 #define MXC_F_AES_CTRL_INTFL_POS 6
<> 144:ef7eb2e8f9f7 132 #define MXC_F_AES_CTRL_INTFL ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTFL_POS))
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 #define MXC_V_AES_CTRL_ENCRYPT_MODE 0
<> 144:ef7eb2e8f9f7 135 #define MXC_V_AES_CTRL_DECRYPT_MODE 1
<> 144:ef7eb2e8f9f7 136 #define MXC_S_AES_CTRL_ENCRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_ENCRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS))
<> 144:ef7eb2e8f9f7 137 #define MXC_S_AES_CTRL_DECRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_DECRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS))
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 #define MXC_V_AES_CTRL_CALC_NEW_EXP_KEY 0
<> 144:ef7eb2e8f9f7 140 #define MXC_V_AES_CTRL_USE_LAST_EXP_KEY 1
<> 144:ef7eb2e8f9f7 141 #define MXC_S_AES_CTRL_CALC_NEW_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_CALC_NEW_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS))
<> 144:ef7eb2e8f9f7 142 #define MXC_S_AES_CTRL_USE_LAST_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_USE_LAST_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS))
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 #define MXC_V_AES_CTRL_KEY_SIZE_128 0
<> 144:ef7eb2e8f9f7 145 #define MXC_V_AES_CTRL_KEY_SIZE_192 1
<> 144:ef7eb2e8f9f7 146 #define MXC_V_AES_CTRL_KEY_SIZE_256 2
<> 144:ef7eb2e8f9f7 147 #define MXC_S_AES_CTRL_KEY_SIZE_128 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_128 << MXC_F_AES_CTRL_KEY_SIZE_POS))
<> 144:ef7eb2e8f9f7 148 #define MXC_S_AES_CTRL_KEY_SIZE_192 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_192 << MXC_F_AES_CTRL_KEY_SIZE_POS))
<> 144:ef7eb2e8f9f7 149 #define MXC_S_AES_CTRL_KEY_SIZE_256 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_256 << MXC_F_AES_CTRL_KEY_SIZE_POS))
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 152 }
<> 144:ef7eb2e8f9f7 153 #endif
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 /**
<> 144:ef7eb2e8f9f7 156 * @}
<> 144:ef7eb2e8f9f7 157 */
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 #endif /* _MXC_AES_REGS_H_ */