Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Maxim/TARGET_MAX32600/adc_regs.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #ifndef _MXC_ADC_REGS_H
<> 144:ef7eb2e8f9f7 35 #define _MXC_ADC_REGS_H
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 38 extern "C" {
<> 144:ef7eb2e8f9f7 39 #endif
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #include <stdint.h>
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /**
<> 144:ef7eb2e8f9f7 44 * @file adc_regs.h
<> 144:ef7eb2e8f9f7 45 * @addtogroup adc ADC
<> 144:ef7eb2e8f9f7 46 * @{
<> 144:ef7eb2e8f9f7 47 */
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /**
<> 144:ef7eb2e8f9f7 50 * @brief Defines ADC Modes.
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52 typedef enum {
<> 144:ef7eb2e8f9f7 53 /** Single Mode Full Rate */
<> 144:ef7eb2e8f9f7 54 MXC_E_ADC_MODE_SMPLCNT_FULL_RATE = 0,
<> 144:ef7eb2e8f9f7 55 /** Single Mode Low Power */
<> 144:ef7eb2e8f9f7 56 MXC_E_ADC_MODE_SMPLCNT_LOW_POWER = 1,
<> 144:ef7eb2e8f9f7 57 /** Continuous Mode Full Rate */
<> 144:ef7eb2e8f9f7 58 MXC_E_ADC_MODE_CONTINUOUS_FULL_RATE = 2,
<> 144:ef7eb2e8f9f7 59 /** Continuous Mode Low Power */
<> 144:ef7eb2e8f9f7 60 MXC_E_ADC_MODE_CONTINUOUS_LOW_POWER = 3,
<> 144:ef7eb2e8f9f7 61 /** Single Mode Full Rate with Scan Enabled */
<> 144:ef7eb2e8f9f7 62 MXC_E_ADC_MODE_SMPLCNT_SCAN_FULL_RATE = 8,
<> 144:ef7eb2e8f9f7 63 /** Single Mode Low Power with Scan Enabled */
<> 144:ef7eb2e8f9f7 64 MXC_E_ADC_MODE_SMPLCNT_SCAN_LOW_POWER = 9,
<> 144:ef7eb2e8f9f7 65 /** Continuous Mode Full Rate with Scan Enabled */
<> 144:ef7eb2e8f9f7 66 MXC_E_ADC_MODE_CONTINUOUS_SCAN_FULL_RATE = 10,
<> 144:ef7eb2e8f9f7 67 /** Continuous Mode Low Power with Scan Enabled */
<> 144:ef7eb2e8f9f7 68 MXC_E_ADC_MODE_CONTINUOUS_SCAN_LOW_POWER = 11
<> 144:ef7eb2e8f9f7 69 } mxc_adc_mode_t;
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 /**
<> 144:ef7eb2e8f9f7 72 * @brief Defines ADC Range Control.
<> 144:ef7eb2e8f9f7 73 */
<> 144:ef7eb2e8f9f7 74 typedef enum {
<> 144:ef7eb2e8f9f7 75 /** Bi-polar Operation (-Vref/2 -> Vref/2) */
<> 144:ef7eb2e8f9f7 76 MXC_E_ADC_RANGE_HALF = 0,
<> 144:ef7eb2e8f9f7 77 /** Bi-polar Operation (-Vref -> Vref) */
<> 144:ef7eb2e8f9f7 78 MXC_E_ADC_RANGE_FULL
<> 144:ef7eb2e8f9f7 79 } mxc_adc_range_t;
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 /**
<> 144:ef7eb2e8f9f7 82 * @brief Defines ADC Bipolar operation.
<> 144:ef7eb2e8f9f7 83 */
<> 144:ef7eb2e8f9f7 84 typedef enum {
<> 144:ef7eb2e8f9f7 85 /** Uni-polar operation (0 -> Vref) */
<> 144:ef7eb2e8f9f7 86 MXC_E_ADC_BI_POL_UNIPOLAR = 0,
<> 144:ef7eb2e8f9f7 87 /** Bi-polar operation see ADC Range Control */
<> 144:ef7eb2e8f9f7 88 MXC_E_ADC_BI_POL_BIPOLAR
<> 144:ef7eb2e8f9f7 89 } mxc_adc_bi_pol_t;
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /**
<> 144:ef7eb2e8f9f7 92 * @brief Defines Decimation Filter Modes.
<> 144:ef7eb2e8f9f7 93 */
<> 144:ef7eb2e8f9f7 94 typedef enum {
<> 144:ef7eb2e8f9f7 95 /** Decimation Filter ByPassed */
<> 144:ef7eb2e8f9f7 96 MXC_E_ADC_AVG_MODE_FILTER_BYPASS = 0,
<> 144:ef7eb2e8f9f7 97 /** Output Average Only*/
<> 144:ef7eb2e8f9f7 98 MXC_E_ADC_AVG_MODE_FILTER_OUTPUT,
<> 144:ef7eb2e8f9f7 99 /** Output Average and Raw Data (Test Mode Only) */
<> 144:ef7eb2e8f9f7 100 MXC_E_ADC_AVG_MODE_FILTER_OUTPUT_RAW
<> 144:ef7eb2e8f9f7 101 } mxc_adc_avg_mode_t;
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /**
<> 144:ef7eb2e8f9f7 104 * @brief Defines ADC StartMode Modes.
<> 144:ef7eb2e8f9f7 105 */
<> 144:ef7eb2e8f9f7 106 typedef enum {
<> 144:ef7eb2e8f9f7 107 /** StarMode via Software */
<> 144:ef7eb2e8f9f7 108 MXC_E_ADC_STRT_MODE_SOFTWARE = 0,
<> 144:ef7eb2e8f9f7 109 /** StarMode via PulseTrain */
<> 144:ef7eb2e8f9f7 110 MXC_E_ADC_STRT_MODE_PULSETRAIN
<> 144:ef7eb2e8f9f7 111 } mxc_adc_strt_mode_t;
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 /**
<> 144:ef7eb2e8f9f7 114 * @brief Defines Mux Channel Select for the Positive Input to the ADC.
<> 144:ef7eb2e8f9f7 115 */
<> 144:ef7eb2e8f9f7 116 typedef enum {
<> 144:ef7eb2e8f9f7 117 /** Single Mode Input AIN0+; Diff Mode AIN0+/AIN8- */
<> 144:ef7eb2e8f9f7 118 MXC_E_ADC_PGA_MUX_CH_SEL_AIN0 = 0,
<> 144:ef7eb2e8f9f7 119 /** Single Mode Input AIN1+; Diff Mode AIN1+/AIN9- */
<> 144:ef7eb2e8f9f7 120 MXC_E_ADC_PGA_MUX_CH_SEL_AIN1 = 1,
<> 144:ef7eb2e8f9f7 121 /** Single Mode Input AIN2+; Diff Mode AIN2+/AIN10- */
<> 144:ef7eb2e8f9f7 122 MXC_E_ADC_PGA_MUX_CH_SEL_AIN2 = 2,
<> 144:ef7eb2e8f9f7 123 /** Single Mode Input AIN3+; Diff Mode AIN3+/AIN11- */
<> 144:ef7eb2e8f9f7 124 MXC_E_ADC_PGA_MUX_CH_SEL_AIN3 = 3,
<> 144:ef7eb2e8f9f7 125 /** Single Mode Input AIN4+; Diff Mode AIN4+/AIN12- */
<> 144:ef7eb2e8f9f7 126 MXC_E_ADC_PGA_MUX_CH_SEL_AIN4 = 4,
<> 144:ef7eb2e8f9f7 127 /** Single Mode Input AIN5+; Diff Mode AIN5+/AIN13- */
<> 144:ef7eb2e8f9f7 128 MXC_E_ADC_PGA_MUX_CH_SEL_AIN5 = 5,
<> 144:ef7eb2e8f9f7 129 /** Single Mode Input AIN6+; Diff Mode AIN6+/AIN14- */
<> 144:ef7eb2e8f9f7 130 MXC_E_ADC_PGA_MUX_CH_SEL_AIN6 = 6,
<> 144:ef7eb2e8f9f7 131 /** Single Mode Input AIN7+; Diff Mode AIN7+/AIN15- */
<> 144:ef7eb2e8f9f7 132 MXC_E_ADC_PGA_MUX_CH_SEL_AIN7 = 7,
<> 144:ef7eb2e8f9f7 133 /** Single Mode Input AIN8+ */
<> 144:ef7eb2e8f9f7 134 MXC_E_ADC_PGA_MUX_CH_SEL_AIN8 = 8,
<> 144:ef7eb2e8f9f7 135 /** Single Mode Input AIN9+ */
<> 144:ef7eb2e8f9f7 136 MXC_E_ADC_PGA_MUX_CH_SEL_AIN9 = 9,
<> 144:ef7eb2e8f9f7 137 /** Single Mode Input AIN10+ */
<> 144:ef7eb2e8f9f7 138 MXC_E_ADC_PGA_MUX_CH_SEL_AIN10 = 10,
<> 144:ef7eb2e8f9f7 139 /** Single Mode Input AIN11+ */
<> 144:ef7eb2e8f9f7 140 MXC_E_ADC_PGA_MUX_CH_SEL_AIN11 = 11,
<> 144:ef7eb2e8f9f7 141 /** Single Mode Input AIN12+ */
<> 144:ef7eb2e8f9f7 142 MXC_E_ADC_PGA_MUX_CH_SEL_AIN12 = 12,
<> 144:ef7eb2e8f9f7 143 /** Single Mode Input AIN13+ */
<> 144:ef7eb2e8f9f7 144 MXC_E_ADC_PGA_MUX_CH_SEL_AIN13 = 13,
<> 144:ef7eb2e8f9f7 145 /** Single Mode Input AIN14+ */
<> 144:ef7eb2e8f9f7 146 MXC_E_ADC_PGA_MUX_CH_SEL_AIN14 = 14,
<> 144:ef7eb2e8f9f7 147 /** Single Mode Input AIN15+ */
<> 144:ef7eb2e8f9f7 148 MXC_E_ADC_PGA_MUX_CH_SEL_AIN15 = 15,
<> 144:ef7eb2e8f9f7 149 /** Positive Input VSSADC */
<> 144:ef7eb2e8f9f7 150 MXC_E_ADC_PGA_MUX_CH_SEL_VSSADC = 16,
<> 144:ef7eb2e8f9f7 151 /** Positive Input TMON_R */
<> 144:ef7eb2e8f9f7 152 MXC_E_ADC_PGA_MUX_CH_SEL_TMON_R = 17,
<> 144:ef7eb2e8f9f7 153 /** Positive Input VDDA/4 */
<> 144:ef7eb2e8f9f7 154 MXC_E_ADC_PGA_MUX_CH_SEL_VDDA4 = 18,
<> 144:ef7eb2e8f9f7 155 /** Positive Input PWRMAN_TST */
<> 144:ef7eb2e8f9f7 156 MXC_E_ADC_PGA_MUX_CH_SEL_PWRMON_TST = 19,
<> 144:ef7eb2e8f9f7 157 /** Positive Input Ain0Div */
<> 144:ef7eb2e8f9f7 158 MXC_E_ADC_PGA_MUX_CH_SEL_AIN0DIV = 20,
<> 144:ef7eb2e8f9f7 159 /** Positive Input OpAmp OUTA */
<> 144:ef7eb2e8f9f7 160 MXC_E_ADC_PGA_MUX_CH_SEL_OUTA = 32,
<> 144:ef7eb2e8f9f7 161 /** Positive Input OpAmp OUTB */
<> 144:ef7eb2e8f9f7 162 MXC_E_ADC_PGA_MUX_CH_SEL_OUTB = 33,
<> 144:ef7eb2e8f9f7 163 /** Positive Input OpAmp OUTC */
<> 144:ef7eb2e8f9f7 164 MXC_E_ADC_PGA_MUX_CH_SEL_OUTC = 34,
<> 144:ef7eb2e8f9f7 165 /** Positive Input OpAmp OUTD */
<> 144:ef7eb2e8f9f7 166 MXC_E_ADC_PGA_MUX_CH_SEL_OUTD = 35,
<> 144:ef7eb2e8f9f7 167 /** Positive INA+ */
<> 144:ef7eb2e8f9f7 168 MXC_E_ADC_PGA_MUX_CH_SEL_INAPLUS = 36,
<> 144:ef7eb2e8f9f7 169 /** Positive SNO_or */
<> 144:ef7eb2e8f9f7 170 MXC_E_ADC_PGA_MUX_CH_SEL_SNO_OR = 37,
<> 144:ef7eb2e8f9f7 171 /** Positive SCM_or */
<> 144:ef7eb2e8f9f7 172 MXC_E_ADC_PGA_MUX_CH_SEL_SCM_OR = 38,
<> 144:ef7eb2e8f9f7 173 /** Positive TPROBE_sense */
<> 144:ef7eb2e8f9f7 174 MXC_E_ADC_PGA_MUX_CH_SEL_TPROBE_SENSE = 48,
<> 144:ef7eb2e8f9f7 175 /** Positive VREFDAC */
<> 144:ef7eb2e8f9f7 176 MXC_E_ADC_PGA_MUX_CH_SEL_VREFDAC = 49,
<> 144:ef7eb2e8f9f7 177 /** Positive VREFADJ */
<> 144:ef7eb2e8f9f7 178 MXC_E_ADC_PGA_MUX_CH_SEL_VREFADJ = 50,
<> 144:ef7eb2e8f9f7 179 /** Positive Vdd3xtal */
<> 144:ef7eb2e8f9f7 180 MXC_E_ADC_PGA_MUX_CH_SEL_VDD3XTAL = 51
<> 144:ef7eb2e8f9f7 181 } mxc_adc_pga_mux_ch_sel_t;
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /**
<> 144:ef7eb2e8f9f7 184 * @brief Decoded with the MUX Channel Select to enable Differential Mode Input to the ADC.
<> 144:ef7eb2e8f9f7 185 */
<> 144:ef7eb2e8f9f7 186 typedef enum {
<> 144:ef7eb2e8f9f7 187 /** Differential Mode Disabled */
<> 144:ef7eb2e8f9f7 188 MXC_E_ADC_PGA_MUX_DIFF_DISABLE = 0,
<> 144:ef7eb2e8f9f7 189 /** Differential Mode Enabled */
<> 144:ef7eb2e8f9f7 190 MXC_E_ADC_PGA_MUX_DIFF_ENABLE
<> 144:ef7eb2e8f9f7 191 } mxc_adc_pga_mux_diff_t;
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /**
<> 144:ef7eb2e8f9f7 194 * @brief Defines the PGA Gain Options.
<> 144:ef7eb2e8f9f7 195 */
<> 144:ef7eb2e8f9f7 196 typedef enum {
<> 144:ef7eb2e8f9f7 197 /** PGA Gain = 1 */
<> 144:ef7eb2e8f9f7 198 MXC_E_ADC_PGA_GAIN_1 = 0,
<> 144:ef7eb2e8f9f7 199 /** PGA Gain = 2 */
<> 144:ef7eb2e8f9f7 200 MXC_E_ADC_PGA_GAIN_2,
<> 144:ef7eb2e8f9f7 201 /** PGA Gain = 4 */
<> 144:ef7eb2e8f9f7 202 MXC_E_ADC_PGA_GAIN_4,
<> 144:ef7eb2e8f9f7 203 /** PGA Gain = 8 */
<> 144:ef7eb2e8f9f7 204 MXC_E_ADC_PGA_GAIN_8,
<> 144:ef7eb2e8f9f7 205 } mxc_adc_pga_gain_t;
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /**
<> 144:ef7eb2e8f9f7 208 * @brief Defines the Switch Control Mode.
<> 144:ef7eb2e8f9f7 209 */
<> 144:ef7eb2e8f9f7 210 typedef enum {
<> 144:ef7eb2e8f9f7 211 /** Switch Control Mode = Software */
<> 144:ef7eb2e8f9f7 212 MXC_E_ADC_SPST_SW_CTRL_SOFTWARE = 0,
<> 144:ef7eb2e8f9f7 213 /** Switch Control Mode = Pulse Train */
<> 144:ef7eb2e8f9f7 214 MXC_E_ADC_SPST_SW_CTRL_PULSETRAIN
<> 144:ef7eb2e8f9f7 215 } mxc_adc_spst_sw_ctrl_t;
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /**
<> 144:ef7eb2e8f9f7 218 * @brief Defines the number of channels to scan when Scan Mode is enabled.
<> 144:ef7eb2e8f9f7 219 */
<> 144:ef7eb2e8f9f7 220 typedef enum {
<> 144:ef7eb2e8f9f7 221 /** Number of Channels to Scan = 1 */
<> 144:ef7eb2e8f9f7 222 MXC_E_ADC_SCAN_CNT_1 = 0,
<> 144:ef7eb2e8f9f7 223 /** Number of Channels to Scan = 2 */
<> 144:ef7eb2e8f9f7 224 MXC_E_ADC_SCAN_CNT_2,
<> 144:ef7eb2e8f9f7 225 /** Number of Channels to Scan = 3 */
<> 144:ef7eb2e8f9f7 226 MXC_E_ADC_SCAN_CNT_3,
<> 144:ef7eb2e8f9f7 227 /** Number of Channels to Scan = 4 */
<> 144:ef7eb2e8f9f7 228 MXC_E_ADC_SCAN_CNT_4,
<> 144:ef7eb2e8f9f7 229 /** Number of Channels to Scan = 5 */
<> 144:ef7eb2e8f9f7 230 MXC_E_ADC_SCAN_CNT_5,
<> 144:ef7eb2e8f9f7 231 /** Number of Channels to Scan = 6 */
<> 144:ef7eb2e8f9f7 232 MXC_E_ADC_SCAN_CNT_6,
<> 144:ef7eb2e8f9f7 233 /** Number of Channels to Scan = 7 */
<> 144:ef7eb2e8f9f7 234 MXC_E_ADC_SCAN_CNT_7,
<> 144:ef7eb2e8f9f7 235 /** Number of Channels to Scan = 8 */
<> 144:ef7eb2e8f9f7 236 MXC_E_ADC_SCAN_CNT_8,
<> 144:ef7eb2e8f9f7 237 } mxc_adc_scan_cnt_t;
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /* Offset Register Description
<> 144:ef7eb2e8f9f7 240 ====== =================================================== */
<> 144:ef7eb2e8f9f7 241 typedef struct {
<> 144:ef7eb2e8f9f7 242 __IO uint32_t ctrl0; /* 0x0000 ADC Control Register 0 */
<> 144:ef7eb2e8f9f7 243 __IO uint32_t pga_ctrl; /* 0x0004 PGA Control Register */
<> 144:ef7eb2e8f9f7 244 __IO uint32_t tg_ctrl0; /* 0x0008 ADC Timing Generator Control 0 */
<> 144:ef7eb2e8f9f7 245 __IO uint32_t tg_ctrl1; /* 0x000C ADC Timing Generator Control 1 */
<> 144:ef7eb2e8f9f7 246 __IO uint32_t limit; /* 0x0010 ADC Limit Settings */
<> 144:ef7eb2e8f9f7 247 __IO uint32_t intr; /* 0x0014 ADC Interrupt Flags and Enable/Disable Controls */
<> 144:ef7eb2e8f9f7 248 __IO uint32_t out; /* 0x0018 ADC Output Register */
<> 144:ef7eb2e8f9f7 249 } mxc_adc_regs_t;
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /* Offset Register Description
<> 144:ef7eb2e8f9f7 252 ====== =================================================== */
<> 144:ef7eb2e8f9f7 253 typedef struct {
<> 144:ef7eb2e8f9f7 254 __IO uint32_t ctrl1; /* 0x0000 ADC Control Register 1 */
<> 144:ef7eb2e8f9f7 255 __IO uint32_t scan1; /* 0x0004 ADC Auto-Scan Settings 1 */
<> 144:ef7eb2e8f9f7 256 __IO uint32_t scan2; /* 0x0008 ADC Auto-Scan Settings 2 */
<> 144:ef7eb2e8f9f7 257 __IO uint32_t ro_cal0; /* 0x000C ADC Ring Osc Calibration 0 */
<> 144:ef7eb2e8f9f7 258 __IO uint32_t ro_cal1; /* 0x0010 ADC Ring Osc Calibration 1 */
<> 144:ef7eb2e8f9f7 259 } mxc_adccfg_regs_t;
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 typedef struct {
<> 144:ef7eb2e8f9f7 262 __IO uint16_t data; /* 0x0000 Read to pull sample data from ADC FIFO */
<> 144:ef7eb2e8f9f7 263 } mxc_adc_fifo_regs_t;
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /*
<> 144:ef7eb2e8f9f7 266 Register offsets for module ADC, ADCCFG, ADC_FIFO
<> 144:ef7eb2e8f9f7 267 */
<> 144:ef7eb2e8f9f7 268 #define MXC_R_ADC_OFFS_CTRL0 ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 269 #define MXC_R_ADC_OFFS_PGA_CTRL ((uint32_t)0x00000004UL)
<> 144:ef7eb2e8f9f7 270 #define MXC_R_ADC_OFFS_TG_CTRL0 ((uint32_t)0x00000008UL)
<> 144:ef7eb2e8f9f7 271 #define MXC_R_ADC_OFFS_TG_CTRL1 ((uint32_t)0x0000000CUL)
<> 144:ef7eb2e8f9f7 272 #define MXC_R_ADC_OFFS_LIMIT ((uint32_t)0x00000010UL)
<> 144:ef7eb2e8f9f7 273 #define MXC_R_ADC_OFFS_INTR ((uint32_t)0x00000014UL)
<> 144:ef7eb2e8f9f7 274 #define MXC_R_ADC_OFFS_OUT ((uint32_t)0x00000018UL)
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 #define MXC_R_ADCCFG_OFFS_CTRL1 ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 277 #define MXC_R_ADCCFG_OFFS_SCAN1 ((uint32_t)0x00000004UL)
<> 144:ef7eb2e8f9f7 278 #define MXC_R_ADCCFG_OFFS_SCAN2 ((uint32_t)0x00000008UL)
<> 144:ef7eb2e8f9f7 279 #define MXC_R_ADCCFG_OFFS_RO_CAL0 ((uint32_t)0x0000000CUL)
<> 144:ef7eb2e8f9f7 280 #define MXC_R_ADCCFG_OFFS_RO_CAL1 ((uint32_t)0x00000010UL)
<> 144:ef7eb2e8f9f7 281 #define MXC_R_ADC_FIFO_OFFS_DATA ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /*
<> 144:ef7eb2e8f9f7 284 Field positions and masks for module ADC.
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286 #define MXC_F_ADC_CTRL0_ADC_WAKE_CNT_POS 0
<> 144:ef7eb2e8f9f7 287 #define MXC_F_ADC_CTRL0_ADC_WAKE_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL0_ADC_WAKE_CNT_POS))
<> 144:ef7eb2e8f9f7 288 #define MXC_F_ADC_CTRL0_ADC_STRT_MODE_POS 5
<> 144:ef7eb2e8f9f7 289 #define MXC_F_ADC_CTRL0_ADC_STRT_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_STRT_MODE_POS))
<> 144:ef7eb2e8f9f7 290 #define MXC_F_ADC_CTRL0_ADC_RANGE_POS 6
<> 144:ef7eb2e8f9f7 291 #define MXC_F_ADC_CTRL0_ADC_RANGE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_RANGE_POS))
<> 144:ef7eb2e8f9f7 292 #define MXC_F_ADC_CTRL0_ADC_BI_POL_POS 7
<> 144:ef7eb2e8f9f7 293 #define MXC_F_ADC_CTRL0_ADC_BI_POL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_BI_POL_POS))
<> 144:ef7eb2e8f9f7 294 #define MXC_F_ADC_CTRL0_ADC_DV_REG_POS 8
<> 144:ef7eb2e8f9f7 295 #define MXC_F_ADC_CTRL0_ADC_DV_REG ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_DV_REG_POS))
<> 144:ef7eb2e8f9f7 296 #define MXC_F_ADC_CTRL0_ADC_DV_POS 9
<> 144:ef7eb2e8f9f7 297 #define MXC_F_ADC_CTRL0_ADC_DV ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_DV_POS))
<> 144:ef7eb2e8f9f7 298 #define MXC_F_ADC_CTRL0_ADC_LMT_DMODE_POS 10
<> 144:ef7eb2e8f9f7 299 #define MXC_F_ADC_CTRL0_ADC_LMT_DMODE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_LMT_DMODE_POS))
<> 144:ef7eb2e8f9f7 300 #define MXC_F_ADC_CTRL0_ADC_SMP_EXT_POS 11
<> 144:ef7eb2e8f9f7 301 #define MXC_F_ADC_CTRL0_ADC_SMP_EXT ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_SMP_EXT_POS))
<> 144:ef7eb2e8f9f7 302 #define MXC_F_ADC_CTRL0_ADC_CLK_EN_POS 12
<> 144:ef7eb2e8f9f7 303 #define MXC_F_ADC_CTRL0_ADC_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_CLK_EN_POS))
<> 144:ef7eb2e8f9f7 304 #define MXC_F_ADC_CTRL0_CPU_ADC_RST_POS 13
<> 144:ef7eb2e8f9f7 305 #define MXC_F_ADC_CTRL0_CPU_ADC_RST ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_RST_POS))
<> 144:ef7eb2e8f9f7 306 #define MXC_F_ADC_CTRL0_CPU_ADC_START_POS 14
<> 144:ef7eb2e8f9f7 307 #define MXC_F_ADC_CTRL0_CPU_ADC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_START_POS))
<> 144:ef7eb2e8f9f7 308 #define MXC_F_ADC_CTRL0_CPU_ADC_EN_POS 15
<> 144:ef7eb2e8f9f7 309 #define MXC_F_ADC_CTRL0_CPU_ADC_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_EN_POS))
<> 144:ef7eb2e8f9f7 310 #define MXC_F_ADC_CTRL0_ADC_FIFO_FULL_POS 18
<> 144:ef7eb2e8f9f7 311 #define MXC_F_ADC_CTRL0_ADC_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_FIFO_FULL_POS))
<> 144:ef7eb2e8f9f7 312 #define MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY_POS 19
<> 144:ef7eb2e8f9f7 313 #define MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY_POS))
<> 144:ef7eb2e8f9f7 314 #define MXC_F_ADC_CTRL0_AVG_MODE_POS 20
<> 144:ef7eb2e8f9f7 315 #define MXC_F_ADC_CTRL0_AVG_MODE ((uint32_t)(0x00000003UL << MXC_F_ADC_CTRL0_AVG_MODE_POS))
<> 144:ef7eb2e8f9f7 316 #define MXC_F_ADC_CTRL0_CPU_DAC_START_POS 22
<> 144:ef7eb2e8f9f7 317 #define MXC_F_ADC_CTRL0_CPU_DAC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_DAC_START_POS))
<> 144:ef7eb2e8f9f7 318 #define MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS 24
<> 144:ef7eb2e8f9f7 319 #define MXC_F_ADC_CTRL0_ADC_CLK_MODE ((uint32_t)(0x00000007UL << MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS))
<> 144:ef7eb2e8f9f7 320 #define MXC_F_ADC_CTRL0_ADC_MODE_POS 28
<> 144:ef7eb2e8f9f7 321 #define MXC_F_ADC_CTRL0_ADC_MODE ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL0_ADC_MODE_POS))
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 #define MXC_F_ADC_PGA_CTRL_PGA_GAIN_POS 0
<> 144:ef7eb2e8f9f7 324 #define MXC_F_ADC_PGA_CTRL_PGA_GAIN ((uint32_t)(0x00000003UL << MXC_F_ADC_PGA_CTRL_PGA_GAIN_POS))
<> 144:ef7eb2e8f9f7 325 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN_POS 2
<> 144:ef7eb2e8f9f7 326 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN_POS))
<> 144:ef7eb2e8f9f7 327 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_POS 3
<> 144:ef7eb2e8f9f7 328 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_POS))
<> 144:ef7eb2e8f9f7 329 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY_POS 4
<> 144:ef7eb2e8f9f7 330 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY_POS))
<> 144:ef7eb2e8f9f7 331 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_POS 5
<> 144:ef7eb2e8f9f7 332 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_POS))
<> 144:ef7eb2e8f9f7 333 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS_POS 6
<> 144:ef7eb2e8f9f7 334 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS_POS))
<> 144:ef7eb2e8f9f7 335 #define MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT_POS 8
<> 144:ef7eb2e8f9f7 336 #define MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT ((uint32_t)(0x0000001FUL << MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT_POS))
<> 144:ef7eb2e8f9f7 337 #define MXC_F_ADC_PGA_CTRL_MUX_SW_AIN_POS 13
<> 144:ef7eb2e8f9f7 338 #define MXC_F_ADC_PGA_CTRL_MUX_SW_AIN ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_SW_AIN_POS))
<> 144:ef7eb2e8f9f7 339 #define MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS 14
<> 144:ef7eb2e8f9f7 340 #define MXC_F_ADC_PGA_CTRL_MUX_DIFF ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS))
<> 144:ef7eb2e8f9f7 341 #define MXC_F_ADC_PGA_CTRL_MUX_MODE_POS 15
<> 144:ef7eb2e8f9f7 342 #define MXC_F_ADC_PGA_CTRL_MUX_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_MODE_POS))
<> 144:ef7eb2e8f9f7 343 #define MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT_POS 20
<> 144:ef7eb2e8f9f7 344 #define MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT_POS))
<> 144:ef7eb2e8f9f7 345 #define MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS 24
<> 144:ef7eb2e8f9f7 346 #define MXC_F_ADC_PGA_CTRL_MUX_CH_SEL ((uint32_t)(0x0000003FUL << MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS))
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 #define MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT_POS 0
<> 144:ef7eb2e8f9f7 349 #define MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT_POS))
<> 144:ef7eb2e8f9f7 350 #define MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS 16
<> 144:ef7eb2e8f9f7 351 #define MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS))
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 #define MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS 0
<> 144:ef7eb2e8f9f7 354 #define MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS))
<> 144:ef7eb2e8f9f7 355 #define MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT_POS 4
<> 144:ef7eb2e8f9f7 356 #define MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT_POS))
<> 144:ef7eb2e8f9f7 357 #define MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT_POS 8
<> 144:ef7eb2e8f9f7 358 #define MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT ((uint32_t)(0x00000007UL << MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT_POS))
<> 144:ef7eb2e8f9f7 359 #define MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS 12
<> 144:ef7eb2e8f9f7 360 #define MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS))
<> 144:ef7eb2e8f9f7 361 #define MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS 16
<> 144:ef7eb2e8f9f7 362 #define MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS))
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 #define MXC_F_ADC_LIMIT_LO_LIMIT_POS 0
<> 144:ef7eb2e8f9f7 365 #define MXC_F_ADC_LIMIT_LO_LIMIT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_LIMIT_LO_LIMIT_POS))
<> 144:ef7eb2e8f9f7 366 #define MXC_F_ADC_LIMIT_HI_LIMIT_POS 16
<> 144:ef7eb2e8f9f7 367 #define MXC_F_ADC_LIMIT_HI_LIMIT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_LIMIT_HI_LIMIT_POS))
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 #define MXC_F_ADC_INTR_FIFO_AF_POS 6
<> 144:ef7eb2e8f9f7 370 #define MXC_F_ADC_INTR_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_AF_POS))
<> 144:ef7eb2e8f9f7 371 #define MXC_F_ADC_INTR_OUT_RNG_IF_POS 7
<> 144:ef7eb2e8f9f7 372 #define MXC_F_ADC_INTR_OUT_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_OUT_RNG_IF_POS))
<> 144:ef7eb2e8f9f7 373 #define MXC_F_ADC_INTR_HI_RNG_IF_POS 8
<> 144:ef7eb2e8f9f7 374 #define MXC_F_ADC_INTR_HI_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_HI_RNG_IF_POS))
<> 144:ef7eb2e8f9f7 375 #define MXC_F_ADC_INTR_LO_RNG_IF_POS 9
<> 144:ef7eb2e8f9f7 376 #define MXC_F_ADC_INTR_LO_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_LO_RNG_IF_POS))
<> 144:ef7eb2e8f9f7 377 #define MXC_F_ADC_INTR_DONE_IF_POS 10
<> 144:ef7eb2e8f9f7 378 #define MXC_F_ADC_INTR_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_DONE_IF_POS))
<> 144:ef7eb2e8f9f7 379 #define MXC_F_ADC_INTR_FIFO_UF_IF_POS 11
<> 144:ef7eb2e8f9f7 380 #define MXC_F_ADC_INTR_FIFO_UF_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_UF_IF_POS))
<> 144:ef7eb2e8f9f7 381 #define MXC_F_ADC_INTR_FIFO_OF_IF_POS 12
<> 144:ef7eb2e8f9f7 382 #define MXC_F_ADC_INTR_FIFO_OF_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_OF_IF_POS))
<> 144:ef7eb2e8f9f7 383 #define MXC_F_ADC_INTR_FIFO_3Q_IF_POS 13
<> 144:ef7eb2e8f9f7 384 #define MXC_F_ADC_INTR_FIFO_3Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_3Q_IF_POS))
<> 144:ef7eb2e8f9f7 385 #define MXC_F_ADC_INTR_FIFO_2Q_IF_POS 14
<> 144:ef7eb2e8f9f7 386 #define MXC_F_ADC_INTR_FIFO_2Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_2Q_IF_POS))
<> 144:ef7eb2e8f9f7 387 #define MXC_F_ADC_INTR_FIFO_1Q_IF_POS 15
<> 144:ef7eb2e8f9f7 388 #define MXC_F_ADC_INTR_FIFO_1Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_1Q_IF_POS))
<> 144:ef7eb2e8f9f7 389 #define MXC_F_ADC_INTR_SPST0_CTRL_MODE_POS 16
<> 144:ef7eb2e8f9f7 390 #define MXC_F_ADC_INTR_SPST0_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST0_CTRL_MODE_POS))
<> 144:ef7eb2e8f9f7 391 #define MXC_F_ADC_INTR_SPST1_CTRL_MODE_POS 17
<> 144:ef7eb2e8f9f7 392 #define MXC_F_ADC_INTR_SPST1_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST1_CTRL_MODE_POS))
<> 144:ef7eb2e8f9f7 393 #define MXC_F_ADC_INTR_SPST2_CTRL_MODE_POS 18
<> 144:ef7eb2e8f9f7 394 #define MXC_F_ADC_INTR_SPST2_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST2_CTRL_MODE_POS))
<> 144:ef7eb2e8f9f7 395 #define MXC_F_ADC_INTR_SPST3_CTRL_MODE_POS 19
<> 144:ef7eb2e8f9f7 396 #define MXC_F_ADC_INTR_SPST3_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST3_CTRL_MODE_POS))
<> 144:ef7eb2e8f9f7 397 #define MXC_F_ADC_INTR_OUT_RNG_IE_POS 23
<> 144:ef7eb2e8f9f7 398 #define MXC_F_ADC_INTR_OUT_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_OUT_RNG_IE_POS))
<> 144:ef7eb2e8f9f7 399 #define MXC_F_ADC_INTR_HI_RNG_IE_POS 24
<> 144:ef7eb2e8f9f7 400 #define MXC_F_ADC_INTR_HI_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_HI_RNG_IE_POS))
<> 144:ef7eb2e8f9f7 401 #define MXC_F_ADC_INTR_LO_RNG_IE_POS 25
<> 144:ef7eb2e8f9f7 402 #define MXC_F_ADC_INTR_LO_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_LO_RNG_IE_POS))
<> 144:ef7eb2e8f9f7 403 #define MXC_F_ADC_INTR_DONE_IE_POS 26
<> 144:ef7eb2e8f9f7 404 #define MXC_F_ADC_INTR_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_DONE_IE_POS))
<> 144:ef7eb2e8f9f7 405 #define MXC_F_ADC_INTR_FIFO_UF_IE_POS 27
<> 144:ef7eb2e8f9f7 406 #define MXC_F_ADC_INTR_FIFO_UF_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_UF_IE_POS))
<> 144:ef7eb2e8f9f7 407 #define MXC_F_ADC_INTR_FIFO_OF_IE_POS 28
<> 144:ef7eb2e8f9f7 408 #define MXC_F_ADC_INTR_FIFO_OF_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_OF_IE_POS))
<> 144:ef7eb2e8f9f7 409 #define MXC_F_ADC_INTR_FIFO_3Q_IE_POS 29
<> 144:ef7eb2e8f9f7 410 #define MXC_F_ADC_INTR_FIFO_3Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_3Q_IE_POS))
<> 144:ef7eb2e8f9f7 411 #define MXC_F_ADC_INTR_FIFO_2Q_IE_POS 30
<> 144:ef7eb2e8f9f7 412 #define MXC_F_ADC_INTR_FIFO_2Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_2Q_IE_POS))
<> 144:ef7eb2e8f9f7 413 #define MXC_F_ADC_INTR_FIFO_1Q_IE_POS 31
<> 144:ef7eb2e8f9f7 414 #define MXC_F_ADC_INTR_FIFO_1Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_1Q_IE_POS))
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 #define MXC_F_ADC_OUT_DATA_REG_POS 0
<> 144:ef7eb2e8f9f7 417 #define MXC_F_ADC_OUT_DATA_REG ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_OUT_DATA_REG_POS))
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 #define MXC_F_ADC_CTRL1_ADC_SCAN_CNT_POS 16
<> 144:ef7eb2e8f9f7 420 #define MXC_F_ADC_CTRL1_ADC_SCAN_CNT ((uint32_t)(0x00000007UL << MXC_F_ADC_CTRL1_ADC_SCAN_CNT_POS))
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 #define MXC_F_ADC_SCAN1_ADC_SCAN0_POS 0
<> 144:ef7eb2e8f9f7 423 #define MXC_F_ADC_SCAN1_ADC_SCAN0 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN0_POS))
<> 144:ef7eb2e8f9f7 424 #define MXC_F_ADC_SCAN1_ADC_SCAN1_POS 8
<> 144:ef7eb2e8f9f7 425 #define MXC_F_ADC_SCAN1_ADC_SCAN1 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN1_POS))
<> 144:ef7eb2e8f9f7 426 #define MXC_F_ADC_SCAN1_ADC_SCAN2_POS 16
<> 144:ef7eb2e8f9f7 427 #define MXC_F_ADC_SCAN1_ADC_SCAN2 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN2_POS))
<> 144:ef7eb2e8f9f7 428 #define MXC_F_ADC_SCAN1_ADC_SCAN3_POS 24
<> 144:ef7eb2e8f9f7 429 #define MXC_F_ADC_SCAN1_ADC_SCAN3 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN3_POS))
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 #define MXC_F_ADC_SCAN2_ADC_SCAN4_POS 0
<> 144:ef7eb2e8f9f7 432 #define MXC_F_ADC_SCAN2_ADC_SCAN4 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN4_POS))
<> 144:ef7eb2e8f9f7 433 #define MXC_F_ADC_SCAN2_ADC_SCAN5_POS 8
<> 144:ef7eb2e8f9f7 434 #define MXC_F_ADC_SCAN2_ADC_SCAN5 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN5_POS))
<> 144:ef7eb2e8f9f7 435 #define MXC_F_ADC_SCAN2_ADC_SCAN6_POS 16
<> 144:ef7eb2e8f9f7 436 #define MXC_F_ADC_SCAN2_ADC_SCAN6 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN6_POS))
<> 144:ef7eb2e8f9f7 437 #define MXC_F_ADC_SCAN2_ADC_SCAN7_POS 24
<> 144:ef7eb2e8f9f7 438 #define MXC_F_ADC_SCAN2_ADC_SCAN7 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN7_POS))
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440 #define MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS 0
<> 144:ef7eb2e8f9f7 441 #define MXC_F_ADC_RO_CAL0_RO_CAL_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS))
<> 144:ef7eb2e8f9f7 442 #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS 1
<> 144:ef7eb2e8f9f7 443 #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS))
<> 144:ef7eb2e8f9f7 444 #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS 2
<> 144:ef7eb2e8f9f7 445 #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS))
<> 144:ef7eb2e8f9f7 446 #define MXC_F_ADC_RO_CAL0_TRM_MU_POS 8
<> 144:ef7eb2e8f9f7 447 #define MXC_F_ADC_RO_CAL0_TRM_MU ((uint32_t)(0x00000FFFUL << MXC_F_ADC_RO_CAL0_TRM_MU_POS))
<> 144:ef7eb2e8f9f7 448 #define MXC_F_ADC_RO_CAL0_RO_TRM_POS 23
<> 144:ef7eb2e8f9f7 449 #define MXC_F_ADC_RO_CAL0_RO_TRM ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL0_RO_TRM_POS))
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 #define MXC_F_ADC_RO_CAL1_TRM_INIT_POS 0
<> 144:ef7eb2e8f9f7 452 #define MXC_F_ADC_RO_CAL1_TRM_INIT ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_INIT_POS))
<> 144:ef7eb2e8f9f7 453 #define MXC_F_ADC_RO_CAL1_TRM_MIN_POS 10
<> 144:ef7eb2e8f9f7 454 #define MXC_F_ADC_RO_CAL1_TRM_MIN ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MIN_POS))
<> 144:ef7eb2e8f9f7 455 #define MXC_F_ADC_RO_CAL1_TRM_MAX_POS 20
<> 144:ef7eb2e8f9f7 456 #define MXC_F_ADC_RO_CAL1_TRM_MAX ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MAX_POS))
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 459 }
<> 144:ef7eb2e8f9f7 460 #endif
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 /**
<> 144:ef7eb2e8f9f7 463 * @}
<> 144:ef7eb2e8f9f7 464 */
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 #endif /* _MXC_ADC_REGS_H */