Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Maxim/TARGET_MAX32610/rtc_regs.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /*******************************************************************************
bogdanm 0:9b334a45a8ff 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Permission is hereby granted, free of charge, to any person obtaining a
bogdanm 0:9b334a45a8ff 5 * copy of this software and associated documentation files (the "Software"),
bogdanm 0:9b334a45a8ff 6 * to deal in the Software without restriction, including without limitation
bogdanm 0:9b334a45a8ff 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
bogdanm 0:9b334a45a8ff 8 * and/or sell copies of the Software, and to permit persons to whom the
bogdanm 0:9b334a45a8ff 9 * Software is furnished to do so, subject to the following conditions:
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * The above copyright notice and this permission notice shall be included
bogdanm 0:9b334a45a8ff 12 * in all copies or substantial portions of the Software.
bogdanm 0:9b334a45a8ff 13 *
bogdanm 0:9b334a45a8ff 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
bogdanm 0:9b334a45a8ff 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
bogdanm 0:9b334a45a8ff 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
bogdanm 0:9b334a45a8ff 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
bogdanm 0:9b334a45a8ff 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
bogdanm 0:9b334a45a8ff 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
bogdanm 0:9b334a45a8ff 20 * OTHER DEALINGS IN THE SOFTWARE.
bogdanm 0:9b334a45a8ff 21 *
bogdanm 0:9b334a45a8ff 22 * Except as contained in this notice, the name of Maxim Integrated
bogdanm 0:9b334a45a8ff 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
bogdanm 0:9b334a45a8ff 24 * Products, Inc. Branding Policy.
bogdanm 0:9b334a45a8ff 25 *
bogdanm 0:9b334a45a8ff 26 * The mere transfer of this software does not imply any licenses
bogdanm 0:9b334a45a8ff 27 * of trade secrets, proprietary technology, copyrights, patents,
bogdanm 0:9b334a45a8ff 28 * trademarks, maskwork rights, or any other form of intellectual
bogdanm 0:9b334a45a8ff 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
bogdanm 0:9b334a45a8ff 30 * ownership rights.
bogdanm 0:9b334a45a8ff 31 *******************************************************************************
bogdanm 0:9b334a45a8ff 32 */
bogdanm 0:9b334a45a8ff 33
bogdanm 0:9b334a45a8ff 34 #ifndef _MXC_RTC_REGS_H
bogdanm 0:9b334a45a8ff 35 #define _MXC_RTC_REGS_H
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 38 extern "C" {
bogdanm 0:9b334a45a8ff 39 #endif
bogdanm 0:9b334a45a8ff 40
bogdanm 0:9b334a45a8ff 41 #include <stdint.h>
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 /**
bogdanm 0:9b334a45a8ff 44 * @file rtc_regs.h
bogdanm 0:9b334a45a8ff 45 * @addtogroup rtc RTCTMR
bogdanm 0:9b334a45a8ff 46 * @{
bogdanm 0:9b334a45a8ff 47 */
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 /**
bogdanm 0:9b334a45a8ff 50 * @brief Defines clock divider for 4096Hz input clock.
bogdanm 0:9b334a45a8ff 51 */
bogdanm 0:9b334a45a8ff 52 typedef enum {
bogdanm 0:9b334a45a8ff 53 /** (4kHz) divide input clock by 2^0 = 1 */
bogdanm 0:9b334a45a8ff 54 MXC_E_RTC_PRESCALE_DIV_2_0 = 0,
bogdanm 0:9b334a45a8ff 55 /** (2kHz) divide input clock by 2^1 = 2 */
bogdanm 0:9b334a45a8ff 56 MXC_E_RTC_PRESCALE_DIV_2_1,
bogdanm 0:9b334a45a8ff 57 /** (1kHz) divide input clock by 2^2 = 4 */
bogdanm 0:9b334a45a8ff 58 MXC_E_RTC_PRESCALE_DIV_2_2,
bogdanm 0:9b334a45a8ff 59 /** (512Hz) divide input clock by 2^3 = 8 */
bogdanm 0:9b334a45a8ff 60 MXC_E_RTC_PRESCALE_DIV_2_3,
bogdanm 0:9b334a45a8ff 61 /** (256Hz) divide input clock by 2^4 = 16 */
bogdanm 0:9b334a45a8ff 62 MXC_E_RTC_PRESCALE_DIV_2_4,
bogdanm 0:9b334a45a8ff 63 /** (128Hz) divide input clock by 2^5 = 32 */
bogdanm 0:9b334a45a8ff 64 MXC_E_RTC_PRESCALE_DIV_2_5,
bogdanm 0:9b334a45a8ff 65 /** (64Hz) divide input clock by 2^6 = 64 */
bogdanm 0:9b334a45a8ff 66 MXC_E_RTC_PRESCALE_DIV_2_6,
bogdanm 0:9b334a45a8ff 67 /** (32Hz) divide input clock by 2^7 = 128 */
bogdanm 0:9b334a45a8ff 68 MXC_E_RTC_PRESCALE_DIV_2_7,
bogdanm 0:9b334a45a8ff 69 /** (16Hz) divide input clock by 2^8 = 256 */
bogdanm 0:9b334a45a8ff 70 MXC_E_RTC_PRESCALE_DIV_2_8,
bogdanm 0:9b334a45a8ff 71 /** (8Hz) divide input clock by 2^9 = 512 */
bogdanm 0:9b334a45a8ff 72 MXC_E_RTC_PRESCALE_DIV_2_9,
bogdanm 0:9b334a45a8ff 73 /** (4Hz) divide input clock by 2^10 = 1024 */
bogdanm 0:9b334a45a8ff 74 MXC_E_RTC_PRESCALE_DIV_2_10,
bogdanm 0:9b334a45a8ff 75 /** (2Hz) divide input clock by 2^11 = 2048 */
bogdanm 0:9b334a45a8ff 76 MXC_E_RTC_PRESCALE_DIV_2_11,
bogdanm 0:9b334a45a8ff 77 /** (1Hz) divide input clock by 2^12 = 4096 */
bogdanm 0:9b334a45a8ff 78 MXC_E_RTC_PRESCALE_DIV_2_12,
bogdanm 0:9b334a45a8ff 79 } mxc_rtc_prescale_t;
bogdanm 0:9b334a45a8ff 80
bogdanm 0:9b334a45a8ff 81 /* Offset Register Description
bogdanm 0:9b334a45a8ff 82 ====== ========================================= */
bogdanm 0:9b334a45a8ff 83 typedef struct {
bogdanm 0:9b334a45a8ff 84 __IO uint32_t ctrl; /* 0x0000 RTC Timer Control */
bogdanm 0:9b334a45a8ff 85 __IO uint32_t timer; /* 0x0004 RTC Timer Count Value */
bogdanm 0:9b334a45a8ff 86 __IO uint32_t comp[2]; /* 0x0008 RTC Alarm (0..1) Compare Registers */
bogdanm 0:9b334a45a8ff 87 __IO uint32_t flags; /* 0x0010 CPU Interrupt and RTC Domain Flags */
bogdanm 0:9b334a45a8ff 88 __I uint32_t rsv0014; /* 0x0014 */
bogdanm 0:9b334a45a8ff 89 __IO uint32_t inten; /* 0x0018 Interrupt Enable Controls */
bogdanm 0:9b334a45a8ff 90 __IO uint32_t prescale; /* 0x001C RTC Timer Prescale Setting */
bogdanm 0:9b334a45a8ff 91 __I uint32_t rsv0020; /* 0x0020 */
bogdanm 0:9b334a45a8ff 92 __IO uint32_t prescale_mask; /* 0x0024 RTC Timer Prescale Compare Mask */
bogdanm 0:9b334a45a8ff 93 __IO uint32_t trim_ctrl; /* 0x0028 RTC Timer Trim Controls */
bogdanm 0:9b334a45a8ff 94 __IO uint32_t trim_value; /* 0x002C RTC Timer Trim Adjustment Interval */
bogdanm 0:9b334a45a8ff 95 } mxc_rtctmr_regs_t;
bogdanm 0:9b334a45a8ff 96
bogdanm 0:9b334a45a8ff 97 /*
bogdanm 0:9b334a45a8ff 98 Register offsets for module RTCTMR.
bogdanm 0:9b334a45a8ff 99 */
bogdanm 0:9b334a45a8ff 100 #define MXC_R_RTCTMR_OFFS_CTRL ((uint32_t)0x00000000UL)
bogdanm 0:9b334a45a8ff 101 #define MXC_R_RTCTMR_OFFS_TIMER ((uint32_t)0x00000004UL)
bogdanm 0:9b334a45a8ff 102 #define MXC_R_RTCTMR_OFFS_COMP_0 ((uint32_t)0x00000008UL)
bogdanm 0:9b334a45a8ff 103 #define MXC_R_RTCTMR_OFFS_COMP_1 ((uint32_t)0x0000000CUL)
bogdanm 0:9b334a45a8ff 104 #define MXC_R_RTCTMR_OFFS_FLAGS ((uint32_t)0x00000010UL)
bogdanm 0:9b334a45a8ff 105 #define MXC_R_RTCTMR_OFFS_INTEN ((uint32_t)0x00000018UL)
bogdanm 0:9b334a45a8ff 106 #define MXC_R_RTCTMR_OFFS_PRESCALE ((uint32_t)0x0000001CUL)
bogdanm 0:9b334a45a8ff 107 #define MXC_R_RTCTMR_OFFS_PRESCALE_MASK ((uint32_t)0x00000024UL)
bogdanm 0:9b334a45a8ff 108 #define MXC_R_RTCTMR_OFFS_TRIM_CTRL ((uint32_t)0x00000028UL)
bogdanm 0:9b334a45a8ff 109 #define MXC_R_RTCTMR_OFFS_TRIM_VALUE ((uint32_t)0x0000002CUL)
bogdanm 0:9b334a45a8ff 110
bogdanm 0:9b334a45a8ff 111 /*
bogdanm 0:9b334a45a8ff 112 Field positions and masks for module RTCTMR.
bogdanm 0:9b334a45a8ff 113 */
bogdanm 0:9b334a45a8ff 114 #define MXC_F_RTC_CTRL_ENABLE_POS 0
bogdanm 0:9b334a45a8ff 115 #define MXC_F_RTC_CTRL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ENABLE_POS))
bogdanm 0:9b334a45a8ff 116 #define MXC_F_RTC_CTRL_CLEAR_POS 1
bogdanm 0:9b334a45a8ff 117 #define MXC_F_RTC_CTRL_CLEAR ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLEAR_POS))
bogdanm 0:9b334a45a8ff 118 #define MXC_F_RTC_CTRL_PENDING_POS 2
bogdanm 0:9b334a45a8ff 119 #define MXC_F_RTC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PENDING_POS))
bogdanm 0:9b334a45a8ff 120 #define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS 3
bogdanm 0:9b334a45a8ff 121 #define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS))
bogdanm 0:9b334a45a8ff 122 #define MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS 4
bogdanm 0:9b334a45a8ff 123 #define MXC_F_RTC_CTRL_AGGRESSIVE_RST ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS))
bogdanm 0:9b334a45a8ff 124 #define MXC_F_RTC_CTRL_EN_ACTIVE_POS 16
bogdanm 0:9b334a45a8ff 125 #define MXC_F_RTC_CTRL_EN_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_EN_ACTIVE_POS))
bogdanm 0:9b334a45a8ff 126 #define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS 17
bogdanm 0:9b334a45a8ff 127 #define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS))
bogdanm 0:9b334a45a8ff 128 #define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS 18
bogdanm 0:9b334a45a8ff 129 #define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS))
bogdanm 0:9b334a45a8ff 130 #define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS 19
bogdanm 0:9b334a45a8ff 131 #define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS))
bogdanm 0:9b334a45a8ff 132 #define MXC_F_RTC_CTRL_SET_ACTIVE_POS 20
bogdanm 0:9b334a45a8ff 133 #define MXC_F_RTC_CTRL_SET_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_SET_ACTIVE_POS))
bogdanm 0:9b334a45a8ff 134 #define MXC_F_RTC_CTRL_CLR_ACTIVE_POS 21
bogdanm 0:9b334a45a8ff 135 #define MXC_F_RTC_CTRL_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLR_ACTIVE_POS))
bogdanm 0:9b334a45a8ff 136 #define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS 22
bogdanm 0:9b334a45a8ff 137 #define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS))
bogdanm 0:9b334a45a8ff 138 #define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS 23
bogdanm 0:9b334a45a8ff 139 #define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS))
bogdanm 0:9b334a45a8ff 140 #define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS 24
bogdanm 0:9b334a45a8ff 141 #define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS))
bogdanm 0:9b334a45a8ff 142 #define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS 25
bogdanm 0:9b334a45a8ff 143 #define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS))
bogdanm 0:9b334a45a8ff 144 #define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS 26
bogdanm 0:9b334a45a8ff 145 #define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS))
bogdanm 0:9b334a45a8ff 146
bogdanm 0:9b334a45a8ff 147 #define MXC_F_RTC_FLAGS_COMP0_POS 0
bogdanm 0:9b334a45a8ff 148 #define MXC_F_RTC_FLAGS_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_POS))
bogdanm 0:9b334a45a8ff 149 #define MXC_F_RTC_FLAGS_COMP1_POS 1
bogdanm 0:9b334a45a8ff 150 #define MXC_F_RTC_FLAGS_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_POS))
bogdanm 0:9b334a45a8ff 151 #define MXC_F_RTC_FLAGS_PRESCALE_COMP_POS 2
bogdanm 0:9b334a45a8ff 152 #define MXC_F_RTC_FLAGS_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCALE_COMP_POS))
bogdanm 0:9b334a45a8ff 153 #define MXC_F_RTC_FLAGS_OVERFLOW_POS 3
bogdanm 0:9b334a45a8ff 154 #define MXC_F_RTC_FLAGS_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_POS))
bogdanm 0:9b334a45a8ff 155 #define MXC_F_RTC_FLAGS_TRIM_POS 4
bogdanm 0:9b334a45a8ff 156 #define MXC_F_RTC_FLAGS_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_POS))
bogdanm 0:9b334a45a8ff 157 #define MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS 8
bogdanm 0:9b334a45a8ff 158 #define MXC_F_RTC_FLAGS_COMP0_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS))
bogdanm 0:9b334a45a8ff 159 #define MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS 9
bogdanm 0:9b334a45a8ff 160 #define MXC_F_RTC_FLAGS_COMP1_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS))
bogdanm 0:9b334a45a8ff 161 #define MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS 10
bogdanm 0:9b334a45a8ff 162 #define MXC_F_RTC_FLAGS_PRESCL_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS))
bogdanm 0:9b334a45a8ff 163 #define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS 11
bogdanm 0:9b334a45a8ff 164 #define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS))
bogdanm 0:9b334a45a8ff 165 #define MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS 12
bogdanm 0:9b334a45a8ff 166 #define MXC_F_RTC_FLAGS_TRIM_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS))
bogdanm 0:9b334a45a8ff 167 #define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS 31
bogdanm 0:9b334a45a8ff 168 #define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS))
bogdanm 0:9b334a45a8ff 169
bogdanm 0:9b334a45a8ff 170 #define MXC_F_RTC_INTEN_COMP0_POS 0
bogdanm 0:9b334a45a8ff 171 #define MXC_F_RTC_INTEN_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP0_POS))
bogdanm 0:9b334a45a8ff 172 #define MXC_F_RTC_INTEN_COMP1_POS 1
bogdanm 0:9b334a45a8ff 173 #define MXC_F_RTC_INTEN_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP1_POS))
bogdanm 0:9b334a45a8ff 174 #define MXC_F_RTC_INTEN_PRESCALE_COMP_POS 2
bogdanm 0:9b334a45a8ff 175 #define MXC_F_RTC_INTEN_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_PRESCALE_COMP_POS))
bogdanm 0:9b334a45a8ff 176 #define MXC_F_RTC_INTEN_OVERFLOW_POS 3
bogdanm 0:9b334a45a8ff 177 #define MXC_F_RTC_INTEN_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_OVERFLOW_POS))
bogdanm 0:9b334a45a8ff 178 #define MXC_F_RTC_INTEN_TRIM_POS 4
bogdanm 0:9b334a45a8ff 179 #define MXC_F_RTC_INTEN_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_TRIM_POS))
bogdanm 0:9b334a45a8ff 180
bogdanm 0:9b334a45a8ff 181 #define MXC_F_RTC_PRESCALE_WIDTH_SELECTION_POS 0
bogdanm 0:9b334a45a8ff 182 #define MXC_F_RTC_PRESCALE_WIDTH_SELECTION ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_WIDTH_SELECTION_POS))
bogdanm 0:9b334a45a8ff 183
bogdanm 0:9b334a45a8ff 184 #define MXC_F_RTC_PRESCALE_MASK_COMP_MASK_POS 0
bogdanm 0:9b334a45a8ff 185 #define MXC_F_RTC_PRESCALE_MASK_COMP_MASK ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_MASK_COMP_MASK_POS))
bogdanm 0:9b334a45a8ff 186
bogdanm 0:9b334a45a8ff 187 #define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS 0
bogdanm 0:9b334a45a8ff 188 #define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS))
bogdanm 0:9b334a45a8ff 189 #define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS 1
bogdanm 0:9b334a45a8ff 190 #define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS))
bogdanm 0:9b334a45a8ff 191 #define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS 2
bogdanm 0:9b334a45a8ff 192 #define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS))
bogdanm 0:9b334a45a8ff 193
bogdanm 0:9b334a45a8ff 194 #define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS 0
bogdanm 0:9b334a45a8ff 195 #define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE ((uint32_t)(0x0003FFFFUL << MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS))
bogdanm 0:9b334a45a8ff 196 #define MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL_POS 18
bogdanm 0:9b334a45a8ff 197 #define MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL_POS))
bogdanm 0:9b334a45a8ff 198
bogdanm 0:9b334a45a8ff 199 #define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS 0
bogdanm 0:9b334a45a8ff 200 #define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER ((uint32_t)(0x0000FFFFUL << MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS))
bogdanm 0:9b334a45a8ff 201
bogdanm 0:9b334a45a8ff 202 #define MXC_F_RTC_CLK_CTRL_OSC1_EN_POS 0
bogdanm 0:9b334a45a8ff 203 #define MXC_F_RTC_CLK_CTRL_OSC1_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC1_EN_POS))
bogdanm 0:9b334a45a8ff 204 #define MXC_F_RTC_CLK_CTRL_OSC2_EN_POS 1
bogdanm 0:9b334a45a8ff 205 #define MXC_F_RTC_CLK_CTRL_OSC2_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC2_EN_POS))
bogdanm 0:9b334a45a8ff 206 #define MXC_F_RTC_CLK_CTRL_NANO_EN_POS 2
bogdanm 0:9b334a45a8ff 207 #define MXC_F_RTC_CLK_CTRL_NANO_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_NANO_EN_POS))
bogdanm 0:9b334a45a8ff 208
bogdanm 0:9b334a45a8ff 209 #define MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE_POS 0
bogdanm 0:9b334a45a8ff 210 #define MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE_POS))
bogdanm 0:9b334a45a8ff 211
bogdanm 0:9b334a45a8ff 212 #define MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS 0
bogdanm 0:9b334a45a8ff 213 #define MXC_F_RTC_OSC_CTRL_OSC_BYPASS ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS))
bogdanm 0:9b334a45a8ff 214 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS 1
bogdanm 0:9b334a45a8ff 215 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS))
bogdanm 0:9b334a45a8ff 216 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS 2
bogdanm 0:9b334a45a8ff 217 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS))
bogdanm 0:9b334a45a8ff 218 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS 3
bogdanm 0:9b334a45a8ff 219 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS))
bogdanm 0:9b334a45a8ff 220
bogdanm 0:9b334a45a8ff 221 /* Offset Register Description
bogdanm 0:9b334a45a8ff 222 ====== ===================================================================== */
bogdanm 0:9b334a45a8ff 223 typedef struct {
bogdanm 0:9b334a45a8ff 224 __IO uint32_t nano_counter; /* 0x0000 Nanoring Counter Read Register */
bogdanm 0:9b334a45a8ff 225 __IO uint32_t clk_ctrl; /* 0x0004 RTC Clock Control Settings */
bogdanm 0:9b334a45a8ff 226 __IO uint32_t dsen_ctrl; /* 0x0008 Dynamic Tamper Sensor Control */
bogdanm 0:9b334a45a8ff 227 __IO uint32_t osc_ctrl; /* 0x000C RTC Oscillator Control */
bogdanm 0:9b334a45a8ff 228 } mxc_rtccfg_regs_t;
bogdanm 0:9b334a45a8ff 229
bogdanm 0:9b334a45a8ff 230 /*
bogdanm 0:9b334a45a8ff 231 Register offsets for module RTCCFG.
bogdanm 0:9b334a45a8ff 232 */
bogdanm 0:9b334a45a8ff 233 #define MXC_R_RTCCFG_OFFS_NANO_COUNTER ((uint32_t)0x00000000UL)
bogdanm 0:9b334a45a8ff 234 #define MXC_R_RTCCFG_OFFS_CLK_CTRL ((uint32_t)0x00000004UL)
bogdanm 0:9b334a45a8ff 235 #define MXC_R_RTCCFG_OFFS_DSEN_CTRL ((uint32_t)0x00000008UL)
bogdanm 0:9b334a45a8ff 236 #define MXC_R_RTCCFG_OFFS_OSC_CTRL ((uint32_t)0x0000000CUL)
bogdanm 0:9b334a45a8ff 237
bogdanm 0:9b334a45a8ff 238 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 239 }
bogdanm 0:9b334a45a8ff 240 #endif
bogdanm 0:9b334a45a8ff 241
bogdanm 0:9b334a45a8ff 242 /**
bogdanm 0:9b334a45a8ff 243 * @}
bogdanm 0:9b334a45a8ff 244 */
bogdanm 0:9b334a45a8ff 245
bogdanm 0:9b334a45a8ff 246 #endif /* _MXC_RTC_REGS_H */