Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pwrseq_regs.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /*******************************************************************************
bogdanm 0:9b334a45a8ff 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Permission is hereby granted, free of charge, to any person obtaining a
bogdanm 0:9b334a45a8ff 5 * copy of this software and associated documentation files (the "Software"),
bogdanm 0:9b334a45a8ff 6 * to deal in the Software without restriction, including without limitation
bogdanm 0:9b334a45a8ff 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
bogdanm 0:9b334a45a8ff 8 * and/or sell copies of the Software, and to permit persons to whom the
bogdanm 0:9b334a45a8ff 9 * Software is furnished to do so, subject to the following conditions:
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * The above copyright notice and this permission notice shall be included
bogdanm 0:9b334a45a8ff 12 * in all copies or substantial portions of the Software.
bogdanm 0:9b334a45a8ff 13 *
bogdanm 0:9b334a45a8ff 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
bogdanm 0:9b334a45a8ff 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
bogdanm 0:9b334a45a8ff 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
bogdanm 0:9b334a45a8ff 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
bogdanm 0:9b334a45a8ff 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
bogdanm 0:9b334a45a8ff 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
bogdanm 0:9b334a45a8ff 20 * OTHER DEALINGS IN THE SOFTWARE.
bogdanm 0:9b334a45a8ff 21 *
bogdanm 0:9b334a45a8ff 22 * Except as contained in this notice, the name of Maxim Integrated
bogdanm 0:9b334a45a8ff 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
bogdanm 0:9b334a45a8ff 24 * Products, Inc. Branding Policy.
bogdanm 0:9b334a45a8ff 25 *
bogdanm 0:9b334a45a8ff 26 * The mere transfer of this software does not imply any licenses
bogdanm 0:9b334a45a8ff 27 * of trade secrets, proprietary technology, copyrights, patents,
bogdanm 0:9b334a45a8ff 28 * trademarks, maskwork rights, or any other form of intellectual
bogdanm 0:9b334a45a8ff 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
bogdanm 0:9b334a45a8ff 30 * ownership rights.
bogdanm 0:9b334a45a8ff 31 *******************************************************************************
bogdanm 0:9b334a45a8ff 32 */
bogdanm 0:9b334a45a8ff 33
bogdanm 0:9b334a45a8ff 34 #ifndef _MXC_PWRSEQ_REGS_H
bogdanm 0:9b334a45a8ff 35 #define _MXC_PWRSEQ_REGS_H
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 38 extern "C" {
bogdanm 0:9b334a45a8ff 39 #endif
bogdanm 0:9b334a45a8ff 40
bogdanm 0:9b334a45a8ff 41 #include <stdint.h>
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 /**
bogdanm 0:9b334a45a8ff 44 * @file pwrseq_regs.h
bogdanm 0:9b334a45a8ff 45 * @addtogroup pwrseq PWRSEQ
bogdanm 0:9b334a45a8ff 46 * @{
bogdanm 0:9b334a45a8ff 47 */
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 /* Offset Register Description
bogdanm 0:9b334a45a8ff 50 ====== ================================================= */
bogdanm 0:9b334a45a8ff 51 typedef struct {
bogdanm 0:9b334a45a8ff 52 __IO uint32_t reg0; /* 0x0000 Power Sequencer Control Register 0 */
bogdanm 0:9b334a45a8ff 53 __IO uint32_t reg1; /* 0x0004 Power Sequencer Control Register 1 */
bogdanm 0:9b334a45a8ff 54 __IO uint32_t reg2; /* 0x0008 Power Sequencer Control Register 2 */
bogdanm 0:9b334a45a8ff 55 __IO uint32_t reg3; /* 0x000C Power Sequencer Control Register 3 */
bogdanm 0:9b334a45a8ff 56 __IO uint32_t reg4; /* 0x0010 Power Sequencer Control Register 4 */
bogdanm 0:9b334a45a8ff 57 __IO uint32_t reg5; /* 0x0014 Power Sequencer Control Register 5 (Trim 0) */
bogdanm 0:9b334a45a8ff 58 __IO uint32_t reg6; /* 0x0018 Power Sequencer Control Register 6 (Trim 1) */
bogdanm 0:9b334a45a8ff 59 __I uint32_t rsv001C; /* 0x001C */
bogdanm 0:9b334a45a8ff 60 __IO uint32_t flags; /* 0x0020 Power Sequencer Flags */
bogdanm 0:9b334a45a8ff 61 __IO uint32_t msk_flags; /* 0x0024 Power Sequencer Flags Mask Register */
bogdanm 0:9b334a45a8ff 62 } mxc_pwrseq_regs_t;
bogdanm 0:9b334a45a8ff 63
bogdanm 0:9b334a45a8ff 64
bogdanm 0:9b334a45a8ff 65 /*
bogdanm 0:9b334a45a8ff 66 Register offsets for module PWRSEQ.
bogdanm 0:9b334a45a8ff 67 */
bogdanm 0:9b334a45a8ff 68 #define MXC_R_PWRSEQ_OFFS_REG0 ((uint32_t)0x00000000UL)
bogdanm 0:9b334a45a8ff 69 #define MXC_R_PWRSEQ_OFFS_REG1 ((uint32_t)0x00000004UL)
bogdanm 0:9b334a45a8ff 70 #define MXC_R_PWRSEQ_OFFS_REG2 ((uint32_t)0x00000008UL)
bogdanm 0:9b334a45a8ff 71 #define MXC_R_PWRSEQ_OFFS_REG3 ((uint32_t)0x0000000CUL)
bogdanm 0:9b334a45a8ff 72 #define MXC_R_PWRSEQ_OFFS_REG4 ((uint32_t)0x00000010UL)
bogdanm 0:9b334a45a8ff 73 #define MXC_R_PWRSEQ_OFFS_REG5 ((uint32_t)0x00000014UL)
bogdanm 0:9b334a45a8ff 74 #define MXC_R_PWRSEQ_OFFS_REG6 ((uint32_t)0x00000018UL)
bogdanm 0:9b334a45a8ff 75 #define MXC_R_PWRSEQ_OFFS_FLAGS ((uint32_t)0x00000020UL)
bogdanm 0:9b334a45a8ff 76 #define MXC_R_PWRSEQ_OFFS_MSK_FLAGS ((uint32_t)0x00000024UL)
bogdanm 0:9b334a45a8ff 77
bogdanm 0:9b334a45a8ff 78
bogdanm 0:9b334a45a8ff 79 /*
bogdanm 0:9b334a45a8ff 80 Field positions and masks for module PWRSEQ.
bogdanm 0:9b334a45a8ff 81 */
bogdanm 0:9b334a45a8ff 82 #define MXC_F_PWRSEQ_REG0_PWR_LP1_POS 0
bogdanm 0:9b334a45a8ff 83 #define MXC_F_PWRSEQ_REG0_PWR_LP1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LP1_POS))
bogdanm 0:9b334a45a8ff 84 #define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS 1
bogdanm 0:9b334a45a8ff 85 #define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS))
bogdanm 0:9b334a45a8ff 86 #define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS 2
bogdanm 0:9b334a45a8ff 87 #define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS))
bogdanm 0:9b334a45a8ff 88 #define MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN_POS 3
bogdanm 0:9b334a45a8ff 89 #define MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN_POS))
bogdanm 0:9b334a45a8ff 90 #define MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP_POS 4
bogdanm 0:9b334a45a8ff 91 #define MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP_POS))
bogdanm 0:9b334a45a8ff 92 #define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN_POS 5
bogdanm 0:9b334a45a8ff 93 #define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN_POS))
bogdanm 0:9b334a45a8ff 94 #define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP_POS 6
bogdanm 0:9b334a45a8ff 95 #define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP_POS))
bogdanm 0:9b334a45a8ff 96 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS 7
bogdanm 0:9b334a45a8ff 97 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS))
bogdanm 0:9b334a45a8ff 98 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS 8
bogdanm 0:9b334a45a8ff 99 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS))
bogdanm 0:9b334a45a8ff 100 #define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS 9
bogdanm 0:9b334a45a8ff 101 #define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS))
bogdanm 0:9b334a45a8ff 102 #define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS 10
bogdanm 0:9b334a45a8ff 103 #define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS))
bogdanm 0:9b334a45a8ff 104 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS 11
bogdanm 0:9b334a45a8ff 105 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS))
bogdanm 0:9b334a45a8ff 106 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS 12
bogdanm 0:9b334a45a8ff 107 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS))
bogdanm 0:9b334a45a8ff 108 #define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN_POS 13
bogdanm 0:9b334a45a8ff 109 #define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN_POS))
bogdanm 0:9b334a45a8ff 110 #define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP_POS 14
bogdanm 0:9b334a45a8ff 111 #define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP_POS))
bogdanm 0:9b334a45a8ff 112 #define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN_POS 15
bogdanm 0:9b334a45a8ff 113 #define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN_POS))
bogdanm 0:9b334a45a8ff 114 #define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP_POS 16
bogdanm 0:9b334a45a8ff 115 #define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP_POS))
bogdanm 0:9b334a45a8ff 116 #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS 17
bogdanm 0:9b334a45a8ff 117 #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS))
bogdanm 0:9b334a45a8ff 118 #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP_POS 18
bogdanm 0:9b334a45a8ff 119 #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP_POS))
bogdanm 0:9b334a45a8ff 120 #define MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN_POS 19
bogdanm 0:9b334a45a8ff 121 #define MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN_POS))
bogdanm 0:9b334a45a8ff 122
bogdanm 0:9b334a45a8ff 123 #define MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG_POS 0
bogdanm 0:9b334a45a8ff 124 #define MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG_POS))
bogdanm 0:9b334a45a8ff 125 #define MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3_POS 8
bogdanm 0:9b334a45a8ff 126 #define MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3_POS))
bogdanm 0:9b334a45a8ff 127 #define MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD_POS 9
bogdanm 0:9b334a45a8ff 128 #define MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD_POS))
bogdanm 0:9b334a45a8ff 129 #define MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO_POS 10
bogdanm 0:9b334a45a8ff 130 #define MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO_POS))
bogdanm 0:9b334a45a8ff 131 #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW_POS 11
bogdanm 0:9b334a45a8ff 132 #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW_POS))
bogdanm 0:9b334a45a8ff 133 #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2_POS 12
bogdanm 0:9b334a45a8ff 134 #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2_POS))
bogdanm 0:9b334a45a8ff 135 #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1_POS 13
bogdanm 0:9b334a45a8ff 136 #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1_POS))
bogdanm 0:9b334a45a8ff 137 #define MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE_POS 14
bogdanm 0:9b334a45a8ff 138 #define MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE_POS))
bogdanm 0:9b334a45a8ff 139
bogdanm 0:9b334a45a8ff 140 #define MXC_F_PWRSEQ_REG2_PWR_RST3_POS 0
bogdanm 0:9b334a45a8ff 141 #define MXC_F_PWRSEQ_REG2_PWR_RST3 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_RST3_POS))
bogdanm 0:9b334a45a8ff 142 #define MXC_F_PWRSEQ_REG2_PWR_W3_POS 5
bogdanm 0:9b334a45a8ff 143 #define MXC_F_PWRSEQ_REG2_PWR_W3 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W3_POS))
bogdanm 0:9b334a45a8ff 144 #define MXC_F_PWRSEQ_REG2_PWR_W1_POS 10
bogdanm 0:9b334a45a8ff 145 #define MXC_F_PWRSEQ_REG2_PWR_W1 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W1_POS))
bogdanm 0:9b334a45a8ff 146 #define MXC_F_PWRSEQ_REG2_PWR_W1_LOW_POS 15
bogdanm 0:9b334a45a8ff 147 #define MXC_F_PWRSEQ_REG2_PWR_W1_LOW ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W1_LOW_POS))
bogdanm 0:9b334a45a8ff 148 #define MXC_F_PWRSEQ_REG2_PWR_WRTC_POS 20
bogdanm 0:9b334a45a8ff 149 #define MXC_F_PWRSEQ_REG2_PWR_WRTC ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_WRTC_POS))
bogdanm 0:9b334a45a8ff 150 #define MXC_F_PWRSEQ_REG2_PWR_WVDDA3_POS 25
bogdanm 0:9b334a45a8ff 151 #define MXC_F_PWRSEQ_REG2_PWR_WVDDA3 ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG2_PWR_WVDDA3_POS))
bogdanm 0:9b334a45a8ff 152
bogdanm 0:9b334a45a8ff 153 #define MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS 0
bogdanm 0:9b334a45a8ff 154 #define MXC_F_PWRSEQ_REG3_PWR_ROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS))
bogdanm 0:9b334a45a8ff 155 #define MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS 3
bogdanm 0:9b334a45a8ff 156 #define MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS))
bogdanm 0:9b334a45a8ff 157 #define MXC_F_PWRSEQ_REG3_PWR_SVMSEL_POS 5
bogdanm 0:9b334a45a8ff 158 #define MXC_F_PWRSEQ_REG3_PWR_SVMSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_SVMSEL_POS))
bogdanm 0:9b334a45a8ff 159 #define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO_POS 8
bogdanm 0:9b334a45a8ff 160 #define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO_POS))
bogdanm 0:9b334a45a8ff 161 #define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL_POS 10
bogdanm 0:9b334a45a8ff 162 #define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL_POS))
bogdanm 0:9b334a45a8ff 163 #define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS 13
bogdanm 0:9b334a45a8ff 164 #define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS))
bogdanm 0:9b334a45a8ff 165 #define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS 15
bogdanm 0:9b334a45a8ff 166 #define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS))
bogdanm 0:9b334a45a8ff 167 #define MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT_POS 16
bogdanm 0:9b334a45a8ff 168 #define MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT_POS))
bogdanm 0:9b334a45a8ff 169 #define MXC_F_PWRSEQ_REG3_PWR_BO_TC_POS 17
bogdanm 0:9b334a45a8ff 170 #define MXC_F_PWRSEQ_REG3_PWR_BO_TC ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_BO_TC_POS))
bogdanm 0:9b334a45a8ff 171
bogdanm 0:9b334a45a8ff 172 #define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS 0
bogdanm 0:9b334a45a8ff 173 #define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS))
bogdanm 0:9b334a45a8ff 174 #define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS 1
bogdanm 0:9b334a45a8ff 175 #define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS))
bogdanm 0:9b334a45a8ff 176 #define MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM_POS 2
bogdanm 0:9b334a45a8ff 177 #define MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM_POS))
bogdanm 0:9b334a45a8ff 178 #define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS 3
bogdanm 0:9b334a45a8ff 179 #define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS))
bogdanm 0:9b334a45a8ff 180 #define MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST_POS 4
bogdanm 0:9b334a45a8ff 181 #define MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST_POS))
bogdanm 0:9b334a45a8ff 182 #define MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF_POS 5
bogdanm 0:9b334a45a8ff 183 #define MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF_POS))
bogdanm 0:9b334a45a8ff 184 #define MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD_POS 6
bogdanm 0:9b334a45a8ff 185 #define MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD_POS))
bogdanm 0:9b334a45a8ff 186
bogdanm 0:9b334a45a8ff 187 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS 0
bogdanm 0:9b334a45a8ff 188 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS))
bogdanm 0:9b334a45a8ff 189 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8_POS 6
bogdanm 0:9b334a45a8ff 190 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8 ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8_POS))
bogdanm 0:9b334a45a8ff 191 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3_POS 10
bogdanm 0:9b334a45a8ff 192 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3_POS))
bogdanm 0:9b334a45a8ff 193 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS 15
bogdanm 0:9b334a45a8ff 194 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF ((uint32_t)(0x0000007FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS))
bogdanm 0:9b334a45a8ff 195
bogdanm 0:9b334a45a8ff 196 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS 0
bogdanm 0:9b334a45a8ff 197 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS))
bogdanm 0:9b334a45a8ff 198 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS 3
bogdanm 0:9b334a45a8ff 199 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS))
bogdanm 0:9b334a45a8ff 200 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS 7
bogdanm 0:9b334a45a8ff 201 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS))
bogdanm 0:9b334a45a8ff 202
bogdanm 0:9b334a45a8ff 203 #define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS 0
bogdanm 0:9b334a45a8ff 204 #define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS))
bogdanm 0:9b334a45a8ff 205 #define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS 1
bogdanm 0:9b334a45a8ff 206 #define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS))
bogdanm 0:9b334a45a8ff 207 #define MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL_POS 2
bogdanm 0:9b334a45a8ff 208 #define MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL_POS))
bogdanm 0:9b334a45a8ff 209 #define MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL_POS 3
bogdanm 0:9b334a45a8ff 210 #define MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL_POS))
bogdanm 0:9b334a45a8ff 211 #define MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP_POS 4
bogdanm 0:9b334a45a8ff 212 #define MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP_POS))
bogdanm 0:9b334a45a8ff 213 #define MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP_POS 5
bogdanm 0:9b334a45a8ff 214 #define MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP_POS))
bogdanm 0:9b334a45a8ff 215 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST_POS 6
bogdanm 0:9b334a45a8ff 216 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST_POS))
bogdanm 0:9b334a45a8ff 217 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN_POS 7
bogdanm 0:9b334a45a8ff 218 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN_POS))
bogdanm 0:9b334a45a8ff 219 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST_POS 8
bogdanm 0:9b334a45a8ff 220 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST_POS))
bogdanm 0:9b334a45a8ff 221 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST_POS 9
bogdanm 0:9b334a45a8ff 222 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST_POS))
bogdanm 0:9b334a45a8ff 223 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN_POS 10
bogdanm 0:9b334a45a8ff 224 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN_POS))
bogdanm 0:9b334a45a8ff 225 #define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN_POS 11
bogdanm 0:9b334a45a8ff 226 #define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN_POS))
bogdanm 0:9b334a45a8ff 227 #define MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL_POS 12
bogdanm 0:9b334a45a8ff 228 #define MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL_POS))
bogdanm 0:9b334a45a8ff 229 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS 13
bogdanm 0:9b334a45a8ff 230 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS))
bogdanm 0:9b334a45a8ff 231 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS 14
bogdanm 0:9b334a45a8ff 232 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS))
bogdanm 0:9b334a45a8ff 233 #define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS 15
bogdanm 0:9b334a45a8ff 234 #define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS))
bogdanm 0:9b334a45a8ff 235 #define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS 16
bogdanm 0:9b334a45a8ff 236 #define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS))
bogdanm 0:9b334a45a8ff 237 #define MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET_POS 17
bogdanm 0:9b334a45a8ff 238 #define MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET_POS))
bogdanm 0:9b334a45a8ff 239 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS 18
bogdanm 0:9b334a45a8ff 240 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
bogdanm 0:9b334a45a8ff 241 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 19
bogdanm 0:9b334a45a8ff 242 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
bogdanm 0:9b334a45a8ff 243 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST_POS 20
bogdanm 0:9b334a45a8ff 244 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST_POS))
bogdanm 0:9b334a45a8ff 245 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST_POS 21
bogdanm 0:9b334a45a8ff 246 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST_POS))
bogdanm 0:9b334a45a8ff 247
bogdanm 0:9b334a45a8ff 248 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS 1
bogdanm 0:9b334a45a8ff 249 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS))
bogdanm 0:9b334a45a8ff 250 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL_POS 2
bogdanm 0:9b334a45a8ff 251 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL_POS))
bogdanm 0:9b334a45a8ff 252 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL_POS 3
bogdanm 0:9b334a45a8ff 253 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL_POS))
bogdanm 0:9b334a45a8ff 254 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP_POS 4
bogdanm 0:9b334a45a8ff 255 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP_POS))
bogdanm 0:9b334a45a8ff 256 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP_POS 5
bogdanm 0:9b334a45a8ff 257 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP_POS))
bogdanm 0:9b334a45a8ff 258 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST_POS 6
bogdanm 0:9b334a45a8ff 259 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST_POS))
bogdanm 0:9b334a45a8ff 260 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN_POS 7
bogdanm 0:9b334a45a8ff 261 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN_POS))
bogdanm 0:9b334a45a8ff 262 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST_POS 8
bogdanm 0:9b334a45a8ff 263 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST_POS))
bogdanm 0:9b334a45a8ff 264 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST_POS 9
bogdanm 0:9b334a45a8ff 265 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST_POS))
bogdanm 0:9b334a45a8ff 266 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN_POS 10
bogdanm 0:9b334a45a8ff 267 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN_POS))
bogdanm 0:9b334a45a8ff 268 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN_POS 11
bogdanm 0:9b334a45a8ff 269 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN_POS))
bogdanm 0:9b334a45a8ff 270 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL_POS 12
bogdanm 0:9b334a45a8ff 271 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL_POS))
bogdanm 0:9b334a45a8ff 272 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS 13
bogdanm 0:9b334a45a8ff 273 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS))
bogdanm 0:9b334a45a8ff 274 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS 14
bogdanm 0:9b334a45a8ff 275 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS))
bogdanm 0:9b334a45a8ff 276 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS 15
bogdanm 0:9b334a45a8ff 277 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS))
bogdanm 0:9b334a45a8ff 278 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS 16
bogdanm 0:9b334a45a8ff 279 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS))
bogdanm 0:9b334a45a8ff 280 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET_POS 17
bogdanm 0:9b334a45a8ff 281 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET_POS))
bogdanm 0:9b334a45a8ff 282 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS 18
bogdanm 0:9b334a45a8ff 283 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
bogdanm 0:9b334a45a8ff 284 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 19
bogdanm 0:9b334a45a8ff 285 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
bogdanm 0:9b334a45a8ff 286 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST_POS 20
bogdanm 0:9b334a45a8ff 287 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST_POS))
bogdanm 0:9b334a45a8ff 288 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST_POS 21
bogdanm 0:9b334a45a8ff 289 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST_POS))
bogdanm 0:9b334a45a8ff 290
bogdanm 0:9b334a45a8ff 291 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 292 }
bogdanm 0:9b334a45a8ff 293 #endif
bogdanm 0:9b334a45a8ff 294
bogdanm 0:9b334a45a8ff 295 /**
bogdanm 0:9b334a45a8ff 296 * @}
bogdanm 0:9b334a45a8ff 297 */
bogdanm 0:9b334a45a8ff 298
bogdanm 0:9b334a45a8ff 299 #endif /* _MXC_PWRSEQ_REGS_H */