Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Maxim/TARGET_MAX32610/gpio_regs.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /*******************************************************************************
bogdanm 0:9b334a45a8ff 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Permission is hereby granted, free of charge, to any person obtaining a
bogdanm 0:9b334a45a8ff 5 * copy of this software and associated documentation files (the "Software"),
bogdanm 0:9b334a45a8ff 6 * to deal in the Software without restriction, including without limitation
bogdanm 0:9b334a45a8ff 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
bogdanm 0:9b334a45a8ff 8 * and/or sell copies of the Software, and to permit persons to whom the
bogdanm 0:9b334a45a8ff 9 * Software is furnished to do so, subject to the following conditions:
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * The above copyright notice and this permission notice shall be included
bogdanm 0:9b334a45a8ff 12 * in all copies or substantial portions of the Software.
bogdanm 0:9b334a45a8ff 13 *
bogdanm 0:9b334a45a8ff 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
bogdanm 0:9b334a45a8ff 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
bogdanm 0:9b334a45a8ff 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
bogdanm 0:9b334a45a8ff 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
bogdanm 0:9b334a45a8ff 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
bogdanm 0:9b334a45a8ff 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
bogdanm 0:9b334a45a8ff 20 * OTHER DEALINGS IN THE SOFTWARE.
bogdanm 0:9b334a45a8ff 21 *
bogdanm 0:9b334a45a8ff 22 * Except as contained in this notice, the name of Maxim Integrated
bogdanm 0:9b334a45a8ff 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
bogdanm 0:9b334a45a8ff 24 * Products, Inc. Branding Policy.
bogdanm 0:9b334a45a8ff 25 *
bogdanm 0:9b334a45a8ff 26 * The mere transfer of this software does not imply any licenses
bogdanm 0:9b334a45a8ff 27 * of trade secrets, proprietary technology, copyrights, patents,
bogdanm 0:9b334a45a8ff 28 * trademarks, maskwork rights, or any other form of intellectual
bogdanm 0:9b334a45a8ff 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
bogdanm 0:9b334a45a8ff 30 * ownership rights.
bogdanm 0:9b334a45a8ff 31 *******************************************************************************
bogdanm 0:9b334a45a8ff 32 */
bogdanm 0:9b334a45a8ff 33
bogdanm 0:9b334a45a8ff 34 #ifndef _MXC_GPIO_REGS_H_
bogdanm 0:9b334a45a8ff 35 #define _MXC_GPIO_REGS_H_
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 38 extern "C" {
bogdanm 0:9b334a45a8ff 39 #endif
bogdanm 0:9b334a45a8ff 40
bogdanm 0:9b334a45a8ff 41 #include <stdint.h>
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 /**
bogdanm 0:9b334a45a8ff 44 * @file gpio_regs.h
bogdanm 0:9b334a45a8ff 45 * @addtogroup gpio GPIO
bogdanm 0:9b334a45a8ff 46 * @{
bogdanm 0:9b334a45a8ff 47 */
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 /* Offset Register Description
bogdanm 0:9b334a45a8ff 50 ============= ========================================== */
bogdanm 0:9b334a45a8ff 51 typedef struct {
bogdanm 0:9b334a45a8ff 52 __I uint32_t rsv000[16]; /* 0x0000-0x003C */
bogdanm 0:9b334a45a8ff 53
bogdanm 0:9b334a45a8ff 54 __IO uint32_t free[8]; /* 0x0040-0x005C Port P[0..7] Free for GPIO Operation Flags */
bogdanm 0:9b334a45a8ff 55 __I uint32_t rsv060[8]; /* 0x0060-0x007C */
bogdanm 0:9b334a45a8ff 56
bogdanm 0:9b334a45a8ff 57 __IO uint32_t out_mode[8]; /* 0x0080-0x009C Port P[0..7] GPIO Output Drive Mode */
bogdanm 0:9b334a45a8ff 58 __I uint32_t rsv0A0[8]; /* 0x00A0-0x00BC */
bogdanm 0:9b334a45a8ff 59
bogdanm 0:9b334a45a8ff 60 __IO uint32_t out_val[8]; /* 0x00C0-0x00DC Port P[0..7] GPIO Output Value */
bogdanm 0:9b334a45a8ff 61 __I uint32_t rsv0E0[8]; /* 0x00E0-0x00FC */
bogdanm 0:9b334a45a8ff 62
bogdanm 0:9b334a45a8ff 63 __IO uint32_t func_sel[8]; /* 0x0100-0x011C Port P[0..7] GPIO Function Select */
bogdanm 0:9b334a45a8ff 64 __I uint32_t rsv120[8]; /* 0x0120-0x013C */
bogdanm 0:9b334a45a8ff 65
bogdanm 0:9b334a45a8ff 66 __IO uint32_t in_mode[8]; /* 0x0140-0x015C Port P[0..7] GPIO Input Monitoring Mode */
bogdanm 0:9b334a45a8ff 67 __I uint32_t rsv160[8]; /* 0x0160-0x017C */
bogdanm 0:9b334a45a8ff 68
bogdanm 0:9b334a45a8ff 69 __IO uint32_t in_val[8]; /* 0x0180-0x019C Port P[0..7] GPIO Input Value */
bogdanm 0:9b334a45a8ff 70 __I uint32_t rsv1A0[8]; /* 0x01A0-0x01BC */
bogdanm 0:9b334a45a8ff 71
bogdanm 0:9b334a45a8ff 72 __IO uint32_t int_mode[8]; /* 0x01C0-0x01DC Port P[0..7] Interrupt Detection Mode */
bogdanm 0:9b334a45a8ff 73 __I uint32_t rsv1E0[8]; /* 0x01E0-0x01FC */
bogdanm 0:9b334a45a8ff 74
bogdanm 0:9b334a45a8ff 75 __IO uint32_t intfl[8]; /* 0x0200-0x021C Port P[0..7] Interrupt Flags */
bogdanm 0:9b334a45a8ff 76 __I uint32_t rsv220[8]; /* 0x0220-0x023C */
bogdanm 0:9b334a45a8ff 77
bogdanm 0:9b334a45a8ff 78 __IO uint32_t inten[8]; /* 0x0240-0x025C Port P[0..7] Interrupt Enables */
bogdanm 0:9b334a45a8ff 79 } mxc_gpio_regs_t;
bogdanm 0:9b334a45a8ff 80
bogdanm 0:9b334a45a8ff 81 /*
bogdanm 0:9b334a45a8ff 82 Register offsets for module GPIO.
bogdanm 0:9b334a45a8ff 83 */
bogdanm 0:9b334a45a8ff 84 #define MXC_R_GPIO_OFFS_FREE_P0 ((uint32_t)0x00000040UL)
bogdanm 0:9b334a45a8ff 85 #define MXC_R_GPIO_OFFS_FREE_P1 ((uint32_t)0x00000044UL)
bogdanm 0:9b334a45a8ff 86 #define MXC_R_GPIO_OFFS_FREE_P2 ((uint32_t)0x00000048UL)
bogdanm 0:9b334a45a8ff 87 #define MXC_R_GPIO_OFFS_FREE_P3 ((uint32_t)0x0000004CUL)
bogdanm 0:9b334a45a8ff 88 #define MXC_R_GPIO_OFFS_FREE_P4 ((uint32_t)0x00000050UL)
bogdanm 0:9b334a45a8ff 89 #define MXC_R_GPIO_OFFS_FREE_P5 ((uint32_t)0x00000054UL)
bogdanm 0:9b334a45a8ff 90 #define MXC_R_GPIO_OFFS_FREE_P6 ((uint32_t)0x00000058UL)
bogdanm 0:9b334a45a8ff 91 #define MXC_R_GPIO_OFFS_FREE_P7 ((uint32_t)0x0000005CUL)
bogdanm 0:9b334a45a8ff 92 #define MXC_R_GPIO_OFFS_OUT_MODE_P0 ((uint32_t)0x00000080UL)
bogdanm 0:9b334a45a8ff 93 #define MXC_R_GPIO_OFFS_OUT_MODE_P1 ((uint32_t)0x00000084UL)
bogdanm 0:9b334a45a8ff 94 #define MXC_R_GPIO_OFFS_OUT_MODE_P2 ((uint32_t)0x00000088UL)
bogdanm 0:9b334a45a8ff 95 #define MXC_R_GPIO_OFFS_OUT_MODE_P3 ((uint32_t)0x0000008CUL)
bogdanm 0:9b334a45a8ff 96 #define MXC_R_GPIO_OFFS_OUT_MODE_P4 ((uint32_t)0x00000090UL)
bogdanm 0:9b334a45a8ff 97 #define MXC_R_GPIO_OFFS_OUT_MODE_P5 ((uint32_t)0x00000094UL)
bogdanm 0:9b334a45a8ff 98 #define MXC_R_GPIO_OFFS_OUT_MODE_P6 ((uint32_t)0x00000098UL)
bogdanm 0:9b334a45a8ff 99 #define MXC_R_GPIO_OFFS_OUT_MODE_P7 ((uint32_t)0x0000009CUL)
bogdanm 0:9b334a45a8ff 100 #define MXC_R_GPIO_OFFS_OUT_VAL_P0 ((uint32_t)0x000000C0UL)
bogdanm 0:9b334a45a8ff 101 #define MXC_R_GPIO_OFFS_OUT_VAL_P1 ((uint32_t)0x000000C4UL)
bogdanm 0:9b334a45a8ff 102 #define MXC_R_GPIO_OFFS_OUT_VAL_P2 ((uint32_t)0x000000C8UL)
bogdanm 0:9b334a45a8ff 103 #define MXC_R_GPIO_OFFS_OUT_VAL_P3 ((uint32_t)0x000000CCUL)
bogdanm 0:9b334a45a8ff 104 #define MXC_R_GPIO_OFFS_OUT_VAL_P4 ((uint32_t)0x000000D0UL)
bogdanm 0:9b334a45a8ff 105 #define MXC_R_GPIO_OFFS_OUT_VAL_P5 ((uint32_t)0x000000D4UL)
bogdanm 0:9b334a45a8ff 106 #define MXC_R_GPIO_OFFS_OUT_VAL_P6 ((uint32_t)0x000000D8UL)
bogdanm 0:9b334a45a8ff 107 #define MXC_R_GPIO_OFFS_OUT_VAL_P7 ((uint32_t)0x000000DCUL)
bogdanm 0:9b334a45a8ff 108 #define MXC_R_GPIO_OFFS_FUNC_SEL_P0 ((uint32_t)0x00000100UL)
bogdanm 0:9b334a45a8ff 109 #define MXC_R_GPIO_OFFS_FUNC_SEL_P1 ((uint32_t)0x00000104UL)
bogdanm 0:9b334a45a8ff 110 #define MXC_R_GPIO_OFFS_FUNC_SEL_P2 ((uint32_t)0x00000108UL)
bogdanm 0:9b334a45a8ff 111 #define MXC_R_GPIO_OFFS_FUNC_SEL_P6 ((uint32_t)0x00000118UL)
bogdanm 0:9b334a45a8ff 112 #define MXC_R_GPIO_OFFS_FUNC_SEL_P7 ((uint32_t)0x0000011CUL)
bogdanm 0:9b334a45a8ff 113 #define MXC_R_GPIO_OFFS_IN_MODE_P0 ((uint32_t)0x00000140UL)
bogdanm 0:9b334a45a8ff 114 #define MXC_R_GPIO_OFFS_IN_MODE_P1 ((uint32_t)0x00000144UL)
bogdanm 0:9b334a45a8ff 115 #define MXC_R_GPIO_OFFS_IN_MODE_P2 ((uint32_t)0x00000148UL)
bogdanm 0:9b334a45a8ff 116 #define MXC_R_GPIO_OFFS_IN_MODE_P3 ((uint32_t)0x0000014CUL)
bogdanm 0:9b334a45a8ff 117 #define MXC_R_GPIO_OFFS_IN_MODE_P4 ((uint32_t)0x00000150UL)
bogdanm 0:9b334a45a8ff 118 #define MXC_R_GPIO_OFFS_IN_MODE_P5 ((uint32_t)0x00000154UL)
bogdanm 0:9b334a45a8ff 119 #define MXC_R_GPIO_OFFS_IN_MODE_P6 ((uint32_t)0x00000158UL)
bogdanm 0:9b334a45a8ff 120 #define MXC_R_GPIO_OFFS_IN_MODE_P7 ((uint32_t)0x0000015CUL)
bogdanm 0:9b334a45a8ff 121 #define MXC_R_GPIO_OFFS_IN_VAL_P0 ((uint32_t)0x00000180UL)
bogdanm 0:9b334a45a8ff 122 #define MXC_R_GPIO_OFFS_IN_VAL_P1 ((uint32_t)0x00000184UL)
bogdanm 0:9b334a45a8ff 123 #define MXC_R_GPIO_OFFS_IN_VAL_P2 ((uint32_t)0x00000188UL)
bogdanm 0:9b334a45a8ff 124 #define MXC_R_GPIO_OFFS_IN_VAL_P3 ((uint32_t)0x0000018CUL)
bogdanm 0:9b334a45a8ff 125 #define MXC_R_GPIO_OFFS_IN_VAL_P4 ((uint32_t)0x00000190UL)
bogdanm 0:9b334a45a8ff 126 #define MXC_R_GPIO_OFFS_IN_VAL_P5 ((uint32_t)0x00000194UL)
bogdanm 0:9b334a45a8ff 127 #define MXC_R_GPIO_OFFS_IN_VAL_P6 ((uint32_t)0x00000198UL)
bogdanm 0:9b334a45a8ff 128 #define MXC_R_GPIO_OFFS_IN_VAL_P7 ((uint32_t)0x0000019CUL)
bogdanm 0:9b334a45a8ff 129 #define MXC_R_GPIO_OFFS_INT_MODE_P0 ((uint32_t)0x000001C0UL)
bogdanm 0:9b334a45a8ff 130 #define MXC_R_GPIO_OFFS_INT_MODE_P1 ((uint32_t)0x000001C4UL)
bogdanm 0:9b334a45a8ff 131 #define MXC_R_GPIO_OFFS_INT_MODE_P2 ((uint32_t)0x000001C8UL)
bogdanm 0:9b334a45a8ff 132 #define MXC_R_GPIO_OFFS_INT_MODE_P3 ((uint32_t)0x000001CCUL)
bogdanm 0:9b334a45a8ff 133 #define MXC_R_GPIO_OFFS_INT_MODE_P4 ((uint32_t)0x000001D0UL)
bogdanm 0:9b334a45a8ff 134 #define MXC_R_GPIO_OFFS_INT_MODE_P5 ((uint32_t)0x000001D4UL)
bogdanm 0:9b334a45a8ff 135 #define MXC_R_GPIO_OFFS_INT_MODE_P6 ((uint32_t)0x000001D8UL)
bogdanm 0:9b334a45a8ff 136 #define MXC_R_GPIO_OFFS_INT_MODE_P7 ((uint32_t)0x000001DCUL)
bogdanm 0:9b334a45a8ff 137 #define MXC_R_GPIO_OFFS_INTFL_P0 ((uint32_t)0x00000200UL)
bogdanm 0:9b334a45a8ff 138 #define MXC_R_GPIO_OFFS_INTFL_P1 ((uint32_t)0x00000204UL)
bogdanm 0:9b334a45a8ff 139 #define MXC_R_GPIO_OFFS_INTFL_P2 ((uint32_t)0x00000208UL)
bogdanm 0:9b334a45a8ff 140 #define MXC_R_GPIO_OFFS_INTFL_P3 ((uint32_t)0x0000020CUL)
bogdanm 0:9b334a45a8ff 141 #define MXC_R_GPIO_OFFS_INTFL_P4 ((uint32_t)0x00000210UL)
bogdanm 0:9b334a45a8ff 142 #define MXC_R_GPIO_OFFS_INTFL_P5 ((uint32_t)0x00000214UL)
bogdanm 0:9b334a45a8ff 143 #define MXC_R_GPIO_OFFS_INTFL_P6 ((uint32_t)0x00000218UL)
bogdanm 0:9b334a45a8ff 144 #define MXC_R_GPIO_OFFS_INTFL_P7 ((uint32_t)0x0000021CUL)
bogdanm 0:9b334a45a8ff 145 #define MXC_R_GPIO_OFFS_INTEN_P0 ((uint32_t)0x00000240UL)
bogdanm 0:9b334a45a8ff 146 #define MXC_R_GPIO_OFFS_INTEN_P1 ((uint32_t)0x00000244UL)
bogdanm 0:9b334a45a8ff 147 #define MXC_R_GPIO_OFFS_INTEN_P2 ((uint32_t)0x00000248UL)
bogdanm 0:9b334a45a8ff 148 #define MXC_R_GPIO_OFFS_INTEN_P3 ((uint32_t)0x0000024CUL)
bogdanm 0:9b334a45a8ff 149 #define MXC_R_GPIO_OFFS_INTEN_P4 ((uint32_t)0x00000250UL)
bogdanm 0:9b334a45a8ff 150 #define MXC_R_GPIO_OFFS_INTEN_P5 ((uint32_t)0x00000254UL)
bogdanm 0:9b334a45a8ff 151 #define MXC_R_GPIO_OFFS_INTEN_P6 ((uint32_t)0x00000258UL)
bogdanm 0:9b334a45a8ff 152 #define MXC_R_GPIO_OFFS_INTEN_P7 ((uint32_t)0x0000025CUL)
bogdanm 0:9b334a45a8ff 153
bogdanm 0:9b334a45a8ff 154
bogdanm 0:9b334a45a8ff 155 /*
bogdanm 0:9b334a45a8ff 156 Field positions and masks for module GPIO.
bogdanm 0:9b334a45a8ff 157 */
bogdanm 0:9b334a45a8ff 158 #define MXC_F_GPIO_FREE_PIN0_POS 0
bogdanm 0:9b334a45a8ff 159 #define MXC_F_GPIO_FREE_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN0_POS))
bogdanm 0:9b334a45a8ff 160 #define MXC_F_GPIO_FREE_PIN1_POS 1
bogdanm 0:9b334a45a8ff 161 #define MXC_F_GPIO_FREE_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN1_POS))
bogdanm 0:9b334a45a8ff 162 #define MXC_F_GPIO_FREE_PIN2_POS 2
bogdanm 0:9b334a45a8ff 163 #define MXC_F_GPIO_FREE_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN2_POS))
bogdanm 0:9b334a45a8ff 164 #define MXC_F_GPIO_FREE_PIN3_POS 3
bogdanm 0:9b334a45a8ff 165 #define MXC_F_GPIO_FREE_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN3_POS))
bogdanm 0:9b334a45a8ff 166 #define MXC_F_GPIO_FREE_PIN4_POS 4
bogdanm 0:9b334a45a8ff 167 #define MXC_F_GPIO_FREE_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN4_POS))
bogdanm 0:9b334a45a8ff 168 #define MXC_F_GPIO_FREE_PIN5_POS 5
bogdanm 0:9b334a45a8ff 169 #define MXC_F_GPIO_FREE_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN5_POS))
bogdanm 0:9b334a45a8ff 170 #define MXC_F_GPIO_FREE_PIN6_POS 6
bogdanm 0:9b334a45a8ff 171 #define MXC_F_GPIO_FREE_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN6_POS))
bogdanm 0:9b334a45a8ff 172 #define MXC_F_GPIO_FREE_PIN7_POS 7
bogdanm 0:9b334a45a8ff 173 #define MXC_F_GPIO_FREE_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN7_POS))
bogdanm 0:9b334a45a8ff 174
bogdanm 0:9b334a45a8ff 175 #define MXC_F_GPIO_OUT_MODE_PIN0_POS 0
bogdanm 0:9b334a45a8ff 176 #define MXC_F_GPIO_OUT_MODE_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN0_POS))
bogdanm 0:9b334a45a8ff 177 #define MXC_F_GPIO_OUT_MODE_PIN1_POS 4
bogdanm 0:9b334a45a8ff 178 #define MXC_F_GPIO_OUT_MODE_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN1_POS))
bogdanm 0:9b334a45a8ff 179 #define MXC_F_GPIO_OUT_MODE_PIN2_POS 8
bogdanm 0:9b334a45a8ff 180 #define MXC_F_GPIO_OUT_MODE_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN2_POS))
bogdanm 0:9b334a45a8ff 181 #define MXC_F_GPIO_OUT_MODE_PIN3_POS 12
bogdanm 0:9b334a45a8ff 182 #define MXC_F_GPIO_OUT_MODE_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN3_POS))
bogdanm 0:9b334a45a8ff 183 #define MXC_F_GPIO_OUT_MODE_PIN4_POS 16
bogdanm 0:9b334a45a8ff 184 #define MXC_F_GPIO_OUT_MODE_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN4_POS))
bogdanm 0:9b334a45a8ff 185 #define MXC_F_GPIO_OUT_MODE_PIN5_POS 20
bogdanm 0:9b334a45a8ff 186 #define MXC_F_GPIO_OUT_MODE_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN5_POS))
bogdanm 0:9b334a45a8ff 187 #define MXC_F_GPIO_OUT_MODE_PIN6_POS 24
bogdanm 0:9b334a45a8ff 188 #define MXC_F_GPIO_OUT_MODE_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN6_POS))
bogdanm 0:9b334a45a8ff 189 #define MXC_F_GPIO_OUT_MODE_PIN7_POS 28
bogdanm 0:9b334a45a8ff 190 #define MXC_F_GPIO_OUT_MODE_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN7_POS))
bogdanm 0:9b334a45a8ff 191
bogdanm 0:9b334a45a8ff 192 #define MXC_F_GPIO_OUT_VAL_PIN0_POS 0
bogdanm 0:9b334a45a8ff 193 #define MXC_F_GPIO_OUT_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN0_POS))
bogdanm 0:9b334a45a8ff 194 #define MXC_F_GPIO_OUT_VAL_PIN1_POS 1
bogdanm 0:9b334a45a8ff 195 #define MXC_F_GPIO_OUT_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN1_POS))
bogdanm 0:9b334a45a8ff 196 #define MXC_F_GPIO_OUT_VAL_PIN2_POS 2
bogdanm 0:9b334a45a8ff 197 #define MXC_F_GPIO_OUT_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN2_POS))
bogdanm 0:9b334a45a8ff 198 #define MXC_F_GPIO_OUT_VAL_PIN3_POS 3
bogdanm 0:9b334a45a8ff 199 #define MXC_F_GPIO_OUT_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN3_POS))
bogdanm 0:9b334a45a8ff 200 #define MXC_F_GPIO_OUT_VAL_PIN4_POS 4
bogdanm 0:9b334a45a8ff 201 #define MXC_F_GPIO_OUT_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN4_POS))
bogdanm 0:9b334a45a8ff 202 #define MXC_F_GPIO_OUT_VAL_PIN5_POS 5
bogdanm 0:9b334a45a8ff 203 #define MXC_F_GPIO_OUT_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN5_POS))
bogdanm 0:9b334a45a8ff 204 #define MXC_F_GPIO_OUT_VAL_PIN6_POS 6
bogdanm 0:9b334a45a8ff 205 #define MXC_F_GPIO_OUT_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN6_POS))
bogdanm 0:9b334a45a8ff 206 #define MXC_F_GPIO_OUT_VAL_PIN7_POS 7
bogdanm 0:9b334a45a8ff 207 #define MXC_F_GPIO_OUT_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN7_POS))
bogdanm 0:9b334a45a8ff 208
bogdanm 0:9b334a45a8ff 209 #define MXC_F_GPIO_FUNC_SEL_PIN0_POS 0
bogdanm 0:9b334a45a8ff 210 #define MXC_F_GPIO_FUNC_SEL_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN0_POS))
bogdanm 0:9b334a45a8ff 211 #define MXC_F_GPIO_FUNC_SEL_PIN1_POS 4
bogdanm 0:9b334a45a8ff 212 #define MXC_F_GPIO_FUNC_SEL_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN1_POS))
bogdanm 0:9b334a45a8ff 213 #define MXC_F_GPIO_FUNC_SEL_PIN2_POS 8
bogdanm 0:9b334a45a8ff 214 #define MXC_F_GPIO_FUNC_SEL_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN2_POS))
bogdanm 0:9b334a45a8ff 215 #define MXC_F_GPIO_FUNC_SEL_PIN3_POS 12
bogdanm 0:9b334a45a8ff 216 #define MXC_F_GPIO_FUNC_SEL_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN3_POS))
bogdanm 0:9b334a45a8ff 217 #define MXC_F_GPIO_FUNC_SEL_PIN4_POS 16
bogdanm 0:9b334a45a8ff 218 #define MXC_F_GPIO_FUNC_SEL_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN4_POS))
bogdanm 0:9b334a45a8ff 219 #define MXC_F_GPIO_FUNC_SEL_PIN5_POS 20
bogdanm 0:9b334a45a8ff 220 #define MXC_F_GPIO_FUNC_SEL_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN5_POS))
bogdanm 0:9b334a45a8ff 221 #define MXC_F_GPIO_FUNC_SEL_PIN6_POS 24
bogdanm 0:9b334a45a8ff 222 #define MXC_F_GPIO_FUNC_SEL_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN6_POS))
bogdanm 0:9b334a45a8ff 223 #define MXC_F_GPIO_FUNC_SEL_PIN7_POS 28
bogdanm 0:9b334a45a8ff 224 #define MXC_F_GPIO_FUNC_SEL_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN7_POS))
bogdanm 0:9b334a45a8ff 225
bogdanm 0:9b334a45a8ff 226 #define MXC_F_GPIO_IN_MODE_PIN0_POS 0
bogdanm 0:9b334a45a8ff 227 #define MXC_F_GPIO_IN_MODE_PIN0 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN0_POS))
bogdanm 0:9b334a45a8ff 228 #define MXC_F_GPIO_IN_MODE_PIN1_POS 4
bogdanm 0:9b334a45a8ff 229 #define MXC_F_GPIO_IN_MODE_PIN1 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN1_POS))
bogdanm 0:9b334a45a8ff 230 #define MXC_F_GPIO_IN_MODE_PIN2_POS 8
bogdanm 0:9b334a45a8ff 231 #define MXC_F_GPIO_IN_MODE_PIN2 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN2_POS))
bogdanm 0:9b334a45a8ff 232 #define MXC_F_GPIO_IN_MODE_PIN3_POS 12
bogdanm 0:9b334a45a8ff 233 #define MXC_F_GPIO_IN_MODE_PIN3 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN3_POS))
bogdanm 0:9b334a45a8ff 234 #define MXC_F_GPIO_IN_MODE_PIN4_POS 16
bogdanm 0:9b334a45a8ff 235 #define MXC_F_GPIO_IN_MODE_PIN4 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN4_POS))
bogdanm 0:9b334a45a8ff 236 #define MXC_F_GPIO_IN_MODE_PIN5_POS 20
bogdanm 0:9b334a45a8ff 237 #define MXC_F_GPIO_IN_MODE_PIN5 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN5_POS))
bogdanm 0:9b334a45a8ff 238 #define MXC_F_GPIO_IN_MODE_PIN6_POS 24
bogdanm 0:9b334a45a8ff 239 #define MXC_F_GPIO_IN_MODE_PIN6 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN6_POS))
bogdanm 0:9b334a45a8ff 240 #define MXC_F_GPIO_IN_MODE_PIN7_POS 28
bogdanm 0:9b334a45a8ff 241 #define MXC_F_GPIO_IN_MODE_PIN7 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN7_POS))
bogdanm 0:9b334a45a8ff 242
bogdanm 0:9b334a45a8ff 243 #define MXC_F_GPIO_IN_VAL_PIN0_POS 0
bogdanm 0:9b334a45a8ff 244 #define MXC_F_GPIO_IN_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN0_POS))
bogdanm 0:9b334a45a8ff 245 #define MXC_F_GPIO_IN_VAL_PIN1_POS 1
bogdanm 0:9b334a45a8ff 246 #define MXC_F_GPIO_IN_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN1_POS))
bogdanm 0:9b334a45a8ff 247 #define MXC_F_GPIO_IN_VAL_PIN2_POS 2
bogdanm 0:9b334a45a8ff 248 #define MXC_F_GPIO_IN_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN2_POS))
bogdanm 0:9b334a45a8ff 249 #define MXC_F_GPIO_IN_VAL_PIN3_POS 3
bogdanm 0:9b334a45a8ff 250 #define MXC_F_GPIO_IN_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN3_POS))
bogdanm 0:9b334a45a8ff 251 #define MXC_F_GPIO_IN_VAL_PIN4_POS 4
bogdanm 0:9b334a45a8ff 252 #define MXC_F_GPIO_IN_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN4_POS))
bogdanm 0:9b334a45a8ff 253 #define MXC_F_GPIO_IN_VAL_PIN5_POS 5
bogdanm 0:9b334a45a8ff 254 #define MXC_F_GPIO_IN_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN5_POS))
bogdanm 0:9b334a45a8ff 255 #define MXC_F_GPIO_IN_VAL_PIN6_POS 6
bogdanm 0:9b334a45a8ff 256 #define MXC_F_GPIO_IN_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN6_POS))
bogdanm 0:9b334a45a8ff 257 #define MXC_F_GPIO_IN_VAL_PIN7_POS 7
bogdanm 0:9b334a45a8ff 258 #define MXC_F_GPIO_IN_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN7_POS))
bogdanm 0:9b334a45a8ff 259
bogdanm 0:9b334a45a8ff 260 #define MXC_F_GPIO_INT_MODE_PIN0_POS 0
bogdanm 0:9b334a45a8ff 261 #define MXC_F_GPIO_INT_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN0_POS))
bogdanm 0:9b334a45a8ff 262 #define MXC_F_GPIO_INT_MODE_PIN1_POS 4
bogdanm 0:9b334a45a8ff 263 #define MXC_F_GPIO_INT_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN1_POS))
bogdanm 0:9b334a45a8ff 264 #define MXC_F_GPIO_INT_MODE_PIN2_POS 8
bogdanm 0:9b334a45a8ff 265 #define MXC_F_GPIO_INT_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN2_POS))
bogdanm 0:9b334a45a8ff 266 #define MXC_F_GPIO_INT_MODE_PIN3_POS 12
bogdanm 0:9b334a45a8ff 267 #define MXC_F_GPIO_INT_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN3_POS))
bogdanm 0:9b334a45a8ff 268 #define MXC_F_GPIO_INT_MODE_PIN4_POS 16
bogdanm 0:9b334a45a8ff 269 #define MXC_F_GPIO_INT_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN4_POS))
bogdanm 0:9b334a45a8ff 270 #define MXC_F_GPIO_INT_MODE_PIN5_POS 20
bogdanm 0:9b334a45a8ff 271 #define MXC_F_GPIO_INT_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN5_POS))
bogdanm 0:9b334a45a8ff 272 #define MXC_F_GPIO_INT_MODE_PIN6_POS 24
bogdanm 0:9b334a45a8ff 273 #define MXC_F_GPIO_INT_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN6_POS))
bogdanm 0:9b334a45a8ff 274 #define MXC_F_GPIO_INT_MODE_PIN7_POS 28
bogdanm 0:9b334a45a8ff 275 #define MXC_F_GPIO_INT_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN7_POS))
bogdanm 0:9b334a45a8ff 276
bogdanm 0:9b334a45a8ff 277 #define MXC_F_GPIO_INTFL_PIN0_POS 0
bogdanm 0:9b334a45a8ff 278 #define MXC_F_GPIO_INTFL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN0_POS))
bogdanm 0:9b334a45a8ff 279 #define MXC_F_GPIO_INTFL_PIN1_POS 1
bogdanm 0:9b334a45a8ff 280 #define MXC_F_GPIO_INTFL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN1_POS))
bogdanm 0:9b334a45a8ff 281 #define MXC_F_GPIO_INTFL_PIN2_POS 2
bogdanm 0:9b334a45a8ff 282 #define MXC_F_GPIO_INTFL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN2_POS))
bogdanm 0:9b334a45a8ff 283 #define MXC_F_GPIO_INTFL_PIN3_POS 3
bogdanm 0:9b334a45a8ff 284 #define MXC_F_GPIO_INTFL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN3_POS))
bogdanm 0:9b334a45a8ff 285 #define MXC_F_GPIO_INTFL_PIN4_POS 4
bogdanm 0:9b334a45a8ff 286 #define MXC_F_GPIO_INTFL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN4_POS))
bogdanm 0:9b334a45a8ff 287 #define MXC_F_GPIO_INTFL_PIN5_POS 5
bogdanm 0:9b334a45a8ff 288 #define MXC_F_GPIO_INTFL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN5_POS))
bogdanm 0:9b334a45a8ff 289 #define MXC_F_GPIO_INTFL_PIN6_POS 6
bogdanm 0:9b334a45a8ff 290 #define MXC_F_GPIO_INTFL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN6_POS))
bogdanm 0:9b334a45a8ff 291 #define MXC_F_GPIO_INTFL_PIN7_POS 7
bogdanm 0:9b334a45a8ff 292 #define MXC_F_GPIO_INTFL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN7_POS))
bogdanm 0:9b334a45a8ff 293
bogdanm 0:9b334a45a8ff 294 #define MXC_F_GPIO_INTEN_PIN0_POS 0
bogdanm 0:9b334a45a8ff 295 #define MXC_F_GPIO_INTEN_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN0_POS))
bogdanm 0:9b334a45a8ff 296 #define MXC_F_GPIO_INTEN_PIN1_POS 1
bogdanm 0:9b334a45a8ff 297 #define MXC_F_GPIO_INTEN_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN1_POS))
bogdanm 0:9b334a45a8ff 298 #define MXC_F_GPIO_INTEN_PIN2_POS 2
bogdanm 0:9b334a45a8ff 299 #define MXC_F_GPIO_INTEN_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN2_POS))
bogdanm 0:9b334a45a8ff 300 #define MXC_F_GPIO_INTEN_PIN3_POS 3
bogdanm 0:9b334a45a8ff 301 #define MXC_F_GPIO_INTEN_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN3_POS))
bogdanm 0:9b334a45a8ff 302 #define MXC_F_GPIO_INTEN_PIN4_POS 4
bogdanm 0:9b334a45a8ff 303 #define MXC_F_GPIO_INTEN_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN4_POS))
bogdanm 0:9b334a45a8ff 304 #define MXC_F_GPIO_INTEN_PIN5_POS 5
bogdanm 0:9b334a45a8ff 305 #define MXC_F_GPIO_INTEN_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN5_POS))
bogdanm 0:9b334a45a8ff 306 #define MXC_F_GPIO_INTEN_PIN6_POS 6
bogdanm 0:9b334a45a8ff 307 #define MXC_F_GPIO_INTEN_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN6_POS))
bogdanm 0:9b334a45a8ff 308 #define MXC_F_GPIO_INTEN_PIN7_POS 7
bogdanm 0:9b334a45a8ff 309 #define MXC_F_GPIO_INTEN_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN7_POS))
bogdanm 0:9b334a45a8ff 310
bogdanm 0:9b334a45a8ff 311
bogdanm 0:9b334a45a8ff 312 /*
bogdanm 0:9b334a45a8ff 313 Field values and shifted values for module GPIO.
bogdanm 0:9b334a45a8ff 314 */
bogdanm 0:9b334a45a8ff 315 #define MXC_V_GPIO_FREE_PIN0_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
bogdanm 0:9b334a45a8ff 316 #define MXC_V_GPIO_FREE_PIN0_AVAILABLE ((uint32_t)(0x0x00000001UL))
bogdanm 0:9b334a45a8ff 317
bogdanm 0:9b334a45a8ff 318 #define MXC_S_GPIO_FREE_PIN0_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN0_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN0_POS))
bogdanm 0:9b334a45a8ff 319 #define MXC_S_GPIO_FREE_PIN0_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN0_AVAILABLE << MXC_F_GPIO_FREE_PIN0_POS))
bogdanm 0:9b334a45a8ff 320
bogdanm 0:9b334a45a8ff 321 #define MXC_V_GPIO_FREE_PIN1_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
bogdanm 0:9b334a45a8ff 322 #define MXC_V_GPIO_FREE_PIN1_AVAILABLE ((uint32_t)(0x0x00000001UL))
bogdanm 0:9b334a45a8ff 323
bogdanm 0:9b334a45a8ff 324 #define MXC_S_GPIO_FREE_PIN1_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN1_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN1_POS))
bogdanm 0:9b334a45a8ff 325 #define MXC_S_GPIO_FREE_PIN1_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN1_AVAILABLE << MXC_F_GPIO_FREE_PIN1_POS))
bogdanm 0:9b334a45a8ff 326
bogdanm 0:9b334a45a8ff 327 #define MXC_V_GPIO_FREE_PIN2_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
bogdanm 0:9b334a45a8ff 328 #define MXC_V_GPIO_FREE_PIN2_AVAILABLE ((uint32_t)(0x0x00000001UL))
bogdanm 0:9b334a45a8ff 329
bogdanm 0:9b334a45a8ff 330 #define MXC_S_GPIO_FREE_PIN2_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN2_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN2_POS))
bogdanm 0:9b334a45a8ff 331 #define MXC_S_GPIO_FREE_PIN2_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN2_AVAILABLE << MXC_F_GPIO_FREE_PIN2_POS))
bogdanm 0:9b334a45a8ff 332
bogdanm 0:9b334a45a8ff 333 #define MXC_V_GPIO_FREE_PIN3_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
bogdanm 0:9b334a45a8ff 334 #define MXC_V_GPIO_FREE_PIN3_AVAILABLE ((uint32_t)(0x0x00000001UL))
bogdanm 0:9b334a45a8ff 335
bogdanm 0:9b334a45a8ff 336 #define MXC_S_GPIO_FREE_PIN3_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN3_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN3_POS))
bogdanm 0:9b334a45a8ff 337 #define MXC_S_GPIO_FREE_PIN3_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN3_AVAILABLE << MXC_F_GPIO_FREE_PIN3_POS))
bogdanm 0:9b334a45a8ff 338
bogdanm 0:9b334a45a8ff 339 #define MXC_V_GPIO_FREE_PIN4_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
bogdanm 0:9b334a45a8ff 340 #define MXC_V_GPIO_FREE_PIN4_AVAILABLE ((uint32_t)(0x0x00000001UL))
bogdanm 0:9b334a45a8ff 341
bogdanm 0:9b334a45a8ff 342 #define MXC_S_GPIO_FREE_PIN4_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN4_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN4_POS))
bogdanm 0:9b334a45a8ff 343 #define MXC_S_GPIO_FREE_PIN4_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN4_AVAILABLE << MXC_F_GPIO_FREE_PIN4_POS))
bogdanm 0:9b334a45a8ff 344
bogdanm 0:9b334a45a8ff 345 #define MXC_V_GPIO_FREE_PIN5_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
bogdanm 0:9b334a45a8ff 346 #define MXC_V_GPIO_FREE_PIN5_AVAILABLE ((uint32_t)(0x0x00000001UL))
bogdanm 0:9b334a45a8ff 347
bogdanm 0:9b334a45a8ff 348 #define MXC_S_GPIO_FREE_PIN5_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN5_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN5_POS))
bogdanm 0:9b334a45a8ff 349 #define MXC_S_GPIO_FREE_PIN5_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN5_AVAILABLE << MXC_F_GPIO_FREE_PIN5_POS))
bogdanm 0:9b334a45a8ff 350
bogdanm 0:9b334a45a8ff 351 #define MXC_V_GPIO_FREE_PIN6_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
bogdanm 0:9b334a45a8ff 352 #define MXC_V_GPIO_FREE_PIN6_AVAILABLE ((uint32_t)(0x0x00000001UL))
bogdanm 0:9b334a45a8ff 353
bogdanm 0:9b334a45a8ff 354 #define MXC_S_GPIO_FREE_PIN6_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN6_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN6_POS))
bogdanm 0:9b334a45a8ff 355 #define MXC_S_GPIO_FREE_PIN6_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN6_AVAILABLE << MXC_F_GPIO_FREE_PIN6_POS))
bogdanm 0:9b334a45a8ff 356
bogdanm 0:9b334a45a8ff 357 #define MXC_V_GPIO_FREE_PIN7_NOT_AVAILABLE ((uint32_t)(0x0x00000000UL))
bogdanm 0:9b334a45a8ff 358 #define MXC_V_GPIO_FREE_PIN7_AVAILABLE ((uint32_t)(0x0x00000001UL))
bogdanm 0:9b334a45a8ff 359
bogdanm 0:9b334a45a8ff 360 #define MXC_S_GPIO_FREE_PIN7_NOT_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN7_NOT_AVAILABLE << MXC_F_GPIO_FREE_PIN7_POS))
bogdanm 0:9b334a45a8ff 361 #define MXC_S_GPIO_FREE_PIN7_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN7_AVAILABLE << MXC_F_GPIO_FREE_PIN7_POS))
bogdanm 0:9b334a45a8ff 362
bogdanm 0:9b334a45a8ff 363 #define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP ((uint32_t)(0x00000000UL))
bogdanm 0:9b334a45a8ff 364 #define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN ((uint32_t)(0x00000001UL))
bogdanm 0:9b334a45a8ff 365 #define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(0x00000002UL))
bogdanm 0:9b334a45a8ff 366 #define MXC_V_GPIO_OUT_MODE_HIGH_Z ((uint32_t)(0x00000003UL))
bogdanm 0:9b334a45a8ff 367 #define MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z ((uint32_t)(0x00000004UL))
bogdanm 0:9b334a45a8ff 368 #define MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE ((uint32_t)(0x00000005UL))
bogdanm 0:9b334a45a8ff 369 #define MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z ((uint32_t)(0x00000006UL))
bogdanm 0:9b334a45a8ff 370 #define MXC_V_GPIO_OUT_MODE_SLOW_DRIVE ((uint32_t)(0x00000007UL))
bogdanm 0:9b334a45a8ff 371 #define MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z ((uint32_t)(0x00000008UL))
bogdanm 0:9b334a45a8ff 372 #define MXC_V_GPIO_OUT_MODE_FAST_DRIVE ((uint32_t)(0x00000009UL))
bogdanm 0:9b334a45a8ff 373
bogdanm 0:9b334a45a8ff 374 #define MXC_S_GPIO_OUT_MODE_PIN0_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN0_POS))
bogdanm 0:9b334a45a8ff 375 #define MXC_S_GPIO_OUT_MODE_PIN0_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN0_POS))
bogdanm 0:9b334a45a8ff 376 #define MXC_S_GPIO_OUT_MODE_PIN0_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN0_POS))
bogdanm 0:9b334a45a8ff 377 #define MXC_S_GPIO_OUT_MODE_PIN0_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN0_POS))
bogdanm 0:9b334a45a8ff 378 #define MXC_S_GPIO_OUT_MODE_PIN0_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN0_POS))
bogdanm 0:9b334a45a8ff 379 #define MXC_S_GPIO_OUT_MODE_PIN0_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN0_POS))
bogdanm 0:9b334a45a8ff 380 #define MXC_S_GPIO_OUT_MODE_PIN0_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN0_POS))
bogdanm 0:9b334a45a8ff 381 #define MXC_S_GPIO_OUT_MODE_PIN0_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN0_POS))
bogdanm 0:9b334a45a8ff 382 #define MXC_S_GPIO_OUT_MODE_PIN0_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN0_POS))
bogdanm 0:9b334a45a8ff 383 #define MXC_S_GPIO_OUT_MODE_PIN0_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN0_POS))
bogdanm 0:9b334a45a8ff 384
bogdanm 0:9b334a45a8ff 385 #define MXC_S_GPIO_OUT_MODE_PIN1_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN1_POS))
bogdanm 0:9b334a45a8ff 386 #define MXC_S_GPIO_OUT_MODE_PIN1_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN1_POS))
bogdanm 0:9b334a45a8ff 387 #define MXC_S_GPIO_OUT_MODE_PIN1_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN1_POS))
bogdanm 0:9b334a45a8ff 388 #define MXC_S_GPIO_OUT_MODE_PIN1_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN1_POS))
bogdanm 0:9b334a45a8ff 389 #define MXC_S_GPIO_OUT_MODE_PIN1_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN1_POS))
bogdanm 0:9b334a45a8ff 390 #define MXC_S_GPIO_OUT_MODE_PIN1_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN1_POS))
bogdanm 0:9b334a45a8ff 391 #define MXC_S_GPIO_OUT_MODE_PIN1_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN1_POS))
bogdanm 0:9b334a45a8ff 392 #define MXC_S_GPIO_OUT_MODE_PIN1_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN1_POS))
bogdanm 0:9b334a45a8ff 393 #define MXC_S_GPIO_OUT_MODE_PIN1_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN1_POS))
bogdanm 0:9b334a45a8ff 394 #define MXC_S_GPIO_OUT_MODE_PIN1_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN1_POS))
bogdanm 0:9b334a45a8ff 395
bogdanm 0:9b334a45a8ff 396 #define MXC_S_GPIO_OUT_MODE_PIN2_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN2_POS))
bogdanm 0:9b334a45a8ff 397 #define MXC_S_GPIO_OUT_MODE_PIN2_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN2_POS))
bogdanm 0:9b334a45a8ff 398 #define MXC_S_GPIO_OUT_MODE_PIN2_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN2_POS))
bogdanm 0:9b334a45a8ff 399 #define MXC_S_GPIO_OUT_MODE_PIN2_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN2_POS))
bogdanm 0:9b334a45a8ff 400 #define MXC_S_GPIO_OUT_MODE_PIN2_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN2_POS))
bogdanm 0:9b334a45a8ff 401 #define MXC_S_GPIO_OUT_MODE_PIN2_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN2_POS))
bogdanm 0:9b334a45a8ff 402 #define MXC_S_GPIO_OUT_MODE_PIN2_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN2_POS))
bogdanm 0:9b334a45a8ff 403 #define MXC_S_GPIO_OUT_MODE_PIN2_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN2_POS))
bogdanm 0:9b334a45a8ff 404 #define MXC_S_GPIO_OUT_MODE_PIN2_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN2_POS))
bogdanm 0:9b334a45a8ff 405 #define MXC_S_GPIO_OUT_MODE_PIN2_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN2_POS))
bogdanm 0:9b334a45a8ff 406
bogdanm 0:9b334a45a8ff 407 #define MXC_S_GPIO_OUT_MODE_PIN3_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN3_POS))
bogdanm 0:9b334a45a8ff 408 #define MXC_S_GPIO_OUT_MODE_PIN3_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN3_POS))
bogdanm 0:9b334a45a8ff 409 #define MXC_S_GPIO_OUT_MODE_PIN3_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN3_POS))
bogdanm 0:9b334a45a8ff 410 #define MXC_S_GPIO_OUT_MODE_PIN3_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN3_POS))
bogdanm 0:9b334a45a8ff 411 #define MXC_S_GPIO_OUT_MODE_PIN3_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN3_POS))
bogdanm 0:9b334a45a8ff 412 #define MXC_S_GPIO_OUT_MODE_PIN3_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN3_POS))
bogdanm 0:9b334a45a8ff 413 #define MXC_S_GPIO_OUT_MODE_PIN3_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN3_POS))
bogdanm 0:9b334a45a8ff 414 #define MXC_S_GPIO_OUT_MODE_PIN3_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN3_POS))
bogdanm 0:9b334a45a8ff 415 #define MXC_S_GPIO_OUT_MODE_PIN3_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN3_POS))
bogdanm 0:9b334a45a8ff 416 #define MXC_S_GPIO_OUT_MODE_PIN3_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN3_POS))
bogdanm 0:9b334a45a8ff 417
bogdanm 0:9b334a45a8ff 418 #define MXC_S_GPIO_OUT_MODE_PIN4_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN4_POS))
bogdanm 0:9b334a45a8ff 419 #define MXC_S_GPIO_OUT_MODE_PIN4_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN4_POS))
bogdanm 0:9b334a45a8ff 420 #define MXC_S_GPIO_OUT_MODE_PIN4_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN4_POS))
bogdanm 0:9b334a45a8ff 421 #define MXC_S_GPIO_OUT_MODE_PIN4_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN4_POS))
bogdanm 0:9b334a45a8ff 422 #define MXC_S_GPIO_OUT_MODE_PIN4_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN4_POS))
bogdanm 0:9b334a45a8ff 423 #define MXC_S_GPIO_OUT_MODE_PIN4_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN4_POS))
bogdanm 0:9b334a45a8ff 424 #define MXC_S_GPIO_OUT_MODE_PIN4_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN4_POS))
bogdanm 0:9b334a45a8ff 425 #define MXC_S_GPIO_OUT_MODE_PIN4_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN4_POS))
bogdanm 0:9b334a45a8ff 426 #define MXC_S_GPIO_OUT_MODE_PIN4_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN4_POS))
bogdanm 0:9b334a45a8ff 427 #define MXC_S_GPIO_OUT_MODE_PIN4_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN4_POS))
bogdanm 0:9b334a45a8ff 428
bogdanm 0:9b334a45a8ff 429 #define MXC_S_GPIO_OUT_MODE_PIN5_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN5_POS))
bogdanm 0:9b334a45a8ff 430 #define MXC_S_GPIO_OUT_MODE_PIN5_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN5_POS))
bogdanm 0:9b334a45a8ff 431 #define MXC_S_GPIO_OUT_MODE_PIN5_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN5_POS))
bogdanm 0:9b334a45a8ff 432 #define MXC_S_GPIO_OUT_MODE_PIN5_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN5_POS))
bogdanm 0:9b334a45a8ff 433 #define MXC_S_GPIO_OUT_MODE_PIN5_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN5_POS))
bogdanm 0:9b334a45a8ff 434 #define MXC_S_GPIO_OUT_MODE_PIN5_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN5_POS))
bogdanm 0:9b334a45a8ff 435 #define MXC_S_GPIO_OUT_MODE_PIN5_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN5_POS))
bogdanm 0:9b334a45a8ff 436 #define MXC_S_GPIO_OUT_MODE_PIN5_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN5_POS))
bogdanm 0:9b334a45a8ff 437 #define MXC_S_GPIO_OUT_MODE_PIN5_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN5_POS))
bogdanm 0:9b334a45a8ff 438 #define MXC_S_GPIO_OUT_MODE_PIN5_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN5_POS))
bogdanm 0:9b334a45a8ff 439
bogdanm 0:9b334a45a8ff 440 #define MXC_S_GPIO_OUT_MODE_PIN6_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN6_POS))
bogdanm 0:9b334a45a8ff 441 #define MXC_S_GPIO_OUT_MODE_PIN6_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN6_POS))
bogdanm 0:9b334a45a8ff 442 #define MXC_S_GPIO_OUT_MODE_PIN6_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN6_POS))
bogdanm 0:9b334a45a8ff 443 #define MXC_S_GPIO_OUT_MODE_PIN6_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN6_POS))
bogdanm 0:9b334a45a8ff 444 #define MXC_S_GPIO_OUT_MODE_PIN6_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN6_POS))
bogdanm 0:9b334a45a8ff 445 #define MXC_S_GPIO_OUT_MODE_PIN6_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN6_POS))
bogdanm 0:9b334a45a8ff 446 #define MXC_S_GPIO_OUT_MODE_PIN6_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN6_POS))
bogdanm 0:9b334a45a8ff 447 #define MXC_S_GPIO_OUT_MODE_PIN6_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN6_POS))
bogdanm 0:9b334a45a8ff 448 #define MXC_S_GPIO_OUT_MODE_PIN6_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN6_POS))
bogdanm 0:9b334a45a8ff 449 #define MXC_S_GPIO_OUT_MODE_PIN6_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN6_POS))
bogdanm 0:9b334a45a8ff 450
bogdanm 0:9b334a45a8ff 451 #define MXC_S_GPIO_OUT_MODE_PIN7_HIGH_Z_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN7_POS))
bogdanm 0:9b334a45a8ff 452 #define MXC_S_GPIO_OUT_MODE_PIN7_OPEN_DRAIN ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN << MXC_F_GPIO_OUT_MODE_PIN7_POS))
bogdanm 0:9b334a45a8ff 453 #define MXC_S_GPIO_OUT_MODE_PIN7_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP << MXC_F_GPIO_OUT_MODE_PIN7_POS))
bogdanm 0:9b334a45a8ff 454 #define MXC_S_GPIO_OUT_MODE_PIN7_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN7_POS))
bogdanm 0:9b334a45a8ff 455 #define MXC_S_GPIO_OUT_MODE_PIN7_NORMAL_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN7_POS))
bogdanm 0:9b334a45a8ff 456 #define MXC_S_GPIO_OUT_MODE_PIN7_NORMAL_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << MXC_F_GPIO_OUT_MODE_PIN7_POS))
bogdanm 0:9b334a45a8ff 457 #define MXC_S_GPIO_OUT_MODE_PIN7_SLOW_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN7_POS))
bogdanm 0:9b334a45a8ff 458 #define MXC_S_GPIO_OUT_MODE_PIN7_SLOW_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE << MXC_F_GPIO_OUT_MODE_PIN7_POS))
bogdanm 0:9b334a45a8ff 459 #define MXC_S_GPIO_OUT_MODE_PIN7_FAST_HIGH_Z ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z << MXC_F_GPIO_OUT_MODE_PIN7_POS))
bogdanm 0:9b334a45a8ff 460 #define MXC_S_GPIO_OUT_MODE_PIN7_FAST_DRIVE ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE << MXC_F_GPIO_OUT_MODE_PIN7_POS))
bogdanm 0:9b334a45a8ff 461
bogdanm 0:9b334a45a8ff 462 #define MXC_V_GPIO_INT_MODE_DISABLED ((uint32_t)(0x00000000UL))
bogdanm 0:9b334a45a8ff 463 #define MXC_V_GPIO_INT_MODE_FALLING_EDGE ((uint32_t)(0x00000001UL))
bogdanm 0:9b334a45a8ff 464 #define MXC_V_GPIO_INT_MODE_RISING_EDGE ((uint32_t)(0x00000002UL))
bogdanm 0:9b334a45a8ff 465 #define MXC_V_GPIO_INT_MODE_BOTH_EDGES ((uint32_t)(0x00000003UL))
bogdanm 0:9b334a45a8ff 466 #define MXC_V_GPIO_INT_MODE_LOW_LEVEL ((uint32_t)(0x00000004UL))
bogdanm 0:9b334a45a8ff 467 #define MXC_V_GPIO_INT_MODE_HIGH_LEVEL ((uint32_t)(0x00000005UL))
bogdanm 0:9b334a45a8ff 468
bogdanm 0:9b334a45a8ff 469 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 470 }
bogdanm 0:9b334a45a8ff 471 #endif
bogdanm 0:9b334a45a8ff 472
bogdanm 0:9b334a45a8ff 473 /**
bogdanm 0:9b334a45a8ff 474 * @}
bogdanm 0:9b334a45a8ff 475 */
bogdanm 0:9b334a45a8ff 476
bogdanm 0:9b334a45a8ff 477 #endif /* _MXC_GPIO_REGS_H_ */