Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Maxim/TARGET_MAX32600/ioman_regs.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /*******************************************************************************
bogdanm 0:9b334a45a8ff 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Permission is hereby granted, free of charge, to any person obtaining a
bogdanm 0:9b334a45a8ff 5 * copy of this software and associated documentation files (the "Software"),
bogdanm 0:9b334a45a8ff 6 * to deal in the Software without restriction, including without limitation
bogdanm 0:9b334a45a8ff 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
bogdanm 0:9b334a45a8ff 8 * and/or sell copies of the Software, and to permit persons to whom the
bogdanm 0:9b334a45a8ff 9 * Software is furnished to do so, subject to the following conditions:
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * The above copyright notice and this permission notice shall be included
bogdanm 0:9b334a45a8ff 12 * in all copies or substantial portions of the Software.
bogdanm 0:9b334a45a8ff 13 *
bogdanm 0:9b334a45a8ff 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
bogdanm 0:9b334a45a8ff 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
bogdanm 0:9b334a45a8ff 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
bogdanm 0:9b334a45a8ff 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
bogdanm 0:9b334a45a8ff 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
bogdanm 0:9b334a45a8ff 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
bogdanm 0:9b334a45a8ff 20 * OTHER DEALINGS IN THE SOFTWARE.
bogdanm 0:9b334a45a8ff 21 *
bogdanm 0:9b334a45a8ff 22 * Except as contained in this notice, the name of Maxim Integrated
bogdanm 0:9b334a45a8ff 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
bogdanm 0:9b334a45a8ff 24 * Products, Inc. Branding Policy.
bogdanm 0:9b334a45a8ff 25 *
bogdanm 0:9b334a45a8ff 26 * The mere transfer of this software does not imply any licenses
bogdanm 0:9b334a45a8ff 27 * of trade secrets, proprietary technology, copyrights, patents,
bogdanm 0:9b334a45a8ff 28 * trademarks, maskwork rights, or any other form of intellectual
bogdanm 0:9b334a45a8ff 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
bogdanm 0:9b334a45a8ff 30 * ownership rights.
bogdanm 0:9b334a45a8ff 31 *******************************************************************************
bogdanm 0:9b334a45a8ff 32 */
bogdanm 0:9b334a45a8ff 33
bogdanm 0:9b334a45a8ff 34 #ifndef _MXC_IOMAN_REGS_H_
bogdanm 0:9b334a45a8ff 35 #define _MXC_IOMAN_REGS_H_
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 38 extern "C" {
bogdanm 0:9b334a45a8ff 39 #endif
bogdanm 0:9b334a45a8ff 40
bogdanm 0:9b334a45a8ff 41 #include <stdint.h>
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 /**
bogdanm 0:9b334a45a8ff 44 * @file ioman_regs.h
bogdanm 0:9b334a45a8ff 45 * @addtogroup ioman IO MUX Manager
bogdanm 0:9b334a45a8ff 46 * @{
bogdanm 0:9b334a45a8ff 47 */
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 typedef enum {
bogdanm 0:9b334a45a8ff 50 /** Pin Mapping 'A' */
bogdanm 0:9b334a45a8ff 51 MXC_E_IOMAN_MAPPING_A = 0,
bogdanm 0:9b334a45a8ff 52 /** Pin Mapping 'B' */
bogdanm 0:9b334a45a8ff 53 MXC_E_IOMAN_MAPPING_B,
bogdanm 0:9b334a45a8ff 54 /** Pin Mapping 'C' */
bogdanm 0:9b334a45a8ff 55 MXC_E_IOMAN_MAPPING_C,
bogdanm 0:9b334a45a8ff 56 /** Pin Mapping 'D' */
bogdanm 0:9b334a45a8ff 57 MXC_E_IOMAN_MAPPING_D,
bogdanm 0:9b334a45a8ff 58 /** Pin Mapping 'E' */
bogdanm 0:9b334a45a8ff 59 MXC_E_IOMAN_MAPPING_E,
bogdanm 0:9b334a45a8ff 60 /** Pin Mapping 'F' */
bogdanm 0:9b334a45a8ff 61 MXC_E_IOMAN_MAPPING_F,
bogdanm 0:9b334a45a8ff 62 /** Pin Mapping 'G' */
bogdanm 0:9b334a45a8ff 63 MXC_E_IOMAN_MAPPING_G,
bogdanm 0:9b334a45a8ff 64 /** Pin Mapping 'H' */
bogdanm 0:9b334a45a8ff 65 MXC_E_IOMAN_MAPPING_H,
bogdanm 0:9b334a45a8ff 66 } ioman_mapping_t;
bogdanm 0:9b334a45a8ff 67
bogdanm 0:9b334a45a8ff 68 /* Offset Register Description
bogdanm 0:9b334a45a8ff 69 ====== ========================================== */
bogdanm 0:9b334a45a8ff 70 typedef struct {
bogdanm 0:9b334a45a8ff 71 __IO uint32_t wud_req0; /* 0x0000 Wakeup Detect Mode Request Register 0 */
bogdanm 0:9b334a45a8ff 72 __IO uint32_t wud_req1; /* 0x0004 Wakeup Detect Mode Request Register 1 */
bogdanm 0:9b334a45a8ff 73 __IO uint32_t wud_ack0; /* 0x0008 Wakeup Detect Mode Acknowledge Register 0 */
bogdanm 0:9b334a45a8ff 74 __IO uint32_t wud_ack1; /* 0x000C Wakeup Detect Mode Acknowledge Register 1 */
bogdanm 0:9b334a45a8ff 75 __IO uint32_t ali_req0; /* 0x0010 Analog Input Request Register 0 */
bogdanm 0:9b334a45a8ff 76 __IO uint32_t ali_req1; /* 0x0014 Analog Input Request Register 1 */
bogdanm 0:9b334a45a8ff 77 __IO uint32_t ali_ack0; /* 0x0018 Analog Input Acknowledge Register 0 */
bogdanm 0:9b334a45a8ff 78 __IO uint32_t ali_ack1; /* 0x001C Analog Input Acknowledge Register 1 */
bogdanm 0:9b334a45a8ff 79 __IO uint32_t spi0_req; /* 0x0020 SPI0 I/O Mode Request */
bogdanm 0:9b334a45a8ff 80 __IO uint32_t spi0_ack; /* 0x0024 SPI0 I/O Mode Acknowledge */
bogdanm 0:9b334a45a8ff 81 __IO uint32_t spi1_req; /* 0x0028 SPI1 I/O Mode Request */
bogdanm 0:9b334a45a8ff 82 __IO uint32_t spi1_ack; /* 0x002C SPI1 I/O Mode Acknowledge */
bogdanm 0:9b334a45a8ff 83 __IO uint32_t spi2_req; /* 0x0030 SPI2 I/O Mode Request */
bogdanm 0:9b334a45a8ff 84 __IO uint32_t spi2_ack; /* 0x0034 SPI2 I/O Mode Acknowledge */
bogdanm 0:9b334a45a8ff 85 __IO uint32_t uart0_req; /* 0x0038 UART0 I/O Mode Request */
bogdanm 0:9b334a45a8ff 86 __IO uint32_t uart0_ack; /* 0x003C UART0 I/O Mode Acknowledge */
bogdanm 0:9b334a45a8ff 87 __IO uint32_t uart1_req; /* 0x0040 UART1 I/O Mode Request */
bogdanm 0:9b334a45a8ff 88 __IO uint32_t uart1_ack; /* 0x0044 UART1 I/O Mode Acknowledge */
bogdanm 0:9b334a45a8ff 89 __IO uint32_t i2cm0_req; /* 0x0048 I2C Master 0 I/O Request */
bogdanm 0:9b334a45a8ff 90 __IO uint32_t i2cm0_ack; /* 0x004C I2C Master 0 I/O Acknowledge */
bogdanm 0:9b334a45a8ff 91 __IO uint32_t i2cs0_req; /* 0x0050 I2C Slave 0 I/O Request */
bogdanm 0:9b334a45a8ff 92 __IO uint32_t i2s0_ack; /* 0x0054 I2C Slave 0 I/O Acknowledge */
bogdanm 0:9b334a45a8ff 93 __IO uint32_t lcd_com_req; /* 0x0058 LCD COM Driver I/O Request */
bogdanm 0:9b334a45a8ff 94 __IO uint32_t lcd_com_ack; /* 0x005C LCD COM Driver I/O Acknowledge */
bogdanm 0:9b334a45a8ff 95 __IO uint32_t lcd_seg_req0; /* 0x0060 LCD SEG Driver I/O Request Register 0 */
bogdanm 0:9b334a45a8ff 96 __IO uint32_t lcd_seg_req1; /* 0x0064 LCD SEG Driver I/O Request Register 1 */
bogdanm 0:9b334a45a8ff 97 __IO uint32_t lcd_seg_ack0; /* 0x0068 LCD SEG Driver I/O Acknowledge Register 0 */
bogdanm 0:9b334a45a8ff 98 __IO uint32_t lcd_seg_ack1; /* 0x006C LCD SEG Driver I/O Acknowledge Register 1 */
bogdanm 0:9b334a45a8ff 99 __IO uint32_t crnt_req; /* 0x0070 Current Drive I/O Request Register */
bogdanm 0:9b334a45a8ff 100 __IO uint32_t io_crnt_ack; /* 0x0074 Current Drive I/O Acknowledge Register */
bogdanm 0:9b334a45a8ff 101 __IO uint32_t crnt_mode; /* 0x0078 Current Drive I/O Mode Control */
bogdanm 0:9b334a45a8ff 102 __IO uint32_t ali_connect0; /* 0x007C Analog I/O Connection Control Register 0 */
bogdanm 0:9b334a45a8ff 103 __IO uint32_t ali_connect1; /* 0x0080 Analog I/O Connection Control Register 1 */
bogdanm 0:9b334a45a8ff 104 __IO uint32_t i2cm1_req; /* 0x0084 I2C Master 1 I/O Request */
bogdanm 0:9b334a45a8ff 105 __IO uint32_t i2cm1_ack; /* 0x0088 I2C Master 1 I/O Acknowledge */
bogdanm 0:9b334a45a8ff 106 __IO uint32_t padx_control; /* 0x008C PADX Control */
bogdanm 0:9b334a45a8ff 107 } mxc_ioman_regs_t;
bogdanm 0:9b334a45a8ff 108
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110 /*
bogdanm 0:9b334a45a8ff 111 Register offsets for module IOMAN.
bogdanm 0:9b334a45a8ff 112 */
bogdanm 0:9b334a45a8ff 113 #define MXC_R_IOMAN_OFFS_WUD_REQ0 ((uint32_t)0x00000000UL)
bogdanm 0:9b334a45a8ff 114 #define MXC_R_IOMAN_OFFS_WUD_REQ1 ((uint32_t)0x00000004UL)
bogdanm 0:9b334a45a8ff 115 #define MXC_R_IOMAN_OFFS_WUD_ACK0 ((uint32_t)0x00000008UL)
bogdanm 0:9b334a45a8ff 116 #define MXC_R_IOMAN_OFFS_WUD_ACK1 ((uint32_t)0x0000000CUL)
bogdanm 0:9b334a45a8ff 117 #define MXC_R_IOMAN_OFFS_ALI_REQ0 ((uint32_t)0x00000010UL)
bogdanm 0:9b334a45a8ff 118 #define MXC_R_IOMAN_OFFS_ALI_REQ1 ((uint32_t)0x00000014UL)
bogdanm 0:9b334a45a8ff 119 #define MXC_R_IOMAN_OFFS_ALI_ACK0 ((uint32_t)0x00000018UL)
bogdanm 0:9b334a45a8ff 120 #define MXC_R_IOMAN_OFFS_ALI_ACK1 ((uint32_t)0x0000001CUL)
bogdanm 0:9b334a45a8ff 121 #define MXC_R_IOMAN_OFFS_SPI0_REQ ((uint32_t)0x00000020UL)
bogdanm 0:9b334a45a8ff 122 #define MXC_R_IOMAN_OFFS_SPI0_ACK ((uint32_t)0x00000024UL)
bogdanm 0:9b334a45a8ff 123 #define MXC_R_IOMAN_OFFS_SPI1_REQ ((uint32_t)0x00000028UL)
bogdanm 0:9b334a45a8ff 124 #define MXC_R_IOMAN_OFFS_SPI1_ACK ((uint32_t)0x0000002CUL)
bogdanm 0:9b334a45a8ff 125 #define MXC_R_IOMAN_OFFS_SPI2_REQ ((uint32_t)0x00000030UL)
bogdanm 0:9b334a45a8ff 126 #define MXC_R_IOMAN_OFFS_SPI2_ACK ((uint32_t)0x00000034UL)
bogdanm 0:9b334a45a8ff 127 #define MXC_R_IOMAN_OFFS_UART0_REQ ((uint32_t)0x00000038UL)
bogdanm 0:9b334a45a8ff 128 #define MXC_R_IOMAN_OFFS_UART0_ACK ((uint32_t)0x0000003CUL)
bogdanm 0:9b334a45a8ff 129 #define MXC_R_IOMAN_OFFS_UART1_REQ ((uint32_t)0x00000040UL)
bogdanm 0:9b334a45a8ff 130 #define MXC_R_IOMAN_OFFS_UART1_ACK ((uint32_t)0x00000044UL)
bogdanm 0:9b334a45a8ff 131 #define MXC_R_IOMAN_OFFS_I2CM0_REQ ((uint32_t)0x00000048UL)
bogdanm 0:9b334a45a8ff 132 #define MXC_R_IOMAN_OFFS_I2CM0_ACK ((uint32_t)0x0000004CUL)
bogdanm 0:9b334a45a8ff 133 #define MXC_R_IOMAN_OFFS_I2CS0_REQ ((uint32_t)0x00000050UL)
bogdanm 0:9b334a45a8ff 134 #define MXC_R_IOMAN_OFFS_I2SC0_ACK ((uint32_t)0x00000054UL)
bogdanm 0:9b334a45a8ff 135 #define MXC_R_IOMAN_OFFS_LCD_COM_REQ ((uint32_t)0x00000058UL)
bogdanm 0:9b334a45a8ff 136 #define MXC_R_IOMAN_OFFS_LCD_COM_ACK ((uint32_t)0x0000005CUL)
bogdanm 0:9b334a45a8ff 137 #define MXC_R_IOMAN_OFFS_LCD_SEG_REQ0 ((uint32_t)0x00000060UL)
bogdanm 0:9b334a45a8ff 138 #define MXC_R_IOMAN_OFFS_LCD_SEG_REQ1 ((uint32_t)0x00000064UL)
bogdanm 0:9b334a45a8ff 139 #define MXC_R_IOMAN_OFFS_LCD_SEG_ACK0 ((uint32_t)0x00000068UL)
bogdanm 0:9b334a45a8ff 140 #define MXC_R_IOMAN_OFFS_LCD_SEG_ACK1 ((uint32_t)0x0000006CUL)
bogdanm 0:9b334a45a8ff 141 #define MXC_R_IOMAN_OFFS_IO_CRNT_REQ ((uint32_t)0x00000070UL)
bogdanm 0:9b334a45a8ff 142 #define MXC_R_IOMAN_OFFS_IO_CRNT_ACK ((uint32_t)0x00000074UL)
bogdanm 0:9b334a45a8ff 143 #define MXC_R_IOMAN_OFFS_IO_CRNT_MODE ((uint32_t)0x00000078UL)
bogdanm 0:9b334a45a8ff 144 #define MXC_R_IOMAN_OFFS_ALI_CONNECT0 ((uint32_t)0x0000007CUL)
bogdanm 0:9b334a45a8ff 145 #define MXC_R_IOMAN_OFFS_ALI_CONNECT1 ((uint32_t)0x00000080UL)
bogdanm 0:9b334a45a8ff 146 #define MXC_R_IOMAN_OFFS_I2CM1_REQ ((uint32_t)0x00000084UL)
bogdanm 0:9b334a45a8ff 147 #define MXC_R_IOMAN_OFFS_I2CM1_ACK ((uint32_t)0x00000088UL)
bogdanm 0:9b334a45a8ff 148 #define MXC_R_IOMAN_OFFS_PADX_CONTROL ((uint32_t)0x0000008CUL)
bogdanm 0:9b334a45a8ff 149
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151 /*
bogdanm 0:9b334a45a8ff 152 Field positions and masks for module IOMAN.
bogdanm 0:9b334a45a8ff 153 */
bogdanm 0:9b334a45a8ff 154 #define MXC_F_IOMAN_WUD_REQ0_PORT0_POS 0
bogdanm 0:9b334a45a8ff 155 #define MXC_F_IOMAN_WUD_REQ0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT0_POS))
bogdanm 0:9b334a45a8ff 156 #define MXC_F_IOMAN_WUD_REQ0_PORT1_POS 8
bogdanm 0:9b334a45a8ff 157 #define MXC_F_IOMAN_WUD_REQ0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT1_POS))
bogdanm 0:9b334a45a8ff 158 #define MXC_F_IOMAN_WUD_REQ0_PORT2_POS 16
bogdanm 0:9b334a45a8ff 159 #define MXC_F_IOMAN_WUD_REQ0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT2_POS))
bogdanm 0:9b334a45a8ff 160 #define MXC_F_IOMAN_WUD_REQ0_PORT3_POS 24
bogdanm 0:9b334a45a8ff 161 #define MXC_F_IOMAN_WUD_REQ0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT3_POS))
bogdanm 0:9b334a45a8ff 162
bogdanm 0:9b334a45a8ff 163 #define MXC_F_IOMAN_WUD_REQ1_PORT4_POS 0
bogdanm 0:9b334a45a8ff 164 #define MXC_F_IOMAN_WUD_REQ1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT4_POS))
bogdanm 0:9b334a45a8ff 165 #define MXC_F_IOMAN_WUD_REQ1_PORT5_POS 8
bogdanm 0:9b334a45a8ff 166 #define MXC_F_IOMAN_WUD_REQ1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT5_POS))
bogdanm 0:9b334a45a8ff 167 #define MXC_F_IOMAN_WUD_REQ1_PORT6_POS 16
bogdanm 0:9b334a45a8ff 168 #define MXC_F_IOMAN_WUD_REQ1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT6_POS))
bogdanm 0:9b334a45a8ff 169 #define MXC_F_IOMAN_WUD_REQ1_PORT7_POS 24
bogdanm 0:9b334a45a8ff 170 #define MXC_F_IOMAN_WUD_REQ1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT7_POS))
bogdanm 0:9b334a45a8ff 171
bogdanm 0:9b334a45a8ff 172 #define MXC_F_IOMAN_WUD_ACK0_PORT0_POS 0
bogdanm 0:9b334a45a8ff 173 #define MXC_F_IOMAN_WUD_ACK0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT0_POS))
bogdanm 0:9b334a45a8ff 174 #define MXC_F_IOMAN_WUD_ACK0_PORT1_POS 8
bogdanm 0:9b334a45a8ff 175 #define MXC_F_IOMAN_WUD_ACK0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT1_POS))
bogdanm 0:9b334a45a8ff 176 #define MXC_F_IOMAN_WUD_ACK0_PORT2_POS 16
bogdanm 0:9b334a45a8ff 177 #define MXC_F_IOMAN_WUD_ACK0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT2_POS))
bogdanm 0:9b334a45a8ff 178 #define MXC_F_IOMAN_WUD_ACK0_PORT3_POS 24
bogdanm 0:9b334a45a8ff 179 #define MXC_F_IOMAN_WUD_ACK0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT3_POS))
bogdanm 0:9b334a45a8ff 180
bogdanm 0:9b334a45a8ff 181 #define MXC_F_IOMAN_WUD_ACK1_PORT4_POS 0
bogdanm 0:9b334a45a8ff 182 #define MXC_F_IOMAN_WUD_ACK1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT4_POS))
bogdanm 0:9b334a45a8ff 183 #define MXC_F_IOMAN_WUD_ACK1_PORT5_POS 8
bogdanm 0:9b334a45a8ff 184 #define MXC_F_IOMAN_WUD_ACK1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT5_POS))
bogdanm 0:9b334a45a8ff 185 #define MXC_F_IOMAN_WUD_ACK1_PORT6_POS 16
bogdanm 0:9b334a45a8ff 186 #define MXC_F_IOMAN_WUD_ACK1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT6_POS))
bogdanm 0:9b334a45a8ff 187 #define MXC_F_IOMAN_WUD_ACK1_PORT7_POS 24
bogdanm 0:9b334a45a8ff 188 #define MXC_F_IOMAN_WUD_ACK1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT7_POS))
bogdanm 0:9b334a45a8ff 189
bogdanm 0:9b334a45a8ff 190 #define MXC_F_IOMAN_ALI_REQ0_PORT0_POS 0
bogdanm 0:9b334a45a8ff 191 #define MXC_F_IOMAN_ALI_REQ0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT0_POS))
bogdanm 0:9b334a45a8ff 192 #define MXC_F_IOMAN_ALI_REQ0_PORT1_POS 8
bogdanm 0:9b334a45a8ff 193 #define MXC_F_IOMAN_ALI_REQ0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT1_POS))
bogdanm 0:9b334a45a8ff 194 #define MXC_F_IOMAN_ALI_REQ0_PORT2_POS 16
bogdanm 0:9b334a45a8ff 195 #define MXC_F_IOMAN_ALI_REQ0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT2_POS))
bogdanm 0:9b334a45a8ff 196 #define MXC_F_IOMAN_ALI_REQ0_PORT3_POS 24
bogdanm 0:9b334a45a8ff 197 #define MXC_F_IOMAN_ALI_REQ0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT3_POS))
bogdanm 0:9b334a45a8ff 198
bogdanm 0:9b334a45a8ff 199 #define MXC_F_IOMAN_ALI_REQ1_PORT4_POS 0
bogdanm 0:9b334a45a8ff 200 #define MXC_F_IOMAN_ALI_REQ1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT4_POS))
bogdanm 0:9b334a45a8ff 201 #define MXC_F_IOMAN_ALI_REQ1_PORT5_POS 8
bogdanm 0:9b334a45a8ff 202 #define MXC_F_IOMAN_ALI_REQ1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT5_POS))
bogdanm 0:9b334a45a8ff 203 #define MXC_F_IOMAN_ALI_REQ1_PORT6_POS 16
bogdanm 0:9b334a45a8ff 204 #define MXC_F_IOMAN_ALI_REQ1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT6_POS))
bogdanm 0:9b334a45a8ff 205 #define MXC_F_IOMAN_ALI_REQ1_PORT7_POS 24
bogdanm 0:9b334a45a8ff 206 #define MXC_F_IOMAN_ALI_REQ1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT7_POS))
bogdanm 0:9b334a45a8ff 207
bogdanm 0:9b334a45a8ff 208 #define MXC_F_IOMAN_ALI_ACK0_PORT0_POS 0
bogdanm 0:9b334a45a8ff 209 #define MXC_F_IOMAN_ALI_ACK0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT0_POS))
bogdanm 0:9b334a45a8ff 210 #define MXC_F_IOMAN_ALI_ACK0_PORT1_POS 8
bogdanm 0:9b334a45a8ff 211 #define MXC_F_IOMAN_ALI_ACK0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT1_POS))
bogdanm 0:9b334a45a8ff 212 #define MXC_F_IOMAN_ALI_ACK0_PORT2_POS 16
bogdanm 0:9b334a45a8ff 213 #define MXC_F_IOMAN_ALI_ACK0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT2_POS))
bogdanm 0:9b334a45a8ff 214 #define MXC_F_IOMAN_ALI_ACK0_PORT3_POS 24
bogdanm 0:9b334a45a8ff 215 #define MXC_F_IOMAN_ALI_ACK0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT3_POS))
bogdanm 0:9b334a45a8ff 216
bogdanm 0:9b334a45a8ff 217 #define MXC_F_IOMAN_ALI_ACK1_PORT4_POS 0
bogdanm 0:9b334a45a8ff 218 #define MXC_F_IOMAN_ALI_ACK1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT4_POS))
bogdanm 0:9b334a45a8ff 219 #define MXC_F_IOMAN_ALI_ACK1_PORT5_POS 8
bogdanm 0:9b334a45a8ff 220 #define MXC_F_IOMAN_ALI_ACK1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT5_POS))
bogdanm 0:9b334a45a8ff 221 #define MXC_F_IOMAN_ALI_ACK1_PORT6_POS 16
bogdanm 0:9b334a45a8ff 222 #define MXC_F_IOMAN_ALI_ACK1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT6_POS))
bogdanm 0:9b334a45a8ff 223 #define MXC_F_IOMAN_ALI_ACK1_PORT7_POS 24
bogdanm 0:9b334a45a8ff 224 #define MXC_F_IOMAN_ALI_ACK1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT7_POS))
bogdanm 0:9b334a45a8ff 225
bogdanm 0:9b334a45a8ff 226 #define MXC_F_IOMAN_SPI_MAPPING_POS 0
bogdanm 0:9b334a45a8ff 227 #define MXC_F_IOMAN_SPI_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPI_MAPPING_POS))
bogdanm 0:9b334a45a8ff 228 #define MXC_F_IOMAN_SPI_CORE_IO_POS 4
bogdanm 0:9b334a45a8ff 229 #define MXC_F_IOMAN_SPI_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_CORE_IO_POS))
bogdanm 0:9b334a45a8ff 230 #define MXC_F_IOMAN_SPI_SS0_IO_POS 8
bogdanm 0:9b334a45a8ff 231 #define MXC_F_IOMAN_SPI_SS0_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS0_IO_POS))
bogdanm 0:9b334a45a8ff 232 #define MXC_F_IOMAN_SPI_SS1_IO_POS 9
bogdanm 0:9b334a45a8ff 233 #define MXC_F_IOMAN_SPI_SS1_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS1_IO_POS))
bogdanm 0:9b334a45a8ff 234 #define MXC_F_IOMAN_SPI_SS2_IO_POS 10
bogdanm 0:9b334a45a8ff 235 #define MXC_F_IOMAN_SPI_SS2_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS2_IO_POS))
bogdanm 0:9b334a45a8ff 236 #define MXC_F_IOMAN_SPI_SS3_IO_POS 11
bogdanm 0:9b334a45a8ff 237 #define MXC_F_IOMAN_SPI_SS3_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS3_IO_POS))
bogdanm 0:9b334a45a8ff 238 #define MXC_F_IOMAN_SPI_SS4_IO_POS 12
bogdanm 0:9b334a45a8ff 239 #define MXC_F_IOMAN_SPI_SS4_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS4_IO_POS))
bogdanm 0:9b334a45a8ff 240 #define MXC_F_IOMAN_SPI_SR0_IO_POS 16
bogdanm 0:9b334a45a8ff 241 #define MXC_F_IOMAN_SPI_SR0_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SR0_IO_POS))
bogdanm 0:9b334a45a8ff 242 #define MXC_F_IOMAN_SPI_SR1_IO_POS 17
bogdanm 0:9b334a45a8ff 243 #define MXC_F_IOMAN_SPI_SR1_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SR1_IO_POS))
bogdanm 0:9b334a45a8ff 244 #define MXC_F_IOMAN_SPI_QUAD_IO_POS 20
bogdanm 0:9b334a45a8ff 245 #define MXC_F_IOMAN_SPI_QUAD_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_QUAD_IO_POS))
bogdanm 0:9b334a45a8ff 246 #define MXC_F_IOMAN_SPI_FAST_MODE_POS 24
bogdanm 0:9b334a45a8ff 247 #define MXC_F_IOMAN_SPI_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_FAST_MODE_POS))
bogdanm 0:9b334a45a8ff 248
bogdanm 0:9b334a45a8ff 249 #define MXC_F_IOMAN_UART_MAPPING_POS 0
bogdanm 0:9b334a45a8ff 250 #define MXC_F_IOMAN_UART_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_UART_MAPPING_POS))
bogdanm 0:9b334a45a8ff 251 #define MXC_F_IOMAN_UART_CORE_IO_POS 4
bogdanm 0:9b334a45a8ff 252 #define MXC_F_IOMAN_UART_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_CORE_IO_POS))
bogdanm 0:9b334a45a8ff 253 #define MXC_F_IOMAN_UART_CTS_IO_POS 5
bogdanm 0:9b334a45a8ff 254 #define MXC_F_IOMAN_UART_CTS_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_CTS_IO_POS))
bogdanm 0:9b334a45a8ff 255 #define MXC_F_IOMAN_UART_RTS_IO_POS 6
bogdanm 0:9b334a45a8ff 256 #define MXC_F_IOMAN_UART_RTS_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_RTS_IO_POS))
bogdanm 0:9b334a45a8ff 257
bogdanm 0:9b334a45a8ff 258 #define MXC_F_IOMAN_I2CM_MAPPING_POS 0
bogdanm 0:9b334a45a8ff 259 #define MXC_F_IOMAN_I2CM_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM_MAPPING_POS))
bogdanm 0:9b334a45a8ff 260 #define MXC_F_IOMAN_I2CM_CORE_IO_POS 4
bogdanm 0:9b334a45a8ff 261 #define MXC_F_IOMAN_I2CM_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM_CORE_IO_POS))
bogdanm 0:9b334a45a8ff 262
bogdanm 0:9b334a45a8ff 263 #define MXC_F_IOMAN_I2CS_MAPPING_POS 0
bogdanm 0:9b334a45a8ff 264 #define MXC_F_IOMAN_I2CS_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CS_MAPPING_POS))
bogdanm 0:9b334a45a8ff 265 #define MXC_F_IOMAN_I2CS_CORE_IO_POS 4
bogdanm 0:9b334a45a8ff 266 #define MXC_F_IOMAN_I2CS_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_CORE_IO_POS))
bogdanm 0:9b334a45a8ff 267
bogdanm 0:9b334a45a8ff 268 #define MXC_F_IOMAN_LCD_COM_REQ_COM_IO_POS 0
bogdanm 0:9b334a45a8ff 269 #define MXC_F_IOMAN_LCD_COM_REQ_COM_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_COM_REQ_COM_IO_POS))
bogdanm 0:9b334a45a8ff 270
bogdanm 0:9b334a45a8ff 271 #define MXC_F_IOMAN_LCD_COM_ACK_COM_IO_POS 0
bogdanm 0:9b334a45a8ff 272 #define MXC_F_IOMAN_LCD_COM_ACK_COM_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_COM_ACK_COM_IO_POS))
bogdanm 0:9b334a45a8ff 273
bogdanm 0:9b334a45a8ff 274 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24_POS 0
bogdanm 0:9b334a45a8ff 275 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24_POS))
bogdanm 0:9b334a45a8ff 276 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25_POS 1
bogdanm 0:9b334a45a8ff 277 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25_POS))
bogdanm 0:9b334a45a8ff 278 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26_POS 2
bogdanm 0:9b334a45a8ff 279 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26_POS))
bogdanm 0:9b334a45a8ff 280 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27_POS 3
bogdanm 0:9b334a45a8ff 281 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27_POS))
bogdanm 0:9b334a45a8ff 282 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28_POS 4
bogdanm 0:9b334a45a8ff 283 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28_POS))
bogdanm 0:9b334a45a8ff 284 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29_POS 5
bogdanm 0:9b334a45a8ff 285 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29_POS))
bogdanm 0:9b334a45a8ff 286 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30_POS 6
bogdanm 0:9b334a45a8ff 287 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30_POS))
bogdanm 0:9b334a45a8ff 288 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31_POS 7
bogdanm 0:9b334a45a8ff 289 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31_POS))
bogdanm 0:9b334a45a8ff 290 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32_POS 8
bogdanm 0:9b334a45a8ff 291 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32_POS))
bogdanm 0:9b334a45a8ff 292 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33_POS 9
bogdanm 0:9b334a45a8ff 293 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33_POS))
bogdanm 0:9b334a45a8ff 294 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34_POS 10
bogdanm 0:9b334a45a8ff 295 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34_POS))
bogdanm 0:9b334a45a8ff 296 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35_POS 11
bogdanm 0:9b334a45a8ff 297 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35_POS))
bogdanm 0:9b334a45a8ff 298 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36_POS 12
bogdanm 0:9b334a45a8ff 299 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36_POS))
bogdanm 0:9b334a45a8ff 300 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37_POS 13
bogdanm 0:9b334a45a8ff 301 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37_POS))
bogdanm 0:9b334a45a8ff 302 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38_POS 14
bogdanm 0:9b334a45a8ff 303 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38_POS))
bogdanm 0:9b334a45a8ff 304 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39_POS 15
bogdanm 0:9b334a45a8ff 305 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39_POS))
bogdanm 0:9b334a45a8ff 306 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40_POS 16
bogdanm 0:9b334a45a8ff 307 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40_POS))
bogdanm 0:9b334a45a8ff 308 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41_POS 17
bogdanm 0:9b334a45a8ff 309 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41_POS))
bogdanm 0:9b334a45a8ff 310 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42_POS 18
bogdanm 0:9b334a45a8ff 311 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42_POS))
bogdanm 0:9b334a45a8ff 312 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43_POS 19
bogdanm 0:9b334a45a8ff 313 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43_POS))
bogdanm 0:9b334a45a8ff 314 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44_POS 20
bogdanm 0:9b334a45a8ff 315 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44_POS))
bogdanm 0:9b334a45a8ff 316 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45_POS 21
bogdanm 0:9b334a45a8ff 317 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45_POS))
bogdanm 0:9b334a45a8ff 318 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46_POS 22
bogdanm 0:9b334a45a8ff 319 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46_POS))
bogdanm 0:9b334a45a8ff 320 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47_POS 23
bogdanm 0:9b334a45a8ff 321 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47_POS))
bogdanm 0:9b334a45a8ff 322 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48_POS 24
bogdanm 0:9b334a45a8ff 323 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48_POS))
bogdanm 0:9b334a45a8ff 324 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49_POS 25
bogdanm 0:9b334a45a8ff 325 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49_POS))
bogdanm 0:9b334a45a8ff 326 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50_POS 26
bogdanm 0:9b334a45a8ff 327 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50_POS))
bogdanm 0:9b334a45a8ff 328 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51_POS 27
bogdanm 0:9b334a45a8ff 329 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51_POS))
bogdanm 0:9b334a45a8ff 330 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52_POS 28
bogdanm 0:9b334a45a8ff 331 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52_POS))
bogdanm 0:9b334a45a8ff 332 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53_POS 29
bogdanm 0:9b334a45a8ff 333 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53_POS))
bogdanm 0:9b334a45a8ff 334 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54_POS 30
bogdanm 0:9b334a45a8ff 335 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54_POS))
bogdanm 0:9b334a45a8ff 336 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55_POS 31
bogdanm 0:9b334a45a8ff 337 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55_POS))
bogdanm 0:9b334a45a8ff 338
bogdanm 0:9b334a45a8ff 339 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56_POS 0
bogdanm 0:9b334a45a8ff 340 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56_POS))
bogdanm 0:9b334a45a8ff 341 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57_POS 1
bogdanm 0:9b334a45a8ff 342 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57_POS))
bogdanm 0:9b334a45a8ff 343 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58_POS 2
bogdanm 0:9b334a45a8ff 344 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58_POS))
bogdanm 0:9b334a45a8ff 345 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59_POS 3
bogdanm 0:9b334a45a8ff 346 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59_POS))
bogdanm 0:9b334a45a8ff 347 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60_POS 4
bogdanm 0:9b334a45a8ff 348 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60_POS))
bogdanm 0:9b334a45a8ff 349 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61_POS 5
bogdanm 0:9b334a45a8ff 350 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61_POS))
bogdanm 0:9b334a45a8ff 351 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62_POS 6
bogdanm 0:9b334a45a8ff 352 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62_POS))
bogdanm 0:9b334a45a8ff 353 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63_POS 7
bogdanm 0:9b334a45a8ff 354 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63_POS))
bogdanm 0:9b334a45a8ff 355
bogdanm 0:9b334a45a8ff 356 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24_POS 0
bogdanm 0:9b334a45a8ff 357 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24_POS))
bogdanm 0:9b334a45a8ff 358 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25_POS 1
bogdanm 0:9b334a45a8ff 359 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25_POS))
bogdanm 0:9b334a45a8ff 360 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26_POS 2
bogdanm 0:9b334a45a8ff 361 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26_POS))
bogdanm 0:9b334a45a8ff 362 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27_POS 3
bogdanm 0:9b334a45a8ff 363 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27_POS))
bogdanm 0:9b334a45a8ff 364 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28_POS 4
bogdanm 0:9b334a45a8ff 365 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28_POS))
bogdanm 0:9b334a45a8ff 366 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29_POS 5
bogdanm 0:9b334a45a8ff 367 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29_POS))
bogdanm 0:9b334a45a8ff 368 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30_POS 6
bogdanm 0:9b334a45a8ff 369 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30_POS))
bogdanm 0:9b334a45a8ff 370 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31_POS 7
bogdanm 0:9b334a45a8ff 371 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31_POS))
bogdanm 0:9b334a45a8ff 372 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32_POS 8
bogdanm 0:9b334a45a8ff 373 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32_POS))
bogdanm 0:9b334a45a8ff 374 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33_POS 9
bogdanm 0:9b334a45a8ff 375 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33_POS))
bogdanm 0:9b334a45a8ff 376 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34_POS 10
bogdanm 0:9b334a45a8ff 377 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34_POS))
bogdanm 0:9b334a45a8ff 378 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35_POS 11
bogdanm 0:9b334a45a8ff 379 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35_POS))
bogdanm 0:9b334a45a8ff 380 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36_POS 12
bogdanm 0:9b334a45a8ff 381 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36_POS))
bogdanm 0:9b334a45a8ff 382 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37_POS 13
bogdanm 0:9b334a45a8ff 383 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37_POS))
bogdanm 0:9b334a45a8ff 384 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38_POS 14
bogdanm 0:9b334a45a8ff 385 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38_POS))
bogdanm 0:9b334a45a8ff 386 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39_POS 15
bogdanm 0:9b334a45a8ff 387 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39_POS))
bogdanm 0:9b334a45a8ff 388 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40_POS 16
bogdanm 0:9b334a45a8ff 389 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40_POS))
bogdanm 0:9b334a45a8ff 390 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41_POS 17
bogdanm 0:9b334a45a8ff 391 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41_POS))
bogdanm 0:9b334a45a8ff 392 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42_POS 18
bogdanm 0:9b334a45a8ff 393 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42_POS))
bogdanm 0:9b334a45a8ff 394 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43_POS 19
bogdanm 0:9b334a45a8ff 395 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43_POS))
bogdanm 0:9b334a45a8ff 396 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44_POS 20
bogdanm 0:9b334a45a8ff 397 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44_POS))
bogdanm 0:9b334a45a8ff 398 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45_POS 21
bogdanm 0:9b334a45a8ff 399 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45_POS))
bogdanm 0:9b334a45a8ff 400 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46_POS 22
bogdanm 0:9b334a45a8ff 401 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46_POS))
bogdanm 0:9b334a45a8ff 402 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47_POS 23
bogdanm 0:9b334a45a8ff 403 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47_POS))
bogdanm 0:9b334a45a8ff 404 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48_POS 24
bogdanm 0:9b334a45a8ff 405 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48_POS))
bogdanm 0:9b334a45a8ff 406 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49_POS 25
bogdanm 0:9b334a45a8ff 407 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49_POS))
bogdanm 0:9b334a45a8ff 408 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50_POS 26
bogdanm 0:9b334a45a8ff 409 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50_POS))
bogdanm 0:9b334a45a8ff 410 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51_POS 27
bogdanm 0:9b334a45a8ff 411 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51_POS))
bogdanm 0:9b334a45a8ff 412 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52_POS 28
bogdanm 0:9b334a45a8ff 413 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52_POS))
bogdanm 0:9b334a45a8ff 414 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53_POS 29
bogdanm 0:9b334a45a8ff 415 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53_POS))
bogdanm 0:9b334a45a8ff 416 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54_POS 30
bogdanm 0:9b334a45a8ff 417 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54_POS))
bogdanm 0:9b334a45a8ff 418 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55_POS 31
bogdanm 0:9b334a45a8ff 419 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55_POS))
bogdanm 0:9b334a45a8ff 420
bogdanm 0:9b334a45a8ff 421 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56_POS 0
bogdanm 0:9b334a45a8ff 422 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56_POS))
bogdanm 0:9b334a45a8ff 423 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57_POS 1
bogdanm 0:9b334a45a8ff 424 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57_POS))
bogdanm 0:9b334a45a8ff 425 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58_POS 2
bogdanm 0:9b334a45a8ff 426 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58_POS))
bogdanm 0:9b334a45a8ff 427 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59_POS 3
bogdanm 0:9b334a45a8ff 428 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59_POS))
bogdanm 0:9b334a45a8ff 429 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60_POS 4
bogdanm 0:9b334a45a8ff 430 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60_POS))
bogdanm 0:9b334a45a8ff 431 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61_POS 5
bogdanm 0:9b334a45a8ff 432 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61_POS))
bogdanm 0:9b334a45a8ff 433 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62_POS 6
bogdanm 0:9b334a45a8ff 434 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62_POS))
bogdanm 0:9b334a45a8ff 435 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63_POS 7
bogdanm 0:9b334a45a8ff 436 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63_POS))
bogdanm 0:9b334a45a8ff 437
bogdanm 0:9b334a45a8ff 438 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0_POS 0
bogdanm 0:9b334a45a8ff 439 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0_POS))
bogdanm 0:9b334a45a8ff 440 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1_POS 1
bogdanm 0:9b334a45a8ff 441 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1_POS))
bogdanm 0:9b334a45a8ff 442 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2_POS 2
bogdanm 0:9b334a45a8ff 443 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2_POS))
bogdanm 0:9b334a45a8ff 444 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3_POS 3
bogdanm 0:9b334a45a8ff 445 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3_POS))
bogdanm 0:9b334a45a8ff 446 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4_POS 4
bogdanm 0:9b334a45a8ff 447 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4_POS))
bogdanm 0:9b334a45a8ff 448 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5_POS 5
bogdanm 0:9b334a45a8ff 449 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5_POS))
bogdanm 0:9b334a45a8ff 450 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6_POS 6
bogdanm 0:9b334a45a8ff 451 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6_POS))
bogdanm 0:9b334a45a8ff 452 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7_POS 7
bogdanm 0:9b334a45a8ff 453 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7_POS))
bogdanm 0:9b334a45a8ff 454
bogdanm 0:9b334a45a8ff 455 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0_POS 0
bogdanm 0:9b334a45a8ff 456 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0_POS))
bogdanm 0:9b334a45a8ff 457 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1_POS 1
bogdanm 0:9b334a45a8ff 458 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1_POS))
bogdanm 0:9b334a45a8ff 459 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2_POS 2
bogdanm 0:9b334a45a8ff 460 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2_POS))
bogdanm 0:9b334a45a8ff 461 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3_POS 3
bogdanm 0:9b334a45a8ff 462 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3_POS))
bogdanm 0:9b334a45a8ff 463 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4_POS 4
bogdanm 0:9b334a45a8ff 464 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4_POS))
bogdanm 0:9b334a45a8ff 465 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5_POS 5
bogdanm 0:9b334a45a8ff 466 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5_POS))
bogdanm 0:9b334a45a8ff 467 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6_POS 6
bogdanm 0:9b334a45a8ff 468 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6_POS))
bogdanm 0:9b334a45a8ff 469 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7_POS 7
bogdanm 0:9b334a45a8ff 470 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7_POS))
bogdanm 0:9b334a45a8ff 471
bogdanm 0:9b334a45a8ff 472 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT0_POS 0
bogdanm 0:9b334a45a8ff 473 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT0 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT0_POS))
bogdanm 0:9b334a45a8ff 474 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT1_POS 4
bogdanm 0:9b334a45a8ff 475 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT1 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT1_POS))
bogdanm 0:9b334a45a8ff 476 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT2_POS 8
bogdanm 0:9b334a45a8ff 477 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT2 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT2_POS))
bogdanm 0:9b334a45a8ff 478 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT3_POS 12
bogdanm 0:9b334a45a8ff 479 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT3 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT3_POS))
bogdanm 0:9b334a45a8ff 480 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT4_POS 16
bogdanm 0:9b334a45a8ff 481 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT4 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT4_POS))
bogdanm 0:9b334a45a8ff 482 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT5_POS 20
bogdanm 0:9b334a45a8ff 483 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT5 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT5_POS))
bogdanm 0:9b334a45a8ff 484 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT6_POS 24
bogdanm 0:9b334a45a8ff 485 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT6 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT6_POS))
bogdanm 0:9b334a45a8ff 486 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT7_POS 28
bogdanm 0:9b334a45a8ff 487 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT7 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT7_POS))
bogdanm 0:9b334a45a8ff 488
bogdanm 0:9b334a45a8ff 489 #define MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL_POS 0
bogdanm 0:9b334a45a8ff 490 #define MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL_POS))
bogdanm 0:9b334a45a8ff 491 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE_POS 4
bogdanm 0:9b334a45a8ff 492 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE ((uint32_t)(0x00000003UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE_POS))
bogdanm 0:9b334a45a8ff 493 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE_POS 6
bogdanm 0:9b334a45a8ff 494 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE_POS))
bogdanm 0:9b334a45a8ff 495 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE_POS 8
bogdanm 0:9b334a45a8ff 496 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE ((uint32_t)(0x00000003UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE_POS))
bogdanm 0:9b334a45a8ff 497 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE_POS 10
bogdanm 0:9b334a45a8ff 498 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE_POS))
bogdanm 0:9b334a45a8ff 499
bogdanm 0:9b334a45a8ff 500 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 501 }
bogdanm 0:9b334a45a8ff 502 #endif
bogdanm 0:9b334a45a8ff 503
bogdanm 0:9b334a45a8ff 504 /**
bogdanm 0:9b334a45a8ff 505 * @}
bogdanm 0:9b334a45a8ff 506 */
bogdanm 0:9b334a45a8ff 507
bogdanm 0:9b334a45a8ff 508 #endif /* _MXC_IOMAN_REGS_H_ */