Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Maxim/TARGET_MAX32600/adc_regs.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /*******************************************************************************
bogdanm 0:9b334a45a8ff 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Permission is hereby granted, free of charge, to any person obtaining a
bogdanm 0:9b334a45a8ff 5 * copy of this software and associated documentation files (the "Software"),
bogdanm 0:9b334a45a8ff 6 * to deal in the Software without restriction, including without limitation
bogdanm 0:9b334a45a8ff 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
bogdanm 0:9b334a45a8ff 8 * and/or sell copies of the Software, and to permit persons to whom the
bogdanm 0:9b334a45a8ff 9 * Software is furnished to do so, subject to the following conditions:
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * The above copyright notice and this permission notice shall be included
bogdanm 0:9b334a45a8ff 12 * in all copies or substantial portions of the Software.
bogdanm 0:9b334a45a8ff 13 *
bogdanm 0:9b334a45a8ff 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
bogdanm 0:9b334a45a8ff 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
bogdanm 0:9b334a45a8ff 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
bogdanm 0:9b334a45a8ff 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
bogdanm 0:9b334a45a8ff 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
bogdanm 0:9b334a45a8ff 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
bogdanm 0:9b334a45a8ff 20 * OTHER DEALINGS IN THE SOFTWARE.
bogdanm 0:9b334a45a8ff 21 *
bogdanm 0:9b334a45a8ff 22 * Except as contained in this notice, the name of Maxim Integrated
bogdanm 0:9b334a45a8ff 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
bogdanm 0:9b334a45a8ff 24 * Products, Inc. Branding Policy.
bogdanm 0:9b334a45a8ff 25 *
bogdanm 0:9b334a45a8ff 26 * The mere transfer of this software does not imply any licenses
bogdanm 0:9b334a45a8ff 27 * of trade secrets, proprietary technology, copyrights, patents,
bogdanm 0:9b334a45a8ff 28 * trademarks, maskwork rights, or any other form of intellectual
bogdanm 0:9b334a45a8ff 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
bogdanm 0:9b334a45a8ff 30 * ownership rights.
bogdanm 0:9b334a45a8ff 31 *******************************************************************************
bogdanm 0:9b334a45a8ff 32 */
bogdanm 0:9b334a45a8ff 33
bogdanm 0:9b334a45a8ff 34 #ifndef _MXC_ADC_REGS_H
bogdanm 0:9b334a45a8ff 35 #define _MXC_ADC_REGS_H
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 38 extern "C" {
bogdanm 0:9b334a45a8ff 39 #endif
bogdanm 0:9b334a45a8ff 40
bogdanm 0:9b334a45a8ff 41 #include <stdint.h>
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 /**
bogdanm 0:9b334a45a8ff 44 * @file adc_regs.h
bogdanm 0:9b334a45a8ff 45 * @addtogroup adc ADC
bogdanm 0:9b334a45a8ff 46 * @{
bogdanm 0:9b334a45a8ff 47 */
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 /**
bogdanm 0:9b334a45a8ff 50 * @brief Defines ADC Modes.
bogdanm 0:9b334a45a8ff 51 */
bogdanm 0:9b334a45a8ff 52 typedef enum {
bogdanm 0:9b334a45a8ff 53 /** Single Mode Full Rate */
bogdanm 0:9b334a45a8ff 54 MXC_E_ADC_MODE_SMPLCNT_FULL_RATE = 0,
bogdanm 0:9b334a45a8ff 55 /** Single Mode Low Power */
bogdanm 0:9b334a45a8ff 56 MXC_E_ADC_MODE_SMPLCNT_LOW_POWER = 1,
bogdanm 0:9b334a45a8ff 57 /** Continuous Mode Full Rate */
bogdanm 0:9b334a45a8ff 58 MXC_E_ADC_MODE_CONTINUOUS_FULL_RATE = 2,
bogdanm 0:9b334a45a8ff 59 /** Continuous Mode Low Power */
bogdanm 0:9b334a45a8ff 60 MXC_E_ADC_MODE_CONTINUOUS_LOW_POWER = 3,
bogdanm 0:9b334a45a8ff 61 /** Single Mode Full Rate with Scan Enabled */
bogdanm 0:9b334a45a8ff 62 MXC_E_ADC_MODE_SMPLCNT_SCAN_FULL_RATE = 8,
bogdanm 0:9b334a45a8ff 63 /** Single Mode Low Power with Scan Enabled */
bogdanm 0:9b334a45a8ff 64 MXC_E_ADC_MODE_SMPLCNT_SCAN_LOW_POWER = 9,
bogdanm 0:9b334a45a8ff 65 /** Continuous Mode Full Rate with Scan Enabled */
bogdanm 0:9b334a45a8ff 66 MXC_E_ADC_MODE_CONTINUOUS_SCAN_FULL_RATE = 10,
bogdanm 0:9b334a45a8ff 67 /** Continuous Mode Low Power with Scan Enabled */
bogdanm 0:9b334a45a8ff 68 MXC_E_ADC_MODE_CONTINUOUS_SCAN_LOW_POWER = 11
bogdanm 0:9b334a45a8ff 69 } mxc_adc_mode_t;
bogdanm 0:9b334a45a8ff 70
bogdanm 0:9b334a45a8ff 71 /**
bogdanm 0:9b334a45a8ff 72 * @brief Defines ADC Range Control.
bogdanm 0:9b334a45a8ff 73 */
bogdanm 0:9b334a45a8ff 74 typedef enum {
bogdanm 0:9b334a45a8ff 75 /** Bi-polar Operation (-Vref/2 -> Vref/2) */
bogdanm 0:9b334a45a8ff 76 MXC_E_ADC_RANGE_HALF = 0,
bogdanm 0:9b334a45a8ff 77 /** Bi-polar Operation (-Vref -> Vref) */
bogdanm 0:9b334a45a8ff 78 MXC_E_ADC_RANGE_FULL
bogdanm 0:9b334a45a8ff 79 } mxc_adc_range_t;
bogdanm 0:9b334a45a8ff 80
bogdanm 0:9b334a45a8ff 81 /**
bogdanm 0:9b334a45a8ff 82 * @brief Defines ADC Bipolar operation.
bogdanm 0:9b334a45a8ff 83 */
bogdanm 0:9b334a45a8ff 84 typedef enum {
bogdanm 0:9b334a45a8ff 85 /** Uni-polar operation (0 -> Vref) */
bogdanm 0:9b334a45a8ff 86 MXC_E_ADC_BI_POL_UNIPOLAR = 0,
bogdanm 0:9b334a45a8ff 87 /** Bi-polar operation see ADC Range Control */
bogdanm 0:9b334a45a8ff 88 MXC_E_ADC_BI_POL_BIPOLAR
bogdanm 0:9b334a45a8ff 89 } mxc_adc_bi_pol_t;
bogdanm 0:9b334a45a8ff 90
bogdanm 0:9b334a45a8ff 91 /**
bogdanm 0:9b334a45a8ff 92 * @brief Defines Decimation Filter Modes.
bogdanm 0:9b334a45a8ff 93 */
bogdanm 0:9b334a45a8ff 94 typedef enum {
bogdanm 0:9b334a45a8ff 95 /** Decimation Filter ByPassed */
bogdanm 0:9b334a45a8ff 96 MXC_E_ADC_AVG_MODE_FILTER_BYPASS = 0,
bogdanm 0:9b334a45a8ff 97 /** Output Average Only*/
bogdanm 0:9b334a45a8ff 98 MXC_E_ADC_AVG_MODE_FILTER_OUTPUT,
bogdanm 0:9b334a45a8ff 99 /** Output Average and Raw Data (Test Mode Only) */
bogdanm 0:9b334a45a8ff 100 MXC_E_ADC_AVG_MODE_FILTER_OUTPUT_RAW
bogdanm 0:9b334a45a8ff 101 } mxc_adc_avg_mode_t;
bogdanm 0:9b334a45a8ff 102
bogdanm 0:9b334a45a8ff 103 /**
bogdanm 0:9b334a45a8ff 104 * @brief Defines ADC StartMode Modes.
bogdanm 0:9b334a45a8ff 105 */
bogdanm 0:9b334a45a8ff 106 typedef enum {
bogdanm 0:9b334a45a8ff 107 /** StarMode via Software */
bogdanm 0:9b334a45a8ff 108 MXC_E_ADC_STRT_MODE_SOFTWARE = 0,
bogdanm 0:9b334a45a8ff 109 /** StarMode via PulseTrain */
bogdanm 0:9b334a45a8ff 110 MXC_E_ADC_STRT_MODE_PULSETRAIN
bogdanm 0:9b334a45a8ff 111 } mxc_adc_strt_mode_t;
bogdanm 0:9b334a45a8ff 112
bogdanm 0:9b334a45a8ff 113 /**
bogdanm 0:9b334a45a8ff 114 * @brief Defines Mux Channel Select for the Positive Input to the ADC.
bogdanm 0:9b334a45a8ff 115 */
bogdanm 0:9b334a45a8ff 116 typedef enum {
bogdanm 0:9b334a45a8ff 117 /** Single Mode Input AIN0+; Diff Mode AIN0+/AIN8- */
bogdanm 0:9b334a45a8ff 118 MXC_E_ADC_PGA_MUX_CH_SEL_AIN0 = 0,
bogdanm 0:9b334a45a8ff 119 /** Single Mode Input AIN1+; Diff Mode AIN1+/AIN9- */
bogdanm 0:9b334a45a8ff 120 MXC_E_ADC_PGA_MUX_CH_SEL_AIN1 = 1,
bogdanm 0:9b334a45a8ff 121 /** Single Mode Input AIN2+; Diff Mode AIN2+/AIN10- */
bogdanm 0:9b334a45a8ff 122 MXC_E_ADC_PGA_MUX_CH_SEL_AIN2 = 2,
bogdanm 0:9b334a45a8ff 123 /** Single Mode Input AIN3+; Diff Mode AIN3+/AIN11- */
bogdanm 0:9b334a45a8ff 124 MXC_E_ADC_PGA_MUX_CH_SEL_AIN3 = 3,
bogdanm 0:9b334a45a8ff 125 /** Single Mode Input AIN4+; Diff Mode AIN4+/AIN12- */
bogdanm 0:9b334a45a8ff 126 MXC_E_ADC_PGA_MUX_CH_SEL_AIN4 = 4,
bogdanm 0:9b334a45a8ff 127 /** Single Mode Input AIN5+; Diff Mode AIN5+/AIN13- */
bogdanm 0:9b334a45a8ff 128 MXC_E_ADC_PGA_MUX_CH_SEL_AIN5 = 5,
bogdanm 0:9b334a45a8ff 129 /** Single Mode Input AIN6+; Diff Mode AIN6+/AIN14- */
bogdanm 0:9b334a45a8ff 130 MXC_E_ADC_PGA_MUX_CH_SEL_AIN6 = 6,
bogdanm 0:9b334a45a8ff 131 /** Single Mode Input AIN7+; Diff Mode AIN7+/AIN15- */
bogdanm 0:9b334a45a8ff 132 MXC_E_ADC_PGA_MUX_CH_SEL_AIN7 = 7,
bogdanm 0:9b334a45a8ff 133 /** Single Mode Input AIN8+ */
bogdanm 0:9b334a45a8ff 134 MXC_E_ADC_PGA_MUX_CH_SEL_AIN8 = 8,
bogdanm 0:9b334a45a8ff 135 /** Single Mode Input AIN9+ */
bogdanm 0:9b334a45a8ff 136 MXC_E_ADC_PGA_MUX_CH_SEL_AIN9 = 9,
bogdanm 0:9b334a45a8ff 137 /** Single Mode Input AIN10+ */
bogdanm 0:9b334a45a8ff 138 MXC_E_ADC_PGA_MUX_CH_SEL_AIN10 = 10,
bogdanm 0:9b334a45a8ff 139 /** Single Mode Input AIN11+ */
bogdanm 0:9b334a45a8ff 140 MXC_E_ADC_PGA_MUX_CH_SEL_AIN11 = 11,
bogdanm 0:9b334a45a8ff 141 /** Single Mode Input AIN12+ */
bogdanm 0:9b334a45a8ff 142 MXC_E_ADC_PGA_MUX_CH_SEL_AIN12 = 12,
bogdanm 0:9b334a45a8ff 143 /** Single Mode Input AIN13+ */
bogdanm 0:9b334a45a8ff 144 MXC_E_ADC_PGA_MUX_CH_SEL_AIN13 = 13,
bogdanm 0:9b334a45a8ff 145 /** Single Mode Input AIN14+ */
bogdanm 0:9b334a45a8ff 146 MXC_E_ADC_PGA_MUX_CH_SEL_AIN14 = 14,
bogdanm 0:9b334a45a8ff 147 /** Single Mode Input AIN15+ */
bogdanm 0:9b334a45a8ff 148 MXC_E_ADC_PGA_MUX_CH_SEL_AIN15 = 15,
bogdanm 0:9b334a45a8ff 149 /** Positive Input VSSADC */
bogdanm 0:9b334a45a8ff 150 MXC_E_ADC_PGA_MUX_CH_SEL_VSSADC = 16,
bogdanm 0:9b334a45a8ff 151 /** Positive Input TMON_R */
bogdanm 0:9b334a45a8ff 152 MXC_E_ADC_PGA_MUX_CH_SEL_TMON_R = 17,
bogdanm 0:9b334a45a8ff 153 /** Positive Input VDDA/4 */
bogdanm 0:9b334a45a8ff 154 MXC_E_ADC_PGA_MUX_CH_SEL_VDDA4 = 18,
bogdanm 0:9b334a45a8ff 155 /** Positive Input PWRMAN_TST */
bogdanm 0:9b334a45a8ff 156 MXC_E_ADC_PGA_MUX_CH_SEL_PWRMON_TST = 19,
bogdanm 0:9b334a45a8ff 157 /** Positive Input Ain0Div */
bogdanm 0:9b334a45a8ff 158 MXC_E_ADC_PGA_MUX_CH_SEL_AIN0DIV = 20,
bogdanm 0:9b334a45a8ff 159 /** Positive Input OpAmp OUTA */
bogdanm 0:9b334a45a8ff 160 MXC_E_ADC_PGA_MUX_CH_SEL_OUTA = 32,
bogdanm 0:9b334a45a8ff 161 /** Positive Input OpAmp OUTB */
bogdanm 0:9b334a45a8ff 162 MXC_E_ADC_PGA_MUX_CH_SEL_OUTB = 33,
bogdanm 0:9b334a45a8ff 163 /** Positive Input OpAmp OUTC */
bogdanm 0:9b334a45a8ff 164 MXC_E_ADC_PGA_MUX_CH_SEL_OUTC = 34,
bogdanm 0:9b334a45a8ff 165 /** Positive Input OpAmp OUTD */
bogdanm 0:9b334a45a8ff 166 MXC_E_ADC_PGA_MUX_CH_SEL_OUTD = 35,
bogdanm 0:9b334a45a8ff 167 /** Positive INA+ */
bogdanm 0:9b334a45a8ff 168 MXC_E_ADC_PGA_MUX_CH_SEL_INAPLUS = 36,
bogdanm 0:9b334a45a8ff 169 /** Positive SNO_or */
bogdanm 0:9b334a45a8ff 170 MXC_E_ADC_PGA_MUX_CH_SEL_SNO_OR = 37,
bogdanm 0:9b334a45a8ff 171 /** Positive SCM_or */
bogdanm 0:9b334a45a8ff 172 MXC_E_ADC_PGA_MUX_CH_SEL_SCM_OR = 38,
bogdanm 0:9b334a45a8ff 173 /** Positive TPROBE_sense */
bogdanm 0:9b334a45a8ff 174 MXC_E_ADC_PGA_MUX_CH_SEL_TPROBE_SENSE = 48,
bogdanm 0:9b334a45a8ff 175 /** Positive VREFDAC */
bogdanm 0:9b334a45a8ff 176 MXC_E_ADC_PGA_MUX_CH_SEL_VREFDAC = 49,
bogdanm 0:9b334a45a8ff 177 /** Positive VREFADJ */
bogdanm 0:9b334a45a8ff 178 MXC_E_ADC_PGA_MUX_CH_SEL_VREFADJ = 50,
bogdanm 0:9b334a45a8ff 179 /** Positive Vdd3xtal */
bogdanm 0:9b334a45a8ff 180 MXC_E_ADC_PGA_MUX_CH_SEL_VDD3XTAL = 51
bogdanm 0:9b334a45a8ff 181 } mxc_adc_pga_mux_ch_sel_t;
bogdanm 0:9b334a45a8ff 182
bogdanm 0:9b334a45a8ff 183 /**
bogdanm 0:9b334a45a8ff 184 * @brief Decoded with the MUX Channel Select to enable Differential Mode Input to the ADC.
bogdanm 0:9b334a45a8ff 185 */
bogdanm 0:9b334a45a8ff 186 typedef enum {
bogdanm 0:9b334a45a8ff 187 /** Differential Mode Disabled */
bogdanm 0:9b334a45a8ff 188 MXC_E_ADC_PGA_MUX_DIFF_DISABLE = 0,
bogdanm 0:9b334a45a8ff 189 /** Differential Mode Enabled */
bogdanm 0:9b334a45a8ff 190 MXC_E_ADC_PGA_MUX_DIFF_ENABLE
bogdanm 0:9b334a45a8ff 191 } mxc_adc_pga_mux_diff_t;
bogdanm 0:9b334a45a8ff 192
bogdanm 0:9b334a45a8ff 193 /**
bogdanm 0:9b334a45a8ff 194 * @brief Defines the PGA Gain Options.
bogdanm 0:9b334a45a8ff 195 */
bogdanm 0:9b334a45a8ff 196 typedef enum {
bogdanm 0:9b334a45a8ff 197 /** PGA Gain = 1 */
bogdanm 0:9b334a45a8ff 198 MXC_E_ADC_PGA_GAIN_1 = 0,
bogdanm 0:9b334a45a8ff 199 /** PGA Gain = 2 */
bogdanm 0:9b334a45a8ff 200 MXC_E_ADC_PGA_GAIN_2,
bogdanm 0:9b334a45a8ff 201 /** PGA Gain = 4 */
bogdanm 0:9b334a45a8ff 202 MXC_E_ADC_PGA_GAIN_4,
bogdanm 0:9b334a45a8ff 203 /** PGA Gain = 8 */
bogdanm 0:9b334a45a8ff 204 MXC_E_ADC_PGA_GAIN_8,
bogdanm 0:9b334a45a8ff 205 } mxc_adc_pga_gain_t;
bogdanm 0:9b334a45a8ff 206
bogdanm 0:9b334a45a8ff 207 /**
bogdanm 0:9b334a45a8ff 208 * @brief Defines the Switch Control Mode.
bogdanm 0:9b334a45a8ff 209 */
bogdanm 0:9b334a45a8ff 210 typedef enum {
bogdanm 0:9b334a45a8ff 211 /** Switch Control Mode = Software */
bogdanm 0:9b334a45a8ff 212 MXC_E_ADC_SPST_SW_CTRL_SOFTWARE = 0,
bogdanm 0:9b334a45a8ff 213 /** Switch Control Mode = Pulse Train */
bogdanm 0:9b334a45a8ff 214 MXC_E_ADC_SPST_SW_CTRL_PULSETRAIN
bogdanm 0:9b334a45a8ff 215 } mxc_adc_spst_sw_ctrl_t;
bogdanm 0:9b334a45a8ff 216
bogdanm 0:9b334a45a8ff 217 /**
bogdanm 0:9b334a45a8ff 218 * @brief Defines the number of channels to scan when Scan Mode is enabled.
bogdanm 0:9b334a45a8ff 219 */
bogdanm 0:9b334a45a8ff 220 typedef enum {
bogdanm 0:9b334a45a8ff 221 /** Number of Channels to Scan = 1 */
bogdanm 0:9b334a45a8ff 222 MXC_E_ADC_SCAN_CNT_1 = 0,
bogdanm 0:9b334a45a8ff 223 /** Number of Channels to Scan = 2 */
bogdanm 0:9b334a45a8ff 224 MXC_E_ADC_SCAN_CNT_2,
bogdanm 0:9b334a45a8ff 225 /** Number of Channels to Scan = 3 */
bogdanm 0:9b334a45a8ff 226 MXC_E_ADC_SCAN_CNT_3,
bogdanm 0:9b334a45a8ff 227 /** Number of Channels to Scan = 4 */
bogdanm 0:9b334a45a8ff 228 MXC_E_ADC_SCAN_CNT_4,
bogdanm 0:9b334a45a8ff 229 /** Number of Channels to Scan = 5 */
bogdanm 0:9b334a45a8ff 230 MXC_E_ADC_SCAN_CNT_5,
bogdanm 0:9b334a45a8ff 231 /** Number of Channels to Scan = 6 */
bogdanm 0:9b334a45a8ff 232 MXC_E_ADC_SCAN_CNT_6,
bogdanm 0:9b334a45a8ff 233 /** Number of Channels to Scan = 7 */
bogdanm 0:9b334a45a8ff 234 MXC_E_ADC_SCAN_CNT_7,
bogdanm 0:9b334a45a8ff 235 /** Number of Channels to Scan = 8 */
bogdanm 0:9b334a45a8ff 236 MXC_E_ADC_SCAN_CNT_8,
bogdanm 0:9b334a45a8ff 237 } mxc_adc_scan_cnt_t;
bogdanm 0:9b334a45a8ff 238
bogdanm 0:9b334a45a8ff 239 /* Offset Register Description
bogdanm 0:9b334a45a8ff 240 ====== =================================================== */
bogdanm 0:9b334a45a8ff 241 typedef struct {
bogdanm 0:9b334a45a8ff 242 __IO uint32_t ctrl0; /* 0x0000 ADC Control Register 0 */
bogdanm 0:9b334a45a8ff 243 __IO uint32_t pga_ctrl; /* 0x0004 PGA Control Register */
bogdanm 0:9b334a45a8ff 244 __IO uint32_t tg_ctrl0; /* 0x0008 ADC Timing Generator Control 0 */
bogdanm 0:9b334a45a8ff 245 __IO uint32_t tg_ctrl1; /* 0x000C ADC Timing Generator Control 1 */
bogdanm 0:9b334a45a8ff 246 __IO uint32_t limit; /* 0x0010 ADC Limit Settings */
bogdanm 0:9b334a45a8ff 247 __IO uint32_t intr; /* 0x0014 ADC Interrupt Flags and Enable/Disable Controls */
bogdanm 0:9b334a45a8ff 248 __IO uint32_t out; /* 0x0018 ADC Output Register */
bogdanm 0:9b334a45a8ff 249 } mxc_adc_regs_t;
bogdanm 0:9b334a45a8ff 250
bogdanm 0:9b334a45a8ff 251 /* Offset Register Description
bogdanm 0:9b334a45a8ff 252 ====== =================================================== */
bogdanm 0:9b334a45a8ff 253 typedef struct {
bogdanm 0:9b334a45a8ff 254 __IO uint32_t ctrl1; /* 0x0000 ADC Control Register 1 */
bogdanm 0:9b334a45a8ff 255 __IO uint32_t scan1; /* 0x0004 ADC Auto-Scan Settings 1 */
bogdanm 0:9b334a45a8ff 256 __IO uint32_t scan2; /* 0x0008 ADC Auto-Scan Settings 2 */
bogdanm 0:9b334a45a8ff 257 __IO uint32_t ro_cal0; /* 0x000C ADC Ring Osc Calibration 0 */
bogdanm 0:9b334a45a8ff 258 __IO uint32_t ro_cal1; /* 0x0010 ADC Ring Osc Calibration 1 */
bogdanm 0:9b334a45a8ff 259 } mxc_adccfg_regs_t;
bogdanm 0:9b334a45a8ff 260
bogdanm 0:9b334a45a8ff 261 typedef struct {
bogdanm 0:9b334a45a8ff 262 __IO uint16_t data; /* 0x0000 Read to pull sample data from ADC FIFO */
bogdanm 0:9b334a45a8ff 263 } mxc_adc_fifo_regs_t;
bogdanm 0:9b334a45a8ff 264
bogdanm 0:9b334a45a8ff 265 /*
bogdanm 0:9b334a45a8ff 266 Register offsets for module ADC, ADCCFG, ADC_FIFO
bogdanm 0:9b334a45a8ff 267 */
bogdanm 0:9b334a45a8ff 268 #define MXC_R_ADC_OFFS_CTRL0 ((uint32_t)0x00000000UL)
bogdanm 0:9b334a45a8ff 269 #define MXC_R_ADC_OFFS_PGA_CTRL ((uint32_t)0x00000004UL)
bogdanm 0:9b334a45a8ff 270 #define MXC_R_ADC_OFFS_TG_CTRL0 ((uint32_t)0x00000008UL)
bogdanm 0:9b334a45a8ff 271 #define MXC_R_ADC_OFFS_TG_CTRL1 ((uint32_t)0x0000000CUL)
bogdanm 0:9b334a45a8ff 272 #define MXC_R_ADC_OFFS_LIMIT ((uint32_t)0x00000010UL)
bogdanm 0:9b334a45a8ff 273 #define MXC_R_ADC_OFFS_INTR ((uint32_t)0x00000014UL)
bogdanm 0:9b334a45a8ff 274 #define MXC_R_ADC_OFFS_OUT ((uint32_t)0x00000018UL)
bogdanm 0:9b334a45a8ff 275
bogdanm 0:9b334a45a8ff 276 #define MXC_R_ADCCFG_OFFS_CTRL1 ((uint32_t)0x00000000UL)
bogdanm 0:9b334a45a8ff 277 #define MXC_R_ADCCFG_OFFS_SCAN1 ((uint32_t)0x00000004UL)
bogdanm 0:9b334a45a8ff 278 #define MXC_R_ADCCFG_OFFS_SCAN2 ((uint32_t)0x00000008UL)
bogdanm 0:9b334a45a8ff 279 #define MXC_R_ADCCFG_OFFS_RO_CAL0 ((uint32_t)0x0000000CUL)
bogdanm 0:9b334a45a8ff 280 #define MXC_R_ADCCFG_OFFS_RO_CAL1 ((uint32_t)0x00000010UL)
bogdanm 0:9b334a45a8ff 281 #define MXC_R_ADC_FIFO_OFFS_DATA ((uint32_t)0x00000000UL)
bogdanm 0:9b334a45a8ff 282
bogdanm 0:9b334a45a8ff 283 /*
bogdanm 0:9b334a45a8ff 284 Field positions and masks for module ADC.
bogdanm 0:9b334a45a8ff 285 */
bogdanm 0:9b334a45a8ff 286 #define MXC_F_ADC_CTRL0_ADC_WAKE_CNT_POS 0
bogdanm 0:9b334a45a8ff 287 #define MXC_F_ADC_CTRL0_ADC_WAKE_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL0_ADC_WAKE_CNT_POS))
bogdanm 0:9b334a45a8ff 288 #define MXC_F_ADC_CTRL0_ADC_STRT_MODE_POS 5
bogdanm 0:9b334a45a8ff 289 #define MXC_F_ADC_CTRL0_ADC_STRT_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_STRT_MODE_POS))
bogdanm 0:9b334a45a8ff 290 #define MXC_F_ADC_CTRL0_ADC_RANGE_POS 6
bogdanm 0:9b334a45a8ff 291 #define MXC_F_ADC_CTRL0_ADC_RANGE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_RANGE_POS))
bogdanm 0:9b334a45a8ff 292 #define MXC_F_ADC_CTRL0_ADC_BI_POL_POS 7
bogdanm 0:9b334a45a8ff 293 #define MXC_F_ADC_CTRL0_ADC_BI_POL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_BI_POL_POS))
bogdanm 0:9b334a45a8ff 294 #define MXC_F_ADC_CTRL0_ADC_DV_REG_POS 8
bogdanm 0:9b334a45a8ff 295 #define MXC_F_ADC_CTRL0_ADC_DV_REG ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_DV_REG_POS))
bogdanm 0:9b334a45a8ff 296 #define MXC_F_ADC_CTRL0_ADC_DV_POS 9
bogdanm 0:9b334a45a8ff 297 #define MXC_F_ADC_CTRL0_ADC_DV ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_DV_POS))
bogdanm 0:9b334a45a8ff 298 #define MXC_F_ADC_CTRL0_ADC_LMT_DMODE_POS 10
bogdanm 0:9b334a45a8ff 299 #define MXC_F_ADC_CTRL0_ADC_LMT_DMODE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_LMT_DMODE_POS))
bogdanm 0:9b334a45a8ff 300 #define MXC_F_ADC_CTRL0_ADC_SMP_EXT_POS 11
bogdanm 0:9b334a45a8ff 301 #define MXC_F_ADC_CTRL0_ADC_SMP_EXT ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_SMP_EXT_POS))
bogdanm 0:9b334a45a8ff 302 #define MXC_F_ADC_CTRL0_ADC_CLK_EN_POS 12
bogdanm 0:9b334a45a8ff 303 #define MXC_F_ADC_CTRL0_ADC_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_CLK_EN_POS))
bogdanm 0:9b334a45a8ff 304 #define MXC_F_ADC_CTRL0_CPU_ADC_RST_POS 13
bogdanm 0:9b334a45a8ff 305 #define MXC_F_ADC_CTRL0_CPU_ADC_RST ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_RST_POS))
bogdanm 0:9b334a45a8ff 306 #define MXC_F_ADC_CTRL0_CPU_ADC_START_POS 14
bogdanm 0:9b334a45a8ff 307 #define MXC_F_ADC_CTRL0_CPU_ADC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_START_POS))
bogdanm 0:9b334a45a8ff 308 #define MXC_F_ADC_CTRL0_CPU_ADC_EN_POS 15
bogdanm 0:9b334a45a8ff 309 #define MXC_F_ADC_CTRL0_CPU_ADC_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_EN_POS))
bogdanm 0:9b334a45a8ff 310 #define MXC_F_ADC_CTRL0_ADC_FIFO_FULL_POS 18
bogdanm 0:9b334a45a8ff 311 #define MXC_F_ADC_CTRL0_ADC_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_FIFO_FULL_POS))
bogdanm 0:9b334a45a8ff 312 #define MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY_POS 19
bogdanm 0:9b334a45a8ff 313 #define MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY_POS))
bogdanm 0:9b334a45a8ff 314 #define MXC_F_ADC_CTRL0_AVG_MODE_POS 20
bogdanm 0:9b334a45a8ff 315 #define MXC_F_ADC_CTRL0_AVG_MODE ((uint32_t)(0x00000003UL << MXC_F_ADC_CTRL0_AVG_MODE_POS))
bogdanm 0:9b334a45a8ff 316 #define MXC_F_ADC_CTRL0_CPU_DAC_START_POS 22
bogdanm 0:9b334a45a8ff 317 #define MXC_F_ADC_CTRL0_CPU_DAC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_DAC_START_POS))
bogdanm 0:9b334a45a8ff 318 #define MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS 24
bogdanm 0:9b334a45a8ff 319 #define MXC_F_ADC_CTRL0_ADC_CLK_MODE ((uint32_t)(0x00000007UL << MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS))
bogdanm 0:9b334a45a8ff 320 #define MXC_F_ADC_CTRL0_ADC_MODE_POS 28
bogdanm 0:9b334a45a8ff 321 #define MXC_F_ADC_CTRL0_ADC_MODE ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL0_ADC_MODE_POS))
bogdanm 0:9b334a45a8ff 322
bogdanm 0:9b334a45a8ff 323 #define MXC_F_ADC_PGA_CTRL_PGA_GAIN_POS 0
bogdanm 0:9b334a45a8ff 324 #define MXC_F_ADC_PGA_CTRL_PGA_GAIN ((uint32_t)(0x00000003UL << MXC_F_ADC_PGA_CTRL_PGA_GAIN_POS))
bogdanm 0:9b334a45a8ff 325 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN_POS 2
bogdanm 0:9b334a45a8ff 326 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN_POS))
bogdanm 0:9b334a45a8ff 327 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_POS 3
bogdanm 0:9b334a45a8ff 328 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_POS))
bogdanm 0:9b334a45a8ff 329 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY_POS 4
bogdanm 0:9b334a45a8ff 330 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY_POS))
bogdanm 0:9b334a45a8ff 331 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_POS 5
bogdanm 0:9b334a45a8ff 332 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_POS))
bogdanm 0:9b334a45a8ff 333 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS_POS 6
bogdanm 0:9b334a45a8ff 334 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS_POS))
bogdanm 0:9b334a45a8ff 335 #define MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT_POS 8
bogdanm 0:9b334a45a8ff 336 #define MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT ((uint32_t)(0x0000001FUL << MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT_POS))
bogdanm 0:9b334a45a8ff 337 #define MXC_F_ADC_PGA_CTRL_MUX_SW_AIN_POS 13
bogdanm 0:9b334a45a8ff 338 #define MXC_F_ADC_PGA_CTRL_MUX_SW_AIN ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_SW_AIN_POS))
bogdanm 0:9b334a45a8ff 339 #define MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS 14
bogdanm 0:9b334a45a8ff 340 #define MXC_F_ADC_PGA_CTRL_MUX_DIFF ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS))
bogdanm 0:9b334a45a8ff 341 #define MXC_F_ADC_PGA_CTRL_MUX_MODE_POS 15
bogdanm 0:9b334a45a8ff 342 #define MXC_F_ADC_PGA_CTRL_MUX_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_MODE_POS))
bogdanm 0:9b334a45a8ff 343 #define MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT_POS 20
bogdanm 0:9b334a45a8ff 344 #define MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT_POS))
bogdanm 0:9b334a45a8ff 345 #define MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS 24
bogdanm 0:9b334a45a8ff 346 #define MXC_F_ADC_PGA_CTRL_MUX_CH_SEL ((uint32_t)(0x0000003FUL << MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS))
bogdanm 0:9b334a45a8ff 347
bogdanm 0:9b334a45a8ff 348 #define MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT_POS 0
bogdanm 0:9b334a45a8ff 349 #define MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT_POS))
bogdanm 0:9b334a45a8ff 350 #define MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS 16
bogdanm 0:9b334a45a8ff 351 #define MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS))
bogdanm 0:9b334a45a8ff 352
bogdanm 0:9b334a45a8ff 353 #define MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS 0
bogdanm 0:9b334a45a8ff 354 #define MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS))
bogdanm 0:9b334a45a8ff 355 #define MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT_POS 4
bogdanm 0:9b334a45a8ff 356 #define MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT_POS))
bogdanm 0:9b334a45a8ff 357 #define MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT_POS 8
bogdanm 0:9b334a45a8ff 358 #define MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT ((uint32_t)(0x00000007UL << MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT_POS))
bogdanm 0:9b334a45a8ff 359 #define MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS 12
bogdanm 0:9b334a45a8ff 360 #define MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS))
bogdanm 0:9b334a45a8ff 361 #define MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS 16
bogdanm 0:9b334a45a8ff 362 #define MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS))
bogdanm 0:9b334a45a8ff 363
bogdanm 0:9b334a45a8ff 364 #define MXC_F_ADC_LIMIT_LO_LIMIT_POS 0
bogdanm 0:9b334a45a8ff 365 #define MXC_F_ADC_LIMIT_LO_LIMIT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_LIMIT_LO_LIMIT_POS))
bogdanm 0:9b334a45a8ff 366 #define MXC_F_ADC_LIMIT_HI_LIMIT_POS 16
bogdanm 0:9b334a45a8ff 367 #define MXC_F_ADC_LIMIT_HI_LIMIT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_LIMIT_HI_LIMIT_POS))
bogdanm 0:9b334a45a8ff 368
bogdanm 0:9b334a45a8ff 369 #define MXC_F_ADC_INTR_FIFO_AF_POS 6
bogdanm 0:9b334a45a8ff 370 #define MXC_F_ADC_INTR_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_AF_POS))
bogdanm 0:9b334a45a8ff 371 #define MXC_F_ADC_INTR_OUT_RNG_IF_POS 7
bogdanm 0:9b334a45a8ff 372 #define MXC_F_ADC_INTR_OUT_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_OUT_RNG_IF_POS))
bogdanm 0:9b334a45a8ff 373 #define MXC_F_ADC_INTR_HI_RNG_IF_POS 8
bogdanm 0:9b334a45a8ff 374 #define MXC_F_ADC_INTR_HI_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_HI_RNG_IF_POS))
bogdanm 0:9b334a45a8ff 375 #define MXC_F_ADC_INTR_LO_RNG_IF_POS 9
bogdanm 0:9b334a45a8ff 376 #define MXC_F_ADC_INTR_LO_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_LO_RNG_IF_POS))
bogdanm 0:9b334a45a8ff 377 #define MXC_F_ADC_INTR_DONE_IF_POS 10
bogdanm 0:9b334a45a8ff 378 #define MXC_F_ADC_INTR_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_DONE_IF_POS))
bogdanm 0:9b334a45a8ff 379 #define MXC_F_ADC_INTR_FIFO_UF_IF_POS 11
bogdanm 0:9b334a45a8ff 380 #define MXC_F_ADC_INTR_FIFO_UF_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_UF_IF_POS))
bogdanm 0:9b334a45a8ff 381 #define MXC_F_ADC_INTR_FIFO_OF_IF_POS 12
bogdanm 0:9b334a45a8ff 382 #define MXC_F_ADC_INTR_FIFO_OF_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_OF_IF_POS))
bogdanm 0:9b334a45a8ff 383 #define MXC_F_ADC_INTR_FIFO_3Q_IF_POS 13
bogdanm 0:9b334a45a8ff 384 #define MXC_F_ADC_INTR_FIFO_3Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_3Q_IF_POS))
bogdanm 0:9b334a45a8ff 385 #define MXC_F_ADC_INTR_FIFO_2Q_IF_POS 14
bogdanm 0:9b334a45a8ff 386 #define MXC_F_ADC_INTR_FIFO_2Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_2Q_IF_POS))
bogdanm 0:9b334a45a8ff 387 #define MXC_F_ADC_INTR_FIFO_1Q_IF_POS 15
bogdanm 0:9b334a45a8ff 388 #define MXC_F_ADC_INTR_FIFO_1Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_1Q_IF_POS))
bogdanm 0:9b334a45a8ff 389 #define MXC_F_ADC_INTR_SPST0_CTRL_MODE_POS 16
bogdanm 0:9b334a45a8ff 390 #define MXC_F_ADC_INTR_SPST0_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST0_CTRL_MODE_POS))
bogdanm 0:9b334a45a8ff 391 #define MXC_F_ADC_INTR_SPST1_CTRL_MODE_POS 17
bogdanm 0:9b334a45a8ff 392 #define MXC_F_ADC_INTR_SPST1_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST1_CTRL_MODE_POS))
bogdanm 0:9b334a45a8ff 393 #define MXC_F_ADC_INTR_SPST2_CTRL_MODE_POS 18
bogdanm 0:9b334a45a8ff 394 #define MXC_F_ADC_INTR_SPST2_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST2_CTRL_MODE_POS))
bogdanm 0:9b334a45a8ff 395 #define MXC_F_ADC_INTR_SPST3_CTRL_MODE_POS 19
bogdanm 0:9b334a45a8ff 396 #define MXC_F_ADC_INTR_SPST3_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST3_CTRL_MODE_POS))
bogdanm 0:9b334a45a8ff 397 #define MXC_F_ADC_INTR_OUT_RNG_IE_POS 23
bogdanm 0:9b334a45a8ff 398 #define MXC_F_ADC_INTR_OUT_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_OUT_RNG_IE_POS))
bogdanm 0:9b334a45a8ff 399 #define MXC_F_ADC_INTR_HI_RNG_IE_POS 24
bogdanm 0:9b334a45a8ff 400 #define MXC_F_ADC_INTR_HI_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_HI_RNG_IE_POS))
bogdanm 0:9b334a45a8ff 401 #define MXC_F_ADC_INTR_LO_RNG_IE_POS 25
bogdanm 0:9b334a45a8ff 402 #define MXC_F_ADC_INTR_LO_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_LO_RNG_IE_POS))
bogdanm 0:9b334a45a8ff 403 #define MXC_F_ADC_INTR_DONE_IE_POS 26
bogdanm 0:9b334a45a8ff 404 #define MXC_F_ADC_INTR_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_DONE_IE_POS))
bogdanm 0:9b334a45a8ff 405 #define MXC_F_ADC_INTR_FIFO_UF_IE_POS 27
bogdanm 0:9b334a45a8ff 406 #define MXC_F_ADC_INTR_FIFO_UF_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_UF_IE_POS))
bogdanm 0:9b334a45a8ff 407 #define MXC_F_ADC_INTR_FIFO_OF_IE_POS 28
bogdanm 0:9b334a45a8ff 408 #define MXC_F_ADC_INTR_FIFO_OF_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_OF_IE_POS))
bogdanm 0:9b334a45a8ff 409 #define MXC_F_ADC_INTR_FIFO_3Q_IE_POS 29
bogdanm 0:9b334a45a8ff 410 #define MXC_F_ADC_INTR_FIFO_3Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_3Q_IE_POS))
bogdanm 0:9b334a45a8ff 411 #define MXC_F_ADC_INTR_FIFO_2Q_IE_POS 30
bogdanm 0:9b334a45a8ff 412 #define MXC_F_ADC_INTR_FIFO_2Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_2Q_IE_POS))
bogdanm 0:9b334a45a8ff 413 #define MXC_F_ADC_INTR_FIFO_1Q_IE_POS 31
bogdanm 0:9b334a45a8ff 414 #define MXC_F_ADC_INTR_FIFO_1Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_1Q_IE_POS))
bogdanm 0:9b334a45a8ff 415
bogdanm 0:9b334a45a8ff 416 #define MXC_F_ADC_OUT_DATA_REG_POS 0
bogdanm 0:9b334a45a8ff 417 #define MXC_F_ADC_OUT_DATA_REG ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_OUT_DATA_REG_POS))
bogdanm 0:9b334a45a8ff 418
bogdanm 0:9b334a45a8ff 419 #define MXC_F_ADC_CTRL1_ADC_SCAN_CNT_POS 16
bogdanm 0:9b334a45a8ff 420 #define MXC_F_ADC_CTRL1_ADC_SCAN_CNT ((uint32_t)(0x00000007UL << MXC_F_ADC_CTRL1_ADC_SCAN_CNT_POS))
bogdanm 0:9b334a45a8ff 421
bogdanm 0:9b334a45a8ff 422 #define MXC_F_ADC_SCAN1_ADC_SCAN0_POS 0
bogdanm 0:9b334a45a8ff 423 #define MXC_F_ADC_SCAN1_ADC_SCAN0 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN0_POS))
bogdanm 0:9b334a45a8ff 424 #define MXC_F_ADC_SCAN1_ADC_SCAN1_POS 8
bogdanm 0:9b334a45a8ff 425 #define MXC_F_ADC_SCAN1_ADC_SCAN1 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN1_POS))
bogdanm 0:9b334a45a8ff 426 #define MXC_F_ADC_SCAN1_ADC_SCAN2_POS 16
bogdanm 0:9b334a45a8ff 427 #define MXC_F_ADC_SCAN1_ADC_SCAN2 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN2_POS))
bogdanm 0:9b334a45a8ff 428 #define MXC_F_ADC_SCAN1_ADC_SCAN3_POS 24
bogdanm 0:9b334a45a8ff 429 #define MXC_F_ADC_SCAN1_ADC_SCAN3 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN3_POS))
bogdanm 0:9b334a45a8ff 430
bogdanm 0:9b334a45a8ff 431 #define MXC_F_ADC_SCAN2_ADC_SCAN4_POS 0
bogdanm 0:9b334a45a8ff 432 #define MXC_F_ADC_SCAN2_ADC_SCAN4 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN4_POS))
bogdanm 0:9b334a45a8ff 433 #define MXC_F_ADC_SCAN2_ADC_SCAN5_POS 8
bogdanm 0:9b334a45a8ff 434 #define MXC_F_ADC_SCAN2_ADC_SCAN5 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN5_POS))
bogdanm 0:9b334a45a8ff 435 #define MXC_F_ADC_SCAN2_ADC_SCAN6_POS 16
bogdanm 0:9b334a45a8ff 436 #define MXC_F_ADC_SCAN2_ADC_SCAN6 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN6_POS))
bogdanm 0:9b334a45a8ff 437 #define MXC_F_ADC_SCAN2_ADC_SCAN7_POS 24
bogdanm 0:9b334a45a8ff 438 #define MXC_F_ADC_SCAN2_ADC_SCAN7 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN7_POS))
bogdanm 0:9b334a45a8ff 439
bogdanm 0:9b334a45a8ff 440 #define MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS 0
bogdanm 0:9b334a45a8ff 441 #define MXC_F_ADC_RO_CAL0_RO_CAL_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS))
bogdanm 0:9b334a45a8ff 442 #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS 1
bogdanm 0:9b334a45a8ff 443 #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS))
bogdanm 0:9b334a45a8ff 444 #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS 2
bogdanm 0:9b334a45a8ff 445 #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS))
bogdanm 0:9b334a45a8ff 446 #define MXC_F_ADC_RO_CAL0_TRM_MU_POS 8
bogdanm 0:9b334a45a8ff 447 #define MXC_F_ADC_RO_CAL0_TRM_MU ((uint32_t)(0x00000FFFUL << MXC_F_ADC_RO_CAL0_TRM_MU_POS))
bogdanm 0:9b334a45a8ff 448 #define MXC_F_ADC_RO_CAL0_RO_TRM_POS 23
bogdanm 0:9b334a45a8ff 449 #define MXC_F_ADC_RO_CAL0_RO_TRM ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL0_RO_TRM_POS))
bogdanm 0:9b334a45a8ff 450
bogdanm 0:9b334a45a8ff 451 #define MXC_F_ADC_RO_CAL1_TRM_INIT_POS 0
bogdanm 0:9b334a45a8ff 452 #define MXC_F_ADC_RO_CAL1_TRM_INIT ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_INIT_POS))
bogdanm 0:9b334a45a8ff 453 #define MXC_F_ADC_RO_CAL1_TRM_MIN_POS 10
bogdanm 0:9b334a45a8ff 454 #define MXC_F_ADC_RO_CAL1_TRM_MIN ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MIN_POS))
bogdanm 0:9b334a45a8ff 455 #define MXC_F_ADC_RO_CAL1_TRM_MAX_POS 20
bogdanm 0:9b334a45a8ff 456 #define MXC_F_ADC_RO_CAL1_TRM_MAX ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MAX_POS))
bogdanm 0:9b334a45a8ff 457
bogdanm 0:9b334a45a8ff 458 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 459 }
bogdanm 0:9b334a45a8ff 460 #endif
bogdanm 0:9b334a45a8ff 461
bogdanm 0:9b334a45a8ff 462 /**
bogdanm 0:9b334a45a8ff 463 * @}
bogdanm 0:9b334a45a8ff 464 */
bogdanm 0:9b334a45a8ff 465
bogdanm 0:9b334a45a8ff 466 #endif /* _MXC_ADC_REGS_H */