Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Maxim/TARGET_MAX32610/spi_regs.h@33:7b49ef75af0b, 2015-12-03 (annotated)

Committer:
mbed_official
Date:
Thu Dec 03 15:15:11 2015 +0000
Revision:
33:7b49ef75af0b
Parent:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Synchronized with git revision 88bbe088da5793b45ba5ebc63521c93611ad2dd7



Full URL: https://github.com/mbedmicro/mbed/commit/88bbe088da5793b45ba5ebc63521c93611ad2dd7/



Adding BLE library

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /*******************************************************************************
bogdanm 0:9b334a45a8ff 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Permission is hereby granted, free of charge, to any person obtaining a
bogdanm 0:9b334a45a8ff 5 * copy of this software and associated documentation files (the "Software"),
bogdanm 0:9b334a45a8ff 6 * to deal in the Software without restriction, including without limitation
bogdanm 0:9b334a45a8ff 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
bogdanm 0:9b334a45a8ff 8 * and/or sell copies of the Software, and to permit persons to whom the
bogdanm 0:9b334a45a8ff 9 * Software is furnished to do so, subject to the following conditions:
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * The above copyright notice and this permission notice shall be included
bogdanm 0:9b334a45a8ff 12 * in all copies or substantial portions of the Software.
bogdanm 0:9b334a45a8ff 13 *
bogdanm 0:9b334a45a8ff 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
bogdanm 0:9b334a45a8ff 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
bogdanm 0:9b334a45a8ff 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
bogdanm 0:9b334a45a8ff 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
bogdanm 0:9b334a45a8ff 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
bogdanm 0:9b334a45a8ff 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
bogdanm 0:9b334a45a8ff 20 * OTHER DEALINGS IN THE SOFTWARE.
bogdanm 0:9b334a45a8ff 21 *
bogdanm 0:9b334a45a8ff 22 * Except as contained in this notice, the name of Maxim Integrated
bogdanm 0:9b334a45a8ff 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
bogdanm 0:9b334a45a8ff 24 * Products, Inc. Branding Policy.
bogdanm 0:9b334a45a8ff 25 *
bogdanm 0:9b334a45a8ff 26 * The mere transfer of this software does not imply any licenses
bogdanm 0:9b334a45a8ff 27 * of trade secrets, proprietary technology, copyrights, patents,
bogdanm 0:9b334a45a8ff 28 * trademarks, maskwork rights, or any other form of intellectual
bogdanm 0:9b334a45a8ff 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
bogdanm 0:9b334a45a8ff 30 * ownership rights.
bogdanm 0:9b334a45a8ff 31 *******************************************************************************
bogdanm 0:9b334a45a8ff 32 */
bogdanm 0:9b334a45a8ff 33
bogdanm 0:9b334a45a8ff 34 #ifndef _MXC_SPI_REGS_H
bogdanm 0:9b334a45a8ff 35 #define _MXC_SPI_REGS_H
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 38 extern "C" {
bogdanm 0:9b334a45a8ff 39 #endif
bogdanm 0:9b334a45a8ff 40
bogdanm 0:9b334a45a8ff 41 #include <stdint.h>
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 /**
bogdanm 0:9b334a45a8ff 44 * @file spi_regs.h
bogdanm 0:9b334a45a8ff 45 * @addtogroup spi SPI
bogdanm 0:9b334a45a8ff 46 * @{
bogdanm 0:9b334a45a8ff 47 */
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 /* Offset Register Description
bogdanm 0:9b334a45a8ff 50 ====== ============================================ */
bogdanm 0:9b334a45a8ff 51 typedef struct {
bogdanm 0:9b334a45a8ff 52 __IO uint32_t mstr_cfg; /* 0x0000 SPI Master Configuration Register */
bogdanm 0:9b334a45a8ff 53 __IO uint32_t ss_sr_polarity; /* 0x0004 Polarity Control for SS and SR Signals */
bogdanm 0:9b334a45a8ff 54 __IO uint32_t gen_ctrl; /* 0x0008 SPI Master General Control Register */
bogdanm 0:9b334a45a8ff 55 __IO uint32_t fifo_ctrl; /* 0x000C SPI Master FIFO Control Register */
bogdanm 0:9b334a45a8ff 56 __IO uint32_t spcl_ctrl; /* 0x0010 SPI Master Special Mode Controls */
bogdanm 0:9b334a45a8ff 57 __IO uint32_t intfl; /* 0x0014 SPI Master Interrupt Flags */
bogdanm 0:9b334a45a8ff 58 __IO uint32_t inten; /* 0x0018 SPI Master Interrupt Enable/Disable Settings */
bogdanm 0:9b334a45a8ff 59 __I uint32_t rsv001C; /* 0x001C Deprecated - was SPI_AHB_RETRY */
bogdanm 0:9b334a45a8ff 60 } mxc_spi_regs_t;
bogdanm 0:9b334a45a8ff 61
bogdanm 0:9b334a45a8ff 62 /**
bogdanm 0:9b334a45a8ff 63 * @brief TX FIFO register. Can do 8, 16, or 32 bit access.
bogdanm 0:9b334a45a8ff 64 */
bogdanm 0:9b334a45a8ff 65 typedef struct {
bogdanm 0:9b334a45a8ff 66 union {
bogdanm 0:9b334a45a8ff 67 __O uint8_t txfifo_8;
bogdanm 0:9b334a45a8ff 68 __O uint16_t txfifo_16;
bogdanm 0:9b334a45a8ff 69 __O uint32_t txfifo_32;
bogdanm 0:9b334a45a8ff 70 };
bogdanm 0:9b334a45a8ff 71 } mxc_spi_txfifo_regs_t;
bogdanm 0:9b334a45a8ff 72
bogdanm 0:9b334a45a8ff 73 /**
bogdanm 0:9b334a45a8ff 74 * @brief RX FIFO register. Can do 8, 16, or 32 bit access.
bogdanm 0:9b334a45a8ff 75 */
bogdanm 0:9b334a45a8ff 76 typedef struct {
bogdanm 0:9b334a45a8ff 77 union {
bogdanm 0:9b334a45a8ff 78 __I uint8_t rxfifo_8;
bogdanm 0:9b334a45a8ff 79 __I uint16_t rxfifo_16;
bogdanm 0:9b334a45a8ff 80 __I uint32_t rxfifo_32;
bogdanm 0:9b334a45a8ff 81 };
bogdanm 0:9b334a45a8ff 82 } mxc_spi_rxfifo_regs_t;
bogdanm 0:9b334a45a8ff 83
bogdanm 0:9b334a45a8ff 84 /*
bogdanm 0:9b334a45a8ff 85 Register offsets for module SPI.
bogdanm 0:9b334a45a8ff 86 */
bogdanm 0:9b334a45a8ff 87 #define MXC_R_SPI_OFFS_MSTR_CFG ((uint32_t)0x00000000UL)
bogdanm 0:9b334a45a8ff 88 #define MXC_R_SPI_OFFS_SS_SR_POLARITY ((uint32_t)0x00000004UL)
bogdanm 0:9b334a45a8ff 89 #define MXC_R_SPI_OFFS_GEN_CTRL ((uint32_t)0x00000008UL)
bogdanm 0:9b334a45a8ff 90 #define MXC_R_SPI_OFFS_FIFO_CTRL ((uint32_t)0x0000000CUL)
bogdanm 0:9b334a45a8ff 91 #define MXC_R_SPI_OFFS_SPCL_CTRL ((uint32_t)0x00000010UL)
bogdanm 0:9b334a45a8ff 92 #define MXC_R_SPI_OFFS_INTFL ((uint32_t)0x00000014UL)
bogdanm 0:9b334a45a8ff 93 #define MXC_R_SPI_OFFS_INTEN ((uint32_t)0x00000018UL)
bogdanm 0:9b334a45a8ff 94
bogdanm 0:9b334a45a8ff 95 #define MXC_R_SPI_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL)
bogdanm 0:9b334a45a8ff 96 #define MXC_R_SPI_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL)
bogdanm 0:9b334a45a8ff 97
bogdanm 0:9b334a45a8ff 98 /*
bogdanm 0:9b334a45a8ff 99 Field positions and masks for module SPI.
bogdanm 0:9b334a45a8ff 100 */
bogdanm 0:9b334a45a8ff 101 #define MXC_F_SPI_MSTR_CFG_SLAVE_SEL_POS 0
bogdanm 0:9b334a45a8ff 102 #define MXC_F_SPI_MSTR_CFG_SLAVE_SEL ((uint32_t)(0x00000007UL << MXC_F_SPI_MSTR_CFG_SLAVE_SEL_POS))
bogdanm 0:9b334a45a8ff 103 #define MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE_POS 3
bogdanm 0:9b334a45a8ff 104 #define MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE_POS))
bogdanm 0:9b334a45a8ff 105 #define MXC_F_SPI_MSTR_CFG_SPI_MODE_POS 4
bogdanm 0:9b334a45a8ff 106 #define MXC_F_SPI_MSTR_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_SPI_MODE_POS))
bogdanm 0:9b334a45a8ff 107 #define MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS 6
bogdanm 0:9b334a45a8ff 108 #define MXC_F_SPI_MSTR_CFG_PAGE_SIZE ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS))
bogdanm 0:9b334a45a8ff 109 #define MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS 8
bogdanm 0:9b334a45a8ff 110 #define MXC_F_SPI_MSTR_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS))
bogdanm 0:9b334a45a8ff 111 #define MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS 12
bogdanm 0:9b334a45a8ff 112 #define MXC_F_SPI_MSTR_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS))
bogdanm 0:9b334a45a8ff 113 #define MXC_F_SPI_MSTR_CFG_ACT_DELAY_POS 16
bogdanm 0:9b334a45a8ff 114 #define MXC_F_SPI_MSTR_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_ACT_DELAY_POS))
bogdanm 0:9b334a45a8ff 115 #define MXC_F_SPI_MSTR_CFG_INACT_DELAY_POS 18
bogdanm 0:9b334a45a8ff 116 #define MXC_F_SPI_MSTR_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_INACT_DELAY_POS))
bogdanm 0:9b334a45a8ff 117 #define MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK_POS 20
bogdanm 0:9b334a45a8ff 118 #define MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK_POS))
bogdanm 0:9b334a45a8ff 119 #define MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK_POS 24
bogdanm 0:9b334a45a8ff 120 #define MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK_POS))
bogdanm 0:9b334a45a8ff 121
mbed_official 33:7b49ef75af0b 122 #define MXC_V_SPI_MSTR_CFG_PAGE_SIZE_4B ((uint32_t)0x00000000UL)
mbed_official 33:7b49ef75af0b 123 #define MXC_V_SPI_MSTR_CFG_PAGE_SIZE_8B ((uint32_t)0x00000001UL)
mbed_official 33:7b49ef75af0b 124 #define MXC_V_SPI_MSTR_CFG_PAGE_SIZE_16B ((uint32_t)0x00000002UL)
mbed_official 33:7b49ef75af0b 125 #define MXC_V_SPI_MSTR_CFG_PAGE_SIZE_32B ((uint32_t)0x00000003UL)
mbed_official 33:7b49ef75af0b 126
mbed_official 33:7b49ef75af0b 127 #define MXC_S_SPI_MSTR_CFG_PAGE_4B (MXC_V_SPI_MSTR_CFG_PAGE_SIZE_4B << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS)
mbed_official 33:7b49ef75af0b 128 #define MXC_S_SPI_MSTR_CFG_PAGE_8B (MXC_V_SPI_MSTR_CFG_PAGE_SIZE_8B << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS)
mbed_official 33:7b49ef75af0b 129 #define MXC_S_SPI_MSTR_CFG_PAGE_16B (MXC_V_SPI_MSTR_CFG_PAGE_SIZE_16B << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS)
mbed_official 33:7b49ef75af0b 130 #define MXC_S_SPI_MSTR_CFG_PAGE_32B (MXC_V_SPI_MSTR_CFG_PAGE_SIZE_32B << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS)
mbed_official 33:7b49ef75af0b 131
bogdanm 0:9b334a45a8ff 132 #define MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY_POS 0
bogdanm 0:9b334a45a8ff 133 #define MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY_POS))
bogdanm 0:9b334a45a8ff 134 #define MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY_POS 8
bogdanm 0:9b334a45a8ff 135 #define MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY_POS))
bogdanm 0:9b334a45a8ff 136
bogdanm 0:9b334a45a8ff 137 #define MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN_POS 0
bogdanm 0:9b334a45a8ff 138 #define MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN_POS))
bogdanm 0:9b334a45a8ff 139 #define MXC_F_SPI_GEN_CTRL_TX_FIFO_EN_POS 1
bogdanm 0:9b334a45a8ff 140 #define MXC_F_SPI_GEN_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_TX_FIFO_EN_POS))
bogdanm 0:9b334a45a8ff 141 #define MXC_F_SPI_GEN_CTRL_RX_FIFO_EN_POS 2
bogdanm 0:9b334a45a8ff 142 #define MXC_F_SPI_GEN_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_RX_FIFO_EN_POS))
bogdanm 0:9b334a45a8ff 143 #define MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE_POS 3
bogdanm 0:9b334a45a8ff 144 #define MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE_POS))
bogdanm 0:9b334a45a8ff 145 #define MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT_POS 4
bogdanm 0:9b334a45a8ff 146 #define MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT_POS))
bogdanm 0:9b334a45a8ff 147 #define MXC_F_SPI_GEN_CTRL_BB_SR_IN_POS 5
bogdanm 0:9b334a45a8ff 148 #define MXC_F_SPI_GEN_CTRL_BB_SR_IN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SR_IN_POS))
bogdanm 0:9b334a45a8ff 149 #define MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT_POS 6
bogdanm 0:9b334a45a8ff 150 #define MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT_POS))
bogdanm 0:9b334a45a8ff 151 #define MXC_F_SPI_GEN_CTRL_BB_SDIO_IN_POS 8
bogdanm 0:9b334a45a8ff 152 #define MXC_F_SPI_GEN_CTRL_BB_SDIO_IN ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_IN_POS))
bogdanm 0:9b334a45a8ff 153 #define MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT_POS 12
bogdanm 0:9b334a45a8ff 154 #define MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT_POS))
bogdanm 0:9b334a45a8ff 155 #define MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN_POS 16
bogdanm 0:9b334a45a8ff 156 #define MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN_POS))
bogdanm 0:9b334a45a8ff 157
bogdanm 0:9b334a45a8ff 158 #define MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS 0
bogdanm 0:9b334a45a8ff 159 #define MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL ((uint32_t)(0x0000000FUL << MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS))
bogdanm 0:9b334a45a8ff 160 #define MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS 8
bogdanm 0:9b334a45a8ff 161 #define MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED ((uint32_t)(0x0000001FUL << MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS))
bogdanm 0:9b334a45a8ff 162 #define MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS 16
bogdanm 0:9b334a45a8ff 163 #define MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS))
bogdanm 0:9b334a45a8ff 164 #define MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS 24
bogdanm 0:9b334a45a8ff 165 #define MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS))
bogdanm 0:9b334a45a8ff 166
bogdanm 0:9b334a45a8ff 167 #define MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE_POS 0
bogdanm 0:9b334a45a8ff 168 #define MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE_POS))
bogdanm 0:9b334a45a8ff 169 #define MXC_F_SPI_SPCL_CTRL_MISO_FC_EN_POS 1
bogdanm 0:9b334a45a8ff 170 #define MXC_F_SPI_SPCL_CTRL_MISO_FC_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_SPCL_CTRL_MISO_FC_EN_POS))
bogdanm 0:9b334a45a8ff 171 #define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT_POS 4
bogdanm 0:9b334a45a8ff 172 #define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT_POS))
bogdanm 0:9b334a45a8ff 173 #define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS 8
bogdanm 0:9b334a45a8ff 174 #define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS))
bogdanm 0:9b334a45a8ff 175
bogdanm 0:9b334a45a8ff 176 #define MXC_F_SPI_INTFL_TX_STALLED_POS 0
bogdanm 0:9b334a45a8ff 177 #define MXC_F_SPI_INTFL_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_STALLED_POS))
bogdanm 0:9b334a45a8ff 178 #define MXC_F_SPI_INTFL_RX_STALLED_POS 1
bogdanm 0:9b334a45a8ff 179 #define MXC_F_SPI_INTFL_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_STALLED_POS))
bogdanm 0:9b334a45a8ff 180 #define MXC_F_SPI_INTFL_TX_READY_POS 2
bogdanm 0:9b334a45a8ff 181 #define MXC_F_SPI_INTFL_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_READY_POS))
bogdanm 0:9b334a45a8ff 182 #define MXC_F_SPI_INTFL_RX_DONE_POS 3
bogdanm 0:9b334a45a8ff 183 #define MXC_F_SPI_INTFL_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_DONE_POS))
bogdanm 0:9b334a45a8ff 184 #define MXC_F_SPI_INTFL_TX_FIFO_AE_POS 4
bogdanm 0:9b334a45a8ff 185 #define MXC_F_SPI_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_FIFO_AE_POS))
bogdanm 0:9b334a45a8ff 186 #define MXC_F_SPI_INTFL_RX_FIFO_AF_POS 5
bogdanm 0:9b334a45a8ff 187 #define MXC_F_SPI_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_FIFO_AF_POS))
bogdanm 0:9b334a45a8ff 188
bogdanm 0:9b334a45a8ff 189 #define MXC_F_SPI_INTEN_TX_STALLED_POS 0
bogdanm 0:9b334a45a8ff 190 #define MXC_F_SPI_INTEN_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_STALLED_POS))
bogdanm 0:9b334a45a8ff 191 #define MXC_F_SPI_INTEN_RX_STALLED_POS 1
bogdanm 0:9b334a45a8ff 192 #define MXC_F_SPI_INTEN_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_STALLED_POS))
bogdanm 0:9b334a45a8ff 193 #define MXC_F_SPI_INTEN_TX_READY_POS 2
bogdanm 0:9b334a45a8ff 194 #define MXC_F_SPI_INTEN_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_READY_POS))
bogdanm 0:9b334a45a8ff 195 #define MXC_F_SPI_INTEN_RX_DONE_POS 3
bogdanm 0:9b334a45a8ff 196 #define MXC_F_SPI_INTEN_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_DONE_POS))
bogdanm 0:9b334a45a8ff 197 #define MXC_F_SPI_INTEN_TX_FIFO_AE_POS 4
bogdanm 0:9b334a45a8ff 198 #define MXC_F_SPI_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_FIFO_AE_POS))
bogdanm 0:9b334a45a8ff 199 #define MXC_F_SPI_INTEN_RX_FIFO_AF_POS 5
bogdanm 0:9b334a45a8ff 200 #define MXC_F_SPI_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_FIFO_AF_POS))
bogdanm 0:9b334a45a8ff 201
bogdanm 0:9b334a45a8ff 202 #define MXC_F_SPI_FIFO_DIR_POS 0
bogdanm 0:9b334a45a8ff 203 #define MXC_F_SPI_FIFO_DIR ((uint32_t)(0x00000003UL << MXC_F_SPI_FIFO_DIR_POS))
bogdanm 0:9b334a45a8ff 204 #define MXC_F_SPI_FIFO_UNIT_POS 2
bogdanm 0:9b334a45a8ff 205 #define MXC_F_SPI_FIFO_UNIT ((uint32_t)(0x00000003UL << MXC_F_SPI_FIFO_UNIT_POS))
bogdanm 0:9b334a45a8ff 206 #define MXC_F_SPI_FIFO_SIZE_POS 4
bogdanm 0:9b334a45a8ff 207 #define MXC_F_SPI_FIFO_SIZE ((uint32_t)(0x0000000FUL << MXC_F_SPI_FIFO_SIZE_POS))
bogdanm 0:9b334a45a8ff 208 #define MXC_F_SPI_FIFO_WIDTH_POS 9
bogdanm 0:9b334a45a8ff 209 #define MXC_F_SPI_FIFO_WIDTH ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_WIDTH_POS))
bogdanm 0:9b334a45a8ff 210 #define MXC_F_SPI_FIFO_ALT_POS 11
bogdanm 0:9b334a45a8ff 211 #define MXC_F_SPI_FIFO_ALT ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_ALT_POS))
bogdanm 0:9b334a45a8ff 212 #define MXC_F_SPI_FIFO_FLOW_POS 12
bogdanm 0:9b334a45a8ff 213 #define MXC_F_SPI_FIFO_FLOW ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_FLOW_POS))
bogdanm 0:9b334a45a8ff 214 #define MXC_F_SPI_FIFO_DASS_POS 13
bogdanm 0:9b334a45a8ff 215 #define MXC_F_SPI_FIFO_DASS ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_DASS_POS))
bogdanm 0:9b334a45a8ff 216
bogdanm 0:9b334a45a8ff 217 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 218 }
bogdanm 0:9b334a45a8ff 219 #endif
bogdanm 0:9b334a45a8ff 220
bogdanm 0:9b334a45a8ff 221 /**
bogdanm 0:9b334a45a8ff 222 * @}
bogdanm 0:9b334a45a8ff 223 */
bogdanm 0:9b334a45a8ff 224
bogdanm 0:9b334a45a8ff 225 #endif /* _MXC_SPI_REGS_H */