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EthernetInterface/lwip-eth/arch/lpc_phy_dp83848.c@0:0ed2a7c7190c, 2013-05-31 (annotated)

Committer:
GordonSin
Date:
Fri May 31 04:09:54 2013 +0000
Revision:
0:0ed2a7c7190c
31/5/2013;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GordonSin 0:0ed2a7c7190c 1 /**********************************************************************
GordonSin 0:0ed2a7c7190c 2 * $Id$ lpc_phy_dp83848.c 2011-11-20
GordonSin 0:0ed2a7c7190c 3 *//**
GordonSin 0:0ed2a7c7190c 4 * @file lpc_phy_dp83848.c
GordonSin 0:0ed2a7c7190c 5 * @brief DP83848C PHY status and control.
GordonSin 0:0ed2a7c7190c 6 * @version 1.0
GordonSin 0:0ed2a7c7190c 7 * @date 20 Nov. 2011
GordonSin 0:0ed2a7c7190c 8 * @author NXP MCU SW Application Team
GordonSin 0:0ed2a7c7190c 9 *
GordonSin 0:0ed2a7c7190c 10 * Copyright(C) 2011, NXP Semiconductor
GordonSin 0:0ed2a7c7190c 11 * All rights reserved.
GordonSin 0:0ed2a7c7190c 12 *
GordonSin 0:0ed2a7c7190c 13 ***********************************************************************
GordonSin 0:0ed2a7c7190c 14 * Software that is described herein is for illustrative purposes only
GordonSin 0:0ed2a7c7190c 15 * which provides customers with programming information regarding the
GordonSin 0:0ed2a7c7190c 16 * products. This software is supplied "AS IS" without any warranties.
GordonSin 0:0ed2a7c7190c 17 * NXP Semiconductors assumes no responsibility or liability for the
GordonSin 0:0ed2a7c7190c 18 * use of the software, conveys no license or title under any patent,
GordonSin 0:0ed2a7c7190c 19 * copyright, or mask work right to the product. NXP Semiconductors
GordonSin 0:0ed2a7c7190c 20 * reserves the right to make changes in the software without
GordonSin 0:0ed2a7c7190c 21 * notification. NXP Semiconductors also make no representation or
GordonSin 0:0ed2a7c7190c 22 * warranty that such application will be suitable for the specified
GordonSin 0:0ed2a7c7190c 23 * use without further testing or modification.
GordonSin 0:0ed2a7c7190c 24 **********************************************************************/
GordonSin 0:0ed2a7c7190c 25
GordonSin 0:0ed2a7c7190c 26 #include "lwip/opt.h"
GordonSin 0:0ed2a7c7190c 27 #include "lwip/err.h"
GordonSin 0:0ed2a7c7190c 28 #include "lwip/tcpip.h"
GordonSin 0:0ed2a7c7190c 29 #include "lwip/snmp.h"
GordonSin 0:0ed2a7c7190c 30 #include "lpc_emac_config.h"
GordonSin 0:0ed2a7c7190c 31 #include "lpc_phy.h"
GordonSin 0:0ed2a7c7190c 32
GordonSin 0:0ed2a7c7190c 33 /** @defgroup dp83848_phy PHY status and control for the DP83848.
GordonSin 0:0ed2a7c7190c 34 * @ingroup lwip_phy
GordonSin 0:0ed2a7c7190c 35 *
GordonSin 0:0ed2a7c7190c 36 * Various functions for controlling and monitoring the status of the
GordonSin 0:0ed2a7c7190c 37 * DP83848 PHY. In polled (standalone) systems, the PHY state must be
GordonSin 0:0ed2a7c7190c 38 * monitored as part of the application. In a threaded (RTOS) system,
GordonSin 0:0ed2a7c7190c 39 * the PHY state is monitored by the PHY handler thread. The MAC
GordonSin 0:0ed2a7c7190c 40 * driver will not transmit unless the PHY link is active.
GordonSin 0:0ed2a7c7190c 41 * @{
GordonSin 0:0ed2a7c7190c 42 */
GordonSin 0:0ed2a7c7190c 43
GordonSin 0:0ed2a7c7190c 44 /** \brief DP83848 PHY register offsets */
GordonSin 0:0ed2a7c7190c 45 #define DP8_BMCR_REG 0x0 /**< Basic Mode Control Register */
GordonSin 0:0ed2a7c7190c 46 #define DP8_BMSR_REG 0x1 /**< Basic Mode Status Reg */
GordonSin 0:0ed2a7c7190c 47 #define DP8_ANADV_REG 0x4 /**< Auto_Neg Advt Reg */
GordonSin 0:0ed2a7c7190c 48 #define DP8_ANLPA_REG 0x5 /**< Auto_neg Link Partner Ability Reg */
GordonSin 0:0ed2a7c7190c 49 #define DP8_ANEEXP_REG 0x6 /**< Auto-neg Expansion Reg */
GordonSin 0:0ed2a7c7190c 50 #define DP8_PHY_STAT_REG 0x10 /**< PHY Status Register */
GordonSin 0:0ed2a7c7190c 51 #define DP8_PHY_INT_CTL_REG 0x11 /**< PHY Interrupt Control Register */
GordonSin 0:0ed2a7c7190c 52 #define DP8_PHY_RBR_REG 0x17 /**< PHY RMII and Bypass Register */
GordonSin 0:0ed2a7c7190c 53 #define DP8_PHY_STS_REG 0x19 /**< PHY Status Register */
GordonSin 0:0ed2a7c7190c 54
GordonSin 0:0ed2a7c7190c 55 /** \brief DP83848 Control register definitions */
GordonSin 0:0ed2a7c7190c 56 #define DP8_RESET (1 << 15) /**< 1= S/W Reset */
GordonSin 0:0ed2a7c7190c 57 #define DP8_LOOPBACK (1 << 14) /**< 1=loopback Enabled */
GordonSin 0:0ed2a7c7190c 58 #define DP8_SPEED_SELECT (1 << 13) /**< 1=Select 100MBps */
GordonSin 0:0ed2a7c7190c 59 #define DP8_AUTONEG (1 << 12) /**< 1=Enable auto-negotiation */
GordonSin 0:0ed2a7c7190c 60 #define DP8_POWER_DOWN (1 << 11) /**< 1=Power down PHY */
GordonSin 0:0ed2a7c7190c 61 #define DP8_ISOLATE (1 << 10) /**< 1=Isolate PHY */
GordonSin 0:0ed2a7c7190c 62 #define DP8_RESTART_AUTONEG (1 << 9) /**< 1=Restart auto-negoatiation */
GordonSin 0:0ed2a7c7190c 63 #define DP8_DUPLEX_MODE (1 << 8) /**< 1=Full duplex mode */
GordonSin 0:0ed2a7c7190c 64 #define DP8_COLLISION_TEST (1 << 7) /**< 1=Perform collsion test */
GordonSin 0:0ed2a7c7190c 65
GordonSin 0:0ed2a7c7190c 66 /** \brief DP83848 Status register definitions */
GordonSin 0:0ed2a7c7190c 67 #define DP8_100BASE_T4 (1 << 15) /**< T4 mode */
GordonSin 0:0ed2a7c7190c 68 #define DP8_100BASE_TX_FD (1 << 14) /**< 100MBps full duplex */
GordonSin 0:0ed2a7c7190c 69 #define DP8_100BASE_TX_HD (1 << 13) /**< 100MBps half duplex */
GordonSin 0:0ed2a7c7190c 70 #define DP8_10BASE_T_FD (1 << 12) /**< 100Bps full duplex */
GordonSin 0:0ed2a7c7190c 71 #define DP8_10BASE_T_HD (1 << 11) /**< 10MBps half duplex */
GordonSin 0:0ed2a7c7190c 72 #define DP8_MF_PREAMB_SUPPR (1 << 6) /**< Preamble suppress */
GordonSin 0:0ed2a7c7190c 73 #define DP8_AUTONEG_COMP (1 << 5) /**< Auto-negotation complete */
GordonSin 0:0ed2a7c7190c 74 #define DP8_RMT_FAULT (1 << 4) /**< Fault */
GordonSin 0:0ed2a7c7190c 75 #define DP8_AUTONEG_ABILITY (1 << 3) /**< Auto-negotation supported */
GordonSin 0:0ed2a7c7190c 76 #define DP8_LINK_STATUS (1 << 2) /**< 1=Link active */
GordonSin 0:0ed2a7c7190c 77 #define DP8_JABBER_DETECT (1 << 1) /**< Jabber detect */
GordonSin 0:0ed2a7c7190c 78 #define DP8_EXTEND_CAPAB (1 << 0) /**< Supports extended capabilities */
GordonSin 0:0ed2a7c7190c 79
GordonSin 0:0ed2a7c7190c 80 /** \brief DP83848 PHY RBR MII dode definitions */
GordonSin 0:0ed2a7c7190c 81 #define DP8_RBR_RMII_MODE (1 << 5) /**< Use RMII mode */
GordonSin 0:0ed2a7c7190c 82
GordonSin 0:0ed2a7c7190c 83 /** \brief DP83848 PHY status definitions */
GordonSin 0:0ed2a7c7190c 84 #define DP8_REMOTEFAULT (1 << 6) /**< Remote fault */
GordonSin 0:0ed2a7c7190c 85 #define DP8_FULLDUPLEX (1 << 2) /**< 1=full duplex */
GordonSin 0:0ed2a7c7190c 86 #define DP8_SPEED10MBPS (1 << 1) /**< 1=10MBps speed */
GordonSin 0:0ed2a7c7190c 87 #define DP8_VALID_LINK (1 << 0) /**< 1=Link active */
GordonSin 0:0ed2a7c7190c 88
GordonSin 0:0ed2a7c7190c 89 /** \brief DP83848 PHY ID register definitions */
GordonSin 0:0ed2a7c7190c 90 #define DP8_PHYID1_OUI 0x2000 /**< Expected PHY ID1 */
GordonSin 0:0ed2a7c7190c 91 #define DP8_PHYID2_OUI 0x5c90 /**< Expected PHY ID2 */
GordonSin 0:0ed2a7c7190c 92
GordonSin 0:0ed2a7c7190c 93 /** \brief PHY status structure used to indicate current status of PHY.
GordonSin 0:0ed2a7c7190c 94 */
GordonSin 0:0ed2a7c7190c 95 typedef struct {
GordonSin 0:0ed2a7c7190c 96 u32_t phy_speed_100mbs:1; /**< 10/100 MBS connection speed flag. */
GordonSin 0:0ed2a7c7190c 97 u32_t phy_full_duplex:1; /**< Half/full duplex connection speed flag. */
GordonSin 0:0ed2a7c7190c 98 u32_t phy_link_active:1; /**< Phy link active flag. */
GordonSin 0:0ed2a7c7190c 99 } PHY_STATUS_TYPE;
GordonSin 0:0ed2a7c7190c 100
GordonSin 0:0ed2a7c7190c 101 /** \brief PHY update flags */
GordonSin 0:0ed2a7c7190c 102 static PHY_STATUS_TYPE physts;
GordonSin 0:0ed2a7c7190c 103
GordonSin 0:0ed2a7c7190c 104 /** \brief Last PHY update flags, used for determing if something has changed */
GordonSin 0:0ed2a7c7190c 105 static PHY_STATUS_TYPE olddphysts;
GordonSin 0:0ed2a7c7190c 106
GordonSin 0:0ed2a7c7190c 107 /** \brief PHY update counter for state machine */
GordonSin 0:0ed2a7c7190c 108 static s32_t phyustate;
GordonSin 0:0ed2a7c7190c 109
GordonSin 0:0ed2a7c7190c 110 /** \brief Update PHY status from passed value
GordonSin 0:0ed2a7c7190c 111 *
GordonSin 0:0ed2a7c7190c 112 * This function updates the current PHY status based on the
GordonSin 0:0ed2a7c7190c 113 * passed PHY status word. The PHY status indicate if the link
GordonSin 0:0ed2a7c7190c 114 * is active, the connection speed, and duplex.
GordonSin 0:0ed2a7c7190c 115 *
GordonSin 0:0ed2a7c7190c 116 * \param[in] netif NETIF structure
GordonSin 0:0ed2a7c7190c 117 * \param[in] linksts Status word from PHY
GordonSin 0:0ed2a7c7190c 118 * \return 1 if the status has changed, otherwise 0
GordonSin 0:0ed2a7c7190c 119 */
GordonSin 0:0ed2a7c7190c 120 static s32_t lpc_update_phy_sts(struct netif *netif, u32_t linksts)
GordonSin 0:0ed2a7c7190c 121 {
GordonSin 0:0ed2a7c7190c 122 s32_t changed = 0;
GordonSin 0:0ed2a7c7190c 123
GordonSin 0:0ed2a7c7190c 124 /* Update link active status */
GordonSin 0:0ed2a7c7190c 125 if (linksts & DP8_VALID_LINK)
GordonSin 0:0ed2a7c7190c 126 physts.phy_link_active = 1;
GordonSin 0:0ed2a7c7190c 127 else
GordonSin 0:0ed2a7c7190c 128 physts.phy_link_active = 0;
GordonSin 0:0ed2a7c7190c 129
GordonSin 0:0ed2a7c7190c 130 /* Full or half duplex */
GordonSin 0:0ed2a7c7190c 131 if (linksts & DP8_FULLDUPLEX)
GordonSin 0:0ed2a7c7190c 132 physts.phy_full_duplex = 1;
GordonSin 0:0ed2a7c7190c 133 else
GordonSin 0:0ed2a7c7190c 134 physts.phy_full_duplex = 0;
GordonSin 0:0ed2a7c7190c 135
GordonSin 0:0ed2a7c7190c 136 /* Configure 100MBit/10MBit mode. */
GordonSin 0:0ed2a7c7190c 137 if (linksts & DP8_SPEED10MBPS)
GordonSin 0:0ed2a7c7190c 138 physts.phy_speed_100mbs = 0;
GordonSin 0:0ed2a7c7190c 139 else
GordonSin 0:0ed2a7c7190c 140 physts.phy_speed_100mbs = 1;
GordonSin 0:0ed2a7c7190c 141
GordonSin 0:0ed2a7c7190c 142 if (physts.phy_speed_100mbs != olddphysts.phy_speed_100mbs) {
GordonSin 0:0ed2a7c7190c 143 changed = 1;
GordonSin 0:0ed2a7c7190c 144 if (physts.phy_speed_100mbs) {
GordonSin 0:0ed2a7c7190c 145 /* 100MBit mode. */
GordonSin 0:0ed2a7c7190c 146 lpc_emac_set_speed(1);
GordonSin 0:0ed2a7c7190c 147
GordonSin 0:0ed2a7c7190c 148 NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 100000000);
GordonSin 0:0ed2a7c7190c 149 }
GordonSin 0:0ed2a7c7190c 150 else {
GordonSin 0:0ed2a7c7190c 151 /* 10MBit mode. */
GordonSin 0:0ed2a7c7190c 152 lpc_emac_set_speed(0);
GordonSin 0:0ed2a7c7190c 153
GordonSin 0:0ed2a7c7190c 154 NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 10000000);
GordonSin 0:0ed2a7c7190c 155 }
GordonSin 0:0ed2a7c7190c 156
GordonSin 0:0ed2a7c7190c 157 olddphysts.phy_speed_100mbs = physts.phy_speed_100mbs;
GordonSin 0:0ed2a7c7190c 158 }
GordonSin 0:0ed2a7c7190c 159
GordonSin 0:0ed2a7c7190c 160 if (physts.phy_full_duplex != olddphysts.phy_full_duplex) {
GordonSin 0:0ed2a7c7190c 161 changed = 1;
GordonSin 0:0ed2a7c7190c 162 if (physts.phy_full_duplex)
GordonSin 0:0ed2a7c7190c 163 lpc_emac_set_duplex(1);
GordonSin 0:0ed2a7c7190c 164 else
GordonSin 0:0ed2a7c7190c 165 lpc_emac_set_duplex(0);
GordonSin 0:0ed2a7c7190c 166
GordonSin 0:0ed2a7c7190c 167 olddphysts.phy_full_duplex = physts.phy_full_duplex;
GordonSin 0:0ed2a7c7190c 168 }
GordonSin 0:0ed2a7c7190c 169
GordonSin 0:0ed2a7c7190c 170 if (physts.phy_link_active != olddphysts.phy_link_active) {
GordonSin 0:0ed2a7c7190c 171 changed = 1;
GordonSin 0:0ed2a7c7190c 172 #if NO_SYS == 1
GordonSin 0:0ed2a7c7190c 173 if (physts.phy_link_active)
GordonSin 0:0ed2a7c7190c 174 netif_set_link_up(netif);
GordonSin 0:0ed2a7c7190c 175 else
GordonSin 0:0ed2a7c7190c 176 netif_set_link_down(netif);
GordonSin 0:0ed2a7c7190c 177 #else
GordonSin 0:0ed2a7c7190c 178 if (physts.phy_link_active)
GordonSin 0:0ed2a7c7190c 179 tcpip_callback_with_block((tcpip_callback_fn) netif_set_link_up,
GordonSin 0:0ed2a7c7190c 180 (void*) netif, 1);
GordonSin 0:0ed2a7c7190c 181 else
GordonSin 0:0ed2a7c7190c 182 tcpip_callback_with_block((tcpip_callback_fn) netif_set_link_down,
GordonSin 0:0ed2a7c7190c 183 (void*) netif, 1);
GordonSin 0:0ed2a7c7190c 184 #endif
GordonSin 0:0ed2a7c7190c 185
GordonSin 0:0ed2a7c7190c 186 olddphysts.phy_link_active = physts.phy_link_active;
GordonSin 0:0ed2a7c7190c 187 }
GordonSin 0:0ed2a7c7190c 188
GordonSin 0:0ed2a7c7190c 189 return changed;
GordonSin 0:0ed2a7c7190c 190 }
GordonSin 0:0ed2a7c7190c 191
GordonSin 0:0ed2a7c7190c 192 /** \brief Initialize the DP83848 PHY.
GordonSin 0:0ed2a7c7190c 193 *
GordonSin 0:0ed2a7c7190c 194 * This function initializes the DP83848 PHY. It will block until
GordonSin 0:0ed2a7c7190c 195 * complete. This function is called as part of the EMAC driver
GordonSin 0:0ed2a7c7190c 196 * initialization. Configuration of the PHY at startup is
GordonSin 0:0ed2a7c7190c 197 * controlled by setting up configuration defines in lpc_phy.h.
GordonSin 0:0ed2a7c7190c 198 *
GordonSin 0:0ed2a7c7190c 199 * \param[in] netif NETIF structure
GordonSin 0:0ed2a7c7190c 200 * \param[in] rmii If set, configures the PHY for RMII mode
GordonSin 0:0ed2a7c7190c 201 * \return ERR_OK if the setup was successful, otherwise ERR_TIMEOUT
GordonSin 0:0ed2a7c7190c 202 */
GordonSin 0:0ed2a7c7190c 203 err_t lpc_phy_init(struct netif *netif, int rmii)
GordonSin 0:0ed2a7c7190c 204 {
GordonSin 0:0ed2a7c7190c 205 u32_t tmp;
GordonSin 0:0ed2a7c7190c 206 s32_t i;
GordonSin 0:0ed2a7c7190c 207
GordonSin 0:0ed2a7c7190c 208 physts.phy_speed_100mbs = olddphysts.phy_speed_100mbs = 2;
GordonSin 0:0ed2a7c7190c 209 physts.phy_full_duplex = olddphysts.phy_full_duplex = 2;
GordonSin 0:0ed2a7c7190c 210 physts.phy_link_active = olddphysts.phy_link_active = 2;
GordonSin 0:0ed2a7c7190c 211 phyustate = 0;
GordonSin 0:0ed2a7c7190c 212
GordonSin 0:0ed2a7c7190c 213 /* Only first read and write are checked for failure */
GordonSin 0:0ed2a7c7190c 214 /* Put the DP83848C in reset mode and wait for completion */
GordonSin 0:0ed2a7c7190c 215 if (lpc_mii_write(DP8_BMCR_REG, DP8_RESET) != 0)
GordonSin 0:0ed2a7c7190c 216 return ERR_TIMEOUT;
GordonSin 0:0ed2a7c7190c 217 i = 400;
GordonSin 0:0ed2a7c7190c 218 while (i > 0) {
GordonSin 0:0ed2a7c7190c 219 osDelay(1); /* 1 ms */
GordonSin 0:0ed2a7c7190c 220 if (lpc_mii_read(DP8_BMCR_REG, &tmp) != 0)
GordonSin 0:0ed2a7c7190c 221 return ERR_TIMEOUT;
GordonSin 0:0ed2a7c7190c 222
GordonSin 0:0ed2a7c7190c 223 if (!(tmp & (DP8_RESET | DP8_POWER_DOWN)))
GordonSin 0:0ed2a7c7190c 224 i = -1;
GordonSin 0:0ed2a7c7190c 225 else
GordonSin 0:0ed2a7c7190c 226 i--;
GordonSin 0:0ed2a7c7190c 227 }
GordonSin 0:0ed2a7c7190c 228 /* Timeout? */
GordonSin 0:0ed2a7c7190c 229 if (i == 0)
GordonSin 0:0ed2a7c7190c 230 return ERR_TIMEOUT;
GordonSin 0:0ed2a7c7190c 231
GordonSin 0:0ed2a7c7190c 232 /* Setup link based on configuration options */
GordonSin 0:0ed2a7c7190c 233 #if PHY_USE_AUTONEG==1
GordonSin 0:0ed2a7c7190c 234 tmp = DP8_AUTONEG;
GordonSin 0:0ed2a7c7190c 235 #else
GordonSin 0:0ed2a7c7190c 236 tmp = 0;
GordonSin 0:0ed2a7c7190c 237 #endif
GordonSin 0:0ed2a7c7190c 238 #if PHY_USE_100MBS==1
GordonSin 0:0ed2a7c7190c 239 tmp |= DP8_SPEED_SELECT;
GordonSin 0:0ed2a7c7190c 240 #endif
GordonSin 0:0ed2a7c7190c 241 #if PHY_USE_FULL_DUPLEX==1
GordonSin 0:0ed2a7c7190c 242 tmp |= DP8_DUPLEX_MODE;
GordonSin 0:0ed2a7c7190c 243 #endif
GordonSin 0:0ed2a7c7190c 244 lpc_mii_write(DP8_BMCR_REG, tmp);
GordonSin 0:0ed2a7c7190c 245
GordonSin 0:0ed2a7c7190c 246 /* Enable RMII mode for PHY */
GordonSin 0:0ed2a7c7190c 247 if (rmii)
GordonSin 0:0ed2a7c7190c 248 lpc_mii_write(DP8_PHY_RBR_REG, DP8_RBR_RMII_MODE);
GordonSin 0:0ed2a7c7190c 249
GordonSin 0:0ed2a7c7190c 250 /* The link is not set active at this point, but will be detected
GordonSin 0:0ed2a7c7190c 251 later */
GordonSin 0:0ed2a7c7190c 252
GordonSin 0:0ed2a7c7190c 253 return ERR_OK;
GordonSin 0:0ed2a7c7190c 254 }
GordonSin 0:0ed2a7c7190c 255
GordonSin 0:0ed2a7c7190c 256 /* Phy status update state machine */
GordonSin 0:0ed2a7c7190c 257 s32_t lpc_phy_sts_sm(struct netif *netif)
GordonSin 0:0ed2a7c7190c 258 {
GordonSin 0:0ed2a7c7190c 259 s32_t changed = 0;
GordonSin 0:0ed2a7c7190c 260
GordonSin 0:0ed2a7c7190c 261 switch (phyustate) {
GordonSin 0:0ed2a7c7190c 262 default:
GordonSin 0:0ed2a7c7190c 263 case 0:
GordonSin 0:0ed2a7c7190c 264 /* Read BMSR to clear faults */
GordonSin 0:0ed2a7c7190c 265 lpc_mii_read_noblock(DP8_PHY_STAT_REG);
GordonSin 0:0ed2a7c7190c 266 phyustate = 1;
GordonSin 0:0ed2a7c7190c 267 break;
GordonSin 0:0ed2a7c7190c 268
GordonSin 0:0ed2a7c7190c 269 case 1:
GordonSin 0:0ed2a7c7190c 270 /* Wait for read status state */
GordonSin 0:0ed2a7c7190c 271 if (!lpc_mii_is_busy()) {
GordonSin 0:0ed2a7c7190c 272 /* Update PHY status */
GordonSin 0:0ed2a7c7190c 273 changed = lpc_update_phy_sts(netif, lpc_mii_read_data());
GordonSin 0:0ed2a7c7190c 274 phyustate = 0;
GordonSin 0:0ed2a7c7190c 275 }
GordonSin 0:0ed2a7c7190c 276 break;
GordonSin 0:0ed2a7c7190c 277 }
GordonSin 0:0ed2a7c7190c 278
GordonSin 0:0ed2a7c7190c 279 return changed;
GordonSin 0:0ed2a7c7190c 280 }
GordonSin 0:0ed2a7c7190c 281
GordonSin 0:0ed2a7c7190c 282 /**
GordonSin 0:0ed2a7c7190c 283 * @}
GordonSin 0:0ed2a7c7190c 284 */
GordonSin 0:0ed2a7c7190c 285
GordonSin 0:0ed2a7c7190c 286 /* --------------------------------- End Of File ------------------------------ */