Damian Gowor / MDebug-src

Debugging library

MDebugger.cpp@1:05bd8eb25467, 2014-06-25 (annotated)

Committer:
Gofs
Date:
Wed Jun 25 14:57:57 2014 +0000
Revision:
1:05bd8eb25467
Parent:
0:57b729dee92c 
Proposal

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Gofs 0:57b729dee92c 1 #include <MDebugger.h>
Gofs 0:57b729dee92c 2 #include <stdio.h>
Gofs 0:57b729dee92c 3 #include <stdarg.h>
Gofs 0:57b729dee92c 4
Gofs 0:57b729dee92c 5 #if MDEBUGGER_CIRCULAR_BUFFER_SIZE_IN_BYTES > 0
Gofs 0:57b729dee92c 6 static unsigned char MDEBUGGER_CIRCULAR_BUFFER[MDEBUGGER_NUMBER_OF_ADDRESS_CHANNELS][MDEBUGGER_CIRCULAR_BUFFER_SIZE_IN_BYTES] = { 0 };
Gofs 0:57b729dee92c 7 static uint32_t MDEBUGGER_CIRCULAR_BUFFER_HEAD[MDEBUGGER_NUMBER_OF_ADDRESS_CHANNELS] = { 0 };
Gofs 0:57b729dee92c 8 static uint32_t MDEBUGGER_CIRCULAR_BUFFER_TAIL[MDEBUGGER_NUMBER_OF_ADDRESS_CHANNELS] = { 0 };
Gofs 0:57b729dee92c 9 static uint32_t MDEBUGGER_CIRCULAR_BUFFER_IS_FULL[MDEBUGGER_NUMBER_OF_ADDRESS_CHANNELS] = { 0 };
Gofs 0:57b729dee92c 10 #endif
Gofs 0:57b729dee92c 11
Gofs 0:57b729dee92c 12 #define ACTLR_REGISTER_VALUE (*((uint32_t*)0xE000E008))
Gofs 0:57b729dee92c 13 #define SYSTICK_REGISTER_VALUE (*((uint32_t*)0xE000E010))
Gofs 0:57b729dee92c 14 #define SYSTICK_RELOAD_VALUE_REGISTER_VALUE (*((uint32_t*)0xE000E014))
Gofs 0:57b729dee92c 15 #define SYSTICK_CURRENT_VALUE_REGISTER_VALUE (*((uint32_t*)0xE000E018))
Gofs 0:57b729dee92c 16 #define SYSTICK_CALIBRATION_REGISTER_VALUE (*((uint32_t*)0xE000E01C))
Gofs 0:57b729dee92c 17
Gofs 0:57b729dee92c 18 #define SETENA0_REGISTER_VALUE (*((uint32_t*)0xE000E200))
Gofs 0:57b729dee92c 19 #define SETENA1_REGISTER_VALUE (*((uint32_t*)0xE000E204))
Gofs 0:57b729dee92c 20 #define SETENA2_REGISTER_VALUE (*((uint32_t*)0xE000E208))
Gofs 0:57b729dee92c 21 #define SETENA3_REGISTER_VALUE (*((uint32_t*)0xE000E20C))
Gofs 0:57b729dee92c 22 #define SETENA4_REGISTER_VALUE (*((uint32_t*)0xE000E210))
Gofs 0:57b729dee92c 23 #define SETENA5_REGISTER_VALUE (*((uint32_t*)0xE000E214))
Gofs 0:57b729dee92c 24 #define SETENA6_REGISTER_VALUE (*((uint32_t*)0xE000E218))
Gofs 0:57b729dee92c 25 #define SETENA7_REGISTER_VALUE (*((uint32_t*)0xE000E21C))
Gofs 0:57b729dee92c 26
Gofs 0:57b729dee92c 27 #define CPUID_REGISTER_VALUE (*((uint32_t*)0xE000ED00))
Gofs 0:57b729dee92c 28 #define ICSR_REGISTER_VALUE (*((uint32_t*)0xE000ED04))
Gofs 0:57b729dee92c 29 #define VTOR_REGISTER_VALUE (*((uint32_t*)0xE000ED08))
Gofs 0:57b729dee92c 30 #define AIRCR_REGISTER_VALUE (*((uint32_t*)0xE000ED0C))
Gofs 0:57b729dee92c 31 #define SCR_REGISTER_VALUE (*((uint32_t*)0xE000ED10))
Gofs 0:57b729dee92c 32 #define CCR_REGISTER_VALUE (*((uint32_t*)0xE000ED14))
Gofs 0:57b729dee92c 33 #define SHPR1_REGISTER_VALUE (*((uint32_t*)0xE000ED18))
Gofs 0:57b729dee92c 34 #define SHPR2_REGISTER_VALUE (*((uint32_t*)0xE000ED1C))
Gofs 0:57b729dee92c 35 #define SHPR3_REGISTER_VALUE (*((uint32_t*)0xE000ED20))
Gofs 0:57b729dee92c 36 #define SHCRS_REGISTER_VALUE (*((uint32_t*)0xE000ED24))
Gofs 0:57b729dee92c 37 #define CFSR_REGISTER_VALUE (*((uint32_t*)0xE000ED28))
Gofs 0:57b729dee92c 38 #define HFSR_REGISTER_VALUE (*((uint32_t*)0xE000ED2C))
Gofs 0:57b729dee92c 39 #define MMAR_REGISTER_VALUE (*((uint32_t*)0xE000ED34))
Gofs 0:57b729dee92c 40 #define BFAR_REGISTER_VALUE (*((uint32_t*)0xE000ED38))
Gofs 0:57b729dee92c 41 #define AFSR_REGISTER_VALUE (*((uint32_t*)0xE000ED3C))
Gofs 0:57b729dee92c 42
Gofs 0:57b729dee92c 43 #define MMU_TYPE_REGISTER_VALUE (*((uint32_t*)0xE000ED90))
Gofs 0:57b729dee92c 44 #define MMU_CONTROL_REGISTER_VALUE (*((uint32_t*)0xE000ED94))
Gofs 0:57b729dee92c 45 #define MMU_RBASR_REGISTER_VALUE (*((uint32_t*)0xE000ED9C))
Gofs 0:57b729dee92c 46
Gofs 0:57b729dee92c 47
Gofs 0:57b729dee92c 48 void mdebug_flush(uint32_t channel)
Gofs 0:57b729dee92c 49 {
Gofs 0:57b729dee92c 50 #if MDEBUGGER_CIRCULAR_BUFFER_SIZE_IN_BYTES > 0
Gofs 0:57b729dee92c 51 if (mdebug_output_buffer_is_empty(channel)) {
Gofs 0:57b729dee92c 52 return;
Gofs 0:57b729dee92c 53 }
Gofs 0:57b729dee92c 54
Gofs 0:57b729dee92c 55 do {
Gofs 0:57b729dee92c 56 mdebug_putc(MDEBUGGER_CIRCULAR_BUFFER[channel][MDEBUGGER_CIRCULAR_BUFFER_TAIL[channel]], channel);
Gofs 0:57b729dee92c 57
Gofs 0:57b729dee92c 58 if (++MDEBUGGER_CIRCULAR_BUFFER_TAIL[channel] == MDEBUGGER_CIRCULAR_BUFFER_SIZE_IN_BYTES) {
Gofs 0:57b729dee92c 59 MDEBUGGER_CIRCULAR_BUFFER_TAIL[channel] = 0;
Gofs 0:57b729dee92c 60 }
Gofs 0:57b729dee92c 61 } while (MDEBUGGER_CIRCULAR_BUFFER_HEAD[channel] != MDEBUGGER_CIRCULAR_BUFFER_TAIL[channel]);
Gofs 0:57b729dee92c 62
Gofs 0:57b729dee92c 63 MDEBUGGER_CIRCULAR_BUFFER_IS_FULL[channel] = 0;
Gofs 0:57b729dee92c 64 #endif
Gofs 0:57b729dee92c 65 }
Gofs 0:57b729dee92c 66
Gofs 0:57b729dee92c 67 void mdebug_write(unsigned char *in_buffer, uint32_t in_buffer_size, uint32_t channel)
Gofs 0:57b729dee92c 68 {
Gofs 0:57b729dee92c 69 uint32_t index;
Gofs 0:57b729dee92c 70
Gofs 0:57b729dee92c 71 #if MDEBUGGER_CIRCULAR_BUFFER_SIZE_IN_BYTES == 0
Gofs 0:57b729dee92c 72 for (index = 0; index < in_buffer_size; ++index) {
Gofs 0:57b729dee92c 73 mdebug_putc(in_buffer[index], channel);
Gofs 0:57b729dee92c 74 }
Gofs 0:57b729dee92c 75 #else
Gofs 0:57b729dee92c 76
Gofs 0:57b729dee92c 77 for (index = 0; index < in_buffer_size; ++index) {
Gofs 0:57b729dee92c 78 MDEBUGGER_CIRCULAR_BUFFER[channel][MDEBUGGER_CIRCULAR_BUFFER_HEAD[channel]] = in_buffer[index];
Gofs 0:57b729dee92c 79
Gofs 0:57b729dee92c 80 if (++MDEBUGGER_CIRCULAR_BUFFER_HEAD[channel] == MDEBUGGER_CIRCULAR_BUFFER_SIZE_IN_BYTES) {
Gofs 0:57b729dee92c 81 MDEBUGGER_CIRCULAR_BUFFER_HEAD[channel] = 0;
Gofs 0:57b729dee92c 82 }
Gofs 0:57b729dee92c 83
Gofs 0:57b729dee92c 84 if (MDEBUGGER_CIRCULAR_BUFFER_HEAD[channel] == MDEBUGGER_CIRCULAR_BUFFER_TAIL[channel]) {
Gofs 0:57b729dee92c 85 MDEBUGGER_CIRCULAR_BUFFER_IS_FULL[channel] = 1;
Gofs 0:57b729dee92c 86 mdebug_flush(channel);
Gofs 0:57b729dee92c 87 }
Gofs 0:57b729dee92c 88 }
Gofs 0:57b729dee92c 89 #endif
Gofs 0:57b729dee92c 90 }
Gofs 0:57b729dee92c 91
Gofs 0:57b729dee92c 92
Gofs 0:57b729dee92c 93
Gofs 0:57b729dee92c 94 void mdebug_printf(uint32_t channel, const char *formatting_string, ...)
Gofs 0:57b729dee92c 95 {
Gofs 0:57b729dee92c 96 va_list arg;
Gofs 0:57b729dee92c 97 unsigned char buffer[128];
Gofs 0:57b729dee92c 98 uint32_t length;
Gofs 0:57b729dee92c 99
Gofs 0:57b729dee92c 100 va_start(arg, formatting_string);
Gofs 0:57b729dee92c 101 length = vsprintf((char*)buffer, formatting_string, arg);
Gofs 0:57b729dee92c 102 va_end(arg);
Gofs 0:57b729dee92c 103
Gofs 0:57b729dee92c 104 mdebug_write(buffer, length, channel);
Gofs 0:57b729dee92c 105 }
Gofs 0:57b729dee92c 106
Gofs 0:57b729dee92c 107 void mdebug_write_unbuffered(unsigned char *in_buffer, uint32_t in_buffer_size, uint32_t channel)
Gofs 0:57b729dee92c 108 {
Gofs 0:57b729dee92c 109 uint32_t index;
Gofs 0:57b729dee92c 110
Gofs 0:57b729dee92c 111 for (index = 0; index < in_buffer_size; ++index) {
Gofs 0:57b729dee92c 112 mdebug_putc(in_buffer[index], channel);
Gofs 0:57b729dee92c 113 }
Gofs 0:57b729dee92c 114 }
Gofs 0:57b729dee92c 115
Gofs 0:57b729dee92c 116
Gofs 0:57b729dee92c 117
Gofs 0:57b729dee92c 118 void mdebug_printf_unbuffered(uint32_t channel, const char *formatting_string, ...)
Gofs 0:57b729dee92c 119 {
Gofs 0:57b729dee92c 120 va_list arg;
Gofs 0:57b729dee92c 121 unsigned char buffer[256];
Gofs 0:57b729dee92c 122 uint32_t length;
Gofs 0:57b729dee92c 123
Gofs 0:57b729dee92c 124 va_start(arg, formatting_string);
Gofs 0:57b729dee92c 125 length = vsprintf((char*)buffer, formatting_string, arg);
Gofs 0:57b729dee92c 126 va_end(arg);
Gofs 0:57b729dee92c 127
Gofs 0:57b729dee92c 128 mdebug_write_unbuffered((unsigned char*)buffer, length, channel);
Gofs 0:57b729dee92c 129 }
Gofs 0:57b729dee92c 130
Gofs 0:57b729dee92c 131 uint32_t mdebug_output_bufer_used_space(uint32_t channel)
Gofs 0:57b729dee92c 132 {
Gofs 0:57b729dee92c 133 #if MDEBUGGER_CIRCULAR_BUFFER_SIZE_IN_BYTES > 0
Gofs 0:57b729dee92c 134 if (MDEBUGGER_CIRCULAR_BUFFER_HEAD[channel] >= MDEBUGGER_CIRCULAR_BUFFER_TAIL[channel]) {
Gofs 0:57b729dee92c 135 return MDEBUGGER_CIRCULAR_BUFFER_HEAD[channel] - MDEBUGGER_CIRCULAR_BUFFER_TAIL[channel];
Gofs 0:57b729dee92c 136 }
Gofs 0:57b729dee92c 137 else {
Gofs 0:57b729dee92c 138 return MDEBUGGER_CIRCULAR_BUFFER_SIZE_IN_BYTES - MDEBUGGER_CIRCULAR_BUFFER_TAIL[channel] + MDEBUGGER_CIRCULAR_BUFFER_HEAD[channel];
Gofs 0:57b729dee92c 139 }
Gofs 0:57b729dee92c 140 #else
Gofs 0:57b729dee92c 141 reuturn 0;
Gofs 0:57b729dee92c 142 #endif
Gofs 0:57b729dee92c 143 }
Gofs 0:57b729dee92c 144
Gofs 0:57b729dee92c 145 uint32_t mdebug_output_buffer_free_space(uint32_t channel)
Gofs 0:57b729dee92c 146 {
Gofs 0:57b729dee92c 147 #if MDEBUGGER_CIRCULAR_BUFFER_SIZE_IN_BYTES > 0
Gofs 0:57b729dee92c 148 return MDEBUGGER_CIRCULAR_BUFFER_SIZE_IN_BYTES - mdebug_output_bufer_used_space(channel);
Gofs 0:57b729dee92c 149 #else
Gofs 0:57b729dee92c 150 reuturn 0;
Gofs 0:57b729dee92c 151 #endif
Gofs 0:57b729dee92c 152 }
Gofs 0:57b729dee92c 153
Gofs 0:57b729dee92c 154 uint32_t mdebug_output_buffer_is_empty(uint32_t channel)
Gofs 0:57b729dee92c 155 {
Gofs 0:57b729dee92c 156 if (MDEBUGGER_CIRCULAR_BUFFER_IS_FULL[channel])
Gofs 0:57b729dee92c 157 {
Gofs 0:57b729dee92c 158 return 0;
Gofs 0:57b729dee92c 159 }
Gofs 0:57b729dee92c 160 else
Gofs 0:57b729dee92c 161 {
Gofs 1:05bd8eb25467 162 return (MDEBUGGER_CIRCULAR_BUFFER_HEAD[channel] == MDEBUGGER_CIRCULAR_BUFFER_TAIL[channel]) ? 1 : 0;
Gofs 0:57b729dee92c 163 }
Gofs 0:57b729dee92c 164 }
Gofs 0:57b729dee92c 165
Gofs 0:57b729dee92c 166
Gofs 0:57b729dee92c 167
Gofs 0:57b729dee92c 168 void mdebug_print_system_info()
Gofs 0:57b729dee92c 169 {
Gofs 0:57b729dee92c 170 uint32_t ControlRegister = __get_CONTROL();
Gofs 1:05bd8eb25467 171 uint32_t MSP = __get_MSP();
Gofs 0:57b729dee92c 172 uint32_t PSP;
Gofs 0:57b729dee92c 173 uint32_t IPSR;
Gofs 0:57b729dee92c 174 uint32_t PRIMASK;
Gofs 0:57b729dee92c 175 uint32_t BASEPRI;
Gofs 0:57b729dee92c 176 uint32_t FAULTMASK;
Gofs 0:57b729dee92c 177
Gofs 0:57b729dee92c 178
Gofs 0:57b729dee92c 179 switch (ControlRegister & 0x00000003)
Gofs 0:57b729dee92c 180 {
Gofs 0:57b729dee92c 181 case 0: // Privileged mode, main stack is used
Gofs 0:57b729dee92c 182 PSP = __get_PSP();
Gofs 0:57b729dee92c 183 break;
Gofs 0:57b729dee92c 184
Gofs 0:57b729dee92c 185 case 2: // Privileged mode, alternate stack is used
Gofs 0:57b729dee92c 186 PSP = __get_PSP();
Gofs 0:57b729dee92c 187 break;
Gofs 0:57b729dee92c 188
Gofs 0:57b729dee92c 189 default: // could not happen
Gofs 0:57b729dee92c 190 break;
Gofs 0:57b729dee92c 191 }
Gofs 0:57b729dee92c 192
Gofs 0:57b729dee92c 193 IPSR = __get_IPSR() & 0x000001FF;
Gofs 0:57b729dee92c 194 PRIMASK = __get_PRIMASK();// & 0x00000001;
Gofs 0:57b729dee92c 195 BASEPRI = __get_BASEPRI(); //& 0x000000FF;
Gofs 0:57b729dee92c 196 FAULTMASK = __get_FAULTMASK();// & 0x00000001;
Gofs 0:57b729dee92c 197
Gofs 0:57b729dee92c 198 mdebug_printf_unbuffered(0, "\r\n\r\n====================");
Gofs 0:57b729dee92c 199 mdebug_printf_unbuffered(0, "\r\nCONTROL:\t\t0x%08X", ControlRegister);
Gofs 0:57b729dee92c 200
Gofs 0:57b729dee92c 201 if (ControlRegister & (1 << 0))
Gofs 0:57b729dee92c 202 {
Gofs 0:57b729dee92c 203 mdebug_printf_unbuffered(0, "\r\n\t* User mode.");
Gofs 0:57b729dee92c 204 }
Gofs 0:57b729dee92c 205 else
Gofs 0:57b729dee92c 206 {
Gofs 0:57b729dee92c 207 mdebug_printf_unbuffered(0, "\r\n\t* Privileged mode.");
Gofs 0:57b729dee92c 208 }
Gofs 0:57b729dee92c 209
Gofs 0:57b729dee92c 210 if (ControlRegister & (1 << 1))
Gofs 0:57b729dee92c 211 {
Gofs 0:57b729dee92c 212 mdebug_printf_unbuffered(0, "\r\n\t* Alternate stack is used.");
Gofs 0:57b729dee92c 213 }
Gofs 0:57b729dee92c 214 else
Gofs 0:57b729dee92c 215 {
Gofs 0:57b729dee92c 216 mdebug_printf_unbuffered(0, "\r\n\t* Main stack is used.");
Gofs 0:57b729dee92c 217 }
Gofs 0:57b729dee92c 218
Gofs 0:57b729dee92c 219 mdebug_printf_unbuffered(0, "\r\n====================");
Gofs 0:57b729dee92c 220 mdebug_printf_unbuffered(0, "\r\nIPSR:\t\t\t0x%08X\r\n\t* Context: ", IPSR);
Gofs 0:57b729dee92c 221
Gofs 0:57b729dee92c 222 if (IPSR > 16)
Gofs 0:57b729dee92c 223 {
Gofs 0:57b729dee92c 224 mdebug_printf_unbuffered(0, "interrupt mode. IRQ no %d.", IPSR - 16);
Gofs 0:57b729dee92c 225 }
Gofs 0:57b729dee92c 226 else
Gofs 0:57b729dee92c 227 {
Gofs 0:57b729dee92c 228 switch (IPSR)
Gofs 0:57b729dee92c 229 {
Gofs 0:57b729dee92c 230 case 0:
Gofs 0:57b729dee92c 231 mdebug_printf_unbuffered(0, "thread mode.");
Gofs 0:57b729dee92c 232 break;
Gofs 0:57b729dee92c 233
Gofs 0:57b729dee92c 234 case 2:
Gofs 0:57b729dee92c 235 mdebug_printf_unbuffered(0, "NMI.");
Gofs 0:57b729dee92c 236 break;
Gofs 0:57b729dee92c 237
Gofs 0:57b729dee92c 238 case 3:
Gofs 0:57b729dee92c 239 mdebug_printf_unbuffered(0, "hard hault.");
Gofs 0:57b729dee92c 240 break;
Gofs 0:57b729dee92c 241
Gofs 0:57b729dee92c 242 case 4:
Gofs 0:57b729dee92c 243 mdebug_printf_unbuffered(0, "mem manage.");
Gofs 0:57b729dee92c 244 break;
Gofs 0:57b729dee92c 245
Gofs 0:57b729dee92c 246 case 5:
Gofs 0:57b729dee92c 247 mdebug_printf_unbuffered(0, "bus bault.");
Gofs 0:57b729dee92c 248 break;
Gofs 0:57b729dee92c 249
Gofs 0:57b729dee92c 250 case 6:
Gofs 0:57b729dee92c 251 mdebug_printf_unbuffered(0, "usage uault.");
Gofs 0:57b729dee92c 252 break;
Gofs 0:57b729dee92c 253
Gofs 0:57b729dee92c 254 case 11:
Gofs 0:57b729dee92c 255 mdebug_printf_unbuffered(0, "SVCall.");
Gofs 0:57b729dee92c 256 break;
Gofs 0:57b729dee92c 257
Gofs 0:57b729dee92c 258 case 14:
Gofs 0:57b729dee92c 259 mdebug_printf_unbuffered(0, "PendSV.");
Gofs 0:57b729dee92c 260 break;
Gofs 0:57b729dee92c 261
Gofs 0:57b729dee92c 262 case 15:
Gofs 0:57b729dee92c 263 mdebug_printf_unbuffered(0, "SysTick.");
Gofs 0:57b729dee92c 264 break;
Gofs 0:57b729dee92c 265
Gofs 0:57b729dee92c 266 default:
Gofs 0:57b729dee92c 267 mdebug_printf_unbuffered(0, "other. Number %d.", IPSR);
Gofs 0:57b729dee92c 268 break;
Gofs 0:57b729dee92c 269 }
Gofs 0:57b729dee92c 270 }
Gofs 0:57b729dee92c 271
Gofs 0:57b729dee92c 272 mdebug_printf_unbuffered(0, "\r\n====================");
Gofs 0:57b729dee92c 273 mdebug_printf_unbuffered(0, "\r\nSYSTICK:\t\t\t0x%08X", SYSTICK_REGISTER_VALUE);
Gofs 0:57b729dee92c 274
Gofs 0:57b729dee92c 275 if (SYSTICK_REGISTER_VALUE & (1 << 0))
Gofs 0:57b729dee92c 276 {
Gofs 0:57b729dee92c 277 mdebug_printf_unbuffered(0, "\r\n\t* SysTick is enabled.");
Gofs 0:57b729dee92c 278 }
Gofs 0:57b729dee92c 279 else
Gofs 0:57b729dee92c 280 {
Gofs 0:57b729dee92c 281 mdebug_printf_unbuffered(0, "\r\n\t* SysTick is disabled.");
Gofs 0:57b729dee92c 282 }
Gofs 0:57b729dee92c 283
Gofs 0:57b729dee92c 284 if (SYSTICK_REGISTER_VALUE & (1 << 1))
Gofs 0:57b729dee92c 285 {
Gofs 0:57b729dee92c 286 mdebug_printf_unbuffered(0, "\r\n\t* SysTick interrupt enabled.");
Gofs 0:57b729dee92c 287 }
Gofs 0:57b729dee92c 288 else
Gofs 0:57b729dee92c 289 {
Gofs 0:57b729dee92c 290 mdebug_printf_unbuffered(0, "\r\n\t* SysTick interrupt disabled.");
Gofs 0:57b729dee92c 291 }
Gofs 0:57b729dee92c 292
Gofs 0:57b729dee92c 293 if (SYSTICK_REGISTER_VALUE & (1 << 2))
Gofs 0:57b729dee92c 294 {
Gofs 0:57b729dee92c 295 mdebug_printf_unbuffered(0, "\r\n\t* SysTick uses core clock.");
Gofs 0:57b729dee92c 296 }
Gofs 0:57b729dee92c 297 else
Gofs 0:57b729dee92c 298 {
Gofs 0:57b729dee92c 299 mdebug_printf_unbuffered(0, "\r\n\t* SysTick uses external clock.");
Gofs 0:57b729dee92c 300 }
Gofs 0:57b729dee92c 301
Gofs 0:57b729dee92c 302 if (SYSTICK_REGISTER_VALUE & (1 << 16))
Gofs 0:57b729dee92c 303 {
Gofs 0:57b729dee92c 304 mdebug_printf_unbuffered(0, "\r\n\t* SysTick COUNTFLAG is set.");
Gofs 0:57b729dee92c 305 }
Gofs 0:57b729dee92c 306 else
Gofs 0:57b729dee92c 307 {
Gofs 0:57b729dee92c 308 mdebug_printf_unbuffered(0, "\r\n\t* SysTick COUNTFLAG is not set.");
Gofs 0:57b729dee92c 309 }
Gofs 0:57b729dee92c 310
Gofs 0:57b729dee92c 311 mdebug_printf_unbuffered(0, "\r\n\t* SysTick reload register value = %d", SYSTICK_RELOAD_VALUE_REGISTER_VALUE);
Gofs 0:57b729dee92c 312 mdebug_printf_unbuffered(0, "\r\n\t* SysTick register current value = %d", SYSTICK_CURRENT_VALUE_REGISTER_VALUE);
Gofs 0:57b729dee92c 313 mdebug_printf_unbuffered(0, "\r\n\t* SysTick calibration register value = %d", SYSTICK_CALIBRATION_REGISTER_VALUE);
Gofs 0:57b729dee92c 314
Gofs 0:57b729dee92c 315
Gofs 0:57b729dee92c 316 mdebug_printf_unbuffered(0, "\r\n====================");
Gofs 0:57b729dee92c 317
Gofs 0:57b729dee92c 318 switch (ControlRegister & 0x00000003)
Gofs 0:57b729dee92c 319 {
Gofs 0:57b729dee92c 320 case 0: // Privileged mode, main stack is used
Gofs 0:57b729dee92c 321 case 2: // Privileged mode, alternate stack is used
Gofs 0:57b729dee92c 322 mdebug_printf_unbuffered(0, "\r\nPSP:\t\t\t0x%08X\tProcess Stack Pointer", PSP);
Gofs 0:57b729dee92c 323
Gofs 0:57b729dee92c 324 case 1: // User mode, main stack is used
Gofs 0:57b729dee92c 325 mdebug_printf_unbuffered(0, "\r\nMSP:\t\t\t0x%08X\tMain Stack Pointer", MSP);
Gofs 0:57b729dee92c 326 break;
Gofs 0:57b729dee92c 327
Gofs 0:57b729dee92c 328 default: // could not happen
Gofs 0:57b729dee92c 329 break;
Gofs 0:57b729dee92c 330 }
Gofs 0:57b729dee92c 331
Gofs 0:57b729dee92c 332 mdebug_printf_unbuffered(0, "\r\n====================");
Gofs 0:57b729dee92c 333 mdebug_printf_unbuffered(0, "\r\nACTLR:\t\t\t0x%08X\tAuxiliary Control Register", ACTLR_REGISTER_VALUE);
Gofs 0:57b729dee92c 334 mdebug_printf_unbuffered(0, "\r\n\t* IT folding is %s", (ACTLR_REGISTER_VALUE & 0x4) == 0 ? "enabled." : "disabled.");
Gofs 0:57b729dee92c 335 mdebug_printf_unbuffered(0, "\r\n\t* Write buffer is %s", (ACTLR_REGISTER_VALUE & 0x2) == 0 ? "enabled." : "disabled.");
Gofs 0:57b729dee92c 336 mdebug_printf_unbuffered(0, "\r\n\t* LDM and STM interruption is %s", (ACTLR_REGISTER_VALUE & 0x1) == 0 ? "enabled." : "disabled.");
Gofs 0:57b729dee92c 337
Gofs 0:57b729dee92c 338 mdebug_printf_unbuffered(0, "\r\n====================");
Gofs 0:57b729dee92c 339 mdebug_printf_unbuffered(0, "\r\nCPUID:\t\t\t0x%08X", CPUID_REGISTER_VALUE);
Gofs 0:57b729dee92c 340
Gofs 0:57b729dee92c 341 mdebug_printf_unbuffered(0, "\r\n====================");
Gofs 0:57b729dee92c 342 mdebug_printf_unbuffered(0, "\r\nICSR:\t\t\t0x%08X\tInterrupt Control and State Register", ICSR_REGISTER_VALUE);
Gofs 0:57b729dee92c 343
Gofs 0:57b729dee92c 344 if (ICSR_REGISTER_VALUE & 0x80000000)
Gofs 0:57b729dee92c 345 {
Gofs 0:57b729dee92c 346 mdebug_printf_unbuffered(0, "\r\n\t* NMI is pending.");
Gofs 0:57b729dee92c 347 }
Gofs 0:57b729dee92c 348
Gofs 0:57b729dee92c 349 if (ICSR_REGISTER_VALUE & (1 << 28))
Gofs 0:57b729dee92c 350 {
Gofs 0:57b729dee92c 351 mdebug_printf_unbuffered(0, "\r\n\t* PendSV is pending.");
Gofs 0:57b729dee92c 352 }
Gofs 0:57b729dee92c 353
Gofs 0:57b729dee92c 354 if (ICSR_REGISTER_VALUE & (1 << 26))
Gofs 0:57b729dee92c 355 {
Gofs 0:57b729dee92c 356 mdebug_printf_unbuffered(0, "\r\n\t* SysTick is pending.");
Gofs 0:57b729dee92c 357 }
Gofs 0:57b729dee92c 358
Gofs 0:57b729dee92c 359
Gofs 0:57b729dee92c 360 mdebug_printf_unbuffered(0, "\r\n\t* Highest priority pending enabled exception: ");
Gofs 0:57b729dee92c 361
Gofs 0:57b729dee92c 362 if (ICSR_REGISTER_VALUE & 0x0003F000)
Gofs 0:57b729dee92c 363 {
Gofs 0:57b729dee92c 364 mdebug_printf_unbuffered(0, "%d", (ICSR_REGISTER_VALUE & 0x0003F000) >> 12);
Gofs 0:57b729dee92c 365 }
Gofs 0:57b729dee92c 366 else
Gofs 0:57b729dee92c 367 {
Gofs 0:57b729dee92c 368 mdebug_printf_unbuffered(0, "no pending exceptions.");
Gofs 0:57b729dee92c 369 }
Gofs 0:57b729dee92c 370
Gofs 0:57b729dee92c 371 if (ICSR_REGISTER_VALUE & (1 << 11))
Gofs 0:57b729dee92c 372 {
Gofs 0:57b729dee92c 373 mdebug_printf_unbuffered(0, "\r\n\t* There are no preempted active exceptions to execute.");
Gofs 0:57b729dee92c 374 }
Gofs 0:57b729dee92c 375 else
Gofs 0:57b729dee92c 376 {
Gofs 0:57b729dee92c 377 mdebug_printf_unbuffered(0, "\r\n\t* There are preempted active exceptions to execute.");
Gofs 0:57b729dee92c 378 }
Gofs 0:57b729dee92c 379
Gofs 0:57b729dee92c 380 mdebug_printf_unbuffered(0, "\r\n====================");
Gofs 0:57b729dee92c 381 mdebug_printf_unbuffered(0, "\r\nVTOR:\t\t\t0x%08X\tVector Table Offset Register", VTOR_REGISTER_VALUE);
Gofs 0:57b729dee92c 382
Gofs 0:57b729dee92c 383 mdebug_printf_unbuffered(0, "\r\n====================");
Gofs 0:57b729dee92c 384 mdebug_printf_unbuffered(0, "\r\nAIRCR:\t\t\t0x%08X\tApplication Interrupt and Reset Control Register", AIRCR_REGISTER_VALUE);
Gofs 0:57b729dee92c 385
Gofs 0:57b729dee92c 386 if (AIRCR_REGISTER_VALUE & (1 << 15))
Gofs 0:57b729dee92c 387 {
Gofs 0:57b729dee92c 388 mdebug_printf_unbuffered(0, "\r\n\t* Endianness: big-endian.");
Gofs 0:57b729dee92c 389 }
Gofs 0:57b729dee92c 390 else
Gofs 0:57b729dee92c 391 {
Gofs 0:57b729dee92c 392 mdebug_printf_unbuffered(0, "\r\n\t* Endianness: little-endian.");
Gofs 0:57b729dee92c 393 }
Gofs 0:57b729dee92c 394
Gofs 0:57b729dee92c 395 mdebug_printf_unbuffered(0, "\r\n====================");
Gofs 0:57b729dee92c 396 mdebug_printf_unbuffered(0, "\r\nSCR:\t\t\t0x%08X\tSystem Control Register", SCR_REGISTER_VALUE);
Gofs 0:57b729dee92c 397
Gofs 0:57b729dee92c 398 if (SCR_REGISTER_VALUE & (1 << 1))
Gofs 0:57b729dee92c 399 {
Gofs 0:57b729dee92c 400 mdebug_printf_unbuffered(0, "\r\n\t* Sleep-on-exit is ON.");
Gofs 0:57b729dee92c 401 }
Gofs 0:57b729dee92c 402 else
Gofs 0:57b729dee92c 403 {
Gofs 0:57b729dee92c 404 mdebug_printf_unbuffered(0, "\r\n\t* Sleep-on-exit is OFF.");
Gofs 0:57b729dee92c 405 }
Gofs 0:57b729dee92c 406
Gofs 0:57b729dee92c 407 if (SCR_REGISTER_VALUE & (1 << 2))
Gofs 0:57b729dee92c 408 {
Gofs 0:57b729dee92c 409 mdebug_printf_unbuffered(0, "\r\n\t* Processor uses deep sleep mode.");
Gofs 0:57b729dee92c 410 }
Gofs 0:57b729dee92c 411 else
Gofs 0:57b729dee92c 412 {
Gofs 0:57b729dee92c 413 mdebug_printf_unbuffered(0, "\r\n\t* Processor uses sleep mode.");
Gofs 0:57b729dee92c 414 }
Gofs 0:57b729dee92c 415
Gofs 0:57b729dee92c 416 if (SCR_REGISTER_VALUE & (1 << 4))
Gofs 0:57b729dee92c 417 {
Gofs 0:57b729dee92c 418 mdebug_printf_unbuffered(0, "\r\n\t* Disabled interrupts can wake up the processor.");
Gofs 0:57b729dee92c 419 }
Gofs 0:57b729dee92c 420 else
Gofs 0:57b729dee92c 421 {
Gofs 0:57b729dee92c 422 mdebug_printf_unbuffered(0, ",\r\n\t* Disabled interrupts cannot wake up the processor.");
Gofs 0:57b729dee92c 423 }
Gofs 0:57b729dee92c 424
Gofs 0:57b729dee92c 425 mdebug_printf_unbuffered(0, "\r\n====================");
Gofs 0:57b729dee92c 426 mdebug_printf_unbuffered(0, "\r\nCCR:\t\t\t0x%08X\tConfiguration and Control Register", CCR_REGISTER_VALUE);
Gofs 0:57b729dee92c 427
Gofs 0:57b729dee92c 428 if (CCR_REGISTER_VALUE & (1 << 0))
Gofs 0:57b729dee92c 429 {
Gofs 0:57b729dee92c 430 mdebug_printf_unbuffered(0, "\r\n\t* EXC_RETURN active.");
Gofs 0:57b729dee92c 431 }
Gofs 0:57b729dee92c 432 else
Gofs 0:57b729dee92c 433 {
Gofs 0:57b729dee92c 434 mdebug_printf_unbuffered(0, "\r\n\t* EXC_RETURN inactive.");
Gofs 0:57b729dee92c 435 }
Gofs 0:57b729dee92c 436
Gofs 0:57b729dee92c 437 if (CCR_REGISTER_VALUE & (1 << 1))
Gofs 0:57b729dee92c 438 {
Gofs 0:57b729dee92c 439 mdebug_printf_unbuffered(0, "\r\n\t* Access to STIR in thread mode is enabled.");
Gofs 0:57b729dee92c 440 }
Gofs 0:57b729dee92c 441 else
Gofs 0:57b729dee92c 442 {
Gofs 0:57b729dee92c 443 mdebug_printf_unbuffered(0, "\r\n\t* Access to STIR in thread mode is disabled.");
Gofs 0:57b729dee92c 444 }
Gofs 0:57b729dee92c 445
Gofs 0:57b729dee92c 446 if (CCR_REGISTER_VALUE & (1 << 3))
Gofs 0:57b729dee92c 447 {
Gofs 0:57b729dee92c 448 mdebug_printf_unbuffered(0, "\r\n\t* Unaligned access generates UsageFault.");
Gofs 0:57b729dee92c 449 }
Gofs 0:57b729dee92c 450 else
Gofs 0:57b729dee92c 451 {
Gofs 0:57b729dee92c 452 mdebug_printf_unbuffered(0, "\r\n\t* Unaligned access doesn't generate UsageFault.");
Gofs 0:57b729dee92c 453 }
Gofs 0:57b729dee92c 454
Gofs 0:57b729dee92c 455 if (CCR_REGISTER_VALUE & (1 << 4))
Gofs 0:57b729dee92c 456 {
Gofs 0:57b729dee92c 457 mdebug_printf_unbuffered(0, "\r\n\t* Div by 0 generates faulting or halting.");
Gofs 0:57b729dee92c 458 }
Gofs 0:57b729dee92c 459 else
Gofs 0:57b729dee92c 460 {
Gofs 0:57b729dee92c 461 mdebug_printf_unbuffered(0, "\r\n\t* Div by 0 returns 0.");
Gofs 0:57b729dee92c 462 }
Gofs 0:57b729dee92c 463
Gofs 0:57b729dee92c 464 if (CCR_REGISTER_VALUE & (1 << 8))
Gofs 0:57b729dee92c 465 {
Gofs 0:57b729dee92c 466 mdebug_printf_unbuffered(0, "\r\n\t* Priority -1 and -2 handlers ignore data bus faults caused by load and store instructions.");
Gofs 0:57b729dee92c 467 }
Gofs 0:57b729dee92c 468 else
Gofs 0:57b729dee92c 469 {
Gofs 0:57b729dee92c 470 mdebug_printf_unbuffered(0, "\r\n\t* Data bus faults caused by load and store instructions cause a lock-up.");
Gofs 0:57b729dee92c 471 }
Gofs 0:57b729dee92c 472
Gofs 0:57b729dee92c 473 if (CCR_REGISTER_VALUE & (1 << 9))
Gofs 0:57b729dee92c 474 {
Gofs 0:57b729dee92c 475 mdebug_printf_unbuffered(0, "\r\n\t* Stack alignment on exception entry is 8-byte aligned.");
Gofs 0:57b729dee92c 476 }
Gofs 0:57b729dee92c 477 else
Gofs 0:57b729dee92c 478 {
Gofs 0:57b729dee92c 479 mdebug_printf_unbuffered(0, "\r\n\t* Stack alignment on exception entry is 4-byte aligned.");
Gofs 0:57b729dee92c 480 }
Gofs 0:57b729dee92c 481
Gofs 0:57b729dee92c 482 mdebug_printf_unbuffered(0, "\r\n====================");
Gofs 0:57b729dee92c 483 mdebug_printf_unbuffered(0, "\r\nSHPR1:\t\t\t0x%08X\tSystem Handler Priority Register 1", SHPR1_REGISTER_VALUE);
Gofs 0:57b729dee92c 484 mdebug_printf_unbuffered(0, "\r\n\t* MemManage pio = %d.\r\n\t* BusFault prio = %d.\r\n\t* UsageFault prio = %d.",
Gofs 0:57b729dee92c 485 SHPR1_REGISTER_VALUE & 0x000000FF,
Gofs 0:57b729dee92c 486 (SHPR1_REGISTER_VALUE & 0x0000FF00) >> 8,
Gofs 0:57b729dee92c 487 (SHPR1_REGISTER_VALUE & 0x00FF0000) >> 16);
Gofs 0:57b729dee92c 488
Gofs 0:57b729dee92c 489 mdebug_printf_unbuffered(0, "\r\n====================");
Gofs 0:57b729dee92c 490 mdebug_printf_unbuffered(0, "\r\nSHPR2:\t\t\t0x%08X\tSystem Handler Priority Register 2", SHPR2_REGISTER_VALUE);
Gofs 0:57b729dee92c 491 mdebug_printf_unbuffered(0, "\r\n\t* SVCall prio = %d.", (SHPR2_REGISTER_VALUE & 0xFF000000) >> 24);
Gofs 0:57b729dee92c 492
Gofs 0:57b729dee92c 493 mdebug_printf_unbuffered(0, "\r\n====================");
Gofs 0:57b729dee92c 494 mdebug_printf_unbuffered(0, "\r\nSHPR3:\t\t\t0x%08X\tSystem Handler Priority Register 3", SHPR3_REGISTER_VALUE);
Gofs 0:57b729dee92c 495 mdebug_printf_unbuffered(0, "\r\n\t* PendSV prio = %d.\r\n\t* SysTick prio = %d.", (SHPR3_REGISTER_VALUE & 0x00FF0000) >> 16, (SHPR3_REGISTER_VALUE & 0xFF000000) >> 24);
Gofs 0:57b729dee92c 496
Gofs 0:57b729dee92c 497 mdebug_printf_unbuffered(0, "\r\n====================");
Gofs 0:57b729dee92c 498 mdebug_printf_unbuffered(0, "\r\nSHCRS:\t\t\t0x%08X\tSystem Handler Control and State Register", SHCRS_REGISTER_VALUE);
Gofs 0:57b729dee92c 499
Gofs 0:57b729dee92c 500 if (SHCRS_REGISTER_VALUE & 0x00000D8B)
Gofs 0:57b729dee92c 501 {
Gofs 0:57b729dee92c 502 mdebug_printf_unbuffered(0, "\r\n\t* Active exceptions:");
Gofs 0:57b729dee92c 503
Gofs 0:57b729dee92c 504 if (SHCRS_REGISTER_VALUE & (1 << 0))
Gofs 0:57b729dee92c 505 {
Gofs 0:57b729dee92c 506 mdebug_printf_unbuffered(0, "\r\n\t\t* MemManage.");
Gofs 0:57b729dee92c 507 }
Gofs 0:57b729dee92c 508
Gofs 0:57b729dee92c 509 if (SHCRS_REGISTER_VALUE & (1 << 1))
Gofs 0:57b729dee92c 510 {
Gofs 0:57b729dee92c 511 mdebug_printf_unbuffered(0, "\r\n\t\t* BusFault.");
Gofs 0:57b729dee92c 512 }
Gofs 0:57b729dee92c 513
Gofs 0:57b729dee92c 514 if (SHCRS_REGISTER_VALUE & (1 << 3))
Gofs 0:57b729dee92c 515 {
Gofs 0:57b729dee92c 516 mdebug_printf_unbuffered(0, "\r\n\t\t* UsageFault.");
Gofs 0:57b729dee92c 517 }
Gofs 0:57b729dee92c 518
Gofs 0:57b729dee92c 519 if (SHCRS_REGISTER_VALUE & (1 << 7))
Gofs 0:57b729dee92c 520 {
Gofs 0:57b729dee92c 521 mdebug_printf_unbuffered(0, "\r\n\t\t* SVCall.");
Gofs 0:57b729dee92c 522 }
Gofs 0:57b729dee92c 523
Gofs 0:57b729dee92c 524 if (SHCRS_REGISTER_VALUE & (1 << 10))
Gofs 0:57b729dee92c 525 {
Gofs 0:57b729dee92c 526 mdebug_printf_unbuffered(0, "\r\n\t\t* PendSV.");
Gofs 0:57b729dee92c 527 }
Gofs 0:57b729dee92c 528
Gofs 0:57b729dee92c 529 if (SHCRS_REGISTER_VALUE & (1 << 11))
Gofs 0:57b729dee92c 530 {
Gofs 0:57b729dee92c 531 mdebug_printf_unbuffered(0, "\r\n\t\t* SysTick.");
Gofs 0:57b729dee92c 532 }
Gofs 0:57b729dee92c 533 }
Gofs 0:57b729dee92c 534
Gofs 0:57b729dee92c 535 if (SHCRS_REGISTER_VALUE & 0x0000F000)
Gofs 0:57b729dee92c 536 {
Gofs 0:57b729dee92c 537 mdebug_printf_unbuffered(0, "\r\n\t* Pending exceptions:");
Gofs 0:57b729dee92c 538
Gofs 0:57b729dee92c 539 if (SHCRS_REGISTER_VALUE & (1 << 12))
Gofs 0:57b729dee92c 540 {
Gofs 0:57b729dee92c 541 mdebug_printf_unbuffered(0, "\r\n\t\t* UsageFault.");
Gofs 0:57b729dee92c 542 }
Gofs 0:57b729dee92c 543
Gofs 0:57b729dee92c 544 if (SHCRS_REGISTER_VALUE & (1 << 13))
Gofs 0:57b729dee92c 545 {
Gofs 0:57b729dee92c 546 mdebug_printf_unbuffered(0, "\r\n\t\t* MemManage.");
Gofs 0:57b729dee92c 547 }
Gofs 0:57b729dee92c 548
Gofs 0:57b729dee92c 549 if (SHCRS_REGISTER_VALUE & (1 << 14))
Gofs 0:57b729dee92c 550 {
Gofs 0:57b729dee92c 551 mdebug_printf_unbuffered(0, "\r\n\t\t* BusFault.");
Gofs 0:57b729dee92c 552 }
Gofs 0:57b729dee92c 553
Gofs 0:57b729dee92c 554 if (SHCRS_REGISTER_VALUE & (1 << 15))
Gofs 0:57b729dee92c 555 {
Gofs 0:57b729dee92c 556 mdebug_printf_unbuffered(0, "\r\n\t\t* SVCall.");
Gofs 0:57b729dee92c 557 }
Gofs 0:57b729dee92c 558 }
Gofs 0:57b729dee92c 559
Gofs 0:57b729dee92c 560 if (SHCRS_REGISTER_VALUE & 0x00070000)
Gofs 0:57b729dee92c 561 {
Gofs 0:57b729dee92c 562 mdebug_printf_unbuffered(0, "\r\n\t* Enabled exceptions: ");
Gofs 0:57b729dee92c 563
Gofs 0:57b729dee92c 564 if (SHCRS_REGISTER_VALUE & (1 << 16))
Gofs 0:57b729dee92c 565 {
Gofs 0:57b729dee92c 566 mdebug_printf_unbuffered(0, "\r\n\t\t* MemManage.");
Gofs 0:57b729dee92c 567 }
Gofs 0:57b729dee92c 568
Gofs 0:57b729dee92c 569 if (SHCRS_REGISTER_VALUE & (1 << 17))
Gofs 0:57b729dee92c 570 {
Gofs 0:57b729dee92c 571 mdebug_printf_unbuffered(0, "\r\n\t\t* BusFault.");
Gofs 0:57b729dee92c 572 }
Gofs 0:57b729dee92c 573
Gofs 0:57b729dee92c 574 if (SHCRS_REGISTER_VALUE & (1 << 18))
Gofs 0:57b729dee92c 575 {
Gofs 0:57b729dee92c 576 mdebug_printf_unbuffered(0, "\r\n\t\t* UsageFault.");
Gofs 0:57b729dee92c 577 }
Gofs 0:57b729dee92c 578 }
Gofs 0:57b729dee92c 579
Gofs 0:57b729dee92c 580 mdebug_printf_unbuffered(0, "\r\n====================");
Gofs 0:57b729dee92c 581 mdebug_printf_unbuffered(0, "\r\nCFSR:\t\t\t0x%08X\tConfigurable Fault Status Register", CFSR_REGISTER_VALUE);
Gofs 0:57b729dee92c 582
Gofs 0:57b729dee92c 583 if (CFSR_REGISTER_VALUE & (1 << 0))
Gofs 0:57b729dee92c 584 {
Gofs 0:57b729dee92c 585 mdebug_printf_unbuffered(0, "\r\n\t* The processor attempted an instruction fetch from a location that does not permit execution.");
Gofs 0:57b729dee92c 586 }
Gofs 0:57b729dee92c 587
Gofs 0:57b729dee92c 588 if (CFSR_REGISTER_VALUE & (1 << 1))
Gofs 0:57b729dee92c 589 {
Gofs 0:57b729dee92c 590 mdebug_printf_unbuffered(0, "\r\n\t* The processor attempted a load or store at a location that does not permit the operation.");
Gofs 0:57b729dee92c 591 }
Gofs 0:57b729dee92c 592
Gofs 0:57b729dee92c 593 if (CFSR_REGISTER_VALUE & (1 << 3))
Gofs 0:57b729dee92c 594 {
Gofs 0:57b729dee92c 595 mdebug_printf_unbuffered(0, "\r\n\t* Unstack for an exception return has caused one or more access violations.");
Gofs 0:57b729dee92c 596 }
Gofs 0:57b729dee92c 597
Gofs 0:57b729dee92c 598 if (CFSR_REGISTER_VALUE & (1 << 4))
Gofs 0:57b729dee92c 599 {
Gofs 0:57b729dee92c 600 mdebug_printf_unbuffered(0, "\r\n\t* Stacking for an exception entry has caused one or more access violations.");
Gofs 0:57b729dee92c 601 }
Gofs 0:57b729dee92c 602
Gofs 0:57b729dee92c 603 if (CFSR_REGISTER_VALUE & (1 << 7))
Gofs 0:57b729dee92c 604 {
Gofs 0:57b729dee92c 605 mdebug_printf_unbuffered(0, "\r\n\t* MMAR holds a valid fault address.");
Gofs 0:57b729dee92c 606 }
Gofs 0:57b729dee92c 607 else
Gofs 0:57b729dee92c 608 {
Gofs 0:57b729dee92c 609 mdebug_printf_unbuffered(0, "\r\n\t* MMAR doesn't hold a valid fault address.");
Gofs 0:57b729dee92c 610 }
Gofs 0:57b729dee92c 611
Gofs 0:57b729dee92c 612 if (CFSR_REGISTER_VALUE & (1 << 8))
Gofs 0:57b729dee92c 613 {
Gofs 0:57b729dee92c 614 mdebug_printf_unbuffered(0, "\r\n\t* Instruction bus error.");
Gofs 0:57b729dee92c 615 }
Gofs 0:57b729dee92c 616
Gofs 0:57b729dee92c 617 if (CFSR_REGISTER_VALUE & (1 << 9))
Gofs 0:57b729dee92c 618 {
Gofs 0:57b729dee92c 619 mdebug_printf_unbuffered(0, "\r\n\t* A data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault.");
Gofs 0:57b729dee92c 620 }
Gofs 0:57b729dee92c 621
Gofs 0:57b729dee92c 622 if (CFSR_REGISTER_VALUE & (1 << 10))
Gofs 0:57b729dee92c 623 {
Gofs 0:57b729dee92c 624 mdebug_printf_unbuffered(0, "\r\n\t* A data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error.");
Gofs 0:57b729dee92c 625 }
Gofs 0:57b729dee92c 626
Gofs 0:57b729dee92c 627 if (CFSR_REGISTER_VALUE & (1 << 11))
Gofs 0:57b729dee92c 628 {
Gofs 0:57b729dee92c 629 mdebug_printf_unbuffered(0, "\r\n\t* Unstack for an exception return has caused one or more BusFaults.");
Gofs 0:57b729dee92c 630 }
Gofs 0:57b729dee92c 631
Gofs 0:57b729dee92c 632 if (CFSR_REGISTER_VALUE & (1 << 12))
Gofs 0:57b729dee92c 633 {
Gofs 0:57b729dee92c 634 mdebug_printf_unbuffered(0, "\r\n\t* Stacking for an exception entry has caused one or more BusFaults.");
Gofs 0:57b729dee92c 635 }
Gofs 0:57b729dee92c 636
Gofs 0:57b729dee92c 637 if (CFSR_REGISTER_VALUE & (1 << 15))
Gofs 0:57b729dee92c 638 {
Gofs 0:57b729dee92c 639 mdebug_printf_unbuffered(0, "\r\n\t* BFAR holds a valid fault address.");
Gofs 0:57b729dee92c 640 }
Gofs 0:57b729dee92c 641 else
Gofs 0:57b729dee92c 642 {
Gofs 0:57b729dee92c 643 mdebug_printf_unbuffered(0, "\r\n\t* Value in BFAR is not a valid fault address.");
Gofs 0:57b729dee92c 644 }
Gofs 0:57b729dee92c 645
Gofs 0:57b729dee92c 646 if (CFSR_REGISTER_VALUE & (1 << 16))
Gofs 0:57b729dee92c 647 {
Gofs 0:57b729dee92c 648 mdebug_printf_unbuffered(0, "\r\n\t* The processor has attempted to execute an undefined instruction.");
Gofs 0:57b729dee92c 649 }
Gofs 0:57b729dee92c 650
Gofs 0:57b729dee92c 651 if (CFSR_REGISTER_VALUE & (1 << 17))
Gofs 0:57b729dee92c 652 {
Gofs 0:57b729dee92c 653 mdebug_printf_unbuffered(0, "\r\n\t* The processor has attempted to execute an instruction that makes illegal use of the EPSR.");
Gofs 0:57b729dee92c 654 }
Gofs 0:57b729dee92c 655
Gofs 0:57b729dee92c 656 if (CFSR_REGISTER_VALUE & (1 << 18))
Gofs 0:57b729dee92c 657 {
Gofs 0:57b729dee92c 658 mdebug_printf_unbuffered(0, "\r\n\t* The processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an invalid context, or an invalid EXC_RETURN value.");
Gofs 0:57b729dee92c 659 }
Gofs 0:57b729dee92c 660
Gofs 0:57b729dee92c 661 if (CFSR_REGISTER_VALUE & (1 << 19))
Gofs 0:57b729dee92c 662 {
Gofs 0:57b729dee92c 663 mdebug_printf_unbuffered(0, "\r\n\t* The processor has attempted to access a coprocessor.");
Gofs 0:57b729dee92c 664 }
Gofs 0:57b729dee92c 665
Gofs 0:57b729dee92c 666 if (CFSR_REGISTER_VALUE & (1 << 24))
Gofs 0:57b729dee92c 667 {
Gofs 0:57b729dee92c 668 mdebug_printf_unbuffered(0, "\r\n\t* The processor has made an unaligned memory access.");
Gofs 0:57b729dee92c 669 }
Gofs 0:57b729dee92c 670
Gofs 0:57b729dee92c 671 if (CFSR_REGISTER_VALUE & (1 << 25))
Gofs 0:57b729dee92c 672 {
Gofs 0:57b729dee92c 673 mdebug_printf_unbuffered(0, "\r\n\t* The processor has executed an SDIV or UDIV instruction with a divisor of 0.");
Gofs 0:57b729dee92c 674 }
Gofs 0:57b729dee92c 675
Gofs 0:57b729dee92c 676 mdebug_printf_unbuffered(0, "\r\n====================");
Gofs 0:57b729dee92c 677 mdebug_printf_unbuffered(0, "\r\nHFSR:\t\t\t0x%08X\tHardFault Status Register", HFSR_REGISTER_VALUE);
Gofs 0:57b729dee92c 678
Gofs 0:57b729dee92c 679 if (HFSR_REGISTER_VALUE & (1 << 1))
Gofs 0:57b729dee92c 680 {
Gofs 0:57b729dee92c 681 mdebug_printf_unbuffered(0, "\r\n\t* BusFault on vector table read.");
Gofs 0:57b729dee92c 682 }
Gofs 0:57b729dee92c 683
Gofs 0:57b729dee92c 684 if (HFSR_REGISTER_VALUE & (1 << 30))
Gofs 0:57b729dee92c 685 {
Gofs 0:57b729dee92c 686 mdebug_printf_unbuffered(0, "\r\n\t* Forced HardFault.");
Gofs 0:57b729dee92c 687 }
Gofs 0:57b729dee92c 688
Gofs 0:57b729dee92c 689 mdebug_printf_unbuffered(0, "\r\n====================");
Gofs 0:57b729dee92c 690 mdebug_printf_unbuffered(0, "\r\nMMAR:\t\t\t0x%08X\tMemManage Fault Address Register", MMAR_REGISTER_VALUE);
Gofs 0:57b729dee92c 691
Gofs 0:57b729dee92c 692 mdebug_printf_unbuffered(0, "\r\n====================");
Gofs 0:57b729dee92c 693 mdebug_printf_unbuffered(0, "\r\nBFAR:\t\t\t0x%08X\tBusFault Address Register", BFAR_REGISTER_VALUE);
Gofs 0:57b729dee92c 694
Gofs 0:57b729dee92c 695 mdebug_printf_unbuffered(0, "\r\n====================");
Gofs 0:57b729dee92c 696 mdebug_printf_unbuffered(0, "\r\nAFSR:\t\t\t0x%08X\tAuxiliary Fault Status Register", AFSR_REGISTER_VALUE);
Gofs 0:57b729dee92c 697
Gofs 0:57b729dee92c 698 mdebug_printf_unbuffered(0, "\r\n====================");
Gofs 0:57b729dee92c 699 mdebug_printf_unbuffered(0, "\r\nPRIMASK:\t\t0x%08X", PRIMASK & 0x00000001);
Gofs 0:57b729dee92c 700 mdebug_printf_unbuffered(0, "\r\nFAULTMASK:\t\t0x%08X", FAULTMASK & 0x00000001);
Gofs 0:57b729dee92c 701 mdebug_printf_unbuffered(0, "\r\nBASEPRI:\t\t0x%08X", BASEPRI & 0x000000FF);
Gofs 0:57b729dee92c 702
Gofs 0:57b729dee92c 703 mdebug_printf_unbuffered(0, "\r\n====================");
Gofs 0:57b729dee92c 704 mdebug_printf_unbuffered(0, "\r\nMMU Type Register:\t\t0x%08X", MMU_TYPE_REGISTER_VALUE);
Gofs 0:57b729dee92c 705 mdebug_printf_unbuffered(0, "\r\nMMU Control Register:\t\t0x%08X", MMU_CONTROL_REGISTER_VALUE);
Gofs 0:57b729dee92c 706 mdebug_printf_unbuffered(0, "\r\nMMU Region Base Address Register:\t\t0x%08X", MMU_RBASR_REGISTER_VALUE);
Gofs 0:57b729dee92c 707 mdebug_printf_unbuffered(0, "\r\n\t* Number of regions supported by MMU: %d.", (MMU_TYPE_REGISTER_VALUE & 0x0000FF00) >> 8);
Gofs 0:57b729dee92c 708 mdebug_printf_unbuffered(0, "\r\n\t* MPU is %s.", (MMU_CONTROL_REGISTER_VALUE & (1 << 0)) == 0 ? "disabled" : "enabled");
Gofs 0:57b729dee92c 709 mdebug_printf_unbuffered(0, "\r\n\t* MPU is %s during the hard fault and NMI handlers.", (MMU_CONTROL_REGISTER_VALUE & (1 << 1)) == 0 ? "disabled" : "enabled");
Gofs 0:57b729dee92c 710 mdebug_printf_unbuffered(0, "\r\n\t* Privileged Default memory map is %s.", (MMU_CONTROL_REGISTER_VALUE & (1 << 2)) == 0 ? "disabled" : "enabled");
Gofs 0:57b729dee92c 711
Gofs 0:57b729dee92c 712
Gofs 0:57b729dee92c 713 mdebug_printf_unbuffered(0, "\r\n====================");
Gofs 0:57b729dee92c 714
Gofs 0:57b729dee92c 715 #if defined(__ARMCC_VERSION)
Gofs 0:57b729dee92c 716 mdebug_printf_unbuffered(0, "\r\n__ARMCC_VERSION\t\t%u", __ARMCC_VERSION);
Gofs 0:57b729dee92c 717 #endif
Gofs 0:57b729dee92c 718
Gofs 0:57b729dee92c 719 #if defined(__ARMCLIB_VERSION)
Gofs 0:57b729dee92c 720 mdebug_printf_unbuffered(0, "\r\n__ARMCLIB_VERSION\t%u", __ARMCLIB_VERSION);
Gofs 0:57b729dee92c 721 #endif
Gofs 0:57b729dee92c 722 }
Gofs 0:57b729dee92c 723