Gonzalo Matarrubia / Mbed LPC1549 mod

This repo contains the libraries of Mbed for LPC1549 with following changes: - IAP commands. - EEPROM write and read. - UART write and read (public) - CAN can_s -> LPC_C_CAN0_Type *can

mbed/TARGET_LPC1549/core_cmInstr.h@0:820a69dfd200, 2015-04-14 (annotated)

Committer:
gmatarrubia
Date:
Tue Apr 14 15:00:13 2015 +0200
Revision:
0:820a69dfd200
Initial repo. IAP commands, EEPROM write/read, UART write/read, CAN

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gmatarrubia 0:820a69dfd200 1 /**************************************************************************//**
gmatarrubia 0:820a69dfd200 2 * @file core_cmInstr.h
gmatarrubia 0:820a69dfd200 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
gmatarrubia 0:820a69dfd200 4 * @version V3.20
gmatarrubia 0:820a69dfd200 5 * @date 05. March 2013
gmatarrubia 0:820a69dfd200 6 *
gmatarrubia 0:820a69dfd200 7 * @note
gmatarrubia 0:820a69dfd200 8 *
gmatarrubia 0:820a69dfd200 9 ******************************************************************************/
gmatarrubia 0:820a69dfd200 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
gmatarrubia 0:820a69dfd200 11
gmatarrubia 0:820a69dfd200 12 All rights reserved.
gmatarrubia 0:820a69dfd200 13 Redistribution and use in source and binary forms, with or without
gmatarrubia 0:820a69dfd200 14 modification, are permitted provided that the following conditions are met:
gmatarrubia 0:820a69dfd200 15 - Redistributions of source code must retain the above copyright
gmatarrubia 0:820a69dfd200 16 notice, this list of conditions and the following disclaimer.
gmatarrubia 0:820a69dfd200 17 - Redistributions in binary form must reproduce the above copyright
gmatarrubia 0:820a69dfd200 18 notice, this list of conditions and the following disclaimer in the
gmatarrubia 0:820a69dfd200 19 documentation and/or other materials provided with the distribution.
gmatarrubia 0:820a69dfd200 20 - Neither the name of ARM nor the names of its contributors may be used
gmatarrubia 0:820a69dfd200 21 to endorse or promote products derived from this software without
gmatarrubia 0:820a69dfd200 22 specific prior written permission.
gmatarrubia 0:820a69dfd200 23 *
gmatarrubia 0:820a69dfd200 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
gmatarrubia 0:820a69dfd200 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
gmatarrubia 0:820a69dfd200 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
gmatarrubia 0:820a69dfd200 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
gmatarrubia 0:820a69dfd200 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
gmatarrubia 0:820a69dfd200 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
gmatarrubia 0:820a69dfd200 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
gmatarrubia 0:820a69dfd200 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
gmatarrubia 0:820a69dfd200 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
gmatarrubia 0:820a69dfd200 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
gmatarrubia 0:820a69dfd200 34 POSSIBILITY OF SUCH DAMAGE.
gmatarrubia 0:820a69dfd200 35 ---------------------------------------------------------------------------*/
gmatarrubia 0:820a69dfd200 36
gmatarrubia 0:820a69dfd200 37
gmatarrubia 0:820a69dfd200 38 #ifndef __CORE_CMINSTR_H
gmatarrubia 0:820a69dfd200 39 #define __CORE_CMINSTR_H
gmatarrubia 0:820a69dfd200 40
gmatarrubia 0:820a69dfd200 41
gmatarrubia 0:820a69dfd200 42 /* ########################## Core Instruction Access ######################### */
gmatarrubia 0:820a69dfd200 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
gmatarrubia 0:820a69dfd200 44 Access to dedicated instructions
gmatarrubia 0:820a69dfd200 45 @{
gmatarrubia 0:820a69dfd200 46 */
gmatarrubia 0:820a69dfd200 47
gmatarrubia 0:820a69dfd200 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
gmatarrubia 0:820a69dfd200 49 /* ARM armcc specific functions */
gmatarrubia 0:820a69dfd200 50
gmatarrubia 0:820a69dfd200 51 #if (__ARMCC_VERSION < 400677)
gmatarrubia 0:820a69dfd200 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
gmatarrubia 0:820a69dfd200 53 #endif
gmatarrubia 0:820a69dfd200 54
gmatarrubia 0:820a69dfd200 55
gmatarrubia 0:820a69dfd200 56 /** \brief No Operation
gmatarrubia 0:820a69dfd200 57
gmatarrubia 0:820a69dfd200 58 No Operation does nothing. This instruction can be used for code alignment purposes.
gmatarrubia 0:820a69dfd200 59 */
gmatarrubia 0:820a69dfd200 60 #define __NOP __nop
gmatarrubia 0:820a69dfd200 61
gmatarrubia 0:820a69dfd200 62
gmatarrubia 0:820a69dfd200 63 /** \brief Wait For Interrupt
gmatarrubia 0:820a69dfd200 64
gmatarrubia 0:820a69dfd200 65 Wait For Interrupt is a hint instruction that suspends execution
gmatarrubia 0:820a69dfd200 66 until one of a number of events occurs.
gmatarrubia 0:820a69dfd200 67 */
gmatarrubia 0:820a69dfd200 68 #define __WFI __wfi
gmatarrubia 0:820a69dfd200 69
gmatarrubia 0:820a69dfd200 70
gmatarrubia 0:820a69dfd200 71 /** \brief Wait For Event
gmatarrubia 0:820a69dfd200 72
gmatarrubia 0:820a69dfd200 73 Wait For Event is a hint instruction that permits the processor to enter
gmatarrubia 0:820a69dfd200 74 a low-power state until one of a number of events occurs.
gmatarrubia 0:820a69dfd200 75 */
gmatarrubia 0:820a69dfd200 76 #define __WFE __wfe
gmatarrubia 0:820a69dfd200 77
gmatarrubia 0:820a69dfd200 78
gmatarrubia 0:820a69dfd200 79 /** \brief Send Event
gmatarrubia 0:820a69dfd200 80
gmatarrubia 0:820a69dfd200 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
gmatarrubia 0:820a69dfd200 82 */
gmatarrubia 0:820a69dfd200 83 #define __SEV __sev
gmatarrubia 0:820a69dfd200 84
gmatarrubia 0:820a69dfd200 85
gmatarrubia 0:820a69dfd200 86 /** \brief Instruction Synchronization Barrier
gmatarrubia 0:820a69dfd200 87
gmatarrubia 0:820a69dfd200 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
gmatarrubia 0:820a69dfd200 89 so that all instructions following the ISB are fetched from cache or
gmatarrubia 0:820a69dfd200 90 memory, after the instruction has been completed.
gmatarrubia 0:820a69dfd200 91 */
gmatarrubia 0:820a69dfd200 92 #define __ISB() __isb(0xF)
gmatarrubia 0:820a69dfd200 93
gmatarrubia 0:820a69dfd200 94
gmatarrubia 0:820a69dfd200 95 /** \brief Data Synchronization Barrier
gmatarrubia 0:820a69dfd200 96
gmatarrubia 0:820a69dfd200 97 This function acts as a special kind of Data Memory Barrier.
gmatarrubia 0:820a69dfd200 98 It completes when all explicit memory accesses before this instruction complete.
gmatarrubia 0:820a69dfd200 99 */
gmatarrubia 0:820a69dfd200 100 #define __DSB() __dsb(0xF)
gmatarrubia 0:820a69dfd200 101
gmatarrubia 0:820a69dfd200 102
gmatarrubia 0:820a69dfd200 103 /** \brief Data Memory Barrier
gmatarrubia 0:820a69dfd200 104
gmatarrubia 0:820a69dfd200 105 This function ensures the apparent order of the explicit memory operations before
gmatarrubia 0:820a69dfd200 106 and after the instruction, without ensuring their completion.
gmatarrubia 0:820a69dfd200 107 */
gmatarrubia 0:820a69dfd200 108 #define __DMB() __dmb(0xF)
gmatarrubia 0:820a69dfd200 109
gmatarrubia 0:820a69dfd200 110
gmatarrubia 0:820a69dfd200 111 /** \brief Reverse byte order (32 bit)
gmatarrubia 0:820a69dfd200 112
gmatarrubia 0:820a69dfd200 113 This function reverses the byte order in integer value.
gmatarrubia 0:820a69dfd200 114
gmatarrubia 0:820a69dfd200 115 \param [in] value Value to reverse
gmatarrubia 0:820a69dfd200 116 \return Reversed value
gmatarrubia 0:820a69dfd200 117 */
gmatarrubia 0:820a69dfd200 118 #define __REV __rev
gmatarrubia 0:820a69dfd200 119
gmatarrubia 0:820a69dfd200 120
gmatarrubia 0:820a69dfd200 121 /** \brief Reverse byte order (16 bit)
gmatarrubia 0:820a69dfd200 122
gmatarrubia 0:820a69dfd200 123 This function reverses the byte order in two unsigned short values.
gmatarrubia 0:820a69dfd200 124
gmatarrubia 0:820a69dfd200 125 \param [in] value Value to reverse
gmatarrubia 0:820a69dfd200 126 \return Reversed value
gmatarrubia 0:820a69dfd200 127 */
gmatarrubia 0:820a69dfd200 128 #ifndef __NO_EMBEDDED_ASM
gmatarrubia 0:820a69dfd200 129 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
gmatarrubia 0:820a69dfd200 130 {
gmatarrubia 0:820a69dfd200 131 rev16 r0, r0
gmatarrubia 0:820a69dfd200 132 bx lr
gmatarrubia 0:820a69dfd200 133 }
gmatarrubia 0:820a69dfd200 134 #endif
gmatarrubia 0:820a69dfd200 135
gmatarrubia 0:820a69dfd200 136 /** \brief Reverse byte order in signed short value
gmatarrubia 0:820a69dfd200 137
gmatarrubia 0:820a69dfd200 138 This function reverses the byte order in a signed short value with sign extension to integer.
gmatarrubia 0:820a69dfd200 139
gmatarrubia 0:820a69dfd200 140 \param [in] value Value to reverse
gmatarrubia 0:820a69dfd200 141 \return Reversed value
gmatarrubia 0:820a69dfd200 142 */
gmatarrubia 0:820a69dfd200 143 #ifndef __NO_EMBEDDED_ASM
gmatarrubia 0:820a69dfd200 144 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
gmatarrubia 0:820a69dfd200 145 {
gmatarrubia 0:820a69dfd200 146 revsh r0, r0
gmatarrubia 0:820a69dfd200 147 bx lr
gmatarrubia 0:820a69dfd200 148 }
gmatarrubia 0:820a69dfd200 149 #endif
gmatarrubia 0:820a69dfd200 150
gmatarrubia 0:820a69dfd200 151
gmatarrubia 0:820a69dfd200 152 /** \brief Rotate Right in unsigned value (32 bit)
gmatarrubia 0:820a69dfd200 153
gmatarrubia 0:820a69dfd200 154 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
gmatarrubia 0:820a69dfd200 155
gmatarrubia 0:820a69dfd200 156 \param [in] value Value to rotate
gmatarrubia 0:820a69dfd200 157 \param [in] value Number of Bits to rotate
gmatarrubia 0:820a69dfd200 158 \return Rotated value
gmatarrubia 0:820a69dfd200 159 */
gmatarrubia 0:820a69dfd200 160 #define __ROR __ror
gmatarrubia 0:820a69dfd200 161
gmatarrubia 0:820a69dfd200 162
gmatarrubia 0:820a69dfd200 163 /** \brief Breakpoint
gmatarrubia 0:820a69dfd200 164
gmatarrubia 0:820a69dfd200 165 This function causes the processor to enter Debug state.
gmatarrubia 0:820a69dfd200 166 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
gmatarrubia 0:820a69dfd200 167
gmatarrubia 0:820a69dfd200 168 \param [in] value is ignored by the processor.
gmatarrubia 0:820a69dfd200 169 If required, a debugger can use it to store additional information about the breakpoint.
gmatarrubia 0:820a69dfd200 170 */
gmatarrubia 0:820a69dfd200 171 #define __BKPT(value) __breakpoint(value)
gmatarrubia 0:820a69dfd200 172
gmatarrubia 0:820a69dfd200 173
gmatarrubia 0:820a69dfd200 174 #if (__CORTEX_M >= 0x03)
gmatarrubia 0:820a69dfd200 175
gmatarrubia 0:820a69dfd200 176 /** \brief Reverse bit order of value
gmatarrubia 0:820a69dfd200 177
gmatarrubia 0:820a69dfd200 178 This function reverses the bit order of the given value.
gmatarrubia 0:820a69dfd200 179
gmatarrubia 0:820a69dfd200 180 \param [in] value Value to reverse
gmatarrubia 0:820a69dfd200 181 \return Reversed value
gmatarrubia 0:820a69dfd200 182 */
gmatarrubia 0:820a69dfd200 183 #define __RBIT __rbit
gmatarrubia 0:820a69dfd200 184
gmatarrubia 0:820a69dfd200 185
gmatarrubia 0:820a69dfd200 186 /** \brief LDR Exclusive (8 bit)
gmatarrubia 0:820a69dfd200 187
gmatarrubia 0:820a69dfd200 188 This function performs a exclusive LDR command for 8 bit value.
gmatarrubia 0:820a69dfd200 189
gmatarrubia 0:820a69dfd200 190 \param [in] ptr Pointer to data
gmatarrubia 0:820a69dfd200 191 \return value of type uint8_t at (*ptr)
gmatarrubia 0:820a69dfd200 192 */
gmatarrubia 0:820a69dfd200 193 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
gmatarrubia 0:820a69dfd200 194
gmatarrubia 0:820a69dfd200 195
gmatarrubia 0:820a69dfd200 196 /** \brief LDR Exclusive (16 bit)
gmatarrubia 0:820a69dfd200 197
gmatarrubia 0:820a69dfd200 198 This function performs a exclusive LDR command for 16 bit values.
gmatarrubia 0:820a69dfd200 199
gmatarrubia 0:820a69dfd200 200 \param [in] ptr Pointer to data
gmatarrubia 0:820a69dfd200 201 \return value of type uint16_t at (*ptr)
gmatarrubia 0:820a69dfd200 202 */
gmatarrubia 0:820a69dfd200 203 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
gmatarrubia 0:820a69dfd200 204
gmatarrubia 0:820a69dfd200 205
gmatarrubia 0:820a69dfd200 206 /** \brief LDR Exclusive (32 bit)
gmatarrubia 0:820a69dfd200 207
gmatarrubia 0:820a69dfd200 208 This function performs a exclusive LDR command for 32 bit values.
gmatarrubia 0:820a69dfd200 209
gmatarrubia 0:820a69dfd200 210 \param [in] ptr Pointer to data
gmatarrubia 0:820a69dfd200 211 \return value of type uint32_t at (*ptr)
gmatarrubia 0:820a69dfd200 212 */
gmatarrubia 0:820a69dfd200 213 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
gmatarrubia 0:820a69dfd200 214
gmatarrubia 0:820a69dfd200 215
gmatarrubia 0:820a69dfd200 216 /** \brief STR Exclusive (8 bit)
gmatarrubia 0:820a69dfd200 217
gmatarrubia 0:820a69dfd200 218 This function performs a exclusive STR command for 8 bit values.
gmatarrubia 0:820a69dfd200 219
gmatarrubia 0:820a69dfd200 220 \param [in] value Value to store
gmatarrubia 0:820a69dfd200 221 \param [in] ptr Pointer to location
gmatarrubia 0:820a69dfd200 222 \return 0 Function succeeded
gmatarrubia 0:820a69dfd200 223 \return 1 Function failed
gmatarrubia 0:820a69dfd200 224 */
gmatarrubia 0:820a69dfd200 225 #define __STREXB(value, ptr) __strex(value, ptr)
gmatarrubia 0:820a69dfd200 226
gmatarrubia 0:820a69dfd200 227
gmatarrubia 0:820a69dfd200 228 /** \brief STR Exclusive (16 bit)
gmatarrubia 0:820a69dfd200 229
gmatarrubia 0:820a69dfd200 230 This function performs a exclusive STR command for 16 bit values.
gmatarrubia 0:820a69dfd200 231
gmatarrubia 0:820a69dfd200 232 \param [in] value Value to store
gmatarrubia 0:820a69dfd200 233 \param [in] ptr Pointer to location
gmatarrubia 0:820a69dfd200 234 \return 0 Function succeeded
gmatarrubia 0:820a69dfd200 235 \return 1 Function failed
gmatarrubia 0:820a69dfd200 236 */
gmatarrubia 0:820a69dfd200 237 #define __STREXH(value, ptr) __strex(value, ptr)
gmatarrubia 0:820a69dfd200 238
gmatarrubia 0:820a69dfd200 239
gmatarrubia 0:820a69dfd200 240 /** \brief STR Exclusive (32 bit)
gmatarrubia 0:820a69dfd200 241
gmatarrubia 0:820a69dfd200 242 This function performs a exclusive STR command for 32 bit values.
gmatarrubia 0:820a69dfd200 243
gmatarrubia 0:820a69dfd200 244 \param [in] value Value to store
gmatarrubia 0:820a69dfd200 245 \param [in] ptr Pointer to location
gmatarrubia 0:820a69dfd200 246 \return 0 Function succeeded
gmatarrubia 0:820a69dfd200 247 \return 1 Function failed
gmatarrubia 0:820a69dfd200 248 */
gmatarrubia 0:820a69dfd200 249 #define __STREXW(value, ptr) __strex(value, ptr)
gmatarrubia 0:820a69dfd200 250
gmatarrubia 0:820a69dfd200 251
gmatarrubia 0:820a69dfd200 252 /** \brief Remove the exclusive lock
gmatarrubia 0:820a69dfd200 253
gmatarrubia 0:820a69dfd200 254 This function removes the exclusive lock which is created by LDREX.
gmatarrubia 0:820a69dfd200 255
gmatarrubia 0:820a69dfd200 256 */
gmatarrubia 0:820a69dfd200 257 #define __CLREX __clrex
gmatarrubia 0:820a69dfd200 258
gmatarrubia 0:820a69dfd200 259
gmatarrubia 0:820a69dfd200 260 /** \brief Signed Saturate
gmatarrubia 0:820a69dfd200 261
gmatarrubia 0:820a69dfd200 262 This function saturates a signed value.
gmatarrubia 0:820a69dfd200 263
gmatarrubia 0:820a69dfd200 264 \param [in] value Value to be saturated
gmatarrubia 0:820a69dfd200 265 \param [in] sat Bit position to saturate to (1..32)
gmatarrubia 0:820a69dfd200 266 \return Saturated value
gmatarrubia 0:820a69dfd200 267 */
gmatarrubia 0:820a69dfd200 268 #define __SSAT __ssat
gmatarrubia 0:820a69dfd200 269
gmatarrubia 0:820a69dfd200 270
gmatarrubia 0:820a69dfd200 271 /** \brief Unsigned Saturate
gmatarrubia 0:820a69dfd200 272
gmatarrubia 0:820a69dfd200 273 This function saturates an unsigned value.
gmatarrubia 0:820a69dfd200 274
gmatarrubia 0:820a69dfd200 275 \param [in] value Value to be saturated
gmatarrubia 0:820a69dfd200 276 \param [in] sat Bit position to saturate to (0..31)
gmatarrubia 0:820a69dfd200 277 \return Saturated value
gmatarrubia 0:820a69dfd200 278 */
gmatarrubia 0:820a69dfd200 279 #define __USAT __usat
gmatarrubia 0:820a69dfd200 280
gmatarrubia 0:820a69dfd200 281
gmatarrubia 0:820a69dfd200 282 /** \brief Count leading zeros
gmatarrubia 0:820a69dfd200 283
gmatarrubia 0:820a69dfd200 284 This function counts the number of leading zeros of a data value.
gmatarrubia 0:820a69dfd200 285
gmatarrubia 0:820a69dfd200 286 \param [in] value Value to count the leading zeros
gmatarrubia 0:820a69dfd200 287 \return number of leading zeros in value
gmatarrubia 0:820a69dfd200 288 */
gmatarrubia 0:820a69dfd200 289 #define __CLZ __clz
gmatarrubia 0:820a69dfd200 290
gmatarrubia 0:820a69dfd200 291 #endif /* (__CORTEX_M >= 0x03) */
gmatarrubia 0:820a69dfd200 292
gmatarrubia 0:820a69dfd200 293
gmatarrubia 0:820a69dfd200 294
gmatarrubia 0:820a69dfd200 295 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
gmatarrubia 0:820a69dfd200 296 /* IAR iccarm specific functions */
gmatarrubia 0:820a69dfd200 297
gmatarrubia 0:820a69dfd200 298 #include <cmsis_iar.h>
gmatarrubia 0:820a69dfd200 299
gmatarrubia 0:820a69dfd200 300
gmatarrubia 0:820a69dfd200 301 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
gmatarrubia 0:820a69dfd200 302 /* TI CCS specific functions */
gmatarrubia 0:820a69dfd200 303
gmatarrubia 0:820a69dfd200 304 #include <cmsis_ccs.h>
gmatarrubia 0:820a69dfd200 305
gmatarrubia 0:820a69dfd200 306
gmatarrubia 0:820a69dfd200 307 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
gmatarrubia 0:820a69dfd200 308 /* GNU gcc specific functions */
gmatarrubia 0:820a69dfd200 309
gmatarrubia 0:820a69dfd200 310 /* Define macros for porting to both thumb1 and thumb2.
gmatarrubia 0:820a69dfd200 311 * For thumb1, use low register (r0-r7), specified by constrant "l"
gmatarrubia 0:820a69dfd200 312 * Otherwise, use general registers, specified by constrant "r" */
gmatarrubia 0:820a69dfd200 313 #if defined (__thumb__) && !defined (__thumb2__)
gmatarrubia 0:820a69dfd200 314 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
gmatarrubia 0:820a69dfd200 315 #define __CMSIS_GCC_USE_REG(r) "l" (r)
gmatarrubia 0:820a69dfd200 316 #else
gmatarrubia 0:820a69dfd200 317 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
gmatarrubia 0:820a69dfd200 318 #define __CMSIS_GCC_USE_REG(r) "r" (r)
gmatarrubia 0:820a69dfd200 319 #endif
gmatarrubia 0:820a69dfd200 320
gmatarrubia 0:820a69dfd200 321 /** \brief No Operation
gmatarrubia 0:820a69dfd200 322
gmatarrubia 0:820a69dfd200 323 No Operation does nothing. This instruction can be used for code alignment purposes.
gmatarrubia 0:820a69dfd200 324 */
gmatarrubia 0:820a69dfd200 325 __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
gmatarrubia 0:820a69dfd200 326 {
gmatarrubia 0:820a69dfd200 327 __ASM volatile ("nop");
gmatarrubia 0:820a69dfd200 328 }
gmatarrubia 0:820a69dfd200 329
gmatarrubia 0:820a69dfd200 330
gmatarrubia 0:820a69dfd200 331 /** \brief Wait For Interrupt
gmatarrubia 0:820a69dfd200 332
gmatarrubia 0:820a69dfd200 333 Wait For Interrupt is a hint instruction that suspends execution
gmatarrubia 0:820a69dfd200 334 until one of a number of events occurs.
gmatarrubia 0:820a69dfd200 335 */
gmatarrubia 0:820a69dfd200 336 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
gmatarrubia 0:820a69dfd200 337 {
gmatarrubia 0:820a69dfd200 338 __ASM volatile ("wfi");
gmatarrubia 0:820a69dfd200 339 }
gmatarrubia 0:820a69dfd200 340
gmatarrubia 0:820a69dfd200 341
gmatarrubia 0:820a69dfd200 342 /** \brief Wait For Event
gmatarrubia 0:820a69dfd200 343
gmatarrubia 0:820a69dfd200 344 Wait For Event is a hint instruction that permits the processor to enter
gmatarrubia 0:820a69dfd200 345 a low-power state until one of a number of events occurs.
gmatarrubia 0:820a69dfd200 346 */
gmatarrubia 0:820a69dfd200 347 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
gmatarrubia 0:820a69dfd200 348 {
gmatarrubia 0:820a69dfd200 349 __ASM volatile ("wfe");
gmatarrubia 0:820a69dfd200 350 }
gmatarrubia 0:820a69dfd200 351
gmatarrubia 0:820a69dfd200 352
gmatarrubia 0:820a69dfd200 353 /** \brief Send Event
gmatarrubia 0:820a69dfd200 354
gmatarrubia 0:820a69dfd200 355 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
gmatarrubia 0:820a69dfd200 356 */
gmatarrubia 0:820a69dfd200 357 __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
gmatarrubia 0:820a69dfd200 358 {
gmatarrubia 0:820a69dfd200 359 __ASM volatile ("sev");
gmatarrubia 0:820a69dfd200 360 }
gmatarrubia 0:820a69dfd200 361
gmatarrubia 0:820a69dfd200 362
gmatarrubia 0:820a69dfd200 363 /** \brief Instruction Synchronization Barrier
gmatarrubia 0:820a69dfd200 364
gmatarrubia 0:820a69dfd200 365 Instruction Synchronization Barrier flushes the pipeline in the processor,
gmatarrubia 0:820a69dfd200 366 so that all instructions following the ISB are fetched from cache or
gmatarrubia 0:820a69dfd200 367 memory, after the instruction has been completed.
gmatarrubia 0:820a69dfd200 368 */
gmatarrubia 0:820a69dfd200 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
gmatarrubia 0:820a69dfd200 370 {
gmatarrubia 0:820a69dfd200 371 __ASM volatile ("isb");
gmatarrubia 0:820a69dfd200 372 }
gmatarrubia 0:820a69dfd200 373
gmatarrubia 0:820a69dfd200 374
gmatarrubia 0:820a69dfd200 375 /** \brief Data Synchronization Barrier
gmatarrubia 0:820a69dfd200 376
gmatarrubia 0:820a69dfd200 377 This function acts as a special kind of Data Memory Barrier.
gmatarrubia 0:820a69dfd200 378 It completes when all explicit memory accesses before this instruction complete.
gmatarrubia 0:820a69dfd200 379 */
gmatarrubia 0:820a69dfd200 380 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
gmatarrubia 0:820a69dfd200 381 {
gmatarrubia 0:820a69dfd200 382 __ASM volatile ("dsb");
gmatarrubia 0:820a69dfd200 383 }
gmatarrubia 0:820a69dfd200 384
gmatarrubia 0:820a69dfd200 385
gmatarrubia 0:820a69dfd200 386 /** \brief Data Memory Barrier
gmatarrubia 0:820a69dfd200 387
gmatarrubia 0:820a69dfd200 388 This function ensures the apparent order of the explicit memory operations before
gmatarrubia 0:820a69dfd200 389 and after the instruction, without ensuring their completion.
gmatarrubia 0:820a69dfd200 390 */
gmatarrubia 0:820a69dfd200 391 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
gmatarrubia 0:820a69dfd200 392 {
gmatarrubia 0:820a69dfd200 393 __ASM volatile ("dmb");
gmatarrubia 0:820a69dfd200 394 }
gmatarrubia 0:820a69dfd200 395
gmatarrubia 0:820a69dfd200 396
gmatarrubia 0:820a69dfd200 397 /** \brief Reverse byte order (32 bit)
gmatarrubia 0:820a69dfd200 398
gmatarrubia 0:820a69dfd200 399 This function reverses the byte order in integer value.
gmatarrubia 0:820a69dfd200 400
gmatarrubia 0:820a69dfd200 401 \param [in] value Value to reverse
gmatarrubia 0:820a69dfd200 402 \return Reversed value
gmatarrubia 0:820a69dfd200 403 */
gmatarrubia 0:820a69dfd200 404 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
gmatarrubia 0:820a69dfd200 405 {
gmatarrubia 0:820a69dfd200 406 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
gmatarrubia 0:820a69dfd200 407 return __builtin_bswap32(value);
gmatarrubia 0:820a69dfd200 408 #else
gmatarrubia 0:820a69dfd200 409 uint32_t result;
gmatarrubia 0:820a69dfd200 410
gmatarrubia 0:820a69dfd200 411 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
gmatarrubia 0:820a69dfd200 412 return(result);
gmatarrubia 0:820a69dfd200 413 #endif
gmatarrubia 0:820a69dfd200 414 }
gmatarrubia 0:820a69dfd200 415
gmatarrubia 0:820a69dfd200 416
gmatarrubia 0:820a69dfd200 417 /** \brief Reverse byte order (16 bit)
gmatarrubia 0:820a69dfd200 418
gmatarrubia 0:820a69dfd200 419 This function reverses the byte order in two unsigned short values.
gmatarrubia 0:820a69dfd200 420
gmatarrubia 0:820a69dfd200 421 \param [in] value Value to reverse
gmatarrubia 0:820a69dfd200 422 \return Reversed value
gmatarrubia 0:820a69dfd200 423 */
gmatarrubia 0:820a69dfd200 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
gmatarrubia 0:820a69dfd200 425 {
gmatarrubia 0:820a69dfd200 426 uint32_t result;
gmatarrubia 0:820a69dfd200 427
gmatarrubia 0:820a69dfd200 428 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
gmatarrubia 0:820a69dfd200 429 return(result);
gmatarrubia 0:820a69dfd200 430 }
gmatarrubia 0:820a69dfd200 431
gmatarrubia 0:820a69dfd200 432
gmatarrubia 0:820a69dfd200 433 /** \brief Reverse byte order in signed short value
gmatarrubia 0:820a69dfd200 434
gmatarrubia 0:820a69dfd200 435 This function reverses the byte order in a signed short value with sign extension to integer.
gmatarrubia 0:820a69dfd200 436
gmatarrubia 0:820a69dfd200 437 \param [in] value Value to reverse
gmatarrubia 0:820a69dfd200 438 \return Reversed value
gmatarrubia 0:820a69dfd200 439 */
gmatarrubia 0:820a69dfd200 440 __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
gmatarrubia 0:820a69dfd200 441 {
gmatarrubia 0:820a69dfd200 442 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
gmatarrubia 0:820a69dfd200 443 return (short)__builtin_bswap16(value);
gmatarrubia 0:820a69dfd200 444 #else
gmatarrubia 0:820a69dfd200 445 uint32_t result;
gmatarrubia 0:820a69dfd200 446
gmatarrubia 0:820a69dfd200 447 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
gmatarrubia 0:820a69dfd200 448 return(result);
gmatarrubia 0:820a69dfd200 449 #endif
gmatarrubia 0:820a69dfd200 450 }
gmatarrubia 0:820a69dfd200 451
gmatarrubia 0:820a69dfd200 452
gmatarrubia 0:820a69dfd200 453 /** \brief Rotate Right in unsigned value (32 bit)
gmatarrubia 0:820a69dfd200 454
gmatarrubia 0:820a69dfd200 455 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
gmatarrubia 0:820a69dfd200 456
gmatarrubia 0:820a69dfd200 457 \param [in] value Value to rotate
gmatarrubia 0:820a69dfd200 458 \param [in] value Number of Bits to rotate
gmatarrubia 0:820a69dfd200 459 \return Rotated value
gmatarrubia 0:820a69dfd200 460 */
gmatarrubia 0:820a69dfd200 461 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 462 {
gmatarrubia 0:820a69dfd200 463 return (op1 >> op2) | (op1 << (32 - op2));
gmatarrubia 0:820a69dfd200 464 }
gmatarrubia 0:820a69dfd200 465
gmatarrubia 0:820a69dfd200 466
gmatarrubia 0:820a69dfd200 467 /** \brief Breakpoint
gmatarrubia 0:820a69dfd200 468
gmatarrubia 0:820a69dfd200 469 This function causes the processor to enter Debug state.
gmatarrubia 0:820a69dfd200 470 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
gmatarrubia 0:820a69dfd200 471
gmatarrubia 0:820a69dfd200 472 \param [in] value is ignored by the processor.
gmatarrubia 0:820a69dfd200 473 If required, a debugger can use it to store additional information about the breakpoint.
gmatarrubia 0:820a69dfd200 474 */
gmatarrubia 0:820a69dfd200 475 #define __BKPT(value) __ASM volatile ("bkpt "#value)
gmatarrubia 0:820a69dfd200 476
gmatarrubia 0:820a69dfd200 477
gmatarrubia 0:820a69dfd200 478 #if (__CORTEX_M >= 0x03)
gmatarrubia 0:820a69dfd200 479
gmatarrubia 0:820a69dfd200 480 /** \brief Reverse bit order of value
gmatarrubia 0:820a69dfd200 481
gmatarrubia 0:820a69dfd200 482 This function reverses the bit order of the given value.
gmatarrubia 0:820a69dfd200 483
gmatarrubia 0:820a69dfd200 484 \param [in] value Value to reverse
gmatarrubia 0:820a69dfd200 485 \return Reversed value
gmatarrubia 0:820a69dfd200 486 */
gmatarrubia 0:820a69dfd200 487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
gmatarrubia 0:820a69dfd200 488 {
gmatarrubia 0:820a69dfd200 489 uint32_t result;
gmatarrubia 0:820a69dfd200 490
gmatarrubia 0:820a69dfd200 491 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
gmatarrubia 0:820a69dfd200 492 return(result);
gmatarrubia 0:820a69dfd200 493 }
gmatarrubia 0:820a69dfd200 494
gmatarrubia 0:820a69dfd200 495
gmatarrubia 0:820a69dfd200 496 /** \brief LDR Exclusive (8 bit)
gmatarrubia 0:820a69dfd200 497
gmatarrubia 0:820a69dfd200 498 This function performs a exclusive LDR command for 8 bit value.
gmatarrubia 0:820a69dfd200 499
gmatarrubia 0:820a69dfd200 500 \param [in] ptr Pointer to data
gmatarrubia 0:820a69dfd200 501 \return value of type uint8_t at (*ptr)
gmatarrubia 0:820a69dfd200 502 */
gmatarrubia 0:820a69dfd200 503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
gmatarrubia 0:820a69dfd200 504 {
gmatarrubia 0:820a69dfd200 505 uint32_t result;
gmatarrubia 0:820a69dfd200 506
gmatarrubia 0:820a69dfd200 507 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
gmatarrubia 0:820a69dfd200 508 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
gmatarrubia 0:820a69dfd200 509 #else
gmatarrubia 0:820a69dfd200 510 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
gmatarrubia 0:820a69dfd200 511 accepted by assembler. So has to use following less efficient pattern.
gmatarrubia 0:820a69dfd200 512 */
gmatarrubia 0:820a69dfd200 513 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
gmatarrubia 0:820a69dfd200 514 #endif
gmatarrubia 0:820a69dfd200 515 return(result);
gmatarrubia 0:820a69dfd200 516 }
gmatarrubia 0:820a69dfd200 517
gmatarrubia 0:820a69dfd200 518
gmatarrubia 0:820a69dfd200 519 /** \brief LDR Exclusive (16 bit)
gmatarrubia 0:820a69dfd200 520
gmatarrubia 0:820a69dfd200 521 This function performs a exclusive LDR command for 16 bit values.
gmatarrubia 0:820a69dfd200 522
gmatarrubia 0:820a69dfd200 523 \param [in] ptr Pointer to data
gmatarrubia 0:820a69dfd200 524 \return value of type uint16_t at (*ptr)
gmatarrubia 0:820a69dfd200 525 */
gmatarrubia 0:820a69dfd200 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
gmatarrubia 0:820a69dfd200 527 {
gmatarrubia 0:820a69dfd200 528 uint32_t result;
gmatarrubia 0:820a69dfd200 529
gmatarrubia 0:820a69dfd200 530 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
gmatarrubia 0:820a69dfd200 531 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
gmatarrubia 0:820a69dfd200 532 #else
gmatarrubia 0:820a69dfd200 533 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
gmatarrubia 0:820a69dfd200 534 accepted by assembler. So has to use following less efficient pattern.
gmatarrubia 0:820a69dfd200 535 */
gmatarrubia 0:820a69dfd200 536 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
gmatarrubia 0:820a69dfd200 537 #endif
gmatarrubia 0:820a69dfd200 538 return(result);
gmatarrubia 0:820a69dfd200 539 }
gmatarrubia 0:820a69dfd200 540
gmatarrubia 0:820a69dfd200 541
gmatarrubia 0:820a69dfd200 542 /** \brief LDR Exclusive (32 bit)
gmatarrubia 0:820a69dfd200 543
gmatarrubia 0:820a69dfd200 544 This function performs a exclusive LDR command for 32 bit values.
gmatarrubia 0:820a69dfd200 545
gmatarrubia 0:820a69dfd200 546 \param [in] ptr Pointer to data
gmatarrubia 0:820a69dfd200 547 \return value of type uint32_t at (*ptr)
gmatarrubia 0:820a69dfd200 548 */
gmatarrubia 0:820a69dfd200 549 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
gmatarrubia 0:820a69dfd200 550 {
gmatarrubia 0:820a69dfd200 551 uint32_t result;
gmatarrubia 0:820a69dfd200 552
gmatarrubia 0:820a69dfd200 553 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
gmatarrubia 0:820a69dfd200 554 return(result);
gmatarrubia 0:820a69dfd200 555 }
gmatarrubia 0:820a69dfd200 556
gmatarrubia 0:820a69dfd200 557
gmatarrubia 0:820a69dfd200 558 /** \brief STR Exclusive (8 bit)
gmatarrubia 0:820a69dfd200 559
gmatarrubia 0:820a69dfd200 560 This function performs a exclusive STR command for 8 bit values.
gmatarrubia 0:820a69dfd200 561
gmatarrubia 0:820a69dfd200 562 \param [in] value Value to store
gmatarrubia 0:820a69dfd200 563 \param [in] ptr Pointer to location
gmatarrubia 0:820a69dfd200 564 \return 0 Function succeeded
gmatarrubia 0:820a69dfd200 565 \return 1 Function failed
gmatarrubia 0:820a69dfd200 566 */
gmatarrubia 0:820a69dfd200 567 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
gmatarrubia 0:820a69dfd200 568 {
gmatarrubia 0:820a69dfd200 569 uint32_t result;
gmatarrubia 0:820a69dfd200 570
gmatarrubia 0:820a69dfd200 571 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
gmatarrubia 0:820a69dfd200 572 return(result);
gmatarrubia 0:820a69dfd200 573 }
gmatarrubia 0:820a69dfd200 574
gmatarrubia 0:820a69dfd200 575
gmatarrubia 0:820a69dfd200 576 /** \brief STR Exclusive (16 bit)
gmatarrubia 0:820a69dfd200 577
gmatarrubia 0:820a69dfd200 578 This function performs a exclusive STR command for 16 bit values.
gmatarrubia 0:820a69dfd200 579
gmatarrubia 0:820a69dfd200 580 \param [in] value Value to store
gmatarrubia 0:820a69dfd200 581 \param [in] ptr Pointer to location
gmatarrubia 0:820a69dfd200 582 \return 0 Function succeeded
gmatarrubia 0:820a69dfd200 583 \return 1 Function failed
gmatarrubia 0:820a69dfd200 584 */
gmatarrubia 0:820a69dfd200 585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
gmatarrubia 0:820a69dfd200 586 {
gmatarrubia 0:820a69dfd200 587 uint32_t result;
gmatarrubia 0:820a69dfd200 588
gmatarrubia 0:820a69dfd200 589 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
gmatarrubia 0:820a69dfd200 590 return(result);
gmatarrubia 0:820a69dfd200 591 }
gmatarrubia 0:820a69dfd200 592
gmatarrubia 0:820a69dfd200 593
gmatarrubia 0:820a69dfd200 594 /** \brief STR Exclusive (32 bit)
gmatarrubia 0:820a69dfd200 595
gmatarrubia 0:820a69dfd200 596 This function performs a exclusive STR command for 32 bit values.
gmatarrubia 0:820a69dfd200 597
gmatarrubia 0:820a69dfd200 598 \param [in] value Value to store
gmatarrubia 0:820a69dfd200 599 \param [in] ptr Pointer to location
gmatarrubia 0:820a69dfd200 600 \return 0 Function succeeded
gmatarrubia 0:820a69dfd200 601 \return 1 Function failed
gmatarrubia 0:820a69dfd200 602 */
gmatarrubia 0:820a69dfd200 603 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
gmatarrubia 0:820a69dfd200 604 {
gmatarrubia 0:820a69dfd200 605 uint32_t result;
gmatarrubia 0:820a69dfd200 606
gmatarrubia 0:820a69dfd200 607 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
gmatarrubia 0:820a69dfd200 608 return(result);
gmatarrubia 0:820a69dfd200 609 }
gmatarrubia 0:820a69dfd200 610
gmatarrubia 0:820a69dfd200 611
gmatarrubia 0:820a69dfd200 612 /** \brief Remove the exclusive lock
gmatarrubia 0:820a69dfd200 613
gmatarrubia 0:820a69dfd200 614 This function removes the exclusive lock which is created by LDREX.
gmatarrubia 0:820a69dfd200 615
gmatarrubia 0:820a69dfd200 616 */
gmatarrubia 0:820a69dfd200 617 __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
gmatarrubia 0:820a69dfd200 618 {
gmatarrubia 0:820a69dfd200 619 __ASM volatile ("clrex" ::: "memory");
gmatarrubia 0:820a69dfd200 620 }
gmatarrubia 0:820a69dfd200 621
gmatarrubia 0:820a69dfd200 622
gmatarrubia 0:820a69dfd200 623 /** \brief Signed Saturate
gmatarrubia 0:820a69dfd200 624
gmatarrubia 0:820a69dfd200 625 This function saturates a signed value.
gmatarrubia 0:820a69dfd200 626
gmatarrubia 0:820a69dfd200 627 \param [in] value Value to be saturated
gmatarrubia 0:820a69dfd200 628 \param [in] sat Bit position to saturate to (1..32)
gmatarrubia 0:820a69dfd200 629 \return Saturated value
gmatarrubia 0:820a69dfd200 630 */
gmatarrubia 0:820a69dfd200 631 #define __SSAT(ARG1,ARG2) \
gmatarrubia 0:820a69dfd200 632 ({ \
gmatarrubia 0:820a69dfd200 633 uint32_t __RES, __ARG1 = (ARG1); \
gmatarrubia 0:820a69dfd200 634 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
gmatarrubia 0:820a69dfd200 635 __RES; \
gmatarrubia 0:820a69dfd200 636 })
gmatarrubia 0:820a69dfd200 637
gmatarrubia 0:820a69dfd200 638
gmatarrubia 0:820a69dfd200 639 /** \brief Unsigned Saturate
gmatarrubia 0:820a69dfd200 640
gmatarrubia 0:820a69dfd200 641 This function saturates an unsigned value.
gmatarrubia 0:820a69dfd200 642
gmatarrubia 0:820a69dfd200 643 \param [in] value Value to be saturated
gmatarrubia 0:820a69dfd200 644 \param [in] sat Bit position to saturate to (0..31)
gmatarrubia 0:820a69dfd200 645 \return Saturated value
gmatarrubia 0:820a69dfd200 646 */
gmatarrubia 0:820a69dfd200 647 #define __USAT(ARG1,ARG2) \
gmatarrubia 0:820a69dfd200 648 ({ \
gmatarrubia 0:820a69dfd200 649 uint32_t __RES, __ARG1 = (ARG1); \
gmatarrubia 0:820a69dfd200 650 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
gmatarrubia 0:820a69dfd200 651 __RES; \
gmatarrubia 0:820a69dfd200 652 })
gmatarrubia 0:820a69dfd200 653
gmatarrubia 0:820a69dfd200 654
gmatarrubia 0:820a69dfd200 655 /** \brief Count leading zeros
gmatarrubia 0:820a69dfd200 656
gmatarrubia 0:820a69dfd200 657 This function counts the number of leading zeros of a data value.
gmatarrubia 0:820a69dfd200 658
gmatarrubia 0:820a69dfd200 659 \param [in] value Value to count the leading zeros
gmatarrubia 0:820a69dfd200 660 \return number of leading zeros in value
gmatarrubia 0:820a69dfd200 661 */
gmatarrubia 0:820a69dfd200 662 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
gmatarrubia 0:820a69dfd200 663 {
gmatarrubia 0:820a69dfd200 664 uint32_t result;
gmatarrubia 0:820a69dfd200 665
gmatarrubia 0:820a69dfd200 666 __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
gmatarrubia 0:820a69dfd200 667 return(result);
gmatarrubia 0:820a69dfd200 668 }
gmatarrubia 0:820a69dfd200 669
gmatarrubia 0:820a69dfd200 670 #endif /* (__CORTEX_M >= 0x03) */
gmatarrubia 0:820a69dfd200 671
gmatarrubia 0:820a69dfd200 672
gmatarrubia 0:820a69dfd200 673
gmatarrubia 0:820a69dfd200 674
gmatarrubia 0:820a69dfd200 675 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
gmatarrubia 0:820a69dfd200 676 /* TASKING carm specific functions */
gmatarrubia 0:820a69dfd200 677
gmatarrubia 0:820a69dfd200 678 /*
gmatarrubia 0:820a69dfd200 679 * The CMSIS functions have been implemented as intrinsics in the compiler.
gmatarrubia 0:820a69dfd200 680 * Please use "carm -?i" to get an up to date list of all intrinsics,
gmatarrubia 0:820a69dfd200 681 * Including the CMSIS ones.
gmatarrubia 0:820a69dfd200 682 */
gmatarrubia 0:820a69dfd200 683
gmatarrubia 0:820a69dfd200 684 #endif
gmatarrubia 0:820a69dfd200 685
gmatarrubia 0:820a69dfd200 686 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
gmatarrubia 0:820a69dfd200 687
gmatarrubia 0:820a69dfd200 688 #endif /* __CORE_CMINSTR_H */