Gonzalo Matarrubia / Mbed LPC1549 mod

This repo contains the libraries of Mbed for LPC1549 with following changes: - IAP commands. - EEPROM write and read. - UART write and read (public) - CAN can_s -> LPC_C_CAN0_Type *can

mbed/TARGET_LPC1549/core_cmFunc.h@0:820a69dfd200, 2015-04-14 (annotated)

Committer:
gmatarrubia
Date:
Tue Apr 14 15:00:13 2015 +0200
Revision:
0:820a69dfd200
Initial repo. IAP commands, EEPROM write/read, UART write/read, CAN

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gmatarrubia 0:820a69dfd200 1 /**************************************************************************//**
gmatarrubia 0:820a69dfd200 2 * @file core_cmFunc.h
gmatarrubia 0:820a69dfd200 3 * @brief CMSIS Cortex-M Core Function Access Header File
gmatarrubia 0:820a69dfd200 4 * @version V3.20
gmatarrubia 0:820a69dfd200 5 * @date 25. February 2013
gmatarrubia 0:820a69dfd200 6 *
gmatarrubia 0:820a69dfd200 7 * @note
gmatarrubia 0:820a69dfd200 8 *
gmatarrubia 0:820a69dfd200 9 ******************************************************************************/
gmatarrubia 0:820a69dfd200 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
gmatarrubia 0:820a69dfd200 11
gmatarrubia 0:820a69dfd200 12 All rights reserved.
gmatarrubia 0:820a69dfd200 13 Redistribution and use in source and binary forms, with or without
gmatarrubia 0:820a69dfd200 14 modification, are permitted provided that the following conditions are met:
gmatarrubia 0:820a69dfd200 15 - Redistributions of source code must retain the above copyright
gmatarrubia 0:820a69dfd200 16 notice, this list of conditions and the following disclaimer.
gmatarrubia 0:820a69dfd200 17 - Redistributions in binary form must reproduce the above copyright
gmatarrubia 0:820a69dfd200 18 notice, this list of conditions and the following disclaimer in the
gmatarrubia 0:820a69dfd200 19 documentation and/or other materials provided with the distribution.
gmatarrubia 0:820a69dfd200 20 - Neither the name of ARM nor the names of its contributors may be used
gmatarrubia 0:820a69dfd200 21 to endorse or promote products derived from this software without
gmatarrubia 0:820a69dfd200 22 specific prior written permission.
gmatarrubia 0:820a69dfd200 23 *
gmatarrubia 0:820a69dfd200 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
gmatarrubia 0:820a69dfd200 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
gmatarrubia 0:820a69dfd200 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
gmatarrubia 0:820a69dfd200 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
gmatarrubia 0:820a69dfd200 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
gmatarrubia 0:820a69dfd200 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
gmatarrubia 0:820a69dfd200 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
gmatarrubia 0:820a69dfd200 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
gmatarrubia 0:820a69dfd200 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
gmatarrubia 0:820a69dfd200 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
gmatarrubia 0:820a69dfd200 34 POSSIBILITY OF SUCH DAMAGE.
gmatarrubia 0:820a69dfd200 35 ---------------------------------------------------------------------------*/
gmatarrubia 0:820a69dfd200 36
gmatarrubia 0:820a69dfd200 37
gmatarrubia 0:820a69dfd200 38 #ifndef __CORE_CMFUNC_H
gmatarrubia 0:820a69dfd200 39 #define __CORE_CMFUNC_H
gmatarrubia 0:820a69dfd200 40
gmatarrubia 0:820a69dfd200 41
gmatarrubia 0:820a69dfd200 42 /* ########################### Core Function Access ########################### */
gmatarrubia 0:820a69dfd200 43 /** \ingroup CMSIS_Core_FunctionInterface
gmatarrubia 0:820a69dfd200 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
gmatarrubia 0:820a69dfd200 45 @{
gmatarrubia 0:820a69dfd200 46 */
gmatarrubia 0:820a69dfd200 47
gmatarrubia 0:820a69dfd200 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
gmatarrubia 0:820a69dfd200 49 /* ARM armcc specific functions */
gmatarrubia 0:820a69dfd200 50
gmatarrubia 0:820a69dfd200 51 #if (__ARMCC_VERSION < 400677)
gmatarrubia 0:820a69dfd200 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
gmatarrubia 0:820a69dfd200 53 #endif
gmatarrubia 0:820a69dfd200 54
gmatarrubia 0:820a69dfd200 55 /* intrinsic void __enable_irq(); */
gmatarrubia 0:820a69dfd200 56 /* intrinsic void __disable_irq(); */
gmatarrubia 0:820a69dfd200 57
gmatarrubia 0:820a69dfd200 58 /** \brief Get Control Register
gmatarrubia 0:820a69dfd200 59
gmatarrubia 0:820a69dfd200 60 This function returns the content of the Control Register.
gmatarrubia 0:820a69dfd200 61
gmatarrubia 0:820a69dfd200 62 \return Control Register value
gmatarrubia 0:820a69dfd200 63 */
gmatarrubia 0:820a69dfd200 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
gmatarrubia 0:820a69dfd200 65 {
gmatarrubia 0:820a69dfd200 66 register uint32_t __regControl __ASM("control");
gmatarrubia 0:820a69dfd200 67 return(__regControl);
gmatarrubia 0:820a69dfd200 68 }
gmatarrubia 0:820a69dfd200 69
gmatarrubia 0:820a69dfd200 70
gmatarrubia 0:820a69dfd200 71 /** \brief Set Control Register
gmatarrubia 0:820a69dfd200 72
gmatarrubia 0:820a69dfd200 73 This function writes the given value to the Control Register.
gmatarrubia 0:820a69dfd200 74
gmatarrubia 0:820a69dfd200 75 \param [in] control Control Register value to set
gmatarrubia 0:820a69dfd200 76 */
gmatarrubia 0:820a69dfd200 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
gmatarrubia 0:820a69dfd200 78 {
gmatarrubia 0:820a69dfd200 79 register uint32_t __regControl __ASM("control");
gmatarrubia 0:820a69dfd200 80 __regControl = control;
gmatarrubia 0:820a69dfd200 81 }
gmatarrubia 0:820a69dfd200 82
gmatarrubia 0:820a69dfd200 83
gmatarrubia 0:820a69dfd200 84 /** \brief Get IPSR Register
gmatarrubia 0:820a69dfd200 85
gmatarrubia 0:820a69dfd200 86 This function returns the content of the IPSR Register.
gmatarrubia 0:820a69dfd200 87
gmatarrubia 0:820a69dfd200 88 \return IPSR Register value
gmatarrubia 0:820a69dfd200 89 */
gmatarrubia 0:820a69dfd200 90 __STATIC_INLINE uint32_t __get_IPSR(void)
gmatarrubia 0:820a69dfd200 91 {
gmatarrubia 0:820a69dfd200 92 register uint32_t __regIPSR __ASM("ipsr");
gmatarrubia 0:820a69dfd200 93 return(__regIPSR);
gmatarrubia 0:820a69dfd200 94 }
gmatarrubia 0:820a69dfd200 95
gmatarrubia 0:820a69dfd200 96
gmatarrubia 0:820a69dfd200 97 /** \brief Get APSR Register
gmatarrubia 0:820a69dfd200 98
gmatarrubia 0:820a69dfd200 99 This function returns the content of the APSR Register.
gmatarrubia 0:820a69dfd200 100
gmatarrubia 0:820a69dfd200 101 \return APSR Register value
gmatarrubia 0:820a69dfd200 102 */
gmatarrubia 0:820a69dfd200 103 __STATIC_INLINE uint32_t __get_APSR(void)
gmatarrubia 0:820a69dfd200 104 {
gmatarrubia 0:820a69dfd200 105 register uint32_t __regAPSR __ASM("apsr");
gmatarrubia 0:820a69dfd200 106 return(__regAPSR);
gmatarrubia 0:820a69dfd200 107 }
gmatarrubia 0:820a69dfd200 108
gmatarrubia 0:820a69dfd200 109
gmatarrubia 0:820a69dfd200 110 /** \brief Get xPSR Register
gmatarrubia 0:820a69dfd200 111
gmatarrubia 0:820a69dfd200 112 This function returns the content of the xPSR Register.
gmatarrubia 0:820a69dfd200 113
gmatarrubia 0:820a69dfd200 114 \return xPSR Register value
gmatarrubia 0:820a69dfd200 115 */
gmatarrubia 0:820a69dfd200 116 __STATIC_INLINE uint32_t __get_xPSR(void)
gmatarrubia 0:820a69dfd200 117 {
gmatarrubia 0:820a69dfd200 118 register uint32_t __regXPSR __ASM("xpsr");
gmatarrubia 0:820a69dfd200 119 return(__regXPSR);
gmatarrubia 0:820a69dfd200 120 }
gmatarrubia 0:820a69dfd200 121
gmatarrubia 0:820a69dfd200 122
gmatarrubia 0:820a69dfd200 123 /** \brief Get Process Stack Pointer
gmatarrubia 0:820a69dfd200 124
gmatarrubia 0:820a69dfd200 125 This function returns the current value of the Process Stack Pointer (PSP).
gmatarrubia 0:820a69dfd200 126
gmatarrubia 0:820a69dfd200 127 \return PSP Register value
gmatarrubia 0:820a69dfd200 128 */
gmatarrubia 0:820a69dfd200 129 __STATIC_INLINE uint32_t __get_PSP(void)
gmatarrubia 0:820a69dfd200 130 {
gmatarrubia 0:820a69dfd200 131 register uint32_t __regProcessStackPointer __ASM("psp");
gmatarrubia 0:820a69dfd200 132 return(__regProcessStackPointer);
gmatarrubia 0:820a69dfd200 133 }
gmatarrubia 0:820a69dfd200 134
gmatarrubia 0:820a69dfd200 135
gmatarrubia 0:820a69dfd200 136 /** \brief Set Process Stack Pointer
gmatarrubia 0:820a69dfd200 137
gmatarrubia 0:820a69dfd200 138 This function assigns the given value to the Process Stack Pointer (PSP).
gmatarrubia 0:820a69dfd200 139
gmatarrubia 0:820a69dfd200 140 \param [in] topOfProcStack Process Stack Pointer value to set
gmatarrubia 0:820a69dfd200 141 */
gmatarrubia 0:820a69dfd200 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
gmatarrubia 0:820a69dfd200 143 {
gmatarrubia 0:820a69dfd200 144 register uint32_t __regProcessStackPointer __ASM("psp");
gmatarrubia 0:820a69dfd200 145 __regProcessStackPointer = topOfProcStack;
gmatarrubia 0:820a69dfd200 146 }
gmatarrubia 0:820a69dfd200 147
gmatarrubia 0:820a69dfd200 148
gmatarrubia 0:820a69dfd200 149 /** \brief Get Main Stack Pointer
gmatarrubia 0:820a69dfd200 150
gmatarrubia 0:820a69dfd200 151 This function returns the current value of the Main Stack Pointer (MSP).
gmatarrubia 0:820a69dfd200 152
gmatarrubia 0:820a69dfd200 153 \return MSP Register value
gmatarrubia 0:820a69dfd200 154 */
gmatarrubia 0:820a69dfd200 155 __STATIC_INLINE uint32_t __get_MSP(void)
gmatarrubia 0:820a69dfd200 156 {
gmatarrubia 0:820a69dfd200 157 register uint32_t __regMainStackPointer __ASM("msp");
gmatarrubia 0:820a69dfd200 158 return(__regMainStackPointer);
gmatarrubia 0:820a69dfd200 159 }
gmatarrubia 0:820a69dfd200 160
gmatarrubia 0:820a69dfd200 161
gmatarrubia 0:820a69dfd200 162 /** \brief Set Main Stack Pointer
gmatarrubia 0:820a69dfd200 163
gmatarrubia 0:820a69dfd200 164 This function assigns the given value to the Main Stack Pointer (MSP).
gmatarrubia 0:820a69dfd200 165
gmatarrubia 0:820a69dfd200 166 \param [in] topOfMainStack Main Stack Pointer value to set
gmatarrubia 0:820a69dfd200 167 */
gmatarrubia 0:820a69dfd200 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
gmatarrubia 0:820a69dfd200 169 {
gmatarrubia 0:820a69dfd200 170 register uint32_t __regMainStackPointer __ASM("msp");
gmatarrubia 0:820a69dfd200 171 __regMainStackPointer = topOfMainStack;
gmatarrubia 0:820a69dfd200 172 }
gmatarrubia 0:820a69dfd200 173
gmatarrubia 0:820a69dfd200 174
gmatarrubia 0:820a69dfd200 175 /** \brief Get Priority Mask
gmatarrubia 0:820a69dfd200 176
gmatarrubia 0:820a69dfd200 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
gmatarrubia 0:820a69dfd200 178
gmatarrubia 0:820a69dfd200 179 \return Priority Mask value
gmatarrubia 0:820a69dfd200 180 */
gmatarrubia 0:820a69dfd200 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
gmatarrubia 0:820a69dfd200 182 {
gmatarrubia 0:820a69dfd200 183 register uint32_t __regPriMask __ASM("primask");
gmatarrubia 0:820a69dfd200 184 return(__regPriMask);
gmatarrubia 0:820a69dfd200 185 }
gmatarrubia 0:820a69dfd200 186
gmatarrubia 0:820a69dfd200 187
gmatarrubia 0:820a69dfd200 188 /** \brief Set Priority Mask
gmatarrubia 0:820a69dfd200 189
gmatarrubia 0:820a69dfd200 190 This function assigns the given value to the Priority Mask Register.
gmatarrubia 0:820a69dfd200 191
gmatarrubia 0:820a69dfd200 192 \param [in] priMask Priority Mask
gmatarrubia 0:820a69dfd200 193 */
gmatarrubia 0:820a69dfd200 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
gmatarrubia 0:820a69dfd200 195 {
gmatarrubia 0:820a69dfd200 196 register uint32_t __regPriMask __ASM("primask");
gmatarrubia 0:820a69dfd200 197 __regPriMask = (priMask);
gmatarrubia 0:820a69dfd200 198 }
gmatarrubia 0:820a69dfd200 199
gmatarrubia 0:820a69dfd200 200
gmatarrubia 0:820a69dfd200 201 #if (__CORTEX_M >= 0x03)
gmatarrubia 0:820a69dfd200 202
gmatarrubia 0:820a69dfd200 203 /** \brief Enable FIQ
gmatarrubia 0:820a69dfd200 204
gmatarrubia 0:820a69dfd200 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
gmatarrubia 0:820a69dfd200 206 Can only be executed in Privileged modes.
gmatarrubia 0:820a69dfd200 207 */
gmatarrubia 0:820a69dfd200 208 #define __enable_fault_irq __enable_fiq
gmatarrubia 0:820a69dfd200 209
gmatarrubia 0:820a69dfd200 210
gmatarrubia 0:820a69dfd200 211 /** \brief Disable FIQ
gmatarrubia 0:820a69dfd200 212
gmatarrubia 0:820a69dfd200 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
gmatarrubia 0:820a69dfd200 214 Can only be executed in Privileged modes.
gmatarrubia 0:820a69dfd200 215 */
gmatarrubia 0:820a69dfd200 216 #define __disable_fault_irq __disable_fiq
gmatarrubia 0:820a69dfd200 217
gmatarrubia 0:820a69dfd200 218
gmatarrubia 0:820a69dfd200 219 /** \brief Get Base Priority
gmatarrubia 0:820a69dfd200 220
gmatarrubia 0:820a69dfd200 221 This function returns the current value of the Base Priority register.
gmatarrubia 0:820a69dfd200 222
gmatarrubia 0:820a69dfd200 223 \return Base Priority register value
gmatarrubia 0:820a69dfd200 224 */
gmatarrubia 0:820a69dfd200 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
gmatarrubia 0:820a69dfd200 226 {
gmatarrubia 0:820a69dfd200 227 register uint32_t __regBasePri __ASM("basepri");
gmatarrubia 0:820a69dfd200 228 return(__regBasePri);
gmatarrubia 0:820a69dfd200 229 }
gmatarrubia 0:820a69dfd200 230
gmatarrubia 0:820a69dfd200 231
gmatarrubia 0:820a69dfd200 232 /** \brief Set Base Priority
gmatarrubia 0:820a69dfd200 233
gmatarrubia 0:820a69dfd200 234 This function assigns the given value to the Base Priority register.
gmatarrubia 0:820a69dfd200 235
gmatarrubia 0:820a69dfd200 236 \param [in] basePri Base Priority value to set
gmatarrubia 0:820a69dfd200 237 */
gmatarrubia 0:820a69dfd200 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
gmatarrubia 0:820a69dfd200 239 {
gmatarrubia 0:820a69dfd200 240 register uint32_t __regBasePri __ASM("basepri");
gmatarrubia 0:820a69dfd200 241 __regBasePri = (basePri & 0xff);
gmatarrubia 0:820a69dfd200 242 }
gmatarrubia 0:820a69dfd200 243
gmatarrubia 0:820a69dfd200 244
gmatarrubia 0:820a69dfd200 245 /** \brief Get Fault Mask
gmatarrubia 0:820a69dfd200 246
gmatarrubia 0:820a69dfd200 247 This function returns the current value of the Fault Mask register.
gmatarrubia 0:820a69dfd200 248
gmatarrubia 0:820a69dfd200 249 \return Fault Mask register value
gmatarrubia 0:820a69dfd200 250 */
gmatarrubia 0:820a69dfd200 251 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
gmatarrubia 0:820a69dfd200 252 {
gmatarrubia 0:820a69dfd200 253 register uint32_t __regFaultMask __ASM("faultmask");
gmatarrubia 0:820a69dfd200 254 return(__regFaultMask);
gmatarrubia 0:820a69dfd200 255 }
gmatarrubia 0:820a69dfd200 256
gmatarrubia 0:820a69dfd200 257
gmatarrubia 0:820a69dfd200 258 /** \brief Set Fault Mask
gmatarrubia 0:820a69dfd200 259
gmatarrubia 0:820a69dfd200 260 This function assigns the given value to the Fault Mask register.
gmatarrubia 0:820a69dfd200 261
gmatarrubia 0:820a69dfd200 262 \param [in] faultMask Fault Mask value to set
gmatarrubia 0:820a69dfd200 263 */
gmatarrubia 0:820a69dfd200 264 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
gmatarrubia 0:820a69dfd200 265 {
gmatarrubia 0:820a69dfd200 266 register uint32_t __regFaultMask __ASM("faultmask");
gmatarrubia 0:820a69dfd200 267 __regFaultMask = (faultMask & (uint32_t)1);
gmatarrubia 0:820a69dfd200 268 }
gmatarrubia 0:820a69dfd200 269
gmatarrubia 0:820a69dfd200 270 #endif /* (__CORTEX_M >= 0x03) */
gmatarrubia 0:820a69dfd200 271
gmatarrubia 0:820a69dfd200 272
gmatarrubia 0:820a69dfd200 273 #if (__CORTEX_M == 0x04)
gmatarrubia 0:820a69dfd200 274
gmatarrubia 0:820a69dfd200 275 /** \brief Get FPSCR
gmatarrubia 0:820a69dfd200 276
gmatarrubia 0:820a69dfd200 277 This function returns the current value of the Floating Point Status/Control register.
gmatarrubia 0:820a69dfd200 278
gmatarrubia 0:820a69dfd200 279 \return Floating Point Status/Control register value
gmatarrubia 0:820a69dfd200 280 */
gmatarrubia 0:820a69dfd200 281 __STATIC_INLINE uint32_t __get_FPSCR(void)
gmatarrubia 0:820a69dfd200 282 {
gmatarrubia 0:820a69dfd200 283 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
gmatarrubia 0:820a69dfd200 284 register uint32_t __regfpscr __ASM("fpscr");
gmatarrubia 0:820a69dfd200 285 return(__regfpscr);
gmatarrubia 0:820a69dfd200 286 #else
gmatarrubia 0:820a69dfd200 287 return(0);
gmatarrubia 0:820a69dfd200 288 #endif
gmatarrubia 0:820a69dfd200 289 }
gmatarrubia 0:820a69dfd200 290
gmatarrubia 0:820a69dfd200 291
gmatarrubia 0:820a69dfd200 292 /** \brief Set FPSCR
gmatarrubia 0:820a69dfd200 293
gmatarrubia 0:820a69dfd200 294 This function assigns the given value to the Floating Point Status/Control register.
gmatarrubia 0:820a69dfd200 295
gmatarrubia 0:820a69dfd200 296 \param [in] fpscr Floating Point Status/Control value to set
gmatarrubia 0:820a69dfd200 297 */
gmatarrubia 0:820a69dfd200 298 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
gmatarrubia 0:820a69dfd200 299 {
gmatarrubia 0:820a69dfd200 300 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
gmatarrubia 0:820a69dfd200 301 register uint32_t __regfpscr __ASM("fpscr");
gmatarrubia 0:820a69dfd200 302 __regfpscr = (fpscr);
gmatarrubia 0:820a69dfd200 303 #endif
gmatarrubia 0:820a69dfd200 304 }
gmatarrubia 0:820a69dfd200 305
gmatarrubia 0:820a69dfd200 306 #endif /* (__CORTEX_M == 0x04) */
gmatarrubia 0:820a69dfd200 307
gmatarrubia 0:820a69dfd200 308
gmatarrubia 0:820a69dfd200 309 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
gmatarrubia 0:820a69dfd200 310 /* IAR iccarm specific functions */
gmatarrubia 0:820a69dfd200 311
gmatarrubia 0:820a69dfd200 312 #include <cmsis_iar.h>
gmatarrubia 0:820a69dfd200 313
gmatarrubia 0:820a69dfd200 314
gmatarrubia 0:820a69dfd200 315 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
gmatarrubia 0:820a69dfd200 316 /* TI CCS specific functions */
gmatarrubia 0:820a69dfd200 317
gmatarrubia 0:820a69dfd200 318 #include <cmsis_ccs.h>
gmatarrubia 0:820a69dfd200 319
gmatarrubia 0:820a69dfd200 320
gmatarrubia 0:820a69dfd200 321 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
gmatarrubia 0:820a69dfd200 322 /* GNU gcc specific functions */
gmatarrubia 0:820a69dfd200 323
gmatarrubia 0:820a69dfd200 324 /** \brief Enable IRQ Interrupts
gmatarrubia 0:820a69dfd200 325
gmatarrubia 0:820a69dfd200 326 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
gmatarrubia 0:820a69dfd200 327 Can only be executed in Privileged modes.
gmatarrubia 0:820a69dfd200 328 */
gmatarrubia 0:820a69dfd200 329 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
gmatarrubia 0:820a69dfd200 330 {
gmatarrubia 0:820a69dfd200 331 __ASM volatile ("cpsie i" : : : "memory");
gmatarrubia 0:820a69dfd200 332 }
gmatarrubia 0:820a69dfd200 333
gmatarrubia 0:820a69dfd200 334
gmatarrubia 0:820a69dfd200 335 /** \brief Disable IRQ Interrupts
gmatarrubia 0:820a69dfd200 336
gmatarrubia 0:820a69dfd200 337 This function disables IRQ interrupts by setting the I-bit in the CPSR.
gmatarrubia 0:820a69dfd200 338 Can only be executed in Privileged modes.
gmatarrubia 0:820a69dfd200 339 */
gmatarrubia 0:820a69dfd200 340 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
gmatarrubia 0:820a69dfd200 341 {
gmatarrubia 0:820a69dfd200 342 __ASM volatile ("cpsid i" : : : "memory");
gmatarrubia 0:820a69dfd200 343 }
gmatarrubia 0:820a69dfd200 344
gmatarrubia 0:820a69dfd200 345
gmatarrubia 0:820a69dfd200 346 /** \brief Get Control Register
gmatarrubia 0:820a69dfd200 347
gmatarrubia 0:820a69dfd200 348 This function returns the content of the Control Register.
gmatarrubia 0:820a69dfd200 349
gmatarrubia 0:820a69dfd200 350 \return Control Register value
gmatarrubia 0:820a69dfd200 351 */
gmatarrubia 0:820a69dfd200 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
gmatarrubia 0:820a69dfd200 353 {
gmatarrubia 0:820a69dfd200 354 uint32_t result;
gmatarrubia 0:820a69dfd200 355
gmatarrubia 0:820a69dfd200 356 __ASM volatile ("MRS %0, control" : "=r" (result) );
gmatarrubia 0:820a69dfd200 357 return(result);
gmatarrubia 0:820a69dfd200 358 }
gmatarrubia 0:820a69dfd200 359
gmatarrubia 0:820a69dfd200 360
gmatarrubia 0:820a69dfd200 361 /** \brief Set Control Register
gmatarrubia 0:820a69dfd200 362
gmatarrubia 0:820a69dfd200 363 This function writes the given value to the Control Register.
gmatarrubia 0:820a69dfd200 364
gmatarrubia 0:820a69dfd200 365 \param [in] control Control Register value to set
gmatarrubia 0:820a69dfd200 366 */
gmatarrubia 0:820a69dfd200 367 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
gmatarrubia 0:820a69dfd200 368 {
gmatarrubia 0:820a69dfd200 369 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
gmatarrubia 0:820a69dfd200 370 }
gmatarrubia 0:820a69dfd200 371
gmatarrubia 0:820a69dfd200 372
gmatarrubia 0:820a69dfd200 373 /** \brief Get IPSR Register
gmatarrubia 0:820a69dfd200 374
gmatarrubia 0:820a69dfd200 375 This function returns the content of the IPSR Register.
gmatarrubia 0:820a69dfd200 376
gmatarrubia 0:820a69dfd200 377 \return IPSR Register value
gmatarrubia 0:820a69dfd200 378 */
gmatarrubia 0:820a69dfd200 379 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
gmatarrubia 0:820a69dfd200 380 {
gmatarrubia 0:820a69dfd200 381 uint32_t result;
gmatarrubia 0:820a69dfd200 382
gmatarrubia 0:820a69dfd200 383 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
gmatarrubia 0:820a69dfd200 384 return(result);
gmatarrubia 0:820a69dfd200 385 }
gmatarrubia 0:820a69dfd200 386
gmatarrubia 0:820a69dfd200 387
gmatarrubia 0:820a69dfd200 388 /** \brief Get APSR Register
gmatarrubia 0:820a69dfd200 389
gmatarrubia 0:820a69dfd200 390 This function returns the content of the APSR Register.
gmatarrubia 0:820a69dfd200 391
gmatarrubia 0:820a69dfd200 392 \return APSR Register value
gmatarrubia 0:820a69dfd200 393 */
gmatarrubia 0:820a69dfd200 394 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
gmatarrubia 0:820a69dfd200 395 {
gmatarrubia 0:820a69dfd200 396 uint32_t result;
gmatarrubia 0:820a69dfd200 397
gmatarrubia 0:820a69dfd200 398 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
gmatarrubia 0:820a69dfd200 399 return(result);
gmatarrubia 0:820a69dfd200 400 }
gmatarrubia 0:820a69dfd200 401
gmatarrubia 0:820a69dfd200 402
gmatarrubia 0:820a69dfd200 403 /** \brief Get xPSR Register
gmatarrubia 0:820a69dfd200 404
gmatarrubia 0:820a69dfd200 405 This function returns the content of the xPSR Register.
gmatarrubia 0:820a69dfd200 406
gmatarrubia 0:820a69dfd200 407 \return xPSR Register value
gmatarrubia 0:820a69dfd200 408 */
gmatarrubia 0:820a69dfd200 409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
gmatarrubia 0:820a69dfd200 410 {
gmatarrubia 0:820a69dfd200 411 uint32_t result;
gmatarrubia 0:820a69dfd200 412
gmatarrubia 0:820a69dfd200 413 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
gmatarrubia 0:820a69dfd200 414 return(result);
gmatarrubia 0:820a69dfd200 415 }
gmatarrubia 0:820a69dfd200 416
gmatarrubia 0:820a69dfd200 417
gmatarrubia 0:820a69dfd200 418 /** \brief Get Process Stack Pointer
gmatarrubia 0:820a69dfd200 419
gmatarrubia 0:820a69dfd200 420 This function returns the current value of the Process Stack Pointer (PSP).
gmatarrubia 0:820a69dfd200 421
gmatarrubia 0:820a69dfd200 422 \return PSP Register value
gmatarrubia 0:820a69dfd200 423 */
gmatarrubia 0:820a69dfd200 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
gmatarrubia 0:820a69dfd200 425 {
gmatarrubia 0:820a69dfd200 426 register uint32_t result;
gmatarrubia 0:820a69dfd200 427
gmatarrubia 0:820a69dfd200 428 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
gmatarrubia 0:820a69dfd200 429 return(result);
gmatarrubia 0:820a69dfd200 430 }
gmatarrubia 0:820a69dfd200 431
gmatarrubia 0:820a69dfd200 432
gmatarrubia 0:820a69dfd200 433 /** \brief Set Process Stack Pointer
gmatarrubia 0:820a69dfd200 434
gmatarrubia 0:820a69dfd200 435 This function assigns the given value to the Process Stack Pointer (PSP).
gmatarrubia 0:820a69dfd200 436
gmatarrubia 0:820a69dfd200 437 \param [in] topOfProcStack Process Stack Pointer value to set
gmatarrubia 0:820a69dfd200 438 */
gmatarrubia 0:820a69dfd200 439 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
gmatarrubia 0:820a69dfd200 440 {
gmatarrubia 0:820a69dfd200 441 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
gmatarrubia 0:820a69dfd200 442 }
gmatarrubia 0:820a69dfd200 443
gmatarrubia 0:820a69dfd200 444
gmatarrubia 0:820a69dfd200 445 /** \brief Get Main Stack Pointer
gmatarrubia 0:820a69dfd200 446
gmatarrubia 0:820a69dfd200 447 This function returns the current value of the Main Stack Pointer (MSP).
gmatarrubia 0:820a69dfd200 448
gmatarrubia 0:820a69dfd200 449 \return MSP Register value
gmatarrubia 0:820a69dfd200 450 */
gmatarrubia 0:820a69dfd200 451 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
gmatarrubia 0:820a69dfd200 452 {
gmatarrubia 0:820a69dfd200 453 register uint32_t result;
gmatarrubia 0:820a69dfd200 454
gmatarrubia 0:820a69dfd200 455 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
gmatarrubia 0:820a69dfd200 456 return(result);
gmatarrubia 0:820a69dfd200 457 }
gmatarrubia 0:820a69dfd200 458
gmatarrubia 0:820a69dfd200 459
gmatarrubia 0:820a69dfd200 460 /** \brief Set Main Stack Pointer
gmatarrubia 0:820a69dfd200 461
gmatarrubia 0:820a69dfd200 462 This function assigns the given value to the Main Stack Pointer (MSP).
gmatarrubia 0:820a69dfd200 463
gmatarrubia 0:820a69dfd200 464 \param [in] topOfMainStack Main Stack Pointer value to set
gmatarrubia 0:820a69dfd200 465 */
gmatarrubia 0:820a69dfd200 466 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
gmatarrubia 0:820a69dfd200 467 {
gmatarrubia 0:820a69dfd200 468 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
gmatarrubia 0:820a69dfd200 469 }
gmatarrubia 0:820a69dfd200 470
gmatarrubia 0:820a69dfd200 471
gmatarrubia 0:820a69dfd200 472 /** \brief Get Priority Mask
gmatarrubia 0:820a69dfd200 473
gmatarrubia 0:820a69dfd200 474 This function returns the current state of the priority mask bit from the Priority Mask Register.
gmatarrubia 0:820a69dfd200 475
gmatarrubia 0:820a69dfd200 476 \return Priority Mask value
gmatarrubia 0:820a69dfd200 477 */
gmatarrubia 0:820a69dfd200 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
gmatarrubia 0:820a69dfd200 479 {
gmatarrubia 0:820a69dfd200 480 uint32_t result;
gmatarrubia 0:820a69dfd200 481
gmatarrubia 0:820a69dfd200 482 __ASM volatile ("MRS %0, primask" : "=r" (result) );
gmatarrubia 0:820a69dfd200 483 return(result);
gmatarrubia 0:820a69dfd200 484 }
gmatarrubia 0:820a69dfd200 485
gmatarrubia 0:820a69dfd200 486
gmatarrubia 0:820a69dfd200 487 /** \brief Set Priority Mask
gmatarrubia 0:820a69dfd200 488
gmatarrubia 0:820a69dfd200 489 This function assigns the given value to the Priority Mask Register.
gmatarrubia 0:820a69dfd200 490
gmatarrubia 0:820a69dfd200 491 \param [in] priMask Priority Mask
gmatarrubia 0:820a69dfd200 492 */
gmatarrubia 0:820a69dfd200 493 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
gmatarrubia 0:820a69dfd200 494 {
gmatarrubia 0:820a69dfd200 495 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
gmatarrubia 0:820a69dfd200 496 }
gmatarrubia 0:820a69dfd200 497
gmatarrubia 0:820a69dfd200 498
gmatarrubia 0:820a69dfd200 499 #if (__CORTEX_M >= 0x03)
gmatarrubia 0:820a69dfd200 500
gmatarrubia 0:820a69dfd200 501 /** \brief Enable FIQ
gmatarrubia 0:820a69dfd200 502
gmatarrubia 0:820a69dfd200 503 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
gmatarrubia 0:820a69dfd200 504 Can only be executed in Privileged modes.
gmatarrubia 0:820a69dfd200 505 */
gmatarrubia 0:820a69dfd200 506 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
gmatarrubia 0:820a69dfd200 507 {
gmatarrubia 0:820a69dfd200 508 __ASM volatile ("cpsie f" : : : "memory");
gmatarrubia 0:820a69dfd200 509 }
gmatarrubia 0:820a69dfd200 510
gmatarrubia 0:820a69dfd200 511
gmatarrubia 0:820a69dfd200 512 /** \brief Disable FIQ
gmatarrubia 0:820a69dfd200 513
gmatarrubia 0:820a69dfd200 514 This function disables FIQ interrupts by setting the F-bit in the CPSR.
gmatarrubia 0:820a69dfd200 515 Can only be executed in Privileged modes.
gmatarrubia 0:820a69dfd200 516 */
gmatarrubia 0:820a69dfd200 517 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
gmatarrubia 0:820a69dfd200 518 {
gmatarrubia 0:820a69dfd200 519 __ASM volatile ("cpsid f" : : : "memory");
gmatarrubia 0:820a69dfd200 520 }
gmatarrubia 0:820a69dfd200 521
gmatarrubia 0:820a69dfd200 522
gmatarrubia 0:820a69dfd200 523 /** \brief Get Base Priority
gmatarrubia 0:820a69dfd200 524
gmatarrubia 0:820a69dfd200 525 This function returns the current value of the Base Priority register.
gmatarrubia 0:820a69dfd200 526
gmatarrubia 0:820a69dfd200 527 \return Base Priority register value
gmatarrubia 0:820a69dfd200 528 */
gmatarrubia 0:820a69dfd200 529 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
gmatarrubia 0:820a69dfd200 530 {
gmatarrubia 0:820a69dfd200 531 uint32_t result;
gmatarrubia 0:820a69dfd200 532
gmatarrubia 0:820a69dfd200 533 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
gmatarrubia 0:820a69dfd200 534 return(result);
gmatarrubia 0:820a69dfd200 535 }
gmatarrubia 0:820a69dfd200 536
gmatarrubia 0:820a69dfd200 537
gmatarrubia 0:820a69dfd200 538 /** \brief Set Base Priority
gmatarrubia 0:820a69dfd200 539
gmatarrubia 0:820a69dfd200 540 This function assigns the given value to the Base Priority register.
gmatarrubia 0:820a69dfd200 541
gmatarrubia 0:820a69dfd200 542 \param [in] basePri Base Priority value to set
gmatarrubia 0:820a69dfd200 543 */
gmatarrubia 0:820a69dfd200 544 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
gmatarrubia 0:820a69dfd200 545 {
gmatarrubia 0:820a69dfd200 546 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
gmatarrubia 0:820a69dfd200 547 }
gmatarrubia 0:820a69dfd200 548
gmatarrubia 0:820a69dfd200 549
gmatarrubia 0:820a69dfd200 550 /** \brief Get Fault Mask
gmatarrubia 0:820a69dfd200 551
gmatarrubia 0:820a69dfd200 552 This function returns the current value of the Fault Mask register.
gmatarrubia 0:820a69dfd200 553
gmatarrubia 0:820a69dfd200 554 \return Fault Mask register value
gmatarrubia 0:820a69dfd200 555 */
gmatarrubia 0:820a69dfd200 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
gmatarrubia 0:820a69dfd200 557 {
gmatarrubia 0:820a69dfd200 558 uint32_t result;
gmatarrubia 0:820a69dfd200 559
gmatarrubia 0:820a69dfd200 560 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
gmatarrubia 0:820a69dfd200 561 return(result);
gmatarrubia 0:820a69dfd200 562 }
gmatarrubia 0:820a69dfd200 563
gmatarrubia 0:820a69dfd200 564
gmatarrubia 0:820a69dfd200 565 /** \brief Set Fault Mask
gmatarrubia 0:820a69dfd200 566
gmatarrubia 0:820a69dfd200 567 This function assigns the given value to the Fault Mask register.
gmatarrubia 0:820a69dfd200 568
gmatarrubia 0:820a69dfd200 569 \param [in] faultMask Fault Mask value to set
gmatarrubia 0:820a69dfd200 570 */
gmatarrubia 0:820a69dfd200 571 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
gmatarrubia 0:820a69dfd200 572 {
gmatarrubia 0:820a69dfd200 573 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
gmatarrubia 0:820a69dfd200 574 }
gmatarrubia 0:820a69dfd200 575
gmatarrubia 0:820a69dfd200 576 #endif /* (__CORTEX_M >= 0x03) */
gmatarrubia 0:820a69dfd200 577
gmatarrubia 0:820a69dfd200 578
gmatarrubia 0:820a69dfd200 579 #if (__CORTEX_M == 0x04)
gmatarrubia 0:820a69dfd200 580
gmatarrubia 0:820a69dfd200 581 /** \brief Get FPSCR
gmatarrubia 0:820a69dfd200 582
gmatarrubia 0:820a69dfd200 583 This function returns the current value of the Floating Point Status/Control register.
gmatarrubia 0:820a69dfd200 584
gmatarrubia 0:820a69dfd200 585 \return Floating Point Status/Control register value
gmatarrubia 0:820a69dfd200 586 */
gmatarrubia 0:820a69dfd200 587 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
gmatarrubia 0:820a69dfd200 588 {
gmatarrubia 0:820a69dfd200 589 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
gmatarrubia 0:820a69dfd200 590 uint32_t result;
gmatarrubia 0:820a69dfd200 591
gmatarrubia 0:820a69dfd200 592 /* Empty asm statement works as a scheduling barrier */
gmatarrubia 0:820a69dfd200 593 __ASM volatile ("");
gmatarrubia 0:820a69dfd200 594 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
gmatarrubia 0:820a69dfd200 595 __ASM volatile ("");
gmatarrubia 0:820a69dfd200 596 return(result);
gmatarrubia 0:820a69dfd200 597 #else
gmatarrubia 0:820a69dfd200 598 return(0);
gmatarrubia 0:820a69dfd200 599 #endif
gmatarrubia 0:820a69dfd200 600 }
gmatarrubia 0:820a69dfd200 601
gmatarrubia 0:820a69dfd200 602
gmatarrubia 0:820a69dfd200 603 /** \brief Set FPSCR
gmatarrubia 0:820a69dfd200 604
gmatarrubia 0:820a69dfd200 605 This function assigns the given value to the Floating Point Status/Control register.
gmatarrubia 0:820a69dfd200 606
gmatarrubia 0:820a69dfd200 607 \param [in] fpscr Floating Point Status/Control value to set
gmatarrubia 0:820a69dfd200 608 */
gmatarrubia 0:820a69dfd200 609 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
gmatarrubia 0:820a69dfd200 610 {
gmatarrubia 0:820a69dfd200 611 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
gmatarrubia 0:820a69dfd200 612 /* Empty asm statement works as a scheduling barrier */
gmatarrubia 0:820a69dfd200 613 __ASM volatile ("");
gmatarrubia 0:820a69dfd200 614 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
gmatarrubia 0:820a69dfd200 615 __ASM volatile ("");
gmatarrubia 0:820a69dfd200 616 #endif
gmatarrubia 0:820a69dfd200 617 }
gmatarrubia 0:820a69dfd200 618
gmatarrubia 0:820a69dfd200 619 #endif /* (__CORTEX_M == 0x04) */
gmatarrubia 0:820a69dfd200 620
gmatarrubia 0:820a69dfd200 621
gmatarrubia 0:820a69dfd200 622 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
gmatarrubia 0:820a69dfd200 623 /* TASKING carm specific functions */
gmatarrubia 0:820a69dfd200 624
gmatarrubia 0:820a69dfd200 625 /*
gmatarrubia 0:820a69dfd200 626 * The CMSIS functions have been implemented as intrinsics in the compiler.
gmatarrubia 0:820a69dfd200 627 * Please use "carm -?i" to get an up to date list of all instrinsics,
gmatarrubia 0:820a69dfd200 628 * Including the CMSIS ones.
gmatarrubia 0:820a69dfd200 629 */
gmatarrubia 0:820a69dfd200 630
gmatarrubia 0:820a69dfd200 631 #endif
gmatarrubia 0:820a69dfd200 632
gmatarrubia 0:820a69dfd200 633 /*@} end of CMSIS_Core_RegAccFunctions */
gmatarrubia 0:820a69dfd200 634
gmatarrubia 0:820a69dfd200 635
gmatarrubia 0:820a69dfd200 636 #endif /* __CORE_CMFUNC_H */