Gonzalo Matarrubia / Mbed LPC1549 mod

This repo contains the libraries of Mbed for LPC1549 with following changes: - IAP commands. - EEPROM write and read. - UART write and read (public) - CAN can_s -> LPC_C_CAN0_Type *can

mbed/TARGET_LPC1549/core_cm4_simd.h@0:820a69dfd200, 2015-04-14 (annotated)

Committer:
gmatarrubia
Date:
Tue Apr 14 15:00:13 2015 +0200
Revision:
0:820a69dfd200
Initial repo. IAP commands, EEPROM write/read, UART write/read, CAN

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gmatarrubia 0:820a69dfd200 1 /**************************************************************************//**
gmatarrubia 0:820a69dfd200 2 * @file core_cm4_simd.h
gmatarrubia 0:820a69dfd200 3 * @brief CMSIS Cortex-M4 SIMD Header File
gmatarrubia 0:820a69dfd200 4 * @version V3.20
gmatarrubia 0:820a69dfd200 5 * @date 25. February 2013
gmatarrubia 0:820a69dfd200 6 *
gmatarrubia 0:820a69dfd200 7 * @note
gmatarrubia 0:820a69dfd200 8 *
gmatarrubia 0:820a69dfd200 9 ******************************************************************************/
gmatarrubia 0:820a69dfd200 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
gmatarrubia 0:820a69dfd200 11
gmatarrubia 0:820a69dfd200 12 All rights reserved.
gmatarrubia 0:820a69dfd200 13 Redistribution and use in source and binary forms, with or without
gmatarrubia 0:820a69dfd200 14 modification, are permitted provided that the following conditions are met:
gmatarrubia 0:820a69dfd200 15 - Redistributions of source code must retain the above copyright
gmatarrubia 0:820a69dfd200 16 notice, this list of conditions and the following disclaimer.
gmatarrubia 0:820a69dfd200 17 - Redistributions in binary form must reproduce the above copyright
gmatarrubia 0:820a69dfd200 18 notice, this list of conditions and the following disclaimer in the
gmatarrubia 0:820a69dfd200 19 documentation and/or other materials provided with the distribution.
gmatarrubia 0:820a69dfd200 20 - Neither the name of ARM nor the names of its contributors may be used
gmatarrubia 0:820a69dfd200 21 to endorse or promote products derived from this software without
gmatarrubia 0:820a69dfd200 22 specific prior written permission.
gmatarrubia 0:820a69dfd200 23 *
gmatarrubia 0:820a69dfd200 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
gmatarrubia 0:820a69dfd200 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
gmatarrubia 0:820a69dfd200 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
gmatarrubia 0:820a69dfd200 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
gmatarrubia 0:820a69dfd200 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
gmatarrubia 0:820a69dfd200 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
gmatarrubia 0:820a69dfd200 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
gmatarrubia 0:820a69dfd200 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
gmatarrubia 0:820a69dfd200 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
gmatarrubia 0:820a69dfd200 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
gmatarrubia 0:820a69dfd200 34 POSSIBILITY OF SUCH DAMAGE.
gmatarrubia 0:820a69dfd200 35 ---------------------------------------------------------------------------*/
gmatarrubia 0:820a69dfd200 36
gmatarrubia 0:820a69dfd200 37
gmatarrubia 0:820a69dfd200 38 #ifdef __cplusplus
gmatarrubia 0:820a69dfd200 39 extern "C" {
gmatarrubia 0:820a69dfd200 40 #endif
gmatarrubia 0:820a69dfd200 41
gmatarrubia 0:820a69dfd200 42 #ifndef __CORE_CM4_SIMD_H
gmatarrubia 0:820a69dfd200 43 #define __CORE_CM4_SIMD_H
gmatarrubia 0:820a69dfd200 44
gmatarrubia 0:820a69dfd200 45
gmatarrubia 0:820a69dfd200 46 /*******************************************************************************
gmatarrubia 0:820a69dfd200 47 * Hardware Abstraction Layer
gmatarrubia 0:820a69dfd200 48 ******************************************************************************/
gmatarrubia 0:820a69dfd200 49
gmatarrubia 0:820a69dfd200 50
gmatarrubia 0:820a69dfd200 51 /* ################### Compiler specific Intrinsics ########################### */
gmatarrubia 0:820a69dfd200 52 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
gmatarrubia 0:820a69dfd200 53 Access to dedicated SIMD instructions
gmatarrubia 0:820a69dfd200 54 @{
gmatarrubia 0:820a69dfd200 55 */
gmatarrubia 0:820a69dfd200 56
gmatarrubia 0:820a69dfd200 57 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
gmatarrubia 0:820a69dfd200 58 /* ARM armcc specific functions */
gmatarrubia 0:820a69dfd200 59
gmatarrubia 0:820a69dfd200 60 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
gmatarrubia 0:820a69dfd200 61 #define __SADD8 __sadd8
gmatarrubia 0:820a69dfd200 62 #define __QADD8 __qadd8
gmatarrubia 0:820a69dfd200 63 #define __SHADD8 __shadd8
gmatarrubia 0:820a69dfd200 64 #define __UADD8 __uadd8
gmatarrubia 0:820a69dfd200 65 #define __UQADD8 __uqadd8
gmatarrubia 0:820a69dfd200 66 #define __UHADD8 __uhadd8
gmatarrubia 0:820a69dfd200 67 #define __SSUB8 __ssub8
gmatarrubia 0:820a69dfd200 68 #define __QSUB8 __qsub8
gmatarrubia 0:820a69dfd200 69 #define __SHSUB8 __shsub8
gmatarrubia 0:820a69dfd200 70 #define __USUB8 __usub8
gmatarrubia 0:820a69dfd200 71 #define __UQSUB8 __uqsub8
gmatarrubia 0:820a69dfd200 72 #define __UHSUB8 __uhsub8
gmatarrubia 0:820a69dfd200 73 #define __SADD16 __sadd16
gmatarrubia 0:820a69dfd200 74 #define __QADD16 __qadd16
gmatarrubia 0:820a69dfd200 75 #define __SHADD16 __shadd16
gmatarrubia 0:820a69dfd200 76 #define __UADD16 __uadd16
gmatarrubia 0:820a69dfd200 77 #define __UQADD16 __uqadd16
gmatarrubia 0:820a69dfd200 78 #define __UHADD16 __uhadd16
gmatarrubia 0:820a69dfd200 79 #define __SSUB16 __ssub16
gmatarrubia 0:820a69dfd200 80 #define __QSUB16 __qsub16
gmatarrubia 0:820a69dfd200 81 #define __SHSUB16 __shsub16
gmatarrubia 0:820a69dfd200 82 #define __USUB16 __usub16
gmatarrubia 0:820a69dfd200 83 #define __UQSUB16 __uqsub16
gmatarrubia 0:820a69dfd200 84 #define __UHSUB16 __uhsub16
gmatarrubia 0:820a69dfd200 85 #define __SASX __sasx
gmatarrubia 0:820a69dfd200 86 #define __QASX __qasx
gmatarrubia 0:820a69dfd200 87 #define __SHASX __shasx
gmatarrubia 0:820a69dfd200 88 #define __UASX __uasx
gmatarrubia 0:820a69dfd200 89 #define __UQASX __uqasx
gmatarrubia 0:820a69dfd200 90 #define __UHASX __uhasx
gmatarrubia 0:820a69dfd200 91 #define __SSAX __ssax
gmatarrubia 0:820a69dfd200 92 #define __QSAX __qsax
gmatarrubia 0:820a69dfd200 93 #define __SHSAX __shsax
gmatarrubia 0:820a69dfd200 94 #define __USAX __usax
gmatarrubia 0:820a69dfd200 95 #define __UQSAX __uqsax
gmatarrubia 0:820a69dfd200 96 #define __UHSAX __uhsax
gmatarrubia 0:820a69dfd200 97 #define __USAD8 __usad8
gmatarrubia 0:820a69dfd200 98 #define __USADA8 __usada8
gmatarrubia 0:820a69dfd200 99 #define __SSAT16 __ssat16
gmatarrubia 0:820a69dfd200 100 #define __USAT16 __usat16
gmatarrubia 0:820a69dfd200 101 #define __UXTB16 __uxtb16
gmatarrubia 0:820a69dfd200 102 #define __UXTAB16 __uxtab16
gmatarrubia 0:820a69dfd200 103 #define __SXTB16 __sxtb16
gmatarrubia 0:820a69dfd200 104 #define __SXTAB16 __sxtab16
gmatarrubia 0:820a69dfd200 105 #define __SMUAD __smuad
gmatarrubia 0:820a69dfd200 106 #define __SMUADX __smuadx
gmatarrubia 0:820a69dfd200 107 #define __SMLAD __smlad
gmatarrubia 0:820a69dfd200 108 #define __SMLADX __smladx
gmatarrubia 0:820a69dfd200 109 #define __SMLALD __smlald
gmatarrubia 0:820a69dfd200 110 #define __SMLALDX __smlaldx
gmatarrubia 0:820a69dfd200 111 #define __SMUSD __smusd
gmatarrubia 0:820a69dfd200 112 #define __SMUSDX __smusdx
gmatarrubia 0:820a69dfd200 113 #define __SMLSD __smlsd
gmatarrubia 0:820a69dfd200 114 #define __SMLSDX __smlsdx
gmatarrubia 0:820a69dfd200 115 #define __SMLSLD __smlsld
gmatarrubia 0:820a69dfd200 116 #define __SMLSLDX __smlsldx
gmatarrubia 0:820a69dfd200 117 #define __SEL __sel
gmatarrubia 0:820a69dfd200 118 #define __QADD __qadd
gmatarrubia 0:820a69dfd200 119 #define __QSUB __qsub
gmatarrubia 0:820a69dfd200 120
gmatarrubia 0:820a69dfd200 121 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
gmatarrubia 0:820a69dfd200 122 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
gmatarrubia 0:820a69dfd200 123
gmatarrubia 0:820a69dfd200 124 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
gmatarrubia 0:820a69dfd200 125 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
gmatarrubia 0:820a69dfd200 126
gmatarrubia 0:820a69dfd200 127 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
gmatarrubia 0:820a69dfd200 128 ((int64_t)(ARG3) << 32) ) >> 32))
gmatarrubia 0:820a69dfd200 129
gmatarrubia 0:820a69dfd200 130 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
gmatarrubia 0:820a69dfd200 131
gmatarrubia 0:820a69dfd200 132
gmatarrubia 0:820a69dfd200 133
gmatarrubia 0:820a69dfd200 134 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
gmatarrubia 0:820a69dfd200 135 /* IAR iccarm specific functions */
gmatarrubia 0:820a69dfd200 136
gmatarrubia 0:820a69dfd200 137 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
gmatarrubia 0:820a69dfd200 138 #include <cmsis_iar.h>
gmatarrubia 0:820a69dfd200 139
gmatarrubia 0:820a69dfd200 140 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
gmatarrubia 0:820a69dfd200 141
gmatarrubia 0:820a69dfd200 142
gmatarrubia 0:820a69dfd200 143
gmatarrubia 0:820a69dfd200 144 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
gmatarrubia 0:820a69dfd200 145 /* TI CCS specific functions */
gmatarrubia 0:820a69dfd200 146
gmatarrubia 0:820a69dfd200 147 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
gmatarrubia 0:820a69dfd200 148 #include <cmsis_ccs.h>
gmatarrubia 0:820a69dfd200 149
gmatarrubia 0:820a69dfd200 150 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
gmatarrubia 0:820a69dfd200 151
gmatarrubia 0:820a69dfd200 152
gmatarrubia 0:820a69dfd200 153
gmatarrubia 0:820a69dfd200 154 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
gmatarrubia 0:820a69dfd200 155 /* GNU gcc specific functions */
gmatarrubia 0:820a69dfd200 156
gmatarrubia 0:820a69dfd200 157 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
gmatarrubia 0:820a69dfd200 158 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 159 {
gmatarrubia 0:820a69dfd200 160 uint32_t result;
gmatarrubia 0:820a69dfd200 161
gmatarrubia 0:820a69dfd200 162 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 163 return(result);
gmatarrubia 0:820a69dfd200 164 }
gmatarrubia 0:820a69dfd200 165
gmatarrubia 0:820a69dfd200 166 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 167 {
gmatarrubia 0:820a69dfd200 168 uint32_t result;
gmatarrubia 0:820a69dfd200 169
gmatarrubia 0:820a69dfd200 170 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 171 return(result);
gmatarrubia 0:820a69dfd200 172 }
gmatarrubia 0:820a69dfd200 173
gmatarrubia 0:820a69dfd200 174 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 175 {
gmatarrubia 0:820a69dfd200 176 uint32_t result;
gmatarrubia 0:820a69dfd200 177
gmatarrubia 0:820a69dfd200 178 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 179 return(result);
gmatarrubia 0:820a69dfd200 180 }
gmatarrubia 0:820a69dfd200 181
gmatarrubia 0:820a69dfd200 182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 183 {
gmatarrubia 0:820a69dfd200 184 uint32_t result;
gmatarrubia 0:820a69dfd200 185
gmatarrubia 0:820a69dfd200 186 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 187 return(result);
gmatarrubia 0:820a69dfd200 188 }
gmatarrubia 0:820a69dfd200 189
gmatarrubia 0:820a69dfd200 190 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 191 {
gmatarrubia 0:820a69dfd200 192 uint32_t result;
gmatarrubia 0:820a69dfd200 193
gmatarrubia 0:820a69dfd200 194 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 195 return(result);
gmatarrubia 0:820a69dfd200 196 }
gmatarrubia 0:820a69dfd200 197
gmatarrubia 0:820a69dfd200 198 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 199 {
gmatarrubia 0:820a69dfd200 200 uint32_t result;
gmatarrubia 0:820a69dfd200 201
gmatarrubia 0:820a69dfd200 202 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 203 return(result);
gmatarrubia 0:820a69dfd200 204 }
gmatarrubia 0:820a69dfd200 205
gmatarrubia 0:820a69dfd200 206
gmatarrubia 0:820a69dfd200 207 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 208 {
gmatarrubia 0:820a69dfd200 209 uint32_t result;
gmatarrubia 0:820a69dfd200 210
gmatarrubia 0:820a69dfd200 211 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 212 return(result);
gmatarrubia 0:820a69dfd200 213 }
gmatarrubia 0:820a69dfd200 214
gmatarrubia 0:820a69dfd200 215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 216 {
gmatarrubia 0:820a69dfd200 217 uint32_t result;
gmatarrubia 0:820a69dfd200 218
gmatarrubia 0:820a69dfd200 219 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 220 return(result);
gmatarrubia 0:820a69dfd200 221 }
gmatarrubia 0:820a69dfd200 222
gmatarrubia 0:820a69dfd200 223 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 224 {
gmatarrubia 0:820a69dfd200 225 uint32_t result;
gmatarrubia 0:820a69dfd200 226
gmatarrubia 0:820a69dfd200 227 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 228 return(result);
gmatarrubia 0:820a69dfd200 229 }
gmatarrubia 0:820a69dfd200 230
gmatarrubia 0:820a69dfd200 231 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 232 {
gmatarrubia 0:820a69dfd200 233 uint32_t result;
gmatarrubia 0:820a69dfd200 234
gmatarrubia 0:820a69dfd200 235 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 236 return(result);
gmatarrubia 0:820a69dfd200 237 }
gmatarrubia 0:820a69dfd200 238
gmatarrubia 0:820a69dfd200 239 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 240 {
gmatarrubia 0:820a69dfd200 241 uint32_t result;
gmatarrubia 0:820a69dfd200 242
gmatarrubia 0:820a69dfd200 243 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 244 return(result);
gmatarrubia 0:820a69dfd200 245 }
gmatarrubia 0:820a69dfd200 246
gmatarrubia 0:820a69dfd200 247 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 248 {
gmatarrubia 0:820a69dfd200 249 uint32_t result;
gmatarrubia 0:820a69dfd200 250
gmatarrubia 0:820a69dfd200 251 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 252 return(result);
gmatarrubia 0:820a69dfd200 253 }
gmatarrubia 0:820a69dfd200 254
gmatarrubia 0:820a69dfd200 255
gmatarrubia 0:820a69dfd200 256 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 257 {
gmatarrubia 0:820a69dfd200 258 uint32_t result;
gmatarrubia 0:820a69dfd200 259
gmatarrubia 0:820a69dfd200 260 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 261 return(result);
gmatarrubia 0:820a69dfd200 262 }
gmatarrubia 0:820a69dfd200 263
gmatarrubia 0:820a69dfd200 264 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 265 {
gmatarrubia 0:820a69dfd200 266 uint32_t result;
gmatarrubia 0:820a69dfd200 267
gmatarrubia 0:820a69dfd200 268 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 269 return(result);
gmatarrubia 0:820a69dfd200 270 }
gmatarrubia 0:820a69dfd200 271
gmatarrubia 0:820a69dfd200 272 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 273 {
gmatarrubia 0:820a69dfd200 274 uint32_t result;
gmatarrubia 0:820a69dfd200 275
gmatarrubia 0:820a69dfd200 276 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 277 return(result);
gmatarrubia 0:820a69dfd200 278 }
gmatarrubia 0:820a69dfd200 279
gmatarrubia 0:820a69dfd200 280 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 281 {
gmatarrubia 0:820a69dfd200 282 uint32_t result;
gmatarrubia 0:820a69dfd200 283
gmatarrubia 0:820a69dfd200 284 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 285 return(result);
gmatarrubia 0:820a69dfd200 286 }
gmatarrubia 0:820a69dfd200 287
gmatarrubia 0:820a69dfd200 288 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 289 {
gmatarrubia 0:820a69dfd200 290 uint32_t result;
gmatarrubia 0:820a69dfd200 291
gmatarrubia 0:820a69dfd200 292 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 293 return(result);
gmatarrubia 0:820a69dfd200 294 }
gmatarrubia 0:820a69dfd200 295
gmatarrubia 0:820a69dfd200 296 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 297 {
gmatarrubia 0:820a69dfd200 298 uint32_t result;
gmatarrubia 0:820a69dfd200 299
gmatarrubia 0:820a69dfd200 300 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 301 return(result);
gmatarrubia 0:820a69dfd200 302 }
gmatarrubia 0:820a69dfd200 303
gmatarrubia 0:820a69dfd200 304 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 305 {
gmatarrubia 0:820a69dfd200 306 uint32_t result;
gmatarrubia 0:820a69dfd200 307
gmatarrubia 0:820a69dfd200 308 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 309 return(result);
gmatarrubia 0:820a69dfd200 310 }
gmatarrubia 0:820a69dfd200 311
gmatarrubia 0:820a69dfd200 312 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 313 {
gmatarrubia 0:820a69dfd200 314 uint32_t result;
gmatarrubia 0:820a69dfd200 315
gmatarrubia 0:820a69dfd200 316 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 317 return(result);
gmatarrubia 0:820a69dfd200 318 }
gmatarrubia 0:820a69dfd200 319
gmatarrubia 0:820a69dfd200 320 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 321 {
gmatarrubia 0:820a69dfd200 322 uint32_t result;
gmatarrubia 0:820a69dfd200 323
gmatarrubia 0:820a69dfd200 324 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 325 return(result);
gmatarrubia 0:820a69dfd200 326 }
gmatarrubia 0:820a69dfd200 327
gmatarrubia 0:820a69dfd200 328 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 329 {
gmatarrubia 0:820a69dfd200 330 uint32_t result;
gmatarrubia 0:820a69dfd200 331
gmatarrubia 0:820a69dfd200 332 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 333 return(result);
gmatarrubia 0:820a69dfd200 334 }
gmatarrubia 0:820a69dfd200 335
gmatarrubia 0:820a69dfd200 336 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 337 {
gmatarrubia 0:820a69dfd200 338 uint32_t result;
gmatarrubia 0:820a69dfd200 339
gmatarrubia 0:820a69dfd200 340 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 341 return(result);
gmatarrubia 0:820a69dfd200 342 }
gmatarrubia 0:820a69dfd200 343
gmatarrubia 0:820a69dfd200 344 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 345 {
gmatarrubia 0:820a69dfd200 346 uint32_t result;
gmatarrubia 0:820a69dfd200 347
gmatarrubia 0:820a69dfd200 348 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 349 return(result);
gmatarrubia 0:820a69dfd200 350 }
gmatarrubia 0:820a69dfd200 351
gmatarrubia 0:820a69dfd200 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 353 {
gmatarrubia 0:820a69dfd200 354 uint32_t result;
gmatarrubia 0:820a69dfd200 355
gmatarrubia 0:820a69dfd200 356 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 357 return(result);
gmatarrubia 0:820a69dfd200 358 }
gmatarrubia 0:820a69dfd200 359
gmatarrubia 0:820a69dfd200 360 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 361 {
gmatarrubia 0:820a69dfd200 362 uint32_t result;
gmatarrubia 0:820a69dfd200 363
gmatarrubia 0:820a69dfd200 364 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 365 return(result);
gmatarrubia 0:820a69dfd200 366 }
gmatarrubia 0:820a69dfd200 367
gmatarrubia 0:820a69dfd200 368 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 369 {
gmatarrubia 0:820a69dfd200 370 uint32_t result;
gmatarrubia 0:820a69dfd200 371
gmatarrubia 0:820a69dfd200 372 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 373 return(result);
gmatarrubia 0:820a69dfd200 374 }
gmatarrubia 0:820a69dfd200 375
gmatarrubia 0:820a69dfd200 376 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 377 {
gmatarrubia 0:820a69dfd200 378 uint32_t result;
gmatarrubia 0:820a69dfd200 379
gmatarrubia 0:820a69dfd200 380 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 381 return(result);
gmatarrubia 0:820a69dfd200 382 }
gmatarrubia 0:820a69dfd200 383
gmatarrubia 0:820a69dfd200 384 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 385 {
gmatarrubia 0:820a69dfd200 386 uint32_t result;
gmatarrubia 0:820a69dfd200 387
gmatarrubia 0:820a69dfd200 388 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 389 return(result);
gmatarrubia 0:820a69dfd200 390 }
gmatarrubia 0:820a69dfd200 391
gmatarrubia 0:820a69dfd200 392 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 393 {
gmatarrubia 0:820a69dfd200 394 uint32_t result;
gmatarrubia 0:820a69dfd200 395
gmatarrubia 0:820a69dfd200 396 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 397 return(result);
gmatarrubia 0:820a69dfd200 398 }
gmatarrubia 0:820a69dfd200 399
gmatarrubia 0:820a69dfd200 400 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 401 {
gmatarrubia 0:820a69dfd200 402 uint32_t result;
gmatarrubia 0:820a69dfd200 403
gmatarrubia 0:820a69dfd200 404 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 405 return(result);
gmatarrubia 0:820a69dfd200 406 }
gmatarrubia 0:820a69dfd200 407
gmatarrubia 0:820a69dfd200 408 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 409 {
gmatarrubia 0:820a69dfd200 410 uint32_t result;
gmatarrubia 0:820a69dfd200 411
gmatarrubia 0:820a69dfd200 412 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 413 return(result);
gmatarrubia 0:820a69dfd200 414 }
gmatarrubia 0:820a69dfd200 415
gmatarrubia 0:820a69dfd200 416 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 417 {
gmatarrubia 0:820a69dfd200 418 uint32_t result;
gmatarrubia 0:820a69dfd200 419
gmatarrubia 0:820a69dfd200 420 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 421 return(result);
gmatarrubia 0:820a69dfd200 422 }
gmatarrubia 0:820a69dfd200 423
gmatarrubia 0:820a69dfd200 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 425 {
gmatarrubia 0:820a69dfd200 426 uint32_t result;
gmatarrubia 0:820a69dfd200 427
gmatarrubia 0:820a69dfd200 428 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 429 return(result);
gmatarrubia 0:820a69dfd200 430 }
gmatarrubia 0:820a69dfd200 431
gmatarrubia 0:820a69dfd200 432 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 433 {
gmatarrubia 0:820a69dfd200 434 uint32_t result;
gmatarrubia 0:820a69dfd200 435
gmatarrubia 0:820a69dfd200 436 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 437 return(result);
gmatarrubia 0:820a69dfd200 438 }
gmatarrubia 0:820a69dfd200 439
gmatarrubia 0:820a69dfd200 440 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 441 {
gmatarrubia 0:820a69dfd200 442 uint32_t result;
gmatarrubia 0:820a69dfd200 443
gmatarrubia 0:820a69dfd200 444 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 445 return(result);
gmatarrubia 0:820a69dfd200 446 }
gmatarrubia 0:820a69dfd200 447
gmatarrubia 0:820a69dfd200 448 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 449 {
gmatarrubia 0:820a69dfd200 450 uint32_t result;
gmatarrubia 0:820a69dfd200 451
gmatarrubia 0:820a69dfd200 452 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 453 return(result);
gmatarrubia 0:820a69dfd200 454 }
gmatarrubia 0:820a69dfd200 455
gmatarrubia 0:820a69dfd200 456 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
gmatarrubia 0:820a69dfd200 457 {
gmatarrubia 0:820a69dfd200 458 uint32_t result;
gmatarrubia 0:820a69dfd200 459
gmatarrubia 0:820a69dfd200 460 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
gmatarrubia 0:820a69dfd200 461 return(result);
gmatarrubia 0:820a69dfd200 462 }
gmatarrubia 0:820a69dfd200 463
gmatarrubia 0:820a69dfd200 464 #define __SSAT16(ARG1,ARG2) \
gmatarrubia 0:820a69dfd200 465 ({ \
gmatarrubia 0:820a69dfd200 466 uint32_t __RES, __ARG1 = (ARG1); \
gmatarrubia 0:820a69dfd200 467 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
gmatarrubia 0:820a69dfd200 468 __RES; \
gmatarrubia 0:820a69dfd200 469 })
gmatarrubia 0:820a69dfd200 470
gmatarrubia 0:820a69dfd200 471 #define __USAT16(ARG1,ARG2) \
gmatarrubia 0:820a69dfd200 472 ({ \
gmatarrubia 0:820a69dfd200 473 uint32_t __RES, __ARG1 = (ARG1); \
gmatarrubia 0:820a69dfd200 474 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
gmatarrubia 0:820a69dfd200 475 __RES; \
gmatarrubia 0:820a69dfd200 476 })
gmatarrubia 0:820a69dfd200 477
gmatarrubia 0:820a69dfd200 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
gmatarrubia 0:820a69dfd200 479 {
gmatarrubia 0:820a69dfd200 480 uint32_t result;
gmatarrubia 0:820a69dfd200 481
gmatarrubia 0:820a69dfd200 482 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
gmatarrubia 0:820a69dfd200 483 return(result);
gmatarrubia 0:820a69dfd200 484 }
gmatarrubia 0:820a69dfd200 485
gmatarrubia 0:820a69dfd200 486 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 487 {
gmatarrubia 0:820a69dfd200 488 uint32_t result;
gmatarrubia 0:820a69dfd200 489
gmatarrubia 0:820a69dfd200 490 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 491 return(result);
gmatarrubia 0:820a69dfd200 492 }
gmatarrubia 0:820a69dfd200 493
gmatarrubia 0:820a69dfd200 494 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
gmatarrubia 0:820a69dfd200 495 {
gmatarrubia 0:820a69dfd200 496 uint32_t result;
gmatarrubia 0:820a69dfd200 497
gmatarrubia 0:820a69dfd200 498 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
gmatarrubia 0:820a69dfd200 499 return(result);
gmatarrubia 0:820a69dfd200 500 }
gmatarrubia 0:820a69dfd200 501
gmatarrubia 0:820a69dfd200 502 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 503 {
gmatarrubia 0:820a69dfd200 504 uint32_t result;
gmatarrubia 0:820a69dfd200 505
gmatarrubia 0:820a69dfd200 506 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 507 return(result);
gmatarrubia 0:820a69dfd200 508 }
gmatarrubia 0:820a69dfd200 509
gmatarrubia 0:820a69dfd200 510 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 511 {
gmatarrubia 0:820a69dfd200 512 uint32_t result;
gmatarrubia 0:820a69dfd200 513
gmatarrubia 0:820a69dfd200 514 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 515 return(result);
gmatarrubia 0:820a69dfd200 516 }
gmatarrubia 0:820a69dfd200 517
gmatarrubia 0:820a69dfd200 518 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 519 {
gmatarrubia 0:820a69dfd200 520 uint32_t result;
gmatarrubia 0:820a69dfd200 521
gmatarrubia 0:820a69dfd200 522 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 523 return(result);
gmatarrubia 0:820a69dfd200 524 }
gmatarrubia 0:820a69dfd200 525
gmatarrubia 0:820a69dfd200 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
gmatarrubia 0:820a69dfd200 527 {
gmatarrubia 0:820a69dfd200 528 uint32_t result;
gmatarrubia 0:820a69dfd200 529
gmatarrubia 0:820a69dfd200 530 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
gmatarrubia 0:820a69dfd200 531 return(result);
gmatarrubia 0:820a69dfd200 532 }
gmatarrubia 0:820a69dfd200 533
gmatarrubia 0:820a69dfd200 534 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
gmatarrubia 0:820a69dfd200 535 {
gmatarrubia 0:820a69dfd200 536 uint32_t result;
gmatarrubia 0:820a69dfd200 537
gmatarrubia 0:820a69dfd200 538 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
gmatarrubia 0:820a69dfd200 539 return(result);
gmatarrubia 0:820a69dfd200 540 }
gmatarrubia 0:820a69dfd200 541
gmatarrubia 0:820a69dfd200 542 #define __SMLALD(ARG1,ARG2,ARG3) \
gmatarrubia 0:820a69dfd200 543 ({ \
gmatarrubia 0:820a69dfd200 544 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
gmatarrubia 0:820a69dfd200 545 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
gmatarrubia 0:820a69dfd200 546 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
gmatarrubia 0:820a69dfd200 547 })
gmatarrubia 0:820a69dfd200 548
gmatarrubia 0:820a69dfd200 549 #define __SMLALDX(ARG1,ARG2,ARG3) \
gmatarrubia 0:820a69dfd200 550 ({ \
gmatarrubia 0:820a69dfd200 551 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
gmatarrubia 0:820a69dfd200 552 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
gmatarrubia 0:820a69dfd200 553 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
gmatarrubia 0:820a69dfd200 554 })
gmatarrubia 0:820a69dfd200 555
gmatarrubia 0:820a69dfd200 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 557 {
gmatarrubia 0:820a69dfd200 558 uint32_t result;
gmatarrubia 0:820a69dfd200 559
gmatarrubia 0:820a69dfd200 560 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 561 return(result);
gmatarrubia 0:820a69dfd200 562 }
gmatarrubia 0:820a69dfd200 563
gmatarrubia 0:820a69dfd200 564 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 565 {
gmatarrubia 0:820a69dfd200 566 uint32_t result;
gmatarrubia 0:820a69dfd200 567
gmatarrubia 0:820a69dfd200 568 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 569 return(result);
gmatarrubia 0:820a69dfd200 570 }
gmatarrubia 0:820a69dfd200 571
gmatarrubia 0:820a69dfd200 572 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
gmatarrubia 0:820a69dfd200 573 {
gmatarrubia 0:820a69dfd200 574 uint32_t result;
gmatarrubia 0:820a69dfd200 575
gmatarrubia 0:820a69dfd200 576 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
gmatarrubia 0:820a69dfd200 577 return(result);
gmatarrubia 0:820a69dfd200 578 }
gmatarrubia 0:820a69dfd200 579
gmatarrubia 0:820a69dfd200 580 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
gmatarrubia 0:820a69dfd200 581 {
gmatarrubia 0:820a69dfd200 582 uint32_t result;
gmatarrubia 0:820a69dfd200 583
gmatarrubia 0:820a69dfd200 584 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
gmatarrubia 0:820a69dfd200 585 return(result);
gmatarrubia 0:820a69dfd200 586 }
gmatarrubia 0:820a69dfd200 587
gmatarrubia 0:820a69dfd200 588 #define __SMLSLD(ARG1,ARG2,ARG3) \
gmatarrubia 0:820a69dfd200 589 ({ \
gmatarrubia 0:820a69dfd200 590 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
gmatarrubia 0:820a69dfd200 591 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
gmatarrubia 0:820a69dfd200 592 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
gmatarrubia 0:820a69dfd200 593 })
gmatarrubia 0:820a69dfd200 594
gmatarrubia 0:820a69dfd200 595 #define __SMLSLDX(ARG1,ARG2,ARG3) \
gmatarrubia 0:820a69dfd200 596 ({ \
gmatarrubia 0:820a69dfd200 597 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
gmatarrubia 0:820a69dfd200 598 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
gmatarrubia 0:820a69dfd200 599 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
gmatarrubia 0:820a69dfd200 600 })
gmatarrubia 0:820a69dfd200 601
gmatarrubia 0:820a69dfd200 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 603 {
gmatarrubia 0:820a69dfd200 604 uint32_t result;
gmatarrubia 0:820a69dfd200 605
gmatarrubia 0:820a69dfd200 606 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 607 return(result);
gmatarrubia 0:820a69dfd200 608 }
gmatarrubia 0:820a69dfd200 609
gmatarrubia 0:820a69dfd200 610 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 611 {
gmatarrubia 0:820a69dfd200 612 uint32_t result;
gmatarrubia 0:820a69dfd200 613
gmatarrubia 0:820a69dfd200 614 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 615 return(result);
gmatarrubia 0:820a69dfd200 616 }
gmatarrubia 0:820a69dfd200 617
gmatarrubia 0:820a69dfd200 618 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
gmatarrubia 0:820a69dfd200 619 {
gmatarrubia 0:820a69dfd200 620 uint32_t result;
gmatarrubia 0:820a69dfd200 621
gmatarrubia 0:820a69dfd200 622 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
gmatarrubia 0:820a69dfd200 623 return(result);
gmatarrubia 0:820a69dfd200 624 }
gmatarrubia 0:820a69dfd200 625
gmatarrubia 0:820a69dfd200 626 #define __PKHBT(ARG1,ARG2,ARG3) \
gmatarrubia 0:820a69dfd200 627 ({ \
gmatarrubia 0:820a69dfd200 628 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
gmatarrubia 0:820a69dfd200 629 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
gmatarrubia 0:820a69dfd200 630 __RES; \
gmatarrubia 0:820a69dfd200 631 })
gmatarrubia 0:820a69dfd200 632
gmatarrubia 0:820a69dfd200 633 #define __PKHTB(ARG1,ARG2,ARG3) \
gmatarrubia 0:820a69dfd200 634 ({ \
gmatarrubia 0:820a69dfd200 635 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
gmatarrubia 0:820a69dfd200 636 if (ARG3 == 0) \
gmatarrubia 0:820a69dfd200 637 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
gmatarrubia 0:820a69dfd200 638 else \
gmatarrubia 0:820a69dfd200 639 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
gmatarrubia 0:820a69dfd200 640 __RES; \
gmatarrubia 0:820a69dfd200 641 })
gmatarrubia 0:820a69dfd200 642
gmatarrubia 0:820a69dfd200 643 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
gmatarrubia 0:820a69dfd200 644 {
gmatarrubia 0:820a69dfd200 645 int32_t result;
gmatarrubia 0:820a69dfd200 646
gmatarrubia 0:820a69dfd200 647 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
gmatarrubia 0:820a69dfd200 648 return(result);
gmatarrubia 0:820a69dfd200 649 }
gmatarrubia 0:820a69dfd200 650
gmatarrubia 0:820a69dfd200 651 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
gmatarrubia 0:820a69dfd200 652
gmatarrubia 0:820a69dfd200 653
gmatarrubia 0:820a69dfd200 654
gmatarrubia 0:820a69dfd200 655 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
gmatarrubia 0:820a69dfd200 656 /* TASKING carm specific functions */
gmatarrubia 0:820a69dfd200 657
gmatarrubia 0:820a69dfd200 658
gmatarrubia 0:820a69dfd200 659 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
gmatarrubia 0:820a69dfd200 660 /* not yet supported */
gmatarrubia 0:820a69dfd200 661 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
gmatarrubia 0:820a69dfd200 662
gmatarrubia 0:820a69dfd200 663
gmatarrubia 0:820a69dfd200 664 #endif
gmatarrubia 0:820a69dfd200 665
gmatarrubia 0:820a69dfd200 666 /*@} end of group CMSIS_SIMD_intrinsics */
gmatarrubia 0:820a69dfd200 667
gmatarrubia 0:820a69dfd200 668
gmatarrubia 0:820a69dfd200 669 #endif /* __CORE_CM4_SIMD_H */
gmatarrubia 0:820a69dfd200 670
gmatarrubia 0:820a69dfd200 671 #ifdef __cplusplus
gmatarrubia 0:820a69dfd200 672 }
gmatarrubia 0:820a69dfd200 673 #endif