Mbed LPC1549 mod - This repo contains the libraries of Mbed for LPC1…

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This repo contains the libraries of Mbed for LPC1549 with following changes: - IAP commands. - EEPROM write and read. - UART write and read (public) - CAN can_s -> LPC_C_CAN0_Type *can

mbed/TARGET_LPC1549/core_cm3.h@0:820a69dfd200, 2015-04-14 (annotated)

Committer:: gmatarrubia
Date:: Tue Apr 14 15:00:13 2015 +0200
Revision:: 0:820a69dfd200

Initial repo. IAP commands, EEPROM write/read, UART write/read, CAN

Who changed what in which revision?

User	Revision	Line number	New contents of line
gmatarrubia	0:820a69dfd200	1	/************************************************************************//
gmatarrubia	0:820a69dfd200	2	* @file core_cm3.h
gmatarrubia	0:820a69dfd200	3	* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
gmatarrubia	0:820a69dfd200	4	* @version V3.20
gmatarrubia	0:820a69dfd200	5	* @date 25. February 2013
gmatarrubia	0:820a69dfd200	6	*
gmatarrubia	0:820a69dfd200	7	* @note
gmatarrubia	0:820a69dfd200	8	*
gmatarrubia	0:820a69dfd200	9	******************************************************************************/
gmatarrubia	0:820a69dfd200	10	/* Copyright (c) 2009 - 2013 ARM LIMITED
gmatarrubia	0:820a69dfd200	11
gmatarrubia	0:820a69dfd200	12	All rights reserved.
gmatarrubia	0:820a69dfd200	13	Redistribution and use in source and binary forms, with or without
gmatarrubia	0:820a69dfd200	14	modification, are permitted provided that the following conditions are met:
gmatarrubia	0:820a69dfd200	15	- Redistributions of source code must retain the above copyright
gmatarrubia	0:820a69dfd200	16	notice, this list of conditions and the following disclaimer.
gmatarrubia	0:820a69dfd200	17	- Redistributions in binary form must reproduce the above copyright
gmatarrubia	0:820a69dfd200	18	notice, this list of conditions and the following disclaimer in the
gmatarrubia	0:820a69dfd200	19	documentation and/or other materials provided with the distribution.
gmatarrubia	0:820a69dfd200	20	- Neither the name of ARM nor the names of its contributors may be used
gmatarrubia	0:820a69dfd200	21	to endorse or promote products derived from this software without
gmatarrubia	0:820a69dfd200	22	specific prior written permission.
gmatarrubia	0:820a69dfd200	23	*
gmatarrubia	0:820a69dfd200	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
gmatarrubia	0:820a69dfd200	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
gmatarrubia	0:820a69dfd200	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
gmatarrubia	0:820a69dfd200	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
gmatarrubia	0:820a69dfd200	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
gmatarrubia	0:820a69dfd200	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
gmatarrubia	0:820a69dfd200	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
gmatarrubia	0:820a69dfd200	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
gmatarrubia	0:820a69dfd200	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
gmatarrubia	0:820a69dfd200	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
gmatarrubia	0:820a69dfd200	34	POSSIBILITY OF SUCH DAMAGE.
gmatarrubia	0:820a69dfd200	35	---------------------------------------------------------------------------*/
gmatarrubia	0:820a69dfd200	36
gmatarrubia	0:820a69dfd200	37
gmatarrubia	0:820a69dfd200	38	#if defined ( __ICCARM__ )
gmatarrubia	0:820a69dfd200	39	#pragma system_include /* treat file as system include file for MISRA check */
gmatarrubia	0:820a69dfd200	40	#endif
gmatarrubia	0:820a69dfd200	41
gmatarrubia	0:820a69dfd200	42	#ifdef __cplusplus
gmatarrubia	0:820a69dfd200	43	extern "C" {
gmatarrubia	0:820a69dfd200	44	#endif
gmatarrubia	0:820a69dfd200	45
gmatarrubia	0:820a69dfd200	46	#ifndef __CORE_CM3_H_GENERIC
gmatarrubia	0:820a69dfd200	47	#define __CORE_CM3_H_GENERIC
gmatarrubia	0:820a69dfd200	48
gmatarrubia	0:820a69dfd200	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
gmatarrubia	0:820a69dfd200	50	CMSIS violates the following MISRA-C:2004 rules:
gmatarrubia	0:820a69dfd200	51
gmatarrubia	0:820a69dfd200	52	\li Required Rule 8.5, object/function definition in header file.<br>
gmatarrubia	0:820a69dfd200	53	Function definitions in header files are used to allow 'inlining'.
gmatarrubia	0:820a69dfd200	54
gmatarrubia	0:820a69dfd200	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
gmatarrubia	0:820a69dfd200	56	Unions are used for effective representation of core registers.
gmatarrubia	0:820a69dfd200	57
gmatarrubia	0:820a69dfd200	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
gmatarrubia	0:820a69dfd200	59	Function-like macros are used to allow more efficient code.
gmatarrubia	0:820a69dfd200	60	*/
gmatarrubia	0:820a69dfd200	61
gmatarrubia	0:820a69dfd200	62
gmatarrubia	0:820a69dfd200	63	/*******************************************************************************
gmatarrubia	0:820a69dfd200	64	* CMSIS definitions
gmatarrubia	0:820a69dfd200	65	******************************************************************************/
gmatarrubia	0:820a69dfd200	66	/** \ingroup Cortex_M3
gmatarrubia	0:820a69dfd200	67	@{
gmatarrubia	0:820a69dfd200	68	*/
gmatarrubia	0:820a69dfd200	69
gmatarrubia	0:820a69dfd200	70	/* CMSIS CM3 definitions */
gmatarrubia	0:820a69dfd200	71	#define __CM3_CMSIS_VERSION_MAIN (0x03) /!< [31:16] CMSIS HAL main version /
gmatarrubia	0:820a69dfd200	72	#define __CM3_CMSIS_VERSION_SUB (0x20) /!< [15:0] CMSIS HAL sub version /
gmatarrubia	0:820a69dfd200	73	#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) \| \
gmatarrubia	0:820a69dfd200	74	__CM3_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
gmatarrubia	0:820a69dfd200	75
gmatarrubia	0:820a69dfd200	76	#define __CORTEX_M (0x03) /!< Cortex-M Core /
gmatarrubia	0:820a69dfd200	77
gmatarrubia	0:820a69dfd200	78
gmatarrubia	0:820a69dfd200	79	#if defined ( __CC_ARM )
gmatarrubia	0:820a69dfd200	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
gmatarrubia	0:820a69dfd200	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
gmatarrubia	0:820a69dfd200	82	#define __STATIC_INLINE static __inline
gmatarrubia	0:820a69dfd200	83
gmatarrubia	0:820a69dfd200	84	#elif defined ( __ICCARM__ )
gmatarrubia	0:820a69dfd200	85	#define __ASM __asm /!< asm keyword for IAR Compiler /
gmatarrubia	0:820a69dfd200	86	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
gmatarrubia	0:820a69dfd200	87	#define __STATIC_INLINE static inline
gmatarrubia	0:820a69dfd200	88
gmatarrubia	0:820a69dfd200	89	#elif defined ( __TMS470__ )
gmatarrubia	0:820a69dfd200	90	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
gmatarrubia	0:820a69dfd200	91	#define __STATIC_INLINE static inline
gmatarrubia	0:820a69dfd200	92
gmatarrubia	0:820a69dfd200	93	#elif defined ( __GNUC__ )
gmatarrubia	0:820a69dfd200	94	#define __ASM __asm /!< asm keyword for GNU Compiler /
gmatarrubia	0:820a69dfd200	95	#define __INLINE inline /!< inline keyword for GNU Compiler /
gmatarrubia	0:820a69dfd200	96	#define __STATIC_INLINE static inline
gmatarrubia	0:820a69dfd200	97
gmatarrubia	0:820a69dfd200	98	#elif defined ( __TASKING__ )
gmatarrubia	0:820a69dfd200	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
gmatarrubia	0:820a69dfd200	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
gmatarrubia	0:820a69dfd200	101	#define __STATIC_INLINE static inline
gmatarrubia	0:820a69dfd200	102
gmatarrubia	0:820a69dfd200	103	#endif
gmatarrubia	0:820a69dfd200	104
gmatarrubia	0:820a69dfd200	105	/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
gmatarrubia	0:820a69dfd200	106	*/
gmatarrubia	0:820a69dfd200	107	#define __FPU_USED 0
gmatarrubia	0:820a69dfd200	108
gmatarrubia	0:820a69dfd200	109	#if defined ( __CC_ARM )
gmatarrubia	0:820a69dfd200	110	#if defined __TARGET_FPU_VFP
gmatarrubia	0:820a69dfd200	111	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
gmatarrubia	0:820a69dfd200	112	#endif
gmatarrubia	0:820a69dfd200	113
gmatarrubia	0:820a69dfd200	114	#elif defined ( __ICCARM__ )
gmatarrubia	0:820a69dfd200	115	#if defined __ARMVFP__
gmatarrubia	0:820a69dfd200	116	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
gmatarrubia	0:820a69dfd200	117	#endif
gmatarrubia	0:820a69dfd200	118
gmatarrubia	0:820a69dfd200	119	#elif defined ( __TMS470__ )
gmatarrubia	0:820a69dfd200	120	#if defined __TI__VFP_SUPPORT____
gmatarrubia	0:820a69dfd200	121	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
gmatarrubia	0:820a69dfd200	122	#endif
gmatarrubia	0:820a69dfd200	123
gmatarrubia	0:820a69dfd200	124	#elif defined ( __GNUC__ )
gmatarrubia	0:820a69dfd200	125	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
gmatarrubia	0:820a69dfd200	126	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
gmatarrubia	0:820a69dfd200	127	#endif
gmatarrubia	0:820a69dfd200	128
gmatarrubia	0:820a69dfd200	129	#elif defined ( __TASKING__ )
gmatarrubia	0:820a69dfd200	130	#if defined __FPU_VFP__
gmatarrubia	0:820a69dfd200	131	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
gmatarrubia	0:820a69dfd200	132	#endif
gmatarrubia	0:820a69dfd200	133	#endif
gmatarrubia	0:820a69dfd200	134
gmatarrubia	0:820a69dfd200	135	#include <stdint.h> /* standard types definitions */
gmatarrubia	0:820a69dfd200	136	#include <core_cmInstr.h> /* Core Instruction Access */
gmatarrubia	0:820a69dfd200	137	#include <core_cmFunc.h> /* Core Function Access */
gmatarrubia	0:820a69dfd200	138
gmatarrubia	0:820a69dfd200	139	#endif /* __CORE_CM3_H_GENERIC */
gmatarrubia	0:820a69dfd200	140
gmatarrubia	0:820a69dfd200	141	#ifndef __CMSIS_GENERIC
gmatarrubia	0:820a69dfd200	142
gmatarrubia	0:820a69dfd200	143	#ifndef __CORE_CM3_H_DEPENDANT
gmatarrubia	0:820a69dfd200	144	#define __CORE_CM3_H_DEPENDANT
gmatarrubia	0:820a69dfd200	145
gmatarrubia	0:820a69dfd200	146	/* check device defines and use defaults */
gmatarrubia	0:820a69dfd200	147	#if defined __CHECK_DEVICE_DEFINES
gmatarrubia	0:820a69dfd200	148	#ifndef __CM3_REV
gmatarrubia	0:820a69dfd200	149	#define __CM3_REV 0x0200
gmatarrubia	0:820a69dfd200	150	#warning "__CM3_REV not defined in device header file; using default!"
gmatarrubia	0:820a69dfd200	151	#endif
gmatarrubia	0:820a69dfd200	152
gmatarrubia	0:820a69dfd200	153	#ifndef __MPU_PRESENT
gmatarrubia	0:820a69dfd200	154	#define __MPU_PRESENT 0
gmatarrubia	0:820a69dfd200	155	#warning "__MPU_PRESENT not defined in device header file; using default!"
gmatarrubia	0:820a69dfd200	156	#endif
gmatarrubia	0:820a69dfd200	157
gmatarrubia	0:820a69dfd200	158	#ifndef __NVIC_PRIO_BITS
gmatarrubia	0:820a69dfd200	159	#define __NVIC_PRIO_BITS 4
gmatarrubia	0:820a69dfd200	160	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
gmatarrubia	0:820a69dfd200	161	#endif
gmatarrubia	0:820a69dfd200	162
gmatarrubia	0:820a69dfd200	163	#ifndef __Vendor_SysTickConfig
gmatarrubia	0:820a69dfd200	164	#define __Vendor_SysTickConfig 0
gmatarrubia	0:820a69dfd200	165	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
gmatarrubia	0:820a69dfd200	166	#endif
gmatarrubia	0:820a69dfd200	167	#endif
gmatarrubia	0:820a69dfd200	168
gmatarrubia	0:820a69dfd200	169	/* IO definitions (access restrictions to peripheral registers) */
gmatarrubia	0:820a69dfd200	170	/**
gmatarrubia	0:820a69dfd200	171	\defgroup CMSIS_glob_defs CMSIS Global Defines
gmatarrubia	0:820a69dfd200	172
gmatarrubia	0:820a69dfd200	173	<strong>IO Type Qualifiers</strong> are used
gmatarrubia	0:820a69dfd200	174	\li to specify the access to peripheral variables.
gmatarrubia	0:820a69dfd200	175	\li for automatic generation of peripheral register debug information.
gmatarrubia	0:820a69dfd200	176	*/
gmatarrubia	0:820a69dfd200	177	#ifdef __cplusplus
gmatarrubia	0:820a69dfd200	178	#define __I volatile /!< Defines 'read only' permissions /
gmatarrubia	0:820a69dfd200	179	#else
gmatarrubia	0:820a69dfd200	180	#define __I volatile const /!< Defines 'read only' permissions /
gmatarrubia	0:820a69dfd200	181	#endif
gmatarrubia	0:820a69dfd200	182	#define __O volatile /!< Defines 'write only' permissions /
gmatarrubia	0:820a69dfd200	183	#define __IO volatile /!< Defines 'read / write' permissions /
gmatarrubia	0:820a69dfd200	184
gmatarrubia	0:820a69dfd200	185	/@} end of group Cortex_M3 /
gmatarrubia	0:820a69dfd200	186
gmatarrubia	0:820a69dfd200	187
gmatarrubia	0:820a69dfd200	188
gmatarrubia	0:820a69dfd200	189	/*******************************************************************************
gmatarrubia	0:820a69dfd200	190	* Register Abstraction
gmatarrubia	0:820a69dfd200	191	Core Register contain:
gmatarrubia	0:820a69dfd200	192	- Core Register
gmatarrubia	0:820a69dfd200	193	- Core NVIC Register
gmatarrubia	0:820a69dfd200	194	- Core SCB Register
gmatarrubia	0:820a69dfd200	195	- Core SysTick Register
gmatarrubia	0:820a69dfd200	196	- Core Debug Register
gmatarrubia	0:820a69dfd200	197	- Core MPU Register
gmatarrubia	0:820a69dfd200	198	******************************************************************************/
gmatarrubia	0:820a69dfd200	199	/** \defgroup CMSIS_core_register Defines and Type Definitions
gmatarrubia	0:820a69dfd200	200	\brief Type definitions and defines for Cortex-M processor based devices.
gmatarrubia	0:820a69dfd200	201	*/
gmatarrubia	0:820a69dfd200	202
gmatarrubia	0:820a69dfd200	203	/** \ingroup CMSIS_core_register
gmatarrubia	0:820a69dfd200	204	\defgroup CMSIS_CORE Status and Control Registers
gmatarrubia	0:820a69dfd200	205	\brief Core Register type definitions.
gmatarrubia	0:820a69dfd200	206	@{
gmatarrubia	0:820a69dfd200	207	*/
gmatarrubia	0:820a69dfd200	208
gmatarrubia	0:820a69dfd200	209	/** \brief Union type to access the Application Program Status Register (APSR).
gmatarrubia	0:820a69dfd200	210	*/
gmatarrubia	0:820a69dfd200	211	typedef union
gmatarrubia	0:820a69dfd200	212	{
gmatarrubia	0:820a69dfd200	213	struct
gmatarrubia	0:820a69dfd200	214	{
gmatarrubia	0:820a69dfd200	215	#if (__CORTEX_M != 0x04)
gmatarrubia	0:820a69dfd200	216	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
gmatarrubia	0:820a69dfd200	217	#else
gmatarrubia	0:820a69dfd200	218	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
gmatarrubia	0:820a69dfd200	219	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
gmatarrubia	0:820a69dfd200	220	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
gmatarrubia	0:820a69dfd200	221	#endif
gmatarrubia	0:820a69dfd200	222	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
gmatarrubia	0:820a69dfd200	223	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
gmatarrubia	0:820a69dfd200	224	uint32_t C:1; /!< bit: 29 Carry condition code flag /
gmatarrubia	0:820a69dfd200	225	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
gmatarrubia	0:820a69dfd200	226	uint32_t N:1; /!< bit: 31 Negative condition code flag /
gmatarrubia	0:820a69dfd200	227	} b; /!< Structure used for bit access /
gmatarrubia	0:820a69dfd200	228	uint32_t w; /!< Type used for word access /
gmatarrubia	0:820a69dfd200	229	} APSR_Type;
gmatarrubia	0:820a69dfd200	230
gmatarrubia	0:820a69dfd200	231
gmatarrubia	0:820a69dfd200	232	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
gmatarrubia	0:820a69dfd200	233	*/
gmatarrubia	0:820a69dfd200	234	typedef union
gmatarrubia	0:820a69dfd200	235	{
gmatarrubia	0:820a69dfd200	236	struct
gmatarrubia	0:820a69dfd200	237	{
gmatarrubia	0:820a69dfd200	238	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
gmatarrubia	0:820a69dfd200	239	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
gmatarrubia	0:820a69dfd200	240	} b; /!< Structure used for bit access /
gmatarrubia	0:820a69dfd200	241	uint32_t w; /!< Type used for word access /
gmatarrubia	0:820a69dfd200	242	} IPSR_Type;
gmatarrubia	0:820a69dfd200	243
gmatarrubia	0:820a69dfd200	244
gmatarrubia	0:820a69dfd200	245	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
gmatarrubia	0:820a69dfd200	246	*/
gmatarrubia	0:820a69dfd200	247	typedef union
gmatarrubia	0:820a69dfd200	248	{
gmatarrubia	0:820a69dfd200	249	struct
gmatarrubia	0:820a69dfd200	250	{
gmatarrubia	0:820a69dfd200	251	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
gmatarrubia	0:820a69dfd200	252	#if (__CORTEX_M != 0x04)
gmatarrubia	0:820a69dfd200	253	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
gmatarrubia	0:820a69dfd200	254	#else
gmatarrubia	0:820a69dfd200	255	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
gmatarrubia	0:820a69dfd200	256	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
gmatarrubia	0:820a69dfd200	257	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
gmatarrubia	0:820a69dfd200	258	#endif
gmatarrubia	0:820a69dfd200	259	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
gmatarrubia	0:820a69dfd200	260	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
gmatarrubia	0:820a69dfd200	261	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
gmatarrubia	0:820a69dfd200	262	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
gmatarrubia	0:820a69dfd200	263	uint32_t C:1; /!< bit: 29 Carry condition code flag /
gmatarrubia	0:820a69dfd200	264	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
gmatarrubia	0:820a69dfd200	265	uint32_t N:1; /!< bit: 31 Negative condition code flag /
gmatarrubia	0:820a69dfd200	266	} b; /!< Structure used for bit access /
gmatarrubia	0:820a69dfd200	267	uint32_t w; /!< Type used for word access /
gmatarrubia	0:820a69dfd200	268	} xPSR_Type;
gmatarrubia	0:820a69dfd200	269
gmatarrubia	0:820a69dfd200	270
gmatarrubia	0:820a69dfd200	271	/** \brief Union type to access the Control Registers (CONTROL).
gmatarrubia	0:820a69dfd200	272	*/
gmatarrubia	0:820a69dfd200	273	typedef union
gmatarrubia	0:820a69dfd200	274	{
gmatarrubia	0:820a69dfd200	275	struct
gmatarrubia	0:820a69dfd200	276	{
gmatarrubia	0:820a69dfd200	277	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
gmatarrubia	0:820a69dfd200	278	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
gmatarrubia	0:820a69dfd200	279	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
gmatarrubia	0:820a69dfd200	280	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
gmatarrubia	0:820a69dfd200	281	} b; /!< Structure used for bit access /
gmatarrubia	0:820a69dfd200	282	uint32_t w; /!< Type used for word access /
gmatarrubia	0:820a69dfd200	283	} CONTROL_Type;
gmatarrubia	0:820a69dfd200	284
gmatarrubia	0:820a69dfd200	285	/@} end of group CMSIS_CORE /
gmatarrubia	0:820a69dfd200	286
gmatarrubia	0:820a69dfd200	287
gmatarrubia	0:820a69dfd200	288	/** \ingroup CMSIS_core_register
gmatarrubia	0:820a69dfd200	289	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
gmatarrubia	0:820a69dfd200	290	\brief Type definitions for the NVIC Registers
gmatarrubia	0:820a69dfd200	291	@{
gmatarrubia	0:820a69dfd200	292	*/
gmatarrubia	0:820a69dfd200	293
gmatarrubia	0:820a69dfd200	294	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
gmatarrubia	0:820a69dfd200	295	*/
gmatarrubia	0:820a69dfd200	296	typedef struct
gmatarrubia	0:820a69dfd200	297	{
gmatarrubia	0:820a69dfd200	298	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
gmatarrubia	0:820a69dfd200	299	uint32_t RESERVED0[24];
gmatarrubia	0:820a69dfd200	300	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
gmatarrubia	0:820a69dfd200	301	uint32_t RSERVED1[24];
gmatarrubia	0:820a69dfd200	302	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
gmatarrubia	0:820a69dfd200	303	uint32_t RESERVED2[24];
gmatarrubia	0:820a69dfd200	304	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
gmatarrubia	0:820a69dfd200	305	uint32_t RESERVED3[24];
gmatarrubia	0:820a69dfd200	306	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
gmatarrubia	0:820a69dfd200	307	uint32_t RESERVED4[56];
gmatarrubia	0:820a69dfd200	308	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
gmatarrubia	0:820a69dfd200	309	uint32_t RESERVED5[644];
gmatarrubia	0:820a69dfd200	310	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
gmatarrubia	0:820a69dfd200	311	} NVIC_Type;
gmatarrubia	0:820a69dfd200	312
gmatarrubia	0:820a69dfd200	313	/* Software Triggered Interrupt Register Definitions */
gmatarrubia	0:820a69dfd200	314	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
gmatarrubia	0:820a69dfd200	315	#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /!< STIR: INTLINESNUM Mask /
gmatarrubia	0:820a69dfd200	316
gmatarrubia	0:820a69dfd200	317	/@} end of group CMSIS_NVIC /
gmatarrubia	0:820a69dfd200	318
gmatarrubia	0:820a69dfd200	319
gmatarrubia	0:820a69dfd200	320	/** \ingroup CMSIS_core_register
gmatarrubia	0:820a69dfd200	321	\defgroup CMSIS_SCB System Control Block (SCB)
gmatarrubia	0:820a69dfd200	322	\brief Type definitions for the System Control Block Registers
gmatarrubia	0:820a69dfd200	323	@{
gmatarrubia	0:820a69dfd200	324	*/
gmatarrubia	0:820a69dfd200	325
gmatarrubia	0:820a69dfd200	326	/** \brief Structure type to access the System Control Block (SCB).
gmatarrubia	0:820a69dfd200	327	*/
gmatarrubia	0:820a69dfd200	328	typedef struct
gmatarrubia	0:820a69dfd200	329	{
gmatarrubia	0:820a69dfd200	330	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
gmatarrubia	0:820a69dfd200	331	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
gmatarrubia	0:820a69dfd200	332	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
gmatarrubia	0:820a69dfd200	333	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
gmatarrubia	0:820a69dfd200	334	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
gmatarrubia	0:820a69dfd200	335	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
gmatarrubia	0:820a69dfd200	336	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
gmatarrubia	0:820a69dfd200	337	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
gmatarrubia	0:820a69dfd200	338	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
gmatarrubia	0:820a69dfd200	339	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
gmatarrubia	0:820a69dfd200	340	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
gmatarrubia	0:820a69dfd200	341	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
gmatarrubia	0:820a69dfd200	342	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
gmatarrubia	0:820a69dfd200	343	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
gmatarrubia	0:820a69dfd200	344	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
gmatarrubia	0:820a69dfd200	345	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
gmatarrubia	0:820a69dfd200	346	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
gmatarrubia	0:820a69dfd200	347	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
gmatarrubia	0:820a69dfd200	348	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
gmatarrubia	0:820a69dfd200	349	uint32_t RESERVED0[5];
gmatarrubia	0:820a69dfd200	350	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
gmatarrubia	0:820a69dfd200	351	} SCB_Type;
gmatarrubia	0:820a69dfd200	352
gmatarrubia	0:820a69dfd200	353	/* SCB CPUID Register Definitions */
gmatarrubia	0:820a69dfd200	354	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
gmatarrubia	0:820a69dfd200	355	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
gmatarrubia	0:820a69dfd200	356
gmatarrubia	0:820a69dfd200	357	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
gmatarrubia	0:820a69dfd200	358	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
gmatarrubia	0:820a69dfd200	359
gmatarrubia	0:820a69dfd200	360	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
gmatarrubia	0:820a69dfd200	361	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
gmatarrubia	0:820a69dfd200	362
gmatarrubia	0:820a69dfd200	363	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
gmatarrubia	0:820a69dfd200	364	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
gmatarrubia	0:820a69dfd200	365
gmatarrubia	0:820a69dfd200	366	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
gmatarrubia	0:820a69dfd200	367	#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /!< SCB CPUID: REVISION Mask /
gmatarrubia	0:820a69dfd200	368
gmatarrubia	0:820a69dfd200	369	/* SCB Interrupt Control State Register Definitions */
gmatarrubia	0:820a69dfd200	370	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
gmatarrubia	0:820a69dfd200	371	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
gmatarrubia	0:820a69dfd200	372
gmatarrubia	0:820a69dfd200	373	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
gmatarrubia	0:820a69dfd200	374	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
gmatarrubia	0:820a69dfd200	375
gmatarrubia	0:820a69dfd200	376	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
gmatarrubia	0:820a69dfd200	377	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
gmatarrubia	0:820a69dfd200	378
gmatarrubia	0:820a69dfd200	379	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
gmatarrubia	0:820a69dfd200	380	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
gmatarrubia	0:820a69dfd200	381
gmatarrubia	0:820a69dfd200	382	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
gmatarrubia	0:820a69dfd200	383	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
gmatarrubia	0:820a69dfd200	384
gmatarrubia	0:820a69dfd200	385	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
gmatarrubia	0:820a69dfd200	386	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
gmatarrubia	0:820a69dfd200	387
gmatarrubia	0:820a69dfd200	388	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
gmatarrubia	0:820a69dfd200	389	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
gmatarrubia	0:820a69dfd200	390
gmatarrubia	0:820a69dfd200	391	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
gmatarrubia	0:820a69dfd200	392	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
gmatarrubia	0:820a69dfd200	393
gmatarrubia	0:820a69dfd200	394	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
gmatarrubia	0:820a69dfd200	395	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
gmatarrubia	0:820a69dfd200	396
gmatarrubia	0:820a69dfd200	397	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
gmatarrubia	0:820a69dfd200	398	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /!< SCB ICSR: VECTACTIVE Mask /
gmatarrubia	0:820a69dfd200	399
gmatarrubia	0:820a69dfd200	400	/* SCB Vector Table Offset Register Definitions */
gmatarrubia	0:820a69dfd200	401	#if (__CM3_REV < 0x0201) /* core r2p1 */
gmatarrubia	0:820a69dfd200	402	#define SCB_VTOR_TBLBASE_Pos 29 /!< SCB VTOR: TBLBASE Position /
gmatarrubia	0:820a69dfd200	403	#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /!< SCB VTOR: TBLBASE Mask /
gmatarrubia	0:820a69dfd200	404
gmatarrubia	0:820a69dfd200	405	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
gmatarrubia	0:820a69dfd200	406	#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
gmatarrubia	0:820a69dfd200	407	#else
gmatarrubia	0:820a69dfd200	408	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
gmatarrubia	0:820a69dfd200	409	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
gmatarrubia	0:820a69dfd200	410	#endif
gmatarrubia	0:820a69dfd200	411
gmatarrubia	0:820a69dfd200	412	/* SCB Application Interrupt and Reset Control Register Definitions */
gmatarrubia	0:820a69dfd200	413	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
gmatarrubia	0:820a69dfd200	414	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
gmatarrubia	0:820a69dfd200	415
gmatarrubia	0:820a69dfd200	416	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
gmatarrubia	0:820a69dfd200	417	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
gmatarrubia	0:820a69dfd200	418
gmatarrubia	0:820a69dfd200	419	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
gmatarrubia	0:820a69dfd200	420	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
gmatarrubia	0:820a69dfd200	421
gmatarrubia	0:820a69dfd200	422	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
gmatarrubia	0:820a69dfd200	423	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
gmatarrubia	0:820a69dfd200	424
gmatarrubia	0:820a69dfd200	425	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
gmatarrubia	0:820a69dfd200	426	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
gmatarrubia	0:820a69dfd200	427
gmatarrubia	0:820a69dfd200	428	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
gmatarrubia	0:820a69dfd200	429	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
gmatarrubia	0:820a69dfd200	430
gmatarrubia	0:820a69dfd200	431	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
gmatarrubia	0:820a69dfd200	432	#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /!< SCB AIRCR: VECTRESET Mask /
gmatarrubia	0:820a69dfd200	433
gmatarrubia	0:820a69dfd200	434	/* SCB System Control Register Definitions */
gmatarrubia	0:820a69dfd200	435	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
gmatarrubia	0:820a69dfd200	436	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
gmatarrubia	0:820a69dfd200	437
gmatarrubia	0:820a69dfd200	438	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
gmatarrubia	0:820a69dfd200	439	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
gmatarrubia	0:820a69dfd200	440
gmatarrubia	0:820a69dfd200	441	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
gmatarrubia	0:820a69dfd200	442	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
gmatarrubia	0:820a69dfd200	443
gmatarrubia	0:820a69dfd200	444	/* SCB Configuration Control Register Definitions */
gmatarrubia	0:820a69dfd200	445	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
gmatarrubia	0:820a69dfd200	446	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
gmatarrubia	0:820a69dfd200	447
gmatarrubia	0:820a69dfd200	448	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
gmatarrubia	0:820a69dfd200	449	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
gmatarrubia	0:820a69dfd200	450
gmatarrubia	0:820a69dfd200	451	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
gmatarrubia	0:820a69dfd200	452	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
gmatarrubia	0:820a69dfd200	453
gmatarrubia	0:820a69dfd200	454	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
gmatarrubia	0:820a69dfd200	455	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
gmatarrubia	0:820a69dfd200	456
gmatarrubia	0:820a69dfd200	457	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
gmatarrubia	0:820a69dfd200	458	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
gmatarrubia	0:820a69dfd200	459
gmatarrubia	0:820a69dfd200	460	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
gmatarrubia	0:820a69dfd200	461	#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /!< SCB CCR: NONBASETHRDENA Mask /
gmatarrubia	0:820a69dfd200	462
gmatarrubia	0:820a69dfd200	463	/* SCB System Handler Control and State Register Definitions */
gmatarrubia	0:820a69dfd200	464	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
gmatarrubia	0:820a69dfd200	465	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
gmatarrubia	0:820a69dfd200	466
gmatarrubia	0:820a69dfd200	467	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
gmatarrubia	0:820a69dfd200	468	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
gmatarrubia	0:820a69dfd200	469
gmatarrubia	0:820a69dfd200	470	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
gmatarrubia	0:820a69dfd200	471	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
gmatarrubia	0:820a69dfd200	472
gmatarrubia	0:820a69dfd200	473	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
gmatarrubia	0:820a69dfd200	474	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
gmatarrubia	0:820a69dfd200	475
gmatarrubia	0:820a69dfd200	476	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
gmatarrubia	0:820a69dfd200	477	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
gmatarrubia	0:820a69dfd200	478
gmatarrubia	0:820a69dfd200	479	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
gmatarrubia	0:820a69dfd200	480	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
gmatarrubia	0:820a69dfd200	481
gmatarrubia	0:820a69dfd200	482	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
gmatarrubia	0:820a69dfd200	483	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
gmatarrubia	0:820a69dfd200	484
gmatarrubia	0:820a69dfd200	485	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
gmatarrubia	0:820a69dfd200	486	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
gmatarrubia	0:820a69dfd200	487
gmatarrubia	0:820a69dfd200	488	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
gmatarrubia	0:820a69dfd200	489	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
gmatarrubia	0:820a69dfd200	490
gmatarrubia	0:820a69dfd200	491	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
gmatarrubia	0:820a69dfd200	492	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
gmatarrubia	0:820a69dfd200	493
gmatarrubia	0:820a69dfd200	494	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
gmatarrubia	0:820a69dfd200	495	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
gmatarrubia	0:820a69dfd200	496
gmatarrubia	0:820a69dfd200	497	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
gmatarrubia	0:820a69dfd200	498	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
gmatarrubia	0:820a69dfd200	499
gmatarrubia	0:820a69dfd200	500	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
gmatarrubia	0:820a69dfd200	501	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
gmatarrubia	0:820a69dfd200	502
gmatarrubia	0:820a69dfd200	503	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
gmatarrubia	0:820a69dfd200	504	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /!< SCB SHCSR: MEMFAULTACT Mask /
gmatarrubia	0:820a69dfd200	505
gmatarrubia	0:820a69dfd200	506	/* SCB Configurable Fault Status Registers Definitions */
gmatarrubia	0:820a69dfd200	507	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
gmatarrubia	0:820a69dfd200	508	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
gmatarrubia	0:820a69dfd200	509
gmatarrubia	0:820a69dfd200	510	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
gmatarrubia	0:820a69dfd200	511	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
gmatarrubia	0:820a69dfd200	512
gmatarrubia	0:820a69dfd200	513	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
gmatarrubia	0:820a69dfd200	514	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
gmatarrubia	0:820a69dfd200	515
gmatarrubia	0:820a69dfd200	516	/* SCB Hard Fault Status Registers Definitions */
gmatarrubia	0:820a69dfd200	517	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
gmatarrubia	0:820a69dfd200	518	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
gmatarrubia	0:820a69dfd200	519
gmatarrubia	0:820a69dfd200	520	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
gmatarrubia	0:820a69dfd200	521	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
gmatarrubia	0:820a69dfd200	522
gmatarrubia	0:820a69dfd200	523	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
gmatarrubia	0:820a69dfd200	524	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
gmatarrubia	0:820a69dfd200	525
gmatarrubia	0:820a69dfd200	526	/* SCB Debug Fault Status Register Definitions */
gmatarrubia	0:820a69dfd200	527	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
gmatarrubia	0:820a69dfd200	528	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
gmatarrubia	0:820a69dfd200	529
gmatarrubia	0:820a69dfd200	530	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
gmatarrubia	0:820a69dfd200	531	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
gmatarrubia	0:820a69dfd200	532
gmatarrubia	0:820a69dfd200	533	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
gmatarrubia	0:820a69dfd200	534	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
gmatarrubia	0:820a69dfd200	535
gmatarrubia	0:820a69dfd200	536	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
gmatarrubia	0:820a69dfd200	537	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
gmatarrubia	0:820a69dfd200	538
gmatarrubia	0:820a69dfd200	539	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
gmatarrubia	0:820a69dfd200	540	#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /!< SCB DFSR: HALTED Mask /
gmatarrubia	0:820a69dfd200	541
gmatarrubia	0:820a69dfd200	542	/@} end of group CMSIS_SCB /
gmatarrubia	0:820a69dfd200	543
gmatarrubia	0:820a69dfd200	544
gmatarrubia	0:820a69dfd200	545	/** \ingroup CMSIS_core_register
gmatarrubia	0:820a69dfd200	546	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
gmatarrubia	0:820a69dfd200	547	\brief Type definitions for the System Control and ID Register not in the SCB
gmatarrubia	0:820a69dfd200	548	@{
gmatarrubia	0:820a69dfd200	549	*/
gmatarrubia	0:820a69dfd200	550
gmatarrubia	0:820a69dfd200	551	/** \brief Structure type to access the System Control and ID Register not in the SCB.
gmatarrubia	0:820a69dfd200	552	*/
gmatarrubia	0:820a69dfd200	553	typedef struct
gmatarrubia	0:820a69dfd200	554	{
gmatarrubia	0:820a69dfd200	555	uint32_t RESERVED0[1];
gmatarrubia	0:820a69dfd200	556	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
gmatarrubia	0:820a69dfd200	557	#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
gmatarrubia	0:820a69dfd200	558	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
gmatarrubia	0:820a69dfd200	559	#else
gmatarrubia	0:820a69dfd200	560	uint32_t RESERVED1[1];
gmatarrubia	0:820a69dfd200	561	#endif
gmatarrubia	0:820a69dfd200	562	} SCnSCB_Type;
gmatarrubia	0:820a69dfd200	563
gmatarrubia	0:820a69dfd200	564	/* Interrupt Controller Type Register Definitions */
gmatarrubia	0:820a69dfd200	565	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
gmatarrubia	0:820a69dfd200	566	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /!< ICTR: INTLINESNUM Mask /
gmatarrubia	0:820a69dfd200	567
gmatarrubia	0:820a69dfd200	568	/* Auxiliary Control Register Definitions */
gmatarrubia	0:820a69dfd200	569
gmatarrubia	0:820a69dfd200	570	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
gmatarrubia	0:820a69dfd200	571	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
gmatarrubia	0:820a69dfd200	572
gmatarrubia	0:820a69dfd200	573	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /!< ACTLR: DISDEFWBUF Position /
gmatarrubia	0:820a69dfd200	574	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
gmatarrubia	0:820a69dfd200	575
gmatarrubia	0:820a69dfd200	576	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
gmatarrubia	0:820a69dfd200	577	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /!< ACTLR: DISMCYCINT Mask /
gmatarrubia	0:820a69dfd200	578
gmatarrubia	0:820a69dfd200	579	/@} end of group CMSIS_SCnotSCB /
gmatarrubia	0:820a69dfd200	580
gmatarrubia	0:820a69dfd200	581
gmatarrubia	0:820a69dfd200	582	/** \ingroup CMSIS_core_register
gmatarrubia	0:820a69dfd200	583	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
gmatarrubia	0:820a69dfd200	584	\brief Type definitions for the System Timer Registers.
gmatarrubia	0:820a69dfd200	585	@{
gmatarrubia	0:820a69dfd200	586	*/
gmatarrubia	0:820a69dfd200	587
gmatarrubia	0:820a69dfd200	588	/** \brief Structure type to access the System Timer (SysTick).
gmatarrubia	0:820a69dfd200	589	*/
gmatarrubia	0:820a69dfd200	590	typedef struct
gmatarrubia	0:820a69dfd200	591	{
gmatarrubia	0:820a69dfd200	592	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
gmatarrubia	0:820a69dfd200	593	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
gmatarrubia	0:820a69dfd200	594	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
gmatarrubia	0:820a69dfd200	595	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
gmatarrubia	0:820a69dfd200	596	} SysTick_Type;
gmatarrubia	0:820a69dfd200	597
gmatarrubia	0:820a69dfd200	598	/* SysTick Control / Status Register Definitions */
gmatarrubia	0:820a69dfd200	599	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
gmatarrubia	0:820a69dfd200	600	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
gmatarrubia	0:820a69dfd200	601
gmatarrubia	0:820a69dfd200	602	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
gmatarrubia	0:820a69dfd200	603	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
gmatarrubia	0:820a69dfd200	604
gmatarrubia	0:820a69dfd200	605	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
gmatarrubia	0:820a69dfd200	606	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
gmatarrubia	0:820a69dfd200	607
gmatarrubia	0:820a69dfd200	608	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
gmatarrubia	0:820a69dfd200	609	#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /!< SysTick CTRL: ENABLE Mask /
gmatarrubia	0:820a69dfd200	610
gmatarrubia	0:820a69dfd200	611	/* SysTick Reload Register Definitions */
gmatarrubia	0:820a69dfd200	612	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
gmatarrubia	0:820a69dfd200	613	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /!< SysTick LOAD: RELOAD Mask /
gmatarrubia	0:820a69dfd200	614
gmatarrubia	0:820a69dfd200	615	/* SysTick Current Register Definitions */
gmatarrubia	0:820a69dfd200	616	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
gmatarrubia	0:820a69dfd200	617	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick VAL: CURRENT Mask /
gmatarrubia	0:820a69dfd200	618
gmatarrubia	0:820a69dfd200	619	/* SysTick Calibration Register Definitions */
gmatarrubia	0:820a69dfd200	620	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
gmatarrubia	0:820a69dfd200	621	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
gmatarrubia	0:820a69dfd200	622
gmatarrubia	0:820a69dfd200	623	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
gmatarrubia	0:820a69dfd200	624	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
gmatarrubia	0:820a69dfd200	625
gmatarrubia	0:820a69dfd200	626	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
gmatarrubia	0:820a69dfd200	627	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick CALIB: TENMS Mask /
gmatarrubia	0:820a69dfd200	628
gmatarrubia	0:820a69dfd200	629	/@} end of group CMSIS_SysTick /
gmatarrubia	0:820a69dfd200	630
gmatarrubia	0:820a69dfd200	631
gmatarrubia	0:820a69dfd200	632	/** \ingroup CMSIS_core_register
gmatarrubia	0:820a69dfd200	633	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
gmatarrubia	0:820a69dfd200	634	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
gmatarrubia	0:820a69dfd200	635	@{
gmatarrubia	0:820a69dfd200	636	*/
gmatarrubia	0:820a69dfd200	637
gmatarrubia	0:820a69dfd200	638	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
gmatarrubia	0:820a69dfd200	639	*/
gmatarrubia	0:820a69dfd200	640	typedef struct
gmatarrubia	0:820a69dfd200	641	{
gmatarrubia	0:820a69dfd200	642	__O union
gmatarrubia	0:820a69dfd200	643	{
gmatarrubia	0:820a69dfd200	644	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
gmatarrubia	0:820a69dfd200	645	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
gmatarrubia	0:820a69dfd200	646	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
gmatarrubia	0:820a69dfd200	647	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
gmatarrubia	0:820a69dfd200	648	uint32_t RESERVED0[864];
gmatarrubia	0:820a69dfd200	649	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
gmatarrubia	0:820a69dfd200	650	uint32_t RESERVED1[15];
gmatarrubia	0:820a69dfd200	651	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
gmatarrubia	0:820a69dfd200	652	uint32_t RESERVED2[15];
gmatarrubia	0:820a69dfd200	653	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
gmatarrubia	0:820a69dfd200	654	uint32_t RESERVED3[29];
gmatarrubia	0:820a69dfd200	655	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
gmatarrubia	0:820a69dfd200	656	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
gmatarrubia	0:820a69dfd200	657	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
gmatarrubia	0:820a69dfd200	658	uint32_t RESERVED4[43];
gmatarrubia	0:820a69dfd200	659	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
gmatarrubia	0:820a69dfd200	660	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
gmatarrubia	0:820a69dfd200	661	uint32_t RESERVED5[6];
gmatarrubia	0:820a69dfd200	662	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
gmatarrubia	0:820a69dfd200	663	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
gmatarrubia	0:820a69dfd200	664	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
gmatarrubia	0:820a69dfd200	665	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
gmatarrubia	0:820a69dfd200	666	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
gmatarrubia	0:820a69dfd200	667	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
gmatarrubia	0:820a69dfd200	668	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
gmatarrubia	0:820a69dfd200	669	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
gmatarrubia	0:820a69dfd200	670	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
gmatarrubia	0:820a69dfd200	671	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
gmatarrubia	0:820a69dfd200	672	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
gmatarrubia	0:820a69dfd200	673	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
gmatarrubia	0:820a69dfd200	674	} ITM_Type;
gmatarrubia	0:820a69dfd200	675
gmatarrubia	0:820a69dfd200	676	/* ITM Trace Privilege Register Definitions */
gmatarrubia	0:820a69dfd200	677	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
gmatarrubia	0:820a69dfd200	678	#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /!< ITM TPR: PRIVMASK Mask /
gmatarrubia	0:820a69dfd200	679
gmatarrubia	0:820a69dfd200	680	/* ITM Trace Control Register Definitions */
gmatarrubia	0:820a69dfd200	681	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
gmatarrubia	0:820a69dfd200	682	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
gmatarrubia	0:820a69dfd200	683
gmatarrubia	0:820a69dfd200	684	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
gmatarrubia	0:820a69dfd200	685	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
gmatarrubia	0:820a69dfd200	686
gmatarrubia	0:820a69dfd200	687	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
gmatarrubia	0:820a69dfd200	688	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
gmatarrubia	0:820a69dfd200	689
gmatarrubia	0:820a69dfd200	690	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
gmatarrubia	0:820a69dfd200	691	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
gmatarrubia	0:820a69dfd200	692
gmatarrubia	0:820a69dfd200	693	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
gmatarrubia	0:820a69dfd200	694	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
gmatarrubia	0:820a69dfd200	695
gmatarrubia	0:820a69dfd200	696	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
gmatarrubia	0:820a69dfd200	697	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
gmatarrubia	0:820a69dfd200	698
gmatarrubia	0:820a69dfd200	699	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
gmatarrubia	0:820a69dfd200	700	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
gmatarrubia	0:820a69dfd200	701
gmatarrubia	0:820a69dfd200	702	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
gmatarrubia	0:820a69dfd200	703	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
gmatarrubia	0:820a69dfd200	704
gmatarrubia	0:820a69dfd200	705	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
gmatarrubia	0:820a69dfd200	706	#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /!< ITM TCR: ITM Enable bit Mask /
gmatarrubia	0:820a69dfd200	707
gmatarrubia	0:820a69dfd200	708	/* ITM Integration Write Register Definitions */
gmatarrubia	0:820a69dfd200	709	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
gmatarrubia	0:820a69dfd200	710	#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /!< ITM IWR: ATVALIDM Mask /
gmatarrubia	0:820a69dfd200	711
gmatarrubia	0:820a69dfd200	712	/* ITM Integration Read Register Definitions */
gmatarrubia	0:820a69dfd200	713	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
gmatarrubia	0:820a69dfd200	714	#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /!< ITM IRR: ATREADYM Mask /
gmatarrubia	0:820a69dfd200	715
gmatarrubia	0:820a69dfd200	716	/* ITM Integration Mode Control Register Definitions */
gmatarrubia	0:820a69dfd200	717	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
gmatarrubia	0:820a69dfd200	718	#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /!< ITM IMCR: INTEGRATION Mask /
gmatarrubia	0:820a69dfd200	719
gmatarrubia	0:820a69dfd200	720	/* ITM Lock Status Register Definitions */
gmatarrubia	0:820a69dfd200	721	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
gmatarrubia	0:820a69dfd200	722	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
gmatarrubia	0:820a69dfd200	723
gmatarrubia	0:820a69dfd200	724	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
gmatarrubia	0:820a69dfd200	725	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
gmatarrubia	0:820a69dfd200	726
gmatarrubia	0:820a69dfd200	727	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
gmatarrubia	0:820a69dfd200	728	#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /!< ITM LSR: Present Mask /
gmatarrubia	0:820a69dfd200	729
gmatarrubia	0:820a69dfd200	730	/@}/ /* end of group CMSIS_ITM */
gmatarrubia	0:820a69dfd200	731
gmatarrubia	0:820a69dfd200	732
gmatarrubia	0:820a69dfd200	733	/** \ingroup CMSIS_core_register
gmatarrubia	0:820a69dfd200	734	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
gmatarrubia	0:820a69dfd200	735	\brief Type definitions for the Data Watchpoint and Trace (DWT)
gmatarrubia	0:820a69dfd200	736	@{
gmatarrubia	0:820a69dfd200	737	*/
gmatarrubia	0:820a69dfd200	738
gmatarrubia	0:820a69dfd200	739	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
gmatarrubia	0:820a69dfd200	740	*/
gmatarrubia	0:820a69dfd200	741	typedef struct
gmatarrubia	0:820a69dfd200	742	{
gmatarrubia	0:820a69dfd200	743	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
gmatarrubia	0:820a69dfd200	744	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
gmatarrubia	0:820a69dfd200	745	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
gmatarrubia	0:820a69dfd200	746	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
gmatarrubia	0:820a69dfd200	747	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
gmatarrubia	0:820a69dfd200	748	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
gmatarrubia	0:820a69dfd200	749	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
gmatarrubia	0:820a69dfd200	750	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
gmatarrubia	0:820a69dfd200	751	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
gmatarrubia	0:820a69dfd200	752	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
gmatarrubia	0:820a69dfd200	753	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
gmatarrubia	0:820a69dfd200	754	uint32_t RESERVED0[1];
gmatarrubia	0:820a69dfd200	755	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
gmatarrubia	0:820a69dfd200	756	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
gmatarrubia	0:820a69dfd200	757	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
gmatarrubia	0:820a69dfd200	758	uint32_t RESERVED1[1];
gmatarrubia	0:820a69dfd200	759	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
gmatarrubia	0:820a69dfd200	760	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
gmatarrubia	0:820a69dfd200	761	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
gmatarrubia	0:820a69dfd200	762	uint32_t RESERVED2[1];
gmatarrubia	0:820a69dfd200	763	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
gmatarrubia	0:820a69dfd200	764	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
gmatarrubia	0:820a69dfd200	765	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
gmatarrubia	0:820a69dfd200	766	} DWT_Type;
gmatarrubia	0:820a69dfd200	767
gmatarrubia	0:820a69dfd200	768	/* DWT Control Register Definitions */
gmatarrubia	0:820a69dfd200	769	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
gmatarrubia	0:820a69dfd200	770	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
gmatarrubia	0:820a69dfd200	771
gmatarrubia	0:820a69dfd200	772	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
gmatarrubia	0:820a69dfd200	773	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
gmatarrubia	0:820a69dfd200	774
gmatarrubia	0:820a69dfd200	775	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
gmatarrubia	0:820a69dfd200	776	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
gmatarrubia	0:820a69dfd200	777
gmatarrubia	0:820a69dfd200	778	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
gmatarrubia	0:820a69dfd200	779	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
gmatarrubia	0:820a69dfd200	780
gmatarrubia	0:820a69dfd200	781	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
gmatarrubia	0:820a69dfd200	782	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
gmatarrubia	0:820a69dfd200	783
gmatarrubia	0:820a69dfd200	784	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
gmatarrubia	0:820a69dfd200	785	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
gmatarrubia	0:820a69dfd200	786
gmatarrubia	0:820a69dfd200	787	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
gmatarrubia	0:820a69dfd200	788	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
gmatarrubia	0:820a69dfd200	789
gmatarrubia	0:820a69dfd200	790	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
gmatarrubia	0:820a69dfd200	791	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
gmatarrubia	0:820a69dfd200	792
gmatarrubia	0:820a69dfd200	793	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
gmatarrubia	0:820a69dfd200	794	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
gmatarrubia	0:820a69dfd200	795
gmatarrubia	0:820a69dfd200	796	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
gmatarrubia	0:820a69dfd200	797	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
gmatarrubia	0:820a69dfd200	798
gmatarrubia	0:820a69dfd200	799	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
gmatarrubia	0:820a69dfd200	800	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
gmatarrubia	0:820a69dfd200	801
gmatarrubia	0:820a69dfd200	802	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
gmatarrubia	0:820a69dfd200	803	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
gmatarrubia	0:820a69dfd200	804
gmatarrubia	0:820a69dfd200	805	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
gmatarrubia	0:820a69dfd200	806	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
gmatarrubia	0:820a69dfd200	807
gmatarrubia	0:820a69dfd200	808	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
gmatarrubia	0:820a69dfd200	809	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
gmatarrubia	0:820a69dfd200	810
gmatarrubia	0:820a69dfd200	811	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
gmatarrubia	0:820a69dfd200	812	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
gmatarrubia	0:820a69dfd200	813
gmatarrubia	0:820a69dfd200	814	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
gmatarrubia	0:820a69dfd200	815	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
gmatarrubia	0:820a69dfd200	816
gmatarrubia	0:820a69dfd200	817	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
gmatarrubia	0:820a69dfd200	818	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
gmatarrubia	0:820a69dfd200	819
gmatarrubia	0:820a69dfd200	820	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
gmatarrubia	0:820a69dfd200	821	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /!< DWT CTRL: CYCCNTENA Mask /
gmatarrubia	0:820a69dfd200	822
gmatarrubia	0:820a69dfd200	823	/* DWT CPI Count Register Definitions */
gmatarrubia	0:820a69dfd200	824	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
gmatarrubia	0:820a69dfd200	825	#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /!< DWT CPICNT: CPICNT Mask /
gmatarrubia	0:820a69dfd200	826
gmatarrubia	0:820a69dfd200	827	/* DWT Exception Overhead Count Register Definitions */
gmatarrubia	0:820a69dfd200	828	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
gmatarrubia	0:820a69dfd200	829	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /!< DWT EXCCNT: EXCCNT Mask /
gmatarrubia	0:820a69dfd200	830
gmatarrubia	0:820a69dfd200	831	/* DWT Sleep Count Register Definitions */
gmatarrubia	0:820a69dfd200	832	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
gmatarrubia	0:820a69dfd200	833	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /!< DWT SLEEPCNT: SLEEPCNT Mask /
gmatarrubia	0:820a69dfd200	834
gmatarrubia	0:820a69dfd200	835	/* DWT LSU Count Register Definitions */
gmatarrubia	0:820a69dfd200	836	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
gmatarrubia	0:820a69dfd200	837	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /!< DWT LSUCNT: LSUCNT Mask /
gmatarrubia	0:820a69dfd200	838
gmatarrubia	0:820a69dfd200	839	/* DWT Folded-instruction Count Register Definitions */
gmatarrubia	0:820a69dfd200	840	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
gmatarrubia	0:820a69dfd200	841	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /!< DWT FOLDCNT: FOLDCNT Mask /
gmatarrubia	0:820a69dfd200	842
gmatarrubia	0:820a69dfd200	843	/* DWT Comparator Mask Register Definitions */
gmatarrubia	0:820a69dfd200	844	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
gmatarrubia	0:820a69dfd200	845	#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /!< DWT MASK: MASK Mask /
gmatarrubia	0:820a69dfd200	846
gmatarrubia	0:820a69dfd200	847	/* DWT Comparator Function Register Definitions */
gmatarrubia	0:820a69dfd200	848	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
gmatarrubia	0:820a69dfd200	849	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
gmatarrubia	0:820a69dfd200	850
gmatarrubia	0:820a69dfd200	851	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
gmatarrubia	0:820a69dfd200	852	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
gmatarrubia	0:820a69dfd200	853
gmatarrubia	0:820a69dfd200	854	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
gmatarrubia	0:820a69dfd200	855	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
gmatarrubia	0:820a69dfd200	856
gmatarrubia	0:820a69dfd200	857	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
gmatarrubia	0:820a69dfd200	858	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
gmatarrubia	0:820a69dfd200	859
gmatarrubia	0:820a69dfd200	860	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
gmatarrubia	0:820a69dfd200	861	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
gmatarrubia	0:820a69dfd200	862
gmatarrubia	0:820a69dfd200	863	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
gmatarrubia	0:820a69dfd200	864	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
gmatarrubia	0:820a69dfd200	865
gmatarrubia	0:820a69dfd200	866	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
gmatarrubia	0:820a69dfd200	867	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
gmatarrubia	0:820a69dfd200	868
gmatarrubia	0:820a69dfd200	869	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
gmatarrubia	0:820a69dfd200	870	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
gmatarrubia	0:820a69dfd200	871
gmatarrubia	0:820a69dfd200	872	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
gmatarrubia	0:820a69dfd200	873	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /!< DWT FUNCTION: FUNCTION Mask /
gmatarrubia	0:820a69dfd200	874
gmatarrubia	0:820a69dfd200	875	/@}/ /* end of group CMSIS_DWT */
gmatarrubia	0:820a69dfd200	876
gmatarrubia	0:820a69dfd200	877
gmatarrubia	0:820a69dfd200	878	/** \ingroup CMSIS_core_register
gmatarrubia	0:820a69dfd200	879	\defgroup CMSIS_TPI Trace Port Interface (TPI)
gmatarrubia	0:820a69dfd200	880	\brief Type definitions for the Trace Port Interface (TPI)
gmatarrubia	0:820a69dfd200	881	@{
gmatarrubia	0:820a69dfd200	882	*/
gmatarrubia	0:820a69dfd200	883
gmatarrubia	0:820a69dfd200	884	/** \brief Structure type to access the Trace Port Interface Register (TPI).
gmatarrubia	0:820a69dfd200	885	*/
gmatarrubia	0:820a69dfd200	886	typedef struct
gmatarrubia	0:820a69dfd200	887	{
gmatarrubia	0:820a69dfd200	888	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
gmatarrubia	0:820a69dfd200	889	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
gmatarrubia	0:820a69dfd200	890	uint32_t RESERVED0[2];
gmatarrubia	0:820a69dfd200	891	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
gmatarrubia	0:820a69dfd200	892	uint32_t RESERVED1[55];
gmatarrubia	0:820a69dfd200	893	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
gmatarrubia	0:820a69dfd200	894	uint32_t RESERVED2[131];
gmatarrubia	0:820a69dfd200	895	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
gmatarrubia	0:820a69dfd200	896	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
gmatarrubia	0:820a69dfd200	897	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
gmatarrubia	0:820a69dfd200	898	uint32_t RESERVED3[759];
gmatarrubia	0:820a69dfd200	899	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
gmatarrubia	0:820a69dfd200	900	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
gmatarrubia	0:820a69dfd200	901	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
gmatarrubia	0:820a69dfd200	902	uint32_t RESERVED4[1];
gmatarrubia	0:820a69dfd200	903	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
gmatarrubia	0:820a69dfd200	904	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
gmatarrubia	0:820a69dfd200	905	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
gmatarrubia	0:820a69dfd200	906	uint32_t RESERVED5[39];
gmatarrubia	0:820a69dfd200	907	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
gmatarrubia	0:820a69dfd200	908	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
gmatarrubia	0:820a69dfd200	909	uint32_t RESERVED7[8];
gmatarrubia	0:820a69dfd200	910	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
gmatarrubia	0:820a69dfd200	911	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
gmatarrubia	0:820a69dfd200	912	} TPI_Type;
gmatarrubia	0:820a69dfd200	913
gmatarrubia	0:820a69dfd200	914	/* TPI Asynchronous Clock Prescaler Register Definitions */
gmatarrubia	0:820a69dfd200	915	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
gmatarrubia	0:820a69dfd200	916	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /!< TPI ACPR: PRESCALER Mask /
gmatarrubia	0:820a69dfd200	917
gmatarrubia	0:820a69dfd200	918	/* TPI Selected Pin Protocol Register Definitions */
gmatarrubia	0:820a69dfd200	919	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
gmatarrubia	0:820a69dfd200	920	#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /!< TPI SPPR: TXMODE Mask /
gmatarrubia	0:820a69dfd200	921
gmatarrubia	0:820a69dfd200	922	/* TPI Formatter and Flush Status Register Definitions */
gmatarrubia	0:820a69dfd200	923	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
gmatarrubia	0:820a69dfd200	924	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
gmatarrubia	0:820a69dfd200	925
gmatarrubia	0:820a69dfd200	926	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
gmatarrubia	0:820a69dfd200	927	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
gmatarrubia	0:820a69dfd200	928
gmatarrubia	0:820a69dfd200	929	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
gmatarrubia	0:820a69dfd200	930	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
gmatarrubia	0:820a69dfd200	931
gmatarrubia	0:820a69dfd200	932	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
gmatarrubia	0:820a69dfd200	933	#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /!< TPI FFSR: FlInProg Mask /
gmatarrubia	0:820a69dfd200	934
gmatarrubia	0:820a69dfd200	935	/* TPI Formatter and Flush Control Register Definitions */
gmatarrubia	0:820a69dfd200	936	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
gmatarrubia	0:820a69dfd200	937	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
gmatarrubia	0:820a69dfd200	938
gmatarrubia	0:820a69dfd200	939	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
gmatarrubia	0:820a69dfd200	940	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
gmatarrubia	0:820a69dfd200	941
gmatarrubia	0:820a69dfd200	942	/* TPI TRIGGER Register Definitions */
gmatarrubia	0:820a69dfd200	943	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
gmatarrubia	0:820a69dfd200	944	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /!< TPI TRIGGER: TRIGGER Mask /
gmatarrubia	0:820a69dfd200	945
gmatarrubia	0:820a69dfd200	946	/* TPI Integration ETM Data Register Definitions (FIFO0) */
gmatarrubia	0:820a69dfd200	947	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
gmatarrubia	0:820a69dfd200	948	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
gmatarrubia	0:820a69dfd200	949
gmatarrubia	0:820a69dfd200	950	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
gmatarrubia	0:820a69dfd200	951	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
gmatarrubia	0:820a69dfd200	952
gmatarrubia	0:820a69dfd200	953	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
gmatarrubia	0:820a69dfd200	954	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
gmatarrubia	0:820a69dfd200	955
gmatarrubia	0:820a69dfd200	956	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
gmatarrubia	0:820a69dfd200	957	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
gmatarrubia	0:820a69dfd200	958
gmatarrubia	0:820a69dfd200	959	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
gmatarrubia	0:820a69dfd200	960	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
gmatarrubia	0:820a69dfd200	961
gmatarrubia	0:820a69dfd200	962	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
gmatarrubia	0:820a69dfd200	963	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
gmatarrubia	0:820a69dfd200	964
gmatarrubia	0:820a69dfd200	965	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
gmatarrubia	0:820a69dfd200	966	#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /!< TPI FIFO0: ETM0 Mask /
gmatarrubia	0:820a69dfd200	967
gmatarrubia	0:820a69dfd200	968	/* TPI ITATBCTR2 Register Definitions */
gmatarrubia	0:820a69dfd200	969	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
gmatarrubia	0:820a69dfd200	970	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /!< TPI ITATBCTR2: ATREADY Mask /
gmatarrubia	0:820a69dfd200	971
gmatarrubia	0:820a69dfd200	972	/* TPI Integration ITM Data Register Definitions (FIFO1) */
gmatarrubia	0:820a69dfd200	973	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
gmatarrubia	0:820a69dfd200	974	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
gmatarrubia	0:820a69dfd200	975
gmatarrubia	0:820a69dfd200	976	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
gmatarrubia	0:820a69dfd200	977	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
gmatarrubia	0:820a69dfd200	978
gmatarrubia	0:820a69dfd200	979	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
gmatarrubia	0:820a69dfd200	980	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
gmatarrubia	0:820a69dfd200	981
gmatarrubia	0:820a69dfd200	982	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
gmatarrubia	0:820a69dfd200	983	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
gmatarrubia	0:820a69dfd200	984
gmatarrubia	0:820a69dfd200	985	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
gmatarrubia	0:820a69dfd200	986	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
gmatarrubia	0:820a69dfd200	987
gmatarrubia	0:820a69dfd200	988	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
gmatarrubia	0:820a69dfd200	989	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
gmatarrubia	0:820a69dfd200	990
gmatarrubia	0:820a69dfd200	991	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
gmatarrubia	0:820a69dfd200	992	#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /!< TPI FIFO1: ITM0 Mask /
gmatarrubia	0:820a69dfd200	993
gmatarrubia	0:820a69dfd200	994	/* TPI ITATBCTR0 Register Definitions */
gmatarrubia	0:820a69dfd200	995	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
gmatarrubia	0:820a69dfd200	996	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /!< TPI ITATBCTR0: ATREADY Mask /
gmatarrubia	0:820a69dfd200	997
gmatarrubia	0:820a69dfd200	998	/* TPI Integration Mode Control Register Definitions */
gmatarrubia	0:820a69dfd200	999	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
gmatarrubia	0:820a69dfd200	1000	#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /!< TPI ITCTRL: Mode Mask /
gmatarrubia	0:820a69dfd200	1001
gmatarrubia	0:820a69dfd200	1002	/* TPI DEVID Register Definitions */
gmatarrubia	0:820a69dfd200	1003	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
gmatarrubia	0:820a69dfd200	1004	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
gmatarrubia	0:820a69dfd200	1005
gmatarrubia	0:820a69dfd200	1006	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
gmatarrubia	0:820a69dfd200	1007	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
gmatarrubia	0:820a69dfd200	1008
gmatarrubia	0:820a69dfd200	1009	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
gmatarrubia	0:820a69dfd200	1010	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
gmatarrubia	0:820a69dfd200	1011
gmatarrubia	0:820a69dfd200	1012	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
gmatarrubia	0:820a69dfd200	1013	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
gmatarrubia	0:820a69dfd200	1014
gmatarrubia	0:820a69dfd200	1015	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
gmatarrubia	0:820a69dfd200	1016	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
gmatarrubia	0:820a69dfd200	1017
gmatarrubia	0:820a69dfd200	1018	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
gmatarrubia	0:820a69dfd200	1019	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /!< TPI DEVID: NrTraceInput Mask /
gmatarrubia	0:820a69dfd200	1020
gmatarrubia	0:820a69dfd200	1021	/* TPI DEVTYPE Register Definitions */
gmatarrubia	0:820a69dfd200	1022	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
gmatarrubia	0:820a69dfd200	1023	#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /!< TPI DEVTYPE: SubType Mask /
gmatarrubia	0:820a69dfd200	1024
gmatarrubia	0:820a69dfd200	1025	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
gmatarrubia	0:820a69dfd200	1026	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
gmatarrubia	0:820a69dfd200	1027
gmatarrubia	0:820a69dfd200	1028	/@}/ /* end of group CMSIS_TPI */
gmatarrubia	0:820a69dfd200	1029
gmatarrubia	0:820a69dfd200	1030
gmatarrubia	0:820a69dfd200	1031	#if (__MPU_PRESENT == 1)
gmatarrubia	0:820a69dfd200	1032	/** \ingroup CMSIS_core_register
gmatarrubia	0:820a69dfd200	1033	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
gmatarrubia	0:820a69dfd200	1034	\brief Type definitions for the Memory Protection Unit (MPU)
gmatarrubia	0:820a69dfd200	1035	@{
gmatarrubia	0:820a69dfd200	1036	*/
gmatarrubia	0:820a69dfd200	1037
gmatarrubia	0:820a69dfd200	1038	/** \brief Structure type to access the Memory Protection Unit (MPU).
gmatarrubia	0:820a69dfd200	1039	*/
gmatarrubia	0:820a69dfd200	1040	typedef struct
gmatarrubia	0:820a69dfd200	1041	{
gmatarrubia	0:820a69dfd200	1042	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
gmatarrubia	0:820a69dfd200	1043	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
gmatarrubia	0:820a69dfd200	1044	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
gmatarrubia	0:820a69dfd200	1045	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
gmatarrubia	0:820a69dfd200	1046	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
gmatarrubia	0:820a69dfd200	1047	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
gmatarrubia	0:820a69dfd200	1048	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
gmatarrubia	0:820a69dfd200	1049	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
gmatarrubia	0:820a69dfd200	1050	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
gmatarrubia	0:820a69dfd200	1051	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
gmatarrubia	0:820a69dfd200	1052	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
gmatarrubia	0:820a69dfd200	1053	} MPU_Type;
gmatarrubia	0:820a69dfd200	1054
gmatarrubia	0:820a69dfd200	1055	/* MPU Type Register */
gmatarrubia	0:820a69dfd200	1056	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
gmatarrubia	0:820a69dfd200	1057	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
gmatarrubia	0:820a69dfd200	1058
gmatarrubia	0:820a69dfd200	1059	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
gmatarrubia	0:820a69dfd200	1060	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
gmatarrubia	0:820a69dfd200	1061
gmatarrubia	0:820a69dfd200	1062	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
gmatarrubia	0:820a69dfd200	1063	#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /!< MPU TYPE: SEPARATE Mask /
gmatarrubia	0:820a69dfd200	1064
gmatarrubia	0:820a69dfd200	1065	/* MPU Control Register */
gmatarrubia	0:820a69dfd200	1066	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
gmatarrubia	0:820a69dfd200	1067	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
gmatarrubia	0:820a69dfd200	1068
gmatarrubia	0:820a69dfd200	1069	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
gmatarrubia	0:820a69dfd200	1070	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
gmatarrubia	0:820a69dfd200	1071
gmatarrubia	0:820a69dfd200	1072	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
gmatarrubia	0:820a69dfd200	1073	#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /!< MPU CTRL: ENABLE Mask /
gmatarrubia	0:820a69dfd200	1074
gmatarrubia	0:820a69dfd200	1075	/* MPU Region Number Register */
gmatarrubia	0:820a69dfd200	1076	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
gmatarrubia	0:820a69dfd200	1077	#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /!< MPU RNR: REGION Mask /
gmatarrubia	0:820a69dfd200	1078
gmatarrubia	0:820a69dfd200	1079	/* MPU Region Base Address Register */
gmatarrubia	0:820a69dfd200	1080	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
gmatarrubia	0:820a69dfd200	1081	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
gmatarrubia	0:820a69dfd200	1082
gmatarrubia	0:820a69dfd200	1083	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
gmatarrubia	0:820a69dfd200	1084	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
gmatarrubia	0:820a69dfd200	1085
gmatarrubia	0:820a69dfd200	1086	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
gmatarrubia	0:820a69dfd200	1087	#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /!< MPU RBAR: REGION Mask /
gmatarrubia	0:820a69dfd200	1088
gmatarrubia	0:820a69dfd200	1089	/* MPU Region Attribute and Size Register */
gmatarrubia	0:820a69dfd200	1090	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
gmatarrubia	0:820a69dfd200	1091	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
gmatarrubia	0:820a69dfd200	1092
gmatarrubia	0:820a69dfd200	1093	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
gmatarrubia	0:820a69dfd200	1094	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
gmatarrubia	0:820a69dfd200	1095
gmatarrubia	0:820a69dfd200	1096	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
gmatarrubia	0:820a69dfd200	1097	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
gmatarrubia	0:820a69dfd200	1098
gmatarrubia	0:820a69dfd200	1099	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
gmatarrubia	0:820a69dfd200	1100	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
gmatarrubia	0:820a69dfd200	1101
gmatarrubia	0:820a69dfd200	1102	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
gmatarrubia	0:820a69dfd200	1103	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
gmatarrubia	0:820a69dfd200	1104
gmatarrubia	0:820a69dfd200	1105	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
gmatarrubia	0:820a69dfd200	1106	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
gmatarrubia	0:820a69dfd200	1107
gmatarrubia	0:820a69dfd200	1108	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
gmatarrubia	0:820a69dfd200	1109	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
gmatarrubia	0:820a69dfd200	1110
gmatarrubia	0:820a69dfd200	1111	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
gmatarrubia	0:820a69dfd200	1112	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
gmatarrubia	0:820a69dfd200	1113
gmatarrubia	0:820a69dfd200	1114	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
gmatarrubia	0:820a69dfd200	1115	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
gmatarrubia	0:820a69dfd200	1116
gmatarrubia	0:820a69dfd200	1117	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
gmatarrubia	0:820a69dfd200	1118	#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /!< MPU RASR: Region enable bit Disable Mask /
gmatarrubia	0:820a69dfd200	1119
gmatarrubia	0:820a69dfd200	1120	/@} end of group CMSIS_MPU /
gmatarrubia	0:820a69dfd200	1121	#endif
gmatarrubia	0:820a69dfd200	1122
gmatarrubia	0:820a69dfd200	1123
gmatarrubia	0:820a69dfd200	1124	/** \ingroup CMSIS_core_register
gmatarrubia	0:820a69dfd200	1125	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
gmatarrubia	0:820a69dfd200	1126	\brief Type definitions for the Core Debug Registers
gmatarrubia	0:820a69dfd200	1127	@{
gmatarrubia	0:820a69dfd200	1128	*/
gmatarrubia	0:820a69dfd200	1129
gmatarrubia	0:820a69dfd200	1130	/** \brief Structure type to access the Core Debug Register (CoreDebug).
gmatarrubia	0:820a69dfd200	1131	*/
gmatarrubia	0:820a69dfd200	1132	typedef struct
gmatarrubia	0:820a69dfd200	1133	{
gmatarrubia	0:820a69dfd200	1134	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
gmatarrubia	0:820a69dfd200	1135	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
gmatarrubia	0:820a69dfd200	1136	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
gmatarrubia	0:820a69dfd200	1137	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
gmatarrubia	0:820a69dfd200	1138	} CoreDebug_Type;
gmatarrubia	0:820a69dfd200	1139
gmatarrubia	0:820a69dfd200	1140	/* Debug Halting Control and Status Register */
gmatarrubia	0:820a69dfd200	1141	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
gmatarrubia	0:820a69dfd200	1142	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
gmatarrubia	0:820a69dfd200	1143
gmatarrubia	0:820a69dfd200	1144	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
gmatarrubia	0:820a69dfd200	1145	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
gmatarrubia	0:820a69dfd200	1146
gmatarrubia	0:820a69dfd200	1147	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
gmatarrubia	0:820a69dfd200	1148	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
gmatarrubia	0:820a69dfd200	1149
gmatarrubia	0:820a69dfd200	1150	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
gmatarrubia	0:820a69dfd200	1151	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
gmatarrubia	0:820a69dfd200	1152
gmatarrubia	0:820a69dfd200	1153	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
gmatarrubia	0:820a69dfd200	1154	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
gmatarrubia	0:820a69dfd200	1155
gmatarrubia	0:820a69dfd200	1156	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
gmatarrubia	0:820a69dfd200	1157	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
gmatarrubia	0:820a69dfd200	1158
gmatarrubia	0:820a69dfd200	1159	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
gmatarrubia	0:820a69dfd200	1160	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
gmatarrubia	0:820a69dfd200	1161
gmatarrubia	0:820a69dfd200	1162	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
gmatarrubia	0:820a69dfd200	1163	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
gmatarrubia	0:820a69dfd200	1164
gmatarrubia	0:820a69dfd200	1165	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
gmatarrubia	0:820a69dfd200	1166	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
gmatarrubia	0:820a69dfd200	1167
gmatarrubia	0:820a69dfd200	1168	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
gmatarrubia	0:820a69dfd200	1169	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
gmatarrubia	0:820a69dfd200	1170
gmatarrubia	0:820a69dfd200	1171	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
gmatarrubia	0:820a69dfd200	1172	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
gmatarrubia	0:820a69dfd200	1173
gmatarrubia	0:820a69dfd200	1174	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
gmatarrubia	0:820a69dfd200	1175	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
gmatarrubia	0:820a69dfd200	1176
gmatarrubia	0:820a69dfd200	1177	/* Debug Core Register Selector Register */
gmatarrubia	0:820a69dfd200	1178	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
gmatarrubia	0:820a69dfd200	1179	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
gmatarrubia	0:820a69dfd200	1180
gmatarrubia	0:820a69dfd200	1181	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
gmatarrubia	0:820a69dfd200	1182	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /!< CoreDebug DCRSR: REGSEL Mask /
gmatarrubia	0:820a69dfd200	1183
gmatarrubia	0:820a69dfd200	1184	/* Debug Exception and Monitor Control Register */
gmatarrubia	0:820a69dfd200	1185	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
gmatarrubia	0:820a69dfd200	1186	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
gmatarrubia	0:820a69dfd200	1187
gmatarrubia	0:820a69dfd200	1188	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
gmatarrubia	0:820a69dfd200	1189	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
gmatarrubia	0:820a69dfd200	1190
gmatarrubia	0:820a69dfd200	1191	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
gmatarrubia	0:820a69dfd200	1192	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
gmatarrubia	0:820a69dfd200	1193
gmatarrubia	0:820a69dfd200	1194	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
gmatarrubia	0:820a69dfd200	1195	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
gmatarrubia	0:820a69dfd200	1196
gmatarrubia	0:820a69dfd200	1197	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
gmatarrubia	0:820a69dfd200	1198	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
gmatarrubia	0:820a69dfd200	1199
gmatarrubia	0:820a69dfd200	1200	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
gmatarrubia	0:820a69dfd200	1201	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
gmatarrubia	0:820a69dfd200	1202
gmatarrubia	0:820a69dfd200	1203	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
gmatarrubia	0:820a69dfd200	1204	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
gmatarrubia	0:820a69dfd200	1205
gmatarrubia	0:820a69dfd200	1206	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
gmatarrubia	0:820a69dfd200	1207	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
gmatarrubia	0:820a69dfd200	1208
gmatarrubia	0:820a69dfd200	1209	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
gmatarrubia	0:820a69dfd200	1210	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
gmatarrubia	0:820a69dfd200	1211
gmatarrubia	0:820a69dfd200	1212	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
gmatarrubia	0:820a69dfd200	1213	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
gmatarrubia	0:820a69dfd200	1214
gmatarrubia	0:820a69dfd200	1215	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
gmatarrubia	0:820a69dfd200	1216	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
gmatarrubia	0:820a69dfd200	1217
gmatarrubia	0:820a69dfd200	1218	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
gmatarrubia	0:820a69dfd200	1219	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
gmatarrubia	0:820a69dfd200	1220
gmatarrubia	0:820a69dfd200	1221	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
gmatarrubia	0:820a69dfd200	1222	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /!< CoreDebug DEMCR: VC_CORERESET Mask /
gmatarrubia	0:820a69dfd200	1223
gmatarrubia	0:820a69dfd200	1224	/@} end of group CMSIS_CoreDebug /
gmatarrubia	0:820a69dfd200	1225
gmatarrubia	0:820a69dfd200	1226
gmatarrubia	0:820a69dfd200	1227	/** \ingroup CMSIS_core_register
gmatarrubia	0:820a69dfd200	1228	\defgroup CMSIS_core_base Core Definitions
gmatarrubia	0:820a69dfd200	1229	\brief Definitions for base addresses, unions, and structures.
gmatarrubia	0:820a69dfd200	1230	@{
gmatarrubia	0:820a69dfd200	1231	*/
gmatarrubia	0:820a69dfd200	1232
gmatarrubia	0:820a69dfd200	1233	/* Memory mapping of Cortex-M3 Hardware */
gmatarrubia	0:820a69dfd200	1234	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
gmatarrubia	0:820a69dfd200	1235	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
gmatarrubia	0:820a69dfd200	1236	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
gmatarrubia	0:820a69dfd200	1237	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
gmatarrubia	0:820a69dfd200	1238	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
gmatarrubia	0:820a69dfd200	1239	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
gmatarrubia	0:820a69dfd200	1240	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
gmatarrubia	0:820a69dfd200	1241	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
gmatarrubia	0:820a69dfd200	1242
gmatarrubia	0:820a69dfd200	1243	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
gmatarrubia	0:820a69dfd200	1244	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
gmatarrubia	0:820a69dfd200	1245	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
gmatarrubia	0:820a69dfd200	1246	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
gmatarrubia	0:820a69dfd200	1247	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
gmatarrubia	0:820a69dfd200	1248	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
gmatarrubia	0:820a69dfd200	1249	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
gmatarrubia	0:820a69dfd200	1250	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
gmatarrubia	0:820a69dfd200	1251
gmatarrubia	0:820a69dfd200	1252	#if (__MPU_PRESENT == 1)
gmatarrubia	0:820a69dfd200	1253	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
gmatarrubia	0:820a69dfd200	1254	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
gmatarrubia	0:820a69dfd200	1255	#endif
gmatarrubia	0:820a69dfd200	1256
gmatarrubia	0:820a69dfd200	1257	/@} /
gmatarrubia	0:820a69dfd200	1258
gmatarrubia	0:820a69dfd200	1259
gmatarrubia	0:820a69dfd200	1260
gmatarrubia	0:820a69dfd200	1261	/*******************************************************************************
gmatarrubia	0:820a69dfd200	1262	* Hardware Abstraction Layer
gmatarrubia	0:820a69dfd200	1263	Core Function Interface contains:
gmatarrubia	0:820a69dfd200	1264	- Core NVIC Functions
gmatarrubia	0:820a69dfd200	1265	- Core SysTick Functions
gmatarrubia	0:820a69dfd200	1266	- Core Debug Functions
gmatarrubia	0:820a69dfd200	1267	- Core Register Access Functions
gmatarrubia	0:820a69dfd200	1268	******************************************************************************/
gmatarrubia	0:820a69dfd200	1269	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
gmatarrubia	0:820a69dfd200	1270	*/
gmatarrubia	0:820a69dfd200	1271
gmatarrubia	0:820a69dfd200	1272
gmatarrubia	0:820a69dfd200	1273
gmatarrubia	0:820a69dfd200	1274	/* ########################## NVIC functions #################################### */
gmatarrubia	0:820a69dfd200	1275	/** \ingroup CMSIS_Core_FunctionInterface
gmatarrubia	0:820a69dfd200	1276	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
gmatarrubia	0:820a69dfd200	1277	\brief Functions that manage interrupts and exceptions via the NVIC.
gmatarrubia	0:820a69dfd200	1278	@{
gmatarrubia	0:820a69dfd200	1279	*/
gmatarrubia	0:820a69dfd200	1280
gmatarrubia	0:820a69dfd200	1281	/** \brief Set Priority Grouping
gmatarrubia	0:820a69dfd200	1282
gmatarrubia	0:820a69dfd200	1283	The function sets the priority grouping field using the required unlock sequence.
gmatarrubia	0:820a69dfd200	1284	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
gmatarrubia	0:820a69dfd200	1285	Only values from 0..7 are used.
gmatarrubia	0:820a69dfd200	1286	In case of a conflict between priority grouping and available
gmatarrubia	0:820a69dfd200	1287	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
gmatarrubia	0:820a69dfd200	1288
gmatarrubia	0:820a69dfd200	1289	\param [in] PriorityGroup Priority grouping field.
gmatarrubia	0:820a69dfd200	1290	*/
gmatarrubia	0:820a69dfd200	1291	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
gmatarrubia	0:820a69dfd200	1292	{
gmatarrubia	0:820a69dfd200	1293	uint32_t reg_value;
gmatarrubia	0:820a69dfd200	1294	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
gmatarrubia	0:820a69dfd200	1295
gmatarrubia	0:820a69dfd200	1296	reg_value = SCB->AIRCR; /* read old register configuration */
gmatarrubia	0:820a69dfd200	1297	reg_value &= ~(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
gmatarrubia	0:820a69dfd200	1298	reg_value = (reg_value \|
gmatarrubia	0:820a69dfd200	1299	((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
gmatarrubia	0:820a69dfd200	1300	(PriorityGroupTmp << 8)); /* Insert write key and priorty group */
gmatarrubia	0:820a69dfd200	1301	SCB->AIRCR = reg_value;
gmatarrubia	0:820a69dfd200	1302	}
gmatarrubia	0:820a69dfd200	1303
gmatarrubia	0:820a69dfd200	1304
gmatarrubia	0:820a69dfd200	1305	/** \brief Get Priority Grouping
gmatarrubia	0:820a69dfd200	1306
gmatarrubia	0:820a69dfd200	1307	The function reads the priority grouping field from the NVIC Interrupt Controller.
gmatarrubia	0:820a69dfd200	1308
gmatarrubia	0:820a69dfd200	1309	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
gmatarrubia	0:820a69dfd200	1310	*/
gmatarrubia	0:820a69dfd200	1311	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
gmatarrubia	0:820a69dfd200	1312	{
gmatarrubia	0:820a69dfd200	1313	return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
gmatarrubia	0:820a69dfd200	1314	}
gmatarrubia	0:820a69dfd200	1315
gmatarrubia	0:820a69dfd200	1316
gmatarrubia	0:820a69dfd200	1317	/** \brief Enable External Interrupt
gmatarrubia	0:820a69dfd200	1318
gmatarrubia	0:820a69dfd200	1319	The function enables a device-specific interrupt in the NVIC interrupt controller.
gmatarrubia	0:820a69dfd200	1320
gmatarrubia	0:820a69dfd200	1321	\param [in] IRQn External interrupt number. Value cannot be negative.
gmatarrubia	0:820a69dfd200	1322	*/
gmatarrubia	0:820a69dfd200	1323	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
gmatarrubia	0:820a69dfd200	1324	{
gmatarrubia	0:820a69dfd200	1325	NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
gmatarrubia	0:820a69dfd200	1326	}
gmatarrubia	0:820a69dfd200	1327
gmatarrubia	0:820a69dfd200	1328
gmatarrubia	0:820a69dfd200	1329	/** \brief Disable External Interrupt
gmatarrubia	0:820a69dfd200	1330
gmatarrubia	0:820a69dfd200	1331	The function disables a device-specific interrupt in the NVIC interrupt controller.
gmatarrubia	0:820a69dfd200	1332
gmatarrubia	0:820a69dfd200	1333	\param [in] IRQn External interrupt number. Value cannot be negative.
gmatarrubia	0:820a69dfd200	1334	*/
gmatarrubia	0:820a69dfd200	1335	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
gmatarrubia	0:820a69dfd200	1336	{
gmatarrubia	0:820a69dfd200	1337	NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
gmatarrubia	0:820a69dfd200	1338	}
gmatarrubia	0:820a69dfd200	1339
gmatarrubia	0:820a69dfd200	1340
gmatarrubia	0:820a69dfd200	1341	/** \brief Get Pending Interrupt
gmatarrubia	0:820a69dfd200	1342
gmatarrubia	0:820a69dfd200	1343	The function reads the pending register in the NVIC and returns the pending bit
gmatarrubia	0:820a69dfd200	1344	for the specified interrupt.
gmatarrubia	0:820a69dfd200	1345
gmatarrubia	0:820a69dfd200	1346	\param [in] IRQn Interrupt number.
gmatarrubia	0:820a69dfd200	1347
gmatarrubia	0:820a69dfd200	1348	\return 0 Interrupt status is not pending.
gmatarrubia	0:820a69dfd200	1349	\return 1 Interrupt status is pending.
gmatarrubia	0:820a69dfd200	1350	*/
gmatarrubia	0:820a69dfd200	1351	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
gmatarrubia	0:820a69dfd200	1352	{
gmatarrubia	0:820a69dfd200	1353	return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
gmatarrubia	0:820a69dfd200	1354	}
gmatarrubia	0:820a69dfd200	1355
gmatarrubia	0:820a69dfd200	1356
gmatarrubia	0:820a69dfd200	1357	/** \brief Set Pending Interrupt
gmatarrubia	0:820a69dfd200	1358
gmatarrubia	0:820a69dfd200	1359	The function sets the pending bit of an external interrupt.
gmatarrubia	0:820a69dfd200	1360
gmatarrubia	0:820a69dfd200	1361	\param [in] IRQn Interrupt number. Value cannot be negative.
gmatarrubia	0:820a69dfd200	1362	*/
gmatarrubia	0:820a69dfd200	1363	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
gmatarrubia	0:820a69dfd200	1364	{
gmatarrubia	0:820a69dfd200	1365	NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
gmatarrubia	0:820a69dfd200	1366	}
gmatarrubia	0:820a69dfd200	1367
gmatarrubia	0:820a69dfd200	1368
gmatarrubia	0:820a69dfd200	1369	/** \brief Clear Pending Interrupt
gmatarrubia	0:820a69dfd200	1370
gmatarrubia	0:820a69dfd200	1371	The function clears the pending bit of an external interrupt.
gmatarrubia	0:820a69dfd200	1372
gmatarrubia	0:820a69dfd200	1373	\param [in] IRQn External interrupt number. Value cannot be negative.
gmatarrubia	0:820a69dfd200	1374	*/
gmatarrubia	0:820a69dfd200	1375	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
gmatarrubia	0:820a69dfd200	1376	{
gmatarrubia	0:820a69dfd200	1377	NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
gmatarrubia	0:820a69dfd200	1378	}
gmatarrubia	0:820a69dfd200	1379
gmatarrubia	0:820a69dfd200	1380
gmatarrubia	0:820a69dfd200	1381	/** \brief Get Active Interrupt
gmatarrubia	0:820a69dfd200	1382
gmatarrubia	0:820a69dfd200	1383	The function reads the active register in NVIC and returns the active bit.
gmatarrubia	0:820a69dfd200	1384
gmatarrubia	0:820a69dfd200	1385	\param [in] IRQn Interrupt number.
gmatarrubia	0:820a69dfd200	1386
gmatarrubia	0:820a69dfd200	1387	\return 0 Interrupt status is not active.
gmatarrubia	0:820a69dfd200	1388	\return 1 Interrupt status is active.
gmatarrubia	0:820a69dfd200	1389	*/
gmatarrubia	0:820a69dfd200	1390	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
gmatarrubia	0:820a69dfd200	1391	{
gmatarrubia	0:820a69dfd200	1392	return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
gmatarrubia	0:820a69dfd200	1393	}
gmatarrubia	0:820a69dfd200	1394
gmatarrubia	0:820a69dfd200	1395
gmatarrubia	0:820a69dfd200	1396	/** \brief Set Interrupt Priority
gmatarrubia	0:820a69dfd200	1397
gmatarrubia	0:820a69dfd200	1398	The function sets the priority of an interrupt.
gmatarrubia	0:820a69dfd200	1399
gmatarrubia	0:820a69dfd200	1400	\note The priority cannot be set for every core interrupt.
gmatarrubia	0:820a69dfd200	1401
gmatarrubia	0:820a69dfd200	1402	\param [in] IRQn Interrupt number.
gmatarrubia	0:820a69dfd200	1403	\param [in] priority Priority to set.
gmatarrubia	0:820a69dfd200	1404	*/
gmatarrubia	0:820a69dfd200	1405	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
gmatarrubia	0:820a69dfd200	1406	{
gmatarrubia	0:820a69dfd200	1407	if(IRQn < 0) {
gmatarrubia	0:820a69dfd200	1408	SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
gmatarrubia	0:820a69dfd200	1409	else {
gmatarrubia	0:820a69dfd200	1410	NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
gmatarrubia	0:820a69dfd200	1411	}
gmatarrubia	0:820a69dfd200	1412
gmatarrubia	0:820a69dfd200	1413
gmatarrubia	0:820a69dfd200	1414	/** \brief Get Interrupt Priority
gmatarrubia	0:820a69dfd200	1415
gmatarrubia	0:820a69dfd200	1416	The function reads the priority of an interrupt. The interrupt
gmatarrubia	0:820a69dfd200	1417	number can be positive to specify an external (device specific)
gmatarrubia	0:820a69dfd200	1418	interrupt, or negative to specify an internal (core) interrupt.
gmatarrubia	0:820a69dfd200	1419
gmatarrubia	0:820a69dfd200	1420
gmatarrubia	0:820a69dfd200	1421	\param [in] IRQn Interrupt number.
gmatarrubia	0:820a69dfd200	1422	\return Interrupt Priority. Value is aligned automatically to the implemented
gmatarrubia	0:820a69dfd200	1423	priority bits of the microcontroller.
gmatarrubia	0:820a69dfd200	1424	*/
gmatarrubia	0:820a69dfd200	1425	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
gmatarrubia	0:820a69dfd200	1426	{
gmatarrubia	0:820a69dfd200	1427
gmatarrubia	0:820a69dfd200	1428	if(IRQn < 0) {
gmatarrubia	0:820a69dfd200	1429	return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
gmatarrubia	0:820a69dfd200	1430	else {
gmatarrubia	0:820a69dfd200	1431	return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
gmatarrubia	0:820a69dfd200	1432	}
gmatarrubia	0:820a69dfd200	1433
gmatarrubia	0:820a69dfd200	1434
gmatarrubia	0:820a69dfd200	1435	/** \brief Encode Priority
gmatarrubia	0:820a69dfd200	1436
gmatarrubia	0:820a69dfd200	1437	The function encodes the priority for an interrupt with the given priority group,
gmatarrubia	0:820a69dfd200	1438	preemptive priority value, and subpriority value.
gmatarrubia	0:820a69dfd200	1439	In case of a conflict between priority grouping and available
gmatarrubia	0:820a69dfd200	1440	priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
gmatarrubia	0:820a69dfd200	1441
gmatarrubia	0:820a69dfd200	1442	\param [in] PriorityGroup Used priority group.
gmatarrubia	0:820a69dfd200	1443	\param [in] PreemptPriority Preemptive priority value (starting from 0).
gmatarrubia	0:820a69dfd200	1444	\param [in] SubPriority Subpriority value (starting from 0).
gmatarrubia	0:820a69dfd200	1445	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
gmatarrubia	0:820a69dfd200	1446	*/
gmatarrubia	0:820a69dfd200	1447	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
gmatarrubia	0:820a69dfd200	1448	{
gmatarrubia	0:820a69dfd200	1449	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
gmatarrubia	0:820a69dfd200	1450	uint32_t PreemptPriorityBits;
gmatarrubia	0:820a69dfd200	1451	uint32_t SubPriorityBits;
gmatarrubia	0:820a69dfd200	1452
gmatarrubia	0:820a69dfd200	1453	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
gmatarrubia	0:820a69dfd200	1454	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
gmatarrubia	0:820a69dfd200	1455
gmatarrubia	0:820a69dfd200	1456	return (
gmatarrubia	0:820a69dfd200	1457	((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) \|
gmatarrubia	0:820a69dfd200	1458	((SubPriority & ((1 << (SubPriorityBits )) - 1)))
gmatarrubia	0:820a69dfd200	1459	);
gmatarrubia	0:820a69dfd200	1460	}
gmatarrubia	0:820a69dfd200	1461
gmatarrubia	0:820a69dfd200	1462
gmatarrubia	0:820a69dfd200	1463	/** \brief Decode Priority
gmatarrubia	0:820a69dfd200	1464
gmatarrubia	0:820a69dfd200	1465	The function decodes an interrupt priority value with a given priority group to
gmatarrubia	0:820a69dfd200	1466	preemptive priority value and subpriority value.
gmatarrubia	0:820a69dfd200	1467	In case of a conflict between priority grouping and available
gmatarrubia	0:820a69dfd200	1468	priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
gmatarrubia	0:820a69dfd200	1469
gmatarrubia	0:820a69dfd200	1470	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
gmatarrubia	0:820a69dfd200	1471	\param [in] PriorityGroup Used priority group.
gmatarrubia	0:820a69dfd200	1472	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
gmatarrubia	0:820a69dfd200	1473	\param [out] pSubPriority Subpriority value (starting from 0).
gmatarrubia	0:820a69dfd200	1474	*/
gmatarrubia	0:820a69dfd200	1475	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
gmatarrubia	0:820a69dfd200	1476	{
gmatarrubia	0:820a69dfd200	1477	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
gmatarrubia	0:820a69dfd200	1478	uint32_t PreemptPriorityBits;
gmatarrubia	0:820a69dfd200	1479	uint32_t SubPriorityBits;
gmatarrubia	0:820a69dfd200	1480
gmatarrubia	0:820a69dfd200	1481	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
gmatarrubia	0:820a69dfd200	1482	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
gmatarrubia	0:820a69dfd200	1483
gmatarrubia	0:820a69dfd200	1484	*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
gmatarrubia	0:820a69dfd200	1485	*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
gmatarrubia	0:820a69dfd200	1486	}
gmatarrubia	0:820a69dfd200	1487
gmatarrubia	0:820a69dfd200	1488
gmatarrubia	0:820a69dfd200	1489	/** \brief System Reset
gmatarrubia	0:820a69dfd200	1490
gmatarrubia	0:820a69dfd200	1491	The function initiates a system reset request to reset the MCU.
gmatarrubia	0:820a69dfd200	1492	*/
gmatarrubia	0:820a69dfd200	1493	__STATIC_INLINE void NVIC_SystemReset(void)
gmatarrubia	0:820a69dfd200	1494	{
gmatarrubia	0:820a69dfd200	1495	__DSB(); /* Ensure all outstanding memory accesses included
gmatarrubia	0:820a69dfd200	1496	buffered write are completed before reset */
gmatarrubia	0:820a69dfd200	1497	SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
gmatarrubia	0:820a69dfd200	1498	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
gmatarrubia	0:820a69dfd200	1499	SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
gmatarrubia	0:820a69dfd200	1500	__DSB(); /* Ensure completion of memory access */
gmatarrubia	0:820a69dfd200	1501	while(1); /* wait until reset */
gmatarrubia	0:820a69dfd200	1502	}
gmatarrubia	0:820a69dfd200	1503
gmatarrubia	0:820a69dfd200	1504	/@} end of CMSIS_Core_NVICFunctions /
gmatarrubia	0:820a69dfd200	1505
gmatarrubia	0:820a69dfd200	1506
gmatarrubia	0:820a69dfd200	1507
gmatarrubia	0:820a69dfd200	1508	/* ################################## SysTick function ############################################ */
gmatarrubia	0:820a69dfd200	1509	/** \ingroup CMSIS_Core_FunctionInterface
gmatarrubia	0:820a69dfd200	1510	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
gmatarrubia	0:820a69dfd200	1511	\brief Functions that configure the System.
gmatarrubia	0:820a69dfd200	1512	@{
gmatarrubia	0:820a69dfd200	1513	*/
gmatarrubia	0:820a69dfd200	1514
gmatarrubia	0:820a69dfd200	1515	#if (__Vendor_SysTickConfig == 0)
gmatarrubia	0:820a69dfd200	1516
gmatarrubia	0:820a69dfd200	1517	/** \brief System Tick Configuration
gmatarrubia	0:820a69dfd200	1518
gmatarrubia	0:820a69dfd200	1519	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
gmatarrubia	0:820a69dfd200	1520	Counter is in free running mode to generate periodic interrupts.
gmatarrubia	0:820a69dfd200	1521
gmatarrubia	0:820a69dfd200	1522	\param [in] ticks Number of ticks between two interrupts.
gmatarrubia	0:820a69dfd200	1523
gmatarrubia	0:820a69dfd200	1524	\return 0 Function succeeded.
gmatarrubia	0:820a69dfd200	1525	\return 1 Function failed.
gmatarrubia	0:820a69dfd200	1526
gmatarrubia	0:820a69dfd200	1527	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
gmatarrubia	0:820a69dfd200	1528	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
gmatarrubia	0:820a69dfd200	1529	must contain a vendor-specific implementation of this function.
gmatarrubia	0:820a69dfd200	1530
gmatarrubia	0:820a69dfd200	1531	*/
gmatarrubia	0:820a69dfd200	1532	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
gmatarrubia	0:820a69dfd200	1533	{
gmatarrubia	0:820a69dfd200	1534	if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
gmatarrubia	0:820a69dfd200	1535
gmatarrubia	0:820a69dfd200	1536	SysTick->LOAD = ticks - 1; /* set reload register */
gmatarrubia	0:820a69dfd200	1537	NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
gmatarrubia	0:820a69dfd200	1538	SysTick->VAL = 0; /* Load the SysTick Counter Value */
gmatarrubia	0:820a69dfd200	1539	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
gmatarrubia	0:820a69dfd200	1540	SysTick_CTRL_TICKINT_Msk \|
gmatarrubia	0:820a69dfd200	1541	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
gmatarrubia	0:820a69dfd200	1542	return (0); /* Function successful */
gmatarrubia	0:820a69dfd200	1543	}
gmatarrubia	0:820a69dfd200	1544
gmatarrubia	0:820a69dfd200	1545	#endif
gmatarrubia	0:820a69dfd200	1546
gmatarrubia	0:820a69dfd200	1547	/@} end of CMSIS_Core_SysTickFunctions /
gmatarrubia	0:820a69dfd200	1548
gmatarrubia	0:820a69dfd200	1549
gmatarrubia	0:820a69dfd200	1550
gmatarrubia	0:820a69dfd200	1551	/* ##################################### Debug In/Output function ########################################### */
gmatarrubia	0:820a69dfd200	1552	/** \ingroup CMSIS_Core_FunctionInterface
gmatarrubia	0:820a69dfd200	1553	\defgroup CMSIS_core_DebugFunctions ITM Functions
gmatarrubia	0:820a69dfd200	1554	\brief Functions that access the ITM debug interface.
gmatarrubia	0:820a69dfd200	1555	@{
gmatarrubia	0:820a69dfd200	1556	*/
gmatarrubia	0:820a69dfd200	1557
gmatarrubia	0:820a69dfd200	1558	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
gmatarrubia	0:820a69dfd200	1559	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
gmatarrubia	0:820a69dfd200	1560
gmatarrubia	0:820a69dfd200	1561
gmatarrubia	0:820a69dfd200	1562	/** \brief ITM Send Character
gmatarrubia	0:820a69dfd200	1563
gmatarrubia	0:820a69dfd200	1564	The function transmits a character via the ITM channel 0, and
gmatarrubia	0:820a69dfd200	1565	\li Just returns when no debugger is connected that has booked the output.
gmatarrubia	0:820a69dfd200	1566	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
gmatarrubia	0:820a69dfd200	1567
gmatarrubia	0:820a69dfd200	1568	\param [in] ch Character to transmit.
gmatarrubia	0:820a69dfd200	1569
gmatarrubia	0:820a69dfd200	1570	\returns Character to transmit.
gmatarrubia	0:820a69dfd200	1571	*/
gmatarrubia	0:820a69dfd200	1572	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
gmatarrubia	0:820a69dfd200	1573	{
gmatarrubia	0:820a69dfd200	1574	if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
gmatarrubia	0:820a69dfd200	1575	(ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
gmatarrubia	0:820a69dfd200	1576	{
gmatarrubia	0:820a69dfd200	1577	while (ITM->PORT[0].u32 == 0);
gmatarrubia	0:820a69dfd200	1578	ITM->PORT[0].u8 = (uint8_t) ch;
gmatarrubia	0:820a69dfd200	1579	}
gmatarrubia	0:820a69dfd200	1580	return (ch);
gmatarrubia	0:820a69dfd200	1581	}
gmatarrubia	0:820a69dfd200	1582
gmatarrubia	0:820a69dfd200	1583
gmatarrubia	0:820a69dfd200	1584	/** \brief ITM Receive Character
gmatarrubia	0:820a69dfd200	1585
gmatarrubia	0:820a69dfd200	1586	The function inputs a character via the external variable \ref ITM_RxBuffer.
gmatarrubia	0:820a69dfd200	1587
gmatarrubia	0:820a69dfd200	1588	\return Received character.
gmatarrubia	0:820a69dfd200	1589	\return -1 No character pending.
gmatarrubia	0:820a69dfd200	1590	*/
gmatarrubia	0:820a69dfd200	1591	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
gmatarrubia	0:820a69dfd200	1592	int32_t ch = -1; /* no character available */
gmatarrubia	0:820a69dfd200	1593
gmatarrubia	0:820a69dfd200	1594	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
gmatarrubia	0:820a69dfd200	1595	ch = ITM_RxBuffer;
gmatarrubia	0:820a69dfd200	1596	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
gmatarrubia	0:820a69dfd200	1597	}
gmatarrubia	0:820a69dfd200	1598
gmatarrubia	0:820a69dfd200	1599	return (ch);
gmatarrubia	0:820a69dfd200	1600	}
gmatarrubia	0:820a69dfd200	1601
gmatarrubia	0:820a69dfd200	1602
gmatarrubia	0:820a69dfd200	1603	/** \brief ITM Check Character
gmatarrubia	0:820a69dfd200	1604
gmatarrubia	0:820a69dfd200	1605	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
gmatarrubia	0:820a69dfd200	1606
gmatarrubia	0:820a69dfd200	1607	\return 0 No character available.
gmatarrubia	0:820a69dfd200	1608	\return 1 Character available.
gmatarrubia	0:820a69dfd200	1609	*/
gmatarrubia	0:820a69dfd200	1610	__STATIC_INLINE int32_t ITM_CheckChar (void) {
gmatarrubia	0:820a69dfd200	1611
gmatarrubia	0:820a69dfd200	1612	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
gmatarrubia	0:820a69dfd200	1613	return (0); /* no character available */
gmatarrubia	0:820a69dfd200	1614	} else {
gmatarrubia	0:820a69dfd200	1615	return (1); /* character available */
gmatarrubia	0:820a69dfd200	1616	}
gmatarrubia	0:820a69dfd200	1617	}
gmatarrubia	0:820a69dfd200	1618
gmatarrubia	0:820a69dfd200	1619	/@} end of CMSIS_core_DebugFunctions /
gmatarrubia	0:820a69dfd200	1620
gmatarrubia	0:820a69dfd200	1621	#endif /* __CORE_CM3_H_DEPENDANT */
gmatarrubia	0:820a69dfd200	1622
gmatarrubia	0:820a69dfd200	1623	#endif /* __CMSIS_GENERIC */
gmatarrubia	0:820a69dfd200	1624
gmatarrubia	0:820a69dfd200	1625	#ifdef __cplusplus
gmatarrubia	0:820a69dfd200	1626	}
gmatarrubia	0:820a69dfd200	1627	#endif

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Type:	Library
Created:	14 Apr 2015
Imports:	10
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	0
Followers:	2

mbed/TARGET_LPC1549/core_cm3.h@0:820a69dfd200, 2015-04-14 (annotated)

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