Gonzalo Matarrubia / Mbed LPC1549 mod

This repo contains the libraries of Mbed for LPC1549 with following changes: - IAP commands. - EEPROM write and read. - UART write and read (public) - CAN can_s -> LPC_C_CAN0_Type *can

mbed/TARGET_LPC1549/core_cm0.h@0:820a69dfd200, 2015-04-14 (annotated)

Committer:
gmatarrubia
Date:
Tue Apr 14 15:00:13 2015 +0200
Revision:
0:820a69dfd200
Initial repo. IAP commands, EEPROM write/read, UART write/read, CAN

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gmatarrubia 0:820a69dfd200 1 /**************************************************************************//**
gmatarrubia 0:820a69dfd200 2 * @file core_cm0.h
gmatarrubia 0:820a69dfd200 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
gmatarrubia 0:820a69dfd200 4 * @version V3.20
gmatarrubia 0:820a69dfd200 5 * @date 25. February 2013
gmatarrubia 0:820a69dfd200 6 *
gmatarrubia 0:820a69dfd200 7 * @note
gmatarrubia 0:820a69dfd200 8 *
gmatarrubia 0:820a69dfd200 9 ******************************************************************************/
gmatarrubia 0:820a69dfd200 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
gmatarrubia 0:820a69dfd200 11
gmatarrubia 0:820a69dfd200 12 All rights reserved.
gmatarrubia 0:820a69dfd200 13 Redistribution and use in source and binary forms, with or without
gmatarrubia 0:820a69dfd200 14 modification, are permitted provided that the following conditions are met:
gmatarrubia 0:820a69dfd200 15 - Redistributions of source code must retain the above copyright
gmatarrubia 0:820a69dfd200 16 notice, this list of conditions and the following disclaimer.
gmatarrubia 0:820a69dfd200 17 - Redistributions in binary form must reproduce the above copyright
gmatarrubia 0:820a69dfd200 18 notice, this list of conditions and the following disclaimer in the
gmatarrubia 0:820a69dfd200 19 documentation and/or other materials provided with the distribution.
gmatarrubia 0:820a69dfd200 20 - Neither the name of ARM nor the names of its contributors may be used
gmatarrubia 0:820a69dfd200 21 to endorse or promote products derived from this software without
gmatarrubia 0:820a69dfd200 22 specific prior written permission.
gmatarrubia 0:820a69dfd200 23 *
gmatarrubia 0:820a69dfd200 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
gmatarrubia 0:820a69dfd200 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
gmatarrubia 0:820a69dfd200 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
gmatarrubia 0:820a69dfd200 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
gmatarrubia 0:820a69dfd200 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
gmatarrubia 0:820a69dfd200 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
gmatarrubia 0:820a69dfd200 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
gmatarrubia 0:820a69dfd200 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
gmatarrubia 0:820a69dfd200 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
gmatarrubia 0:820a69dfd200 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
gmatarrubia 0:820a69dfd200 34 POSSIBILITY OF SUCH DAMAGE.
gmatarrubia 0:820a69dfd200 35 ---------------------------------------------------------------------------*/
gmatarrubia 0:820a69dfd200 36
gmatarrubia 0:820a69dfd200 37
gmatarrubia 0:820a69dfd200 38 #if defined ( __ICCARM__ )
gmatarrubia 0:820a69dfd200 39 #pragma system_include /* treat file as system include file for MISRA check */
gmatarrubia 0:820a69dfd200 40 #endif
gmatarrubia 0:820a69dfd200 41
gmatarrubia 0:820a69dfd200 42 #ifdef __cplusplus
gmatarrubia 0:820a69dfd200 43 extern "C" {
gmatarrubia 0:820a69dfd200 44 #endif
gmatarrubia 0:820a69dfd200 45
gmatarrubia 0:820a69dfd200 46 #ifndef __CORE_CM0_H_GENERIC
gmatarrubia 0:820a69dfd200 47 #define __CORE_CM0_H_GENERIC
gmatarrubia 0:820a69dfd200 48
gmatarrubia 0:820a69dfd200 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
gmatarrubia 0:820a69dfd200 50 CMSIS violates the following MISRA-C:2004 rules:
gmatarrubia 0:820a69dfd200 51
gmatarrubia 0:820a69dfd200 52 \li Required Rule 8.5, object/function definition in header file.<br>
gmatarrubia 0:820a69dfd200 53 Function definitions in header files are used to allow 'inlining'.
gmatarrubia 0:820a69dfd200 54
gmatarrubia 0:820a69dfd200 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
gmatarrubia 0:820a69dfd200 56 Unions are used for effective representation of core registers.
gmatarrubia 0:820a69dfd200 57
gmatarrubia 0:820a69dfd200 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
gmatarrubia 0:820a69dfd200 59 Function-like macros are used to allow more efficient code.
gmatarrubia 0:820a69dfd200 60 */
gmatarrubia 0:820a69dfd200 61
gmatarrubia 0:820a69dfd200 62
gmatarrubia 0:820a69dfd200 63 /*******************************************************************************
gmatarrubia 0:820a69dfd200 64 * CMSIS definitions
gmatarrubia 0:820a69dfd200 65 ******************************************************************************/
gmatarrubia 0:820a69dfd200 66 /** \ingroup Cortex_M0
gmatarrubia 0:820a69dfd200 67 @{
gmatarrubia 0:820a69dfd200 68 */
gmatarrubia 0:820a69dfd200 69
gmatarrubia 0:820a69dfd200 70 /* CMSIS CM0 definitions */
gmatarrubia 0:820a69dfd200 71 #define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
gmatarrubia 0:820a69dfd200 72 #define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
gmatarrubia 0:820a69dfd200 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
gmatarrubia 0:820a69dfd200 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
gmatarrubia 0:820a69dfd200 75
gmatarrubia 0:820a69dfd200 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
gmatarrubia 0:820a69dfd200 77
gmatarrubia 0:820a69dfd200 78
gmatarrubia 0:820a69dfd200 79 #if defined ( __CC_ARM )
gmatarrubia 0:820a69dfd200 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
gmatarrubia 0:820a69dfd200 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
gmatarrubia 0:820a69dfd200 82 #define __STATIC_INLINE static __inline
gmatarrubia 0:820a69dfd200 83
gmatarrubia 0:820a69dfd200 84 #elif defined ( __ICCARM__ )
gmatarrubia 0:820a69dfd200 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
gmatarrubia 0:820a69dfd200 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
gmatarrubia 0:820a69dfd200 87 #define __STATIC_INLINE static inline
gmatarrubia 0:820a69dfd200 88
gmatarrubia 0:820a69dfd200 89 #elif defined ( __GNUC__ )
gmatarrubia 0:820a69dfd200 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
gmatarrubia 0:820a69dfd200 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
gmatarrubia 0:820a69dfd200 92 #define __STATIC_INLINE static inline
gmatarrubia 0:820a69dfd200 93
gmatarrubia 0:820a69dfd200 94 #elif defined ( __TASKING__ )
gmatarrubia 0:820a69dfd200 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
gmatarrubia 0:820a69dfd200 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
gmatarrubia 0:820a69dfd200 97 #define __STATIC_INLINE static inline
gmatarrubia 0:820a69dfd200 98
gmatarrubia 0:820a69dfd200 99 #endif
gmatarrubia 0:820a69dfd200 100
gmatarrubia 0:820a69dfd200 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
gmatarrubia 0:820a69dfd200 102 */
gmatarrubia 0:820a69dfd200 103 #define __FPU_USED 0
gmatarrubia 0:820a69dfd200 104
gmatarrubia 0:820a69dfd200 105 #if defined ( __CC_ARM )
gmatarrubia 0:820a69dfd200 106 #if defined __TARGET_FPU_VFP
gmatarrubia 0:820a69dfd200 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
gmatarrubia 0:820a69dfd200 108 #endif
gmatarrubia 0:820a69dfd200 109
gmatarrubia 0:820a69dfd200 110 #elif defined ( __ICCARM__ )
gmatarrubia 0:820a69dfd200 111 #if defined __ARMVFP__
gmatarrubia 0:820a69dfd200 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
gmatarrubia 0:820a69dfd200 113 #endif
gmatarrubia 0:820a69dfd200 114
gmatarrubia 0:820a69dfd200 115 #elif defined ( __GNUC__ )
gmatarrubia 0:820a69dfd200 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
gmatarrubia 0:820a69dfd200 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
gmatarrubia 0:820a69dfd200 118 #endif
gmatarrubia 0:820a69dfd200 119
gmatarrubia 0:820a69dfd200 120 #elif defined ( __TASKING__ )
gmatarrubia 0:820a69dfd200 121 #if defined __FPU_VFP__
gmatarrubia 0:820a69dfd200 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
gmatarrubia 0:820a69dfd200 123 #endif
gmatarrubia 0:820a69dfd200 124 #endif
gmatarrubia 0:820a69dfd200 125
gmatarrubia 0:820a69dfd200 126 #include <stdint.h> /* standard types definitions */
gmatarrubia 0:820a69dfd200 127 #include <core_cmInstr.h> /* Core Instruction Access */
gmatarrubia 0:820a69dfd200 128 #include <core_cmFunc.h> /* Core Function Access */
gmatarrubia 0:820a69dfd200 129
gmatarrubia 0:820a69dfd200 130 #endif /* __CORE_CM0_H_GENERIC */
gmatarrubia 0:820a69dfd200 131
gmatarrubia 0:820a69dfd200 132 #ifndef __CMSIS_GENERIC
gmatarrubia 0:820a69dfd200 133
gmatarrubia 0:820a69dfd200 134 #ifndef __CORE_CM0_H_DEPENDANT
gmatarrubia 0:820a69dfd200 135 #define __CORE_CM0_H_DEPENDANT
gmatarrubia 0:820a69dfd200 136
gmatarrubia 0:820a69dfd200 137 /* check device defines and use defaults */
gmatarrubia 0:820a69dfd200 138 #if defined __CHECK_DEVICE_DEFINES
gmatarrubia 0:820a69dfd200 139 #ifndef __CM0_REV
gmatarrubia 0:820a69dfd200 140 #define __CM0_REV 0x0000
gmatarrubia 0:820a69dfd200 141 #warning "__CM0_REV not defined in device header file; using default!"
gmatarrubia 0:820a69dfd200 142 #endif
gmatarrubia 0:820a69dfd200 143
gmatarrubia 0:820a69dfd200 144 #ifndef __NVIC_PRIO_BITS
gmatarrubia 0:820a69dfd200 145 #define __NVIC_PRIO_BITS 2
gmatarrubia 0:820a69dfd200 146 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
gmatarrubia 0:820a69dfd200 147 #endif
gmatarrubia 0:820a69dfd200 148
gmatarrubia 0:820a69dfd200 149 #ifndef __Vendor_SysTickConfig
gmatarrubia 0:820a69dfd200 150 #define __Vendor_SysTickConfig 0
gmatarrubia 0:820a69dfd200 151 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
gmatarrubia 0:820a69dfd200 152 #endif
gmatarrubia 0:820a69dfd200 153 #endif
gmatarrubia 0:820a69dfd200 154
gmatarrubia 0:820a69dfd200 155 /* IO definitions (access restrictions to peripheral registers) */
gmatarrubia 0:820a69dfd200 156 /**
gmatarrubia 0:820a69dfd200 157 \defgroup CMSIS_glob_defs CMSIS Global Defines
gmatarrubia 0:820a69dfd200 158
gmatarrubia 0:820a69dfd200 159 <strong>IO Type Qualifiers</strong> are used
gmatarrubia 0:820a69dfd200 160 \li to specify the access to peripheral variables.
gmatarrubia 0:820a69dfd200 161 \li for automatic generation of peripheral register debug information.
gmatarrubia 0:820a69dfd200 162 */
gmatarrubia 0:820a69dfd200 163 #ifdef __cplusplus
gmatarrubia 0:820a69dfd200 164 #define __I volatile /*!< Defines 'read only' permissions */
gmatarrubia 0:820a69dfd200 165 #else
gmatarrubia 0:820a69dfd200 166 #define __I volatile const /*!< Defines 'read only' permissions */
gmatarrubia 0:820a69dfd200 167 #endif
gmatarrubia 0:820a69dfd200 168 #define __O volatile /*!< Defines 'write only' permissions */
gmatarrubia 0:820a69dfd200 169 #define __IO volatile /*!< Defines 'read / write' permissions */
gmatarrubia 0:820a69dfd200 170
gmatarrubia 0:820a69dfd200 171 /*@} end of group Cortex_M0 */
gmatarrubia 0:820a69dfd200 172
gmatarrubia 0:820a69dfd200 173
gmatarrubia 0:820a69dfd200 174
gmatarrubia 0:820a69dfd200 175 /*******************************************************************************
gmatarrubia 0:820a69dfd200 176 * Register Abstraction
gmatarrubia 0:820a69dfd200 177 Core Register contain:
gmatarrubia 0:820a69dfd200 178 - Core Register
gmatarrubia 0:820a69dfd200 179 - Core NVIC Register
gmatarrubia 0:820a69dfd200 180 - Core SCB Register
gmatarrubia 0:820a69dfd200 181 - Core SysTick Register
gmatarrubia 0:820a69dfd200 182 ******************************************************************************/
gmatarrubia 0:820a69dfd200 183 /** \defgroup CMSIS_core_register Defines and Type Definitions
gmatarrubia 0:820a69dfd200 184 \brief Type definitions and defines for Cortex-M processor based devices.
gmatarrubia 0:820a69dfd200 185 */
gmatarrubia 0:820a69dfd200 186
gmatarrubia 0:820a69dfd200 187 /** \ingroup CMSIS_core_register
gmatarrubia 0:820a69dfd200 188 \defgroup CMSIS_CORE Status and Control Registers
gmatarrubia 0:820a69dfd200 189 \brief Core Register type definitions.
gmatarrubia 0:820a69dfd200 190 @{
gmatarrubia 0:820a69dfd200 191 */
gmatarrubia 0:820a69dfd200 192
gmatarrubia 0:820a69dfd200 193 /** \brief Union type to access the Application Program Status Register (APSR).
gmatarrubia 0:820a69dfd200 194 */
gmatarrubia 0:820a69dfd200 195 typedef union
gmatarrubia 0:820a69dfd200 196 {
gmatarrubia 0:820a69dfd200 197 struct
gmatarrubia 0:820a69dfd200 198 {
gmatarrubia 0:820a69dfd200 199 #if (__CORTEX_M != 0x04)
gmatarrubia 0:820a69dfd200 200 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
gmatarrubia 0:820a69dfd200 201 #else
gmatarrubia 0:820a69dfd200 202 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
gmatarrubia 0:820a69dfd200 203 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
gmatarrubia 0:820a69dfd200 204 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
gmatarrubia 0:820a69dfd200 205 #endif
gmatarrubia 0:820a69dfd200 206 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
gmatarrubia 0:820a69dfd200 207 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
gmatarrubia 0:820a69dfd200 208 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
gmatarrubia 0:820a69dfd200 209 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
gmatarrubia 0:820a69dfd200 210 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
gmatarrubia 0:820a69dfd200 211 } b; /*!< Structure used for bit access */
gmatarrubia 0:820a69dfd200 212 uint32_t w; /*!< Type used for word access */
gmatarrubia 0:820a69dfd200 213 } APSR_Type;
gmatarrubia 0:820a69dfd200 214
gmatarrubia 0:820a69dfd200 215
gmatarrubia 0:820a69dfd200 216 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
gmatarrubia 0:820a69dfd200 217 */
gmatarrubia 0:820a69dfd200 218 typedef union
gmatarrubia 0:820a69dfd200 219 {
gmatarrubia 0:820a69dfd200 220 struct
gmatarrubia 0:820a69dfd200 221 {
gmatarrubia 0:820a69dfd200 222 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
gmatarrubia 0:820a69dfd200 223 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
gmatarrubia 0:820a69dfd200 224 } b; /*!< Structure used for bit access */
gmatarrubia 0:820a69dfd200 225 uint32_t w; /*!< Type used for word access */
gmatarrubia 0:820a69dfd200 226 } IPSR_Type;
gmatarrubia 0:820a69dfd200 227
gmatarrubia 0:820a69dfd200 228
gmatarrubia 0:820a69dfd200 229 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
gmatarrubia 0:820a69dfd200 230 */
gmatarrubia 0:820a69dfd200 231 typedef union
gmatarrubia 0:820a69dfd200 232 {
gmatarrubia 0:820a69dfd200 233 struct
gmatarrubia 0:820a69dfd200 234 {
gmatarrubia 0:820a69dfd200 235 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
gmatarrubia 0:820a69dfd200 236 #if (__CORTEX_M != 0x04)
gmatarrubia 0:820a69dfd200 237 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
gmatarrubia 0:820a69dfd200 238 #else
gmatarrubia 0:820a69dfd200 239 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
gmatarrubia 0:820a69dfd200 240 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
gmatarrubia 0:820a69dfd200 241 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
gmatarrubia 0:820a69dfd200 242 #endif
gmatarrubia 0:820a69dfd200 243 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
gmatarrubia 0:820a69dfd200 244 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
gmatarrubia 0:820a69dfd200 245 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
gmatarrubia 0:820a69dfd200 246 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
gmatarrubia 0:820a69dfd200 247 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
gmatarrubia 0:820a69dfd200 248 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
gmatarrubia 0:820a69dfd200 249 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
gmatarrubia 0:820a69dfd200 250 } b; /*!< Structure used for bit access */
gmatarrubia 0:820a69dfd200 251 uint32_t w; /*!< Type used for word access */
gmatarrubia 0:820a69dfd200 252 } xPSR_Type;
gmatarrubia 0:820a69dfd200 253
gmatarrubia 0:820a69dfd200 254
gmatarrubia 0:820a69dfd200 255 /** \brief Union type to access the Control Registers (CONTROL).
gmatarrubia 0:820a69dfd200 256 */
gmatarrubia 0:820a69dfd200 257 typedef union
gmatarrubia 0:820a69dfd200 258 {
gmatarrubia 0:820a69dfd200 259 struct
gmatarrubia 0:820a69dfd200 260 {
gmatarrubia 0:820a69dfd200 261 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
gmatarrubia 0:820a69dfd200 262 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
gmatarrubia 0:820a69dfd200 263 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
gmatarrubia 0:820a69dfd200 264 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
gmatarrubia 0:820a69dfd200 265 } b; /*!< Structure used for bit access */
gmatarrubia 0:820a69dfd200 266 uint32_t w; /*!< Type used for word access */
gmatarrubia 0:820a69dfd200 267 } CONTROL_Type;
gmatarrubia 0:820a69dfd200 268
gmatarrubia 0:820a69dfd200 269 /*@} end of group CMSIS_CORE */
gmatarrubia 0:820a69dfd200 270
gmatarrubia 0:820a69dfd200 271
gmatarrubia 0:820a69dfd200 272 /** \ingroup CMSIS_core_register
gmatarrubia 0:820a69dfd200 273 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
gmatarrubia 0:820a69dfd200 274 \brief Type definitions for the NVIC Registers
gmatarrubia 0:820a69dfd200 275 @{
gmatarrubia 0:820a69dfd200 276 */
gmatarrubia 0:820a69dfd200 277
gmatarrubia 0:820a69dfd200 278 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
gmatarrubia 0:820a69dfd200 279 */
gmatarrubia 0:820a69dfd200 280 typedef struct
gmatarrubia 0:820a69dfd200 281 {
gmatarrubia 0:820a69dfd200 282 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
gmatarrubia 0:820a69dfd200 283 uint32_t RESERVED0[31];
gmatarrubia 0:820a69dfd200 284 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
gmatarrubia 0:820a69dfd200 285 uint32_t RSERVED1[31];
gmatarrubia 0:820a69dfd200 286 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
gmatarrubia 0:820a69dfd200 287 uint32_t RESERVED2[31];
gmatarrubia 0:820a69dfd200 288 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
gmatarrubia 0:820a69dfd200 289 uint32_t RESERVED3[31];
gmatarrubia 0:820a69dfd200 290 uint32_t RESERVED4[64];
gmatarrubia 0:820a69dfd200 291 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
gmatarrubia 0:820a69dfd200 292 } NVIC_Type;
gmatarrubia 0:820a69dfd200 293
gmatarrubia 0:820a69dfd200 294 /*@} end of group CMSIS_NVIC */
gmatarrubia 0:820a69dfd200 295
gmatarrubia 0:820a69dfd200 296
gmatarrubia 0:820a69dfd200 297 /** \ingroup CMSIS_core_register
gmatarrubia 0:820a69dfd200 298 \defgroup CMSIS_SCB System Control Block (SCB)
gmatarrubia 0:820a69dfd200 299 \brief Type definitions for the System Control Block Registers
gmatarrubia 0:820a69dfd200 300 @{
gmatarrubia 0:820a69dfd200 301 */
gmatarrubia 0:820a69dfd200 302
gmatarrubia 0:820a69dfd200 303 /** \brief Structure type to access the System Control Block (SCB).
gmatarrubia 0:820a69dfd200 304 */
gmatarrubia 0:820a69dfd200 305 typedef struct
gmatarrubia 0:820a69dfd200 306 {
gmatarrubia 0:820a69dfd200 307 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
gmatarrubia 0:820a69dfd200 308 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
gmatarrubia 0:820a69dfd200 309 uint32_t RESERVED0;
gmatarrubia 0:820a69dfd200 310 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
gmatarrubia 0:820a69dfd200 311 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
gmatarrubia 0:820a69dfd200 312 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
gmatarrubia 0:820a69dfd200 313 uint32_t RESERVED1;
gmatarrubia 0:820a69dfd200 314 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
gmatarrubia 0:820a69dfd200 315 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
gmatarrubia 0:820a69dfd200 316 } SCB_Type;
gmatarrubia 0:820a69dfd200 317
gmatarrubia 0:820a69dfd200 318 /* SCB CPUID Register Definitions */
gmatarrubia 0:820a69dfd200 319 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
gmatarrubia 0:820a69dfd200 320 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
gmatarrubia 0:820a69dfd200 321
gmatarrubia 0:820a69dfd200 322 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
gmatarrubia 0:820a69dfd200 323 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
gmatarrubia 0:820a69dfd200 324
gmatarrubia 0:820a69dfd200 325 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
gmatarrubia 0:820a69dfd200 326 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
gmatarrubia 0:820a69dfd200 327
gmatarrubia 0:820a69dfd200 328 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
gmatarrubia 0:820a69dfd200 329 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
gmatarrubia 0:820a69dfd200 330
gmatarrubia 0:820a69dfd200 331 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
gmatarrubia 0:820a69dfd200 332 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
gmatarrubia 0:820a69dfd200 333
gmatarrubia 0:820a69dfd200 334 /* SCB Interrupt Control State Register Definitions */
gmatarrubia 0:820a69dfd200 335 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
gmatarrubia 0:820a69dfd200 336 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
gmatarrubia 0:820a69dfd200 337
gmatarrubia 0:820a69dfd200 338 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
gmatarrubia 0:820a69dfd200 339 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
gmatarrubia 0:820a69dfd200 340
gmatarrubia 0:820a69dfd200 341 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
gmatarrubia 0:820a69dfd200 342 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
gmatarrubia 0:820a69dfd200 343
gmatarrubia 0:820a69dfd200 344 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
gmatarrubia 0:820a69dfd200 345 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
gmatarrubia 0:820a69dfd200 346
gmatarrubia 0:820a69dfd200 347 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
gmatarrubia 0:820a69dfd200 348 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
gmatarrubia 0:820a69dfd200 349
gmatarrubia 0:820a69dfd200 350 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
gmatarrubia 0:820a69dfd200 351 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
gmatarrubia 0:820a69dfd200 352
gmatarrubia 0:820a69dfd200 353 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
gmatarrubia 0:820a69dfd200 354 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
gmatarrubia 0:820a69dfd200 355
gmatarrubia 0:820a69dfd200 356 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
gmatarrubia 0:820a69dfd200 357 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
gmatarrubia 0:820a69dfd200 358
gmatarrubia 0:820a69dfd200 359 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
gmatarrubia 0:820a69dfd200 360 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
gmatarrubia 0:820a69dfd200 361
gmatarrubia 0:820a69dfd200 362 /* SCB Application Interrupt and Reset Control Register Definitions */
gmatarrubia 0:820a69dfd200 363 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
gmatarrubia 0:820a69dfd200 364 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
gmatarrubia 0:820a69dfd200 365
gmatarrubia 0:820a69dfd200 366 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
gmatarrubia 0:820a69dfd200 367 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
gmatarrubia 0:820a69dfd200 368
gmatarrubia 0:820a69dfd200 369 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
gmatarrubia 0:820a69dfd200 370 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
gmatarrubia 0:820a69dfd200 371
gmatarrubia 0:820a69dfd200 372 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
gmatarrubia 0:820a69dfd200 373 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
gmatarrubia 0:820a69dfd200 374
gmatarrubia 0:820a69dfd200 375 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
gmatarrubia 0:820a69dfd200 376 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
gmatarrubia 0:820a69dfd200 377
gmatarrubia 0:820a69dfd200 378 /* SCB System Control Register Definitions */
gmatarrubia 0:820a69dfd200 379 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
gmatarrubia 0:820a69dfd200 380 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
gmatarrubia 0:820a69dfd200 381
gmatarrubia 0:820a69dfd200 382 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
gmatarrubia 0:820a69dfd200 383 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
gmatarrubia 0:820a69dfd200 384
gmatarrubia 0:820a69dfd200 385 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
gmatarrubia 0:820a69dfd200 386 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
gmatarrubia 0:820a69dfd200 387
gmatarrubia 0:820a69dfd200 388 /* SCB Configuration Control Register Definitions */
gmatarrubia 0:820a69dfd200 389 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
gmatarrubia 0:820a69dfd200 390 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
gmatarrubia 0:820a69dfd200 391
gmatarrubia 0:820a69dfd200 392 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
gmatarrubia 0:820a69dfd200 393 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
gmatarrubia 0:820a69dfd200 394
gmatarrubia 0:820a69dfd200 395 /* SCB System Handler Control and State Register Definitions */
gmatarrubia 0:820a69dfd200 396 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
gmatarrubia 0:820a69dfd200 397 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
gmatarrubia 0:820a69dfd200 398
gmatarrubia 0:820a69dfd200 399 /*@} end of group CMSIS_SCB */
gmatarrubia 0:820a69dfd200 400
gmatarrubia 0:820a69dfd200 401
gmatarrubia 0:820a69dfd200 402 /** \ingroup CMSIS_core_register
gmatarrubia 0:820a69dfd200 403 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
gmatarrubia 0:820a69dfd200 404 \brief Type definitions for the System Timer Registers.
gmatarrubia 0:820a69dfd200 405 @{
gmatarrubia 0:820a69dfd200 406 */
gmatarrubia 0:820a69dfd200 407
gmatarrubia 0:820a69dfd200 408 /** \brief Structure type to access the System Timer (SysTick).
gmatarrubia 0:820a69dfd200 409 */
gmatarrubia 0:820a69dfd200 410 typedef struct
gmatarrubia 0:820a69dfd200 411 {
gmatarrubia 0:820a69dfd200 412 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
gmatarrubia 0:820a69dfd200 413 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
gmatarrubia 0:820a69dfd200 414 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
gmatarrubia 0:820a69dfd200 415 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
gmatarrubia 0:820a69dfd200 416 } SysTick_Type;
gmatarrubia 0:820a69dfd200 417
gmatarrubia 0:820a69dfd200 418 /* SysTick Control / Status Register Definitions */
gmatarrubia 0:820a69dfd200 419 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
gmatarrubia 0:820a69dfd200 420 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
gmatarrubia 0:820a69dfd200 421
gmatarrubia 0:820a69dfd200 422 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
gmatarrubia 0:820a69dfd200 423 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
gmatarrubia 0:820a69dfd200 424
gmatarrubia 0:820a69dfd200 425 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
gmatarrubia 0:820a69dfd200 426 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
gmatarrubia 0:820a69dfd200 427
gmatarrubia 0:820a69dfd200 428 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
gmatarrubia 0:820a69dfd200 429 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
gmatarrubia 0:820a69dfd200 430
gmatarrubia 0:820a69dfd200 431 /* SysTick Reload Register Definitions */
gmatarrubia 0:820a69dfd200 432 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
gmatarrubia 0:820a69dfd200 433 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
gmatarrubia 0:820a69dfd200 434
gmatarrubia 0:820a69dfd200 435 /* SysTick Current Register Definitions */
gmatarrubia 0:820a69dfd200 436 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
gmatarrubia 0:820a69dfd200 437 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
gmatarrubia 0:820a69dfd200 438
gmatarrubia 0:820a69dfd200 439 /* SysTick Calibration Register Definitions */
gmatarrubia 0:820a69dfd200 440 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
gmatarrubia 0:820a69dfd200 441 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
gmatarrubia 0:820a69dfd200 442
gmatarrubia 0:820a69dfd200 443 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
gmatarrubia 0:820a69dfd200 444 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
gmatarrubia 0:820a69dfd200 445
gmatarrubia 0:820a69dfd200 446 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
gmatarrubia 0:820a69dfd200 447 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
gmatarrubia 0:820a69dfd200 448
gmatarrubia 0:820a69dfd200 449 /*@} end of group CMSIS_SysTick */
gmatarrubia 0:820a69dfd200 450
gmatarrubia 0:820a69dfd200 451
gmatarrubia 0:820a69dfd200 452 /** \ingroup CMSIS_core_register
gmatarrubia 0:820a69dfd200 453 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
gmatarrubia 0:820a69dfd200 454 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
gmatarrubia 0:820a69dfd200 455 are only accessible over DAP and not via processor. Therefore
gmatarrubia 0:820a69dfd200 456 they are not covered by the Cortex-M0 header file.
gmatarrubia 0:820a69dfd200 457 @{
gmatarrubia 0:820a69dfd200 458 */
gmatarrubia 0:820a69dfd200 459 /*@} end of group CMSIS_CoreDebug */
gmatarrubia 0:820a69dfd200 460
gmatarrubia 0:820a69dfd200 461
gmatarrubia 0:820a69dfd200 462 /** \ingroup CMSIS_core_register
gmatarrubia 0:820a69dfd200 463 \defgroup CMSIS_core_base Core Definitions
gmatarrubia 0:820a69dfd200 464 \brief Definitions for base addresses, unions, and structures.
gmatarrubia 0:820a69dfd200 465 @{
gmatarrubia 0:820a69dfd200 466 */
gmatarrubia 0:820a69dfd200 467
gmatarrubia 0:820a69dfd200 468 /* Memory mapping of Cortex-M0 Hardware */
gmatarrubia 0:820a69dfd200 469 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
gmatarrubia 0:820a69dfd200 470 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
gmatarrubia 0:820a69dfd200 471 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
gmatarrubia 0:820a69dfd200 472 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
gmatarrubia 0:820a69dfd200 473
gmatarrubia 0:820a69dfd200 474 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
gmatarrubia 0:820a69dfd200 475 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
gmatarrubia 0:820a69dfd200 476 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
gmatarrubia 0:820a69dfd200 477
gmatarrubia 0:820a69dfd200 478
gmatarrubia 0:820a69dfd200 479 /*@} */
gmatarrubia 0:820a69dfd200 480
gmatarrubia 0:820a69dfd200 481
gmatarrubia 0:820a69dfd200 482
gmatarrubia 0:820a69dfd200 483 /*******************************************************************************
gmatarrubia 0:820a69dfd200 484 * Hardware Abstraction Layer
gmatarrubia 0:820a69dfd200 485 Core Function Interface contains:
gmatarrubia 0:820a69dfd200 486 - Core NVIC Functions
gmatarrubia 0:820a69dfd200 487 - Core SysTick Functions
gmatarrubia 0:820a69dfd200 488 - Core Register Access Functions
gmatarrubia 0:820a69dfd200 489 ******************************************************************************/
gmatarrubia 0:820a69dfd200 490 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
gmatarrubia 0:820a69dfd200 491 */
gmatarrubia 0:820a69dfd200 492
gmatarrubia 0:820a69dfd200 493
gmatarrubia 0:820a69dfd200 494
gmatarrubia 0:820a69dfd200 495 /* ########################## NVIC functions #################################### */
gmatarrubia 0:820a69dfd200 496 /** \ingroup CMSIS_Core_FunctionInterface
gmatarrubia 0:820a69dfd200 497 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
gmatarrubia 0:820a69dfd200 498 \brief Functions that manage interrupts and exceptions via the NVIC.
gmatarrubia 0:820a69dfd200 499 @{
gmatarrubia 0:820a69dfd200 500 */
gmatarrubia 0:820a69dfd200 501
gmatarrubia 0:820a69dfd200 502 /* Interrupt Priorities are WORD accessible only under ARMv6M */
gmatarrubia 0:820a69dfd200 503 /* The following MACROS handle generation of the register offset and byte masks */
gmatarrubia 0:820a69dfd200 504 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
gmatarrubia 0:820a69dfd200 505 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
gmatarrubia 0:820a69dfd200 506 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
gmatarrubia 0:820a69dfd200 507
gmatarrubia 0:820a69dfd200 508
gmatarrubia 0:820a69dfd200 509 /** \brief Enable External Interrupt
gmatarrubia 0:820a69dfd200 510
gmatarrubia 0:820a69dfd200 511 The function enables a device-specific interrupt in the NVIC interrupt controller.
gmatarrubia 0:820a69dfd200 512
gmatarrubia 0:820a69dfd200 513 \param [in] IRQn External interrupt number. Value cannot be negative.
gmatarrubia 0:820a69dfd200 514 */
gmatarrubia 0:820a69dfd200 515 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
gmatarrubia 0:820a69dfd200 516 {
gmatarrubia 0:820a69dfd200 517 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
gmatarrubia 0:820a69dfd200 518 }
gmatarrubia 0:820a69dfd200 519
gmatarrubia 0:820a69dfd200 520
gmatarrubia 0:820a69dfd200 521 /** \brief Disable External Interrupt
gmatarrubia 0:820a69dfd200 522
gmatarrubia 0:820a69dfd200 523 The function disables a device-specific interrupt in the NVIC interrupt controller.
gmatarrubia 0:820a69dfd200 524
gmatarrubia 0:820a69dfd200 525 \param [in] IRQn External interrupt number. Value cannot be negative.
gmatarrubia 0:820a69dfd200 526 */
gmatarrubia 0:820a69dfd200 527 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
gmatarrubia 0:820a69dfd200 528 {
gmatarrubia 0:820a69dfd200 529 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
gmatarrubia 0:820a69dfd200 530 }
gmatarrubia 0:820a69dfd200 531
gmatarrubia 0:820a69dfd200 532
gmatarrubia 0:820a69dfd200 533 /** \brief Get Pending Interrupt
gmatarrubia 0:820a69dfd200 534
gmatarrubia 0:820a69dfd200 535 The function reads the pending register in the NVIC and returns the pending bit
gmatarrubia 0:820a69dfd200 536 for the specified interrupt.
gmatarrubia 0:820a69dfd200 537
gmatarrubia 0:820a69dfd200 538 \param [in] IRQn Interrupt number.
gmatarrubia 0:820a69dfd200 539
gmatarrubia 0:820a69dfd200 540 \return 0 Interrupt status is not pending.
gmatarrubia 0:820a69dfd200 541 \return 1 Interrupt status is pending.
gmatarrubia 0:820a69dfd200 542 */
gmatarrubia 0:820a69dfd200 543 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
gmatarrubia 0:820a69dfd200 544 {
gmatarrubia 0:820a69dfd200 545 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
gmatarrubia 0:820a69dfd200 546 }
gmatarrubia 0:820a69dfd200 547
gmatarrubia 0:820a69dfd200 548
gmatarrubia 0:820a69dfd200 549 /** \brief Set Pending Interrupt
gmatarrubia 0:820a69dfd200 550
gmatarrubia 0:820a69dfd200 551 The function sets the pending bit of an external interrupt.
gmatarrubia 0:820a69dfd200 552
gmatarrubia 0:820a69dfd200 553 \param [in] IRQn Interrupt number. Value cannot be negative.
gmatarrubia 0:820a69dfd200 554 */
gmatarrubia 0:820a69dfd200 555 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
gmatarrubia 0:820a69dfd200 556 {
gmatarrubia 0:820a69dfd200 557 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
gmatarrubia 0:820a69dfd200 558 }
gmatarrubia 0:820a69dfd200 559
gmatarrubia 0:820a69dfd200 560
gmatarrubia 0:820a69dfd200 561 /** \brief Clear Pending Interrupt
gmatarrubia 0:820a69dfd200 562
gmatarrubia 0:820a69dfd200 563 The function clears the pending bit of an external interrupt.
gmatarrubia 0:820a69dfd200 564
gmatarrubia 0:820a69dfd200 565 \param [in] IRQn External interrupt number. Value cannot be negative.
gmatarrubia 0:820a69dfd200 566 */
gmatarrubia 0:820a69dfd200 567 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
gmatarrubia 0:820a69dfd200 568 {
gmatarrubia 0:820a69dfd200 569 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
gmatarrubia 0:820a69dfd200 570 }
gmatarrubia 0:820a69dfd200 571
gmatarrubia 0:820a69dfd200 572
gmatarrubia 0:820a69dfd200 573 /** \brief Set Interrupt Priority
gmatarrubia 0:820a69dfd200 574
gmatarrubia 0:820a69dfd200 575 The function sets the priority of an interrupt.
gmatarrubia 0:820a69dfd200 576
gmatarrubia 0:820a69dfd200 577 \note The priority cannot be set for every core interrupt.
gmatarrubia 0:820a69dfd200 578
gmatarrubia 0:820a69dfd200 579 \param [in] IRQn Interrupt number.
gmatarrubia 0:820a69dfd200 580 \param [in] priority Priority to set.
gmatarrubia 0:820a69dfd200 581 */
gmatarrubia 0:820a69dfd200 582 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
gmatarrubia 0:820a69dfd200 583 {
gmatarrubia 0:820a69dfd200 584 if(IRQn < 0) {
gmatarrubia 0:820a69dfd200 585 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
gmatarrubia 0:820a69dfd200 586 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
gmatarrubia 0:820a69dfd200 587 else {
gmatarrubia 0:820a69dfd200 588 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
gmatarrubia 0:820a69dfd200 589 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
gmatarrubia 0:820a69dfd200 590 }
gmatarrubia 0:820a69dfd200 591
gmatarrubia 0:820a69dfd200 592
gmatarrubia 0:820a69dfd200 593 /** \brief Get Interrupt Priority
gmatarrubia 0:820a69dfd200 594
gmatarrubia 0:820a69dfd200 595 The function reads the priority of an interrupt. The interrupt
gmatarrubia 0:820a69dfd200 596 number can be positive to specify an external (device specific)
gmatarrubia 0:820a69dfd200 597 interrupt, or negative to specify an internal (core) interrupt.
gmatarrubia 0:820a69dfd200 598
gmatarrubia 0:820a69dfd200 599
gmatarrubia 0:820a69dfd200 600 \param [in] IRQn Interrupt number.
gmatarrubia 0:820a69dfd200 601 \return Interrupt Priority. Value is aligned automatically to the implemented
gmatarrubia 0:820a69dfd200 602 priority bits of the microcontroller.
gmatarrubia 0:820a69dfd200 603 */
gmatarrubia 0:820a69dfd200 604 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
gmatarrubia 0:820a69dfd200 605 {
gmatarrubia 0:820a69dfd200 606
gmatarrubia 0:820a69dfd200 607 if(IRQn < 0) {
gmatarrubia 0:820a69dfd200 608 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
gmatarrubia 0:820a69dfd200 609 else {
gmatarrubia 0:820a69dfd200 610 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
gmatarrubia 0:820a69dfd200 611 }
gmatarrubia 0:820a69dfd200 612
gmatarrubia 0:820a69dfd200 613
gmatarrubia 0:820a69dfd200 614 /** \brief System Reset
gmatarrubia 0:820a69dfd200 615
gmatarrubia 0:820a69dfd200 616 The function initiates a system reset request to reset the MCU.
gmatarrubia 0:820a69dfd200 617 */
gmatarrubia 0:820a69dfd200 618 __STATIC_INLINE void NVIC_SystemReset(void)
gmatarrubia 0:820a69dfd200 619 {
gmatarrubia 0:820a69dfd200 620 __DSB(); /* Ensure all outstanding memory accesses included
gmatarrubia 0:820a69dfd200 621 buffered write are completed before reset */
gmatarrubia 0:820a69dfd200 622 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
gmatarrubia 0:820a69dfd200 623 SCB_AIRCR_SYSRESETREQ_Msk);
gmatarrubia 0:820a69dfd200 624 __DSB(); /* Ensure completion of memory access */
gmatarrubia 0:820a69dfd200 625 while(1); /* wait until reset */
gmatarrubia 0:820a69dfd200 626 }
gmatarrubia 0:820a69dfd200 627
gmatarrubia 0:820a69dfd200 628 /*@} end of CMSIS_Core_NVICFunctions */
gmatarrubia 0:820a69dfd200 629
gmatarrubia 0:820a69dfd200 630
gmatarrubia 0:820a69dfd200 631
gmatarrubia 0:820a69dfd200 632 /* ################################## SysTick function ############################################ */
gmatarrubia 0:820a69dfd200 633 /** \ingroup CMSIS_Core_FunctionInterface
gmatarrubia 0:820a69dfd200 634 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
gmatarrubia 0:820a69dfd200 635 \brief Functions that configure the System.
gmatarrubia 0:820a69dfd200 636 @{
gmatarrubia 0:820a69dfd200 637 */
gmatarrubia 0:820a69dfd200 638
gmatarrubia 0:820a69dfd200 639 #if (__Vendor_SysTickConfig == 0)
gmatarrubia 0:820a69dfd200 640
gmatarrubia 0:820a69dfd200 641 /** \brief System Tick Configuration
gmatarrubia 0:820a69dfd200 642
gmatarrubia 0:820a69dfd200 643 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
gmatarrubia 0:820a69dfd200 644 Counter is in free running mode to generate periodic interrupts.
gmatarrubia 0:820a69dfd200 645
gmatarrubia 0:820a69dfd200 646 \param [in] ticks Number of ticks between two interrupts.
gmatarrubia 0:820a69dfd200 647
gmatarrubia 0:820a69dfd200 648 \return 0 Function succeeded.
gmatarrubia 0:820a69dfd200 649 \return 1 Function failed.
gmatarrubia 0:820a69dfd200 650
gmatarrubia 0:820a69dfd200 651 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
gmatarrubia 0:820a69dfd200 652 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
gmatarrubia 0:820a69dfd200 653 must contain a vendor-specific implementation of this function.
gmatarrubia 0:820a69dfd200 654
gmatarrubia 0:820a69dfd200 655 */
gmatarrubia 0:820a69dfd200 656 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
gmatarrubia 0:820a69dfd200 657 {
gmatarrubia 0:820a69dfd200 658 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
gmatarrubia 0:820a69dfd200 659
gmatarrubia 0:820a69dfd200 660 SysTick->LOAD = ticks - 1; /* set reload register */
gmatarrubia 0:820a69dfd200 661 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
gmatarrubia 0:820a69dfd200 662 SysTick->VAL = 0; /* Load the SysTick Counter Value */
gmatarrubia 0:820a69dfd200 663 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
gmatarrubia 0:820a69dfd200 664 SysTick_CTRL_TICKINT_Msk |
gmatarrubia 0:820a69dfd200 665 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
gmatarrubia 0:820a69dfd200 666 return (0); /* Function successful */
gmatarrubia 0:820a69dfd200 667 }
gmatarrubia 0:820a69dfd200 668
gmatarrubia 0:820a69dfd200 669 #endif
gmatarrubia 0:820a69dfd200 670
gmatarrubia 0:820a69dfd200 671 /*@} end of CMSIS_Core_SysTickFunctions */
gmatarrubia 0:820a69dfd200 672
gmatarrubia 0:820a69dfd200 673
gmatarrubia 0:820a69dfd200 674
gmatarrubia 0:820a69dfd200 675
gmatarrubia 0:820a69dfd200 676 #endif /* __CORE_CM0_H_DEPENDANT */
gmatarrubia 0:820a69dfd200 677
gmatarrubia 0:820a69dfd200 678 #endif /* __CMSIS_GENERIC */
gmatarrubia 0:820a69dfd200 679
gmatarrubia 0:820a69dfd200 680 #ifdef __cplusplus
gmatarrubia 0:820a69dfd200 681 }
gmatarrubia 0:820a69dfd200 682 #endif