Gonzalo Matarrubia / Mbed LPC1549 mod

This repo contains the libraries of Mbed for LPC1549 with following changes: - IAP commands. - EEPROM write and read. - UART write and read (public) - CAN can_s -> LPC_C_CAN0_Type *can

mbed/TARGET_LPC1549/core_caFunc.h@0:820a69dfd200, 2015-04-14 (annotated)

Committer:
gmatarrubia
Date:
Tue Apr 14 15:00:13 2015 +0200
Revision:
0:820a69dfd200
Initial repo. IAP commands, EEPROM write/read, UART write/read, CAN

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gmatarrubia 0:820a69dfd200 1 /**************************************************************************//**
gmatarrubia 0:820a69dfd200 2 * @file core_caFunc.h
gmatarrubia 0:820a69dfd200 3 * @brief CMSIS Cortex-A Core Function Access Header File
gmatarrubia 0:820a69dfd200 4 * @version V3.10
gmatarrubia 0:820a69dfd200 5 * @date 9 May 2013
gmatarrubia 0:820a69dfd200 6 *
gmatarrubia 0:820a69dfd200 7 * @note
gmatarrubia 0:820a69dfd200 8 *
gmatarrubia 0:820a69dfd200 9 ******************************************************************************/
gmatarrubia 0:820a69dfd200 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
gmatarrubia 0:820a69dfd200 11
gmatarrubia 0:820a69dfd200 12 All rights reserved.
gmatarrubia 0:820a69dfd200 13 Redistribution and use in source and binary forms, with or without
gmatarrubia 0:820a69dfd200 14 modification, are permitted provided that the following conditions are met:
gmatarrubia 0:820a69dfd200 15 - Redistributions of source code must retain the above copyright
gmatarrubia 0:820a69dfd200 16 notice, this list of conditions and the following disclaimer.
gmatarrubia 0:820a69dfd200 17 - Redistributions in binary form must reproduce the above copyright
gmatarrubia 0:820a69dfd200 18 notice, this list of conditions and the following disclaimer in the
gmatarrubia 0:820a69dfd200 19 documentation and/or other materials provided with the distribution.
gmatarrubia 0:820a69dfd200 20 - Neither the name of ARM nor the names of its contributors may be used
gmatarrubia 0:820a69dfd200 21 to endorse or promote products derived from this software without
gmatarrubia 0:820a69dfd200 22 specific prior written permission.
gmatarrubia 0:820a69dfd200 23 *
gmatarrubia 0:820a69dfd200 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
gmatarrubia 0:820a69dfd200 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
gmatarrubia 0:820a69dfd200 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
gmatarrubia 0:820a69dfd200 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
gmatarrubia 0:820a69dfd200 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
gmatarrubia 0:820a69dfd200 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
gmatarrubia 0:820a69dfd200 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
gmatarrubia 0:820a69dfd200 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
gmatarrubia 0:820a69dfd200 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
gmatarrubia 0:820a69dfd200 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
gmatarrubia 0:820a69dfd200 34 POSSIBILITY OF SUCH DAMAGE.
gmatarrubia 0:820a69dfd200 35 ---------------------------------------------------------------------------*/
gmatarrubia 0:820a69dfd200 36
gmatarrubia 0:820a69dfd200 37
gmatarrubia 0:820a69dfd200 38 #ifndef __CORE_CAFUNC_H__
gmatarrubia 0:820a69dfd200 39 #define __CORE_CAFUNC_H__
gmatarrubia 0:820a69dfd200 40
gmatarrubia 0:820a69dfd200 41
gmatarrubia 0:820a69dfd200 42 /* ########################### Core Function Access ########################### */
gmatarrubia 0:820a69dfd200 43 /** \ingroup CMSIS_Core_FunctionInterface
gmatarrubia 0:820a69dfd200 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
gmatarrubia 0:820a69dfd200 45 @{
gmatarrubia 0:820a69dfd200 46 */
gmatarrubia 0:820a69dfd200 47
gmatarrubia 0:820a69dfd200 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
gmatarrubia 0:820a69dfd200 49 /* ARM armcc specific functions */
gmatarrubia 0:820a69dfd200 50
gmatarrubia 0:820a69dfd200 51 #if (__ARMCC_VERSION < 400677)
gmatarrubia 0:820a69dfd200 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
gmatarrubia 0:820a69dfd200 53 #endif
gmatarrubia 0:820a69dfd200 54
gmatarrubia 0:820a69dfd200 55 #define MODE_USR 0x10
gmatarrubia 0:820a69dfd200 56 #define MODE_FIQ 0x11
gmatarrubia 0:820a69dfd200 57 #define MODE_IRQ 0x12
gmatarrubia 0:820a69dfd200 58 #define MODE_SVC 0x13
gmatarrubia 0:820a69dfd200 59 #define MODE_MON 0x16
gmatarrubia 0:820a69dfd200 60 #define MODE_ABT 0x17
gmatarrubia 0:820a69dfd200 61 #define MODE_HYP 0x1A
gmatarrubia 0:820a69dfd200 62 #define MODE_UND 0x1B
gmatarrubia 0:820a69dfd200 63 #define MODE_SYS 0x1F
gmatarrubia 0:820a69dfd200 64
gmatarrubia 0:820a69dfd200 65 /** \brief Get APSR Register
gmatarrubia 0:820a69dfd200 66
gmatarrubia 0:820a69dfd200 67 This function returns the content of the APSR Register.
gmatarrubia 0:820a69dfd200 68
gmatarrubia 0:820a69dfd200 69 \return APSR Register value
gmatarrubia 0:820a69dfd200 70 */
gmatarrubia 0:820a69dfd200 71 __STATIC_INLINE uint32_t __get_APSR(void)
gmatarrubia 0:820a69dfd200 72 {
gmatarrubia 0:820a69dfd200 73 register uint32_t __regAPSR __ASM("apsr");
gmatarrubia 0:820a69dfd200 74 return(__regAPSR);
gmatarrubia 0:820a69dfd200 75 }
gmatarrubia 0:820a69dfd200 76
gmatarrubia 0:820a69dfd200 77
gmatarrubia 0:820a69dfd200 78 /** \brief Get CPSR Register
gmatarrubia 0:820a69dfd200 79
gmatarrubia 0:820a69dfd200 80 This function returns the content of the CPSR Register.
gmatarrubia 0:820a69dfd200 81
gmatarrubia 0:820a69dfd200 82 \return CPSR Register value
gmatarrubia 0:820a69dfd200 83 */
gmatarrubia 0:820a69dfd200 84 __STATIC_INLINE uint32_t __get_CPSR(void)
gmatarrubia 0:820a69dfd200 85 {
gmatarrubia 0:820a69dfd200 86 register uint32_t __regCPSR __ASM("cpsr");
gmatarrubia 0:820a69dfd200 87 return(__regCPSR);
gmatarrubia 0:820a69dfd200 88 }
gmatarrubia 0:820a69dfd200 89
gmatarrubia 0:820a69dfd200 90 /** \brief Set Stack Pointer
gmatarrubia 0:820a69dfd200 91
gmatarrubia 0:820a69dfd200 92 This function assigns the given value to the current stack pointer.
gmatarrubia 0:820a69dfd200 93
gmatarrubia 0:820a69dfd200 94 \param [in] topOfStack Stack Pointer value to set
gmatarrubia 0:820a69dfd200 95 */
gmatarrubia 0:820a69dfd200 96 register uint32_t __regSP __ASM("sp");
gmatarrubia 0:820a69dfd200 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
gmatarrubia 0:820a69dfd200 98 {
gmatarrubia 0:820a69dfd200 99 __regSP = topOfStack;
gmatarrubia 0:820a69dfd200 100 }
gmatarrubia 0:820a69dfd200 101
gmatarrubia 0:820a69dfd200 102
gmatarrubia 0:820a69dfd200 103 /** \brief Get link register
gmatarrubia 0:820a69dfd200 104
gmatarrubia 0:820a69dfd200 105 This function returns the value of the link register
gmatarrubia 0:820a69dfd200 106
gmatarrubia 0:820a69dfd200 107 \return Value of link register
gmatarrubia 0:820a69dfd200 108 */
gmatarrubia 0:820a69dfd200 109 register uint32_t __reglr __ASM("lr");
gmatarrubia 0:820a69dfd200 110 __STATIC_INLINE uint32_t __get_LR(void)
gmatarrubia 0:820a69dfd200 111 {
gmatarrubia 0:820a69dfd200 112 return(__reglr);
gmatarrubia 0:820a69dfd200 113 }
gmatarrubia 0:820a69dfd200 114
gmatarrubia 0:820a69dfd200 115 /** \brief Set link register
gmatarrubia 0:820a69dfd200 116
gmatarrubia 0:820a69dfd200 117 This function sets the value of the link register
gmatarrubia 0:820a69dfd200 118
gmatarrubia 0:820a69dfd200 119 \param [in] lr LR value to set
gmatarrubia 0:820a69dfd200 120 */
gmatarrubia 0:820a69dfd200 121 __STATIC_INLINE void __set_LR(uint32_t lr)
gmatarrubia 0:820a69dfd200 122 {
gmatarrubia 0:820a69dfd200 123 __reglr = lr;
gmatarrubia 0:820a69dfd200 124 }
gmatarrubia 0:820a69dfd200 125
gmatarrubia 0:820a69dfd200 126 /** \brief Set Process Stack Pointer
gmatarrubia 0:820a69dfd200 127
gmatarrubia 0:820a69dfd200 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
gmatarrubia 0:820a69dfd200 129
gmatarrubia 0:820a69dfd200 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
gmatarrubia 0:820a69dfd200 131 */
gmatarrubia 0:820a69dfd200 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
gmatarrubia 0:820a69dfd200 133 {
gmatarrubia 0:820a69dfd200 134 ARM
gmatarrubia 0:820a69dfd200 135 PRESERVE8
gmatarrubia 0:820a69dfd200 136
gmatarrubia 0:820a69dfd200 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
gmatarrubia 0:820a69dfd200 138 MRS R1, CPSR
gmatarrubia 0:820a69dfd200 139 CPS #MODE_SYS ;no effect in USR mode
gmatarrubia 0:820a69dfd200 140 MOV SP, R0
gmatarrubia 0:820a69dfd200 141 MSR CPSR_c, R1 ;no effect in USR mode
gmatarrubia 0:820a69dfd200 142 ISB
gmatarrubia 0:820a69dfd200 143 BX LR
gmatarrubia 0:820a69dfd200 144
gmatarrubia 0:820a69dfd200 145 }
gmatarrubia 0:820a69dfd200 146
gmatarrubia 0:820a69dfd200 147 /** \brief Set User Mode
gmatarrubia 0:820a69dfd200 148
gmatarrubia 0:820a69dfd200 149 This function changes the processor state to User Mode
gmatarrubia 0:820a69dfd200 150
gmatarrubia 0:820a69dfd200 151 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
gmatarrubia 0:820a69dfd200 152 */
gmatarrubia 0:820a69dfd200 153 __STATIC_ASM void __set_CPS_USR(void)
gmatarrubia 0:820a69dfd200 154 {
gmatarrubia 0:820a69dfd200 155 ARM
gmatarrubia 0:820a69dfd200 156
gmatarrubia 0:820a69dfd200 157 CPS #MODE_USR
gmatarrubia 0:820a69dfd200 158 BX LR
gmatarrubia 0:820a69dfd200 159 }
gmatarrubia 0:820a69dfd200 160
gmatarrubia 0:820a69dfd200 161
gmatarrubia 0:820a69dfd200 162 /** \brief Enable FIQ
gmatarrubia 0:820a69dfd200 163
gmatarrubia 0:820a69dfd200 164 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
gmatarrubia 0:820a69dfd200 165 Can only be executed in Privileged modes.
gmatarrubia 0:820a69dfd200 166 */
gmatarrubia 0:820a69dfd200 167 #define __enable_fault_irq __enable_fiq
gmatarrubia 0:820a69dfd200 168
gmatarrubia 0:820a69dfd200 169
gmatarrubia 0:820a69dfd200 170 /** \brief Disable FIQ
gmatarrubia 0:820a69dfd200 171
gmatarrubia 0:820a69dfd200 172 This function disables FIQ interrupts by setting the F-bit in the CPSR.
gmatarrubia 0:820a69dfd200 173 Can only be executed in Privileged modes.
gmatarrubia 0:820a69dfd200 174 */
gmatarrubia 0:820a69dfd200 175 #define __disable_fault_irq __disable_fiq
gmatarrubia 0:820a69dfd200 176
gmatarrubia 0:820a69dfd200 177
gmatarrubia 0:820a69dfd200 178 /** \brief Get FPSCR
gmatarrubia 0:820a69dfd200 179
gmatarrubia 0:820a69dfd200 180 This function returns the current value of the Floating Point Status/Control register.
gmatarrubia 0:820a69dfd200 181
gmatarrubia 0:820a69dfd200 182 \return Floating Point Status/Control register value
gmatarrubia 0:820a69dfd200 183 */
gmatarrubia 0:820a69dfd200 184 __STATIC_INLINE uint32_t __get_FPSCR(void)
gmatarrubia 0:820a69dfd200 185 {
gmatarrubia 0:820a69dfd200 186 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
gmatarrubia 0:820a69dfd200 187 register uint32_t __regfpscr __ASM("fpscr");
gmatarrubia 0:820a69dfd200 188 return(__regfpscr);
gmatarrubia 0:820a69dfd200 189 #else
gmatarrubia 0:820a69dfd200 190 return(0);
gmatarrubia 0:820a69dfd200 191 #endif
gmatarrubia 0:820a69dfd200 192 }
gmatarrubia 0:820a69dfd200 193
gmatarrubia 0:820a69dfd200 194
gmatarrubia 0:820a69dfd200 195 /** \brief Set FPSCR
gmatarrubia 0:820a69dfd200 196
gmatarrubia 0:820a69dfd200 197 This function assigns the given value to the Floating Point Status/Control register.
gmatarrubia 0:820a69dfd200 198
gmatarrubia 0:820a69dfd200 199 \param [in] fpscr Floating Point Status/Control value to set
gmatarrubia 0:820a69dfd200 200 */
gmatarrubia 0:820a69dfd200 201 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
gmatarrubia 0:820a69dfd200 202 {
gmatarrubia 0:820a69dfd200 203 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
gmatarrubia 0:820a69dfd200 204 register uint32_t __regfpscr __ASM("fpscr");
gmatarrubia 0:820a69dfd200 205 __regfpscr = (fpscr);
gmatarrubia 0:820a69dfd200 206 #endif
gmatarrubia 0:820a69dfd200 207 }
gmatarrubia 0:820a69dfd200 208
gmatarrubia 0:820a69dfd200 209 /** \brief Get FPEXC
gmatarrubia 0:820a69dfd200 210
gmatarrubia 0:820a69dfd200 211 This function returns the current value of the Floating Point Exception Control register.
gmatarrubia 0:820a69dfd200 212
gmatarrubia 0:820a69dfd200 213 \return Floating Point Exception Control register value
gmatarrubia 0:820a69dfd200 214 */
gmatarrubia 0:820a69dfd200 215 __STATIC_INLINE uint32_t __get_FPEXC(void)
gmatarrubia 0:820a69dfd200 216 {
gmatarrubia 0:820a69dfd200 217 #if (__FPU_PRESENT == 1)
gmatarrubia 0:820a69dfd200 218 register uint32_t __regfpexc __ASM("fpexc");
gmatarrubia 0:820a69dfd200 219 return(__regfpexc);
gmatarrubia 0:820a69dfd200 220 #else
gmatarrubia 0:820a69dfd200 221 return(0);
gmatarrubia 0:820a69dfd200 222 #endif
gmatarrubia 0:820a69dfd200 223 }
gmatarrubia 0:820a69dfd200 224
gmatarrubia 0:820a69dfd200 225
gmatarrubia 0:820a69dfd200 226 /** \brief Set FPEXC
gmatarrubia 0:820a69dfd200 227
gmatarrubia 0:820a69dfd200 228 This function assigns the given value to the Floating Point Exception Control register.
gmatarrubia 0:820a69dfd200 229
gmatarrubia 0:820a69dfd200 230 \param [in] fpscr Floating Point Exception Control value to set
gmatarrubia 0:820a69dfd200 231 */
gmatarrubia 0:820a69dfd200 232 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
gmatarrubia 0:820a69dfd200 233 {
gmatarrubia 0:820a69dfd200 234 #if (__FPU_PRESENT == 1)
gmatarrubia 0:820a69dfd200 235 register uint32_t __regfpexc __ASM("fpexc");
gmatarrubia 0:820a69dfd200 236 __regfpexc = (fpexc);
gmatarrubia 0:820a69dfd200 237 #endif
gmatarrubia 0:820a69dfd200 238 }
gmatarrubia 0:820a69dfd200 239
gmatarrubia 0:820a69dfd200 240 /** \brief Get CPACR
gmatarrubia 0:820a69dfd200 241
gmatarrubia 0:820a69dfd200 242 This function returns the current value of the Coprocessor Access Control register.
gmatarrubia 0:820a69dfd200 243
gmatarrubia 0:820a69dfd200 244 \return Coprocessor Access Control register value
gmatarrubia 0:820a69dfd200 245 */
gmatarrubia 0:820a69dfd200 246 __STATIC_INLINE uint32_t __get_CPACR(void)
gmatarrubia 0:820a69dfd200 247 {
gmatarrubia 0:820a69dfd200 248 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
gmatarrubia 0:820a69dfd200 249 return __regCPACR;
gmatarrubia 0:820a69dfd200 250 }
gmatarrubia 0:820a69dfd200 251
gmatarrubia 0:820a69dfd200 252 /** \brief Set CPACR
gmatarrubia 0:820a69dfd200 253
gmatarrubia 0:820a69dfd200 254 This function assigns the given value to the Coprocessor Access Control register.
gmatarrubia 0:820a69dfd200 255
gmatarrubia 0:820a69dfd200 256 \param [in] cpacr Coporcessor Acccess Control value to set
gmatarrubia 0:820a69dfd200 257 */
gmatarrubia 0:820a69dfd200 258 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
gmatarrubia 0:820a69dfd200 259 {
gmatarrubia 0:820a69dfd200 260 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
gmatarrubia 0:820a69dfd200 261 __regCPACR = cpacr;
gmatarrubia 0:820a69dfd200 262 __ISB();
gmatarrubia 0:820a69dfd200 263 }
gmatarrubia 0:820a69dfd200 264
gmatarrubia 0:820a69dfd200 265 /** \brief Get CBAR
gmatarrubia 0:820a69dfd200 266
gmatarrubia 0:820a69dfd200 267 This function returns the value of the Configuration Base Address register.
gmatarrubia 0:820a69dfd200 268
gmatarrubia 0:820a69dfd200 269 \return Configuration Base Address register value
gmatarrubia 0:820a69dfd200 270 */
gmatarrubia 0:820a69dfd200 271 __STATIC_INLINE uint32_t __get_CBAR() {
gmatarrubia 0:820a69dfd200 272 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
gmatarrubia 0:820a69dfd200 273 return(__regCBAR);
gmatarrubia 0:820a69dfd200 274 }
gmatarrubia 0:820a69dfd200 275
gmatarrubia 0:820a69dfd200 276 /** \brief Get TTBR0
gmatarrubia 0:820a69dfd200 277
gmatarrubia 0:820a69dfd200 278 This function returns the value of the Configuration Base Address register.
gmatarrubia 0:820a69dfd200 279
gmatarrubia 0:820a69dfd200 280 \return Translation Table Base Register 0 value
gmatarrubia 0:820a69dfd200 281 */
gmatarrubia 0:820a69dfd200 282 __STATIC_INLINE uint32_t __get_TTBR0() {
gmatarrubia 0:820a69dfd200 283 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
gmatarrubia 0:820a69dfd200 284 return(__regTTBR0);
gmatarrubia 0:820a69dfd200 285 }
gmatarrubia 0:820a69dfd200 286
gmatarrubia 0:820a69dfd200 287 /** \brief Set TTBR0
gmatarrubia 0:820a69dfd200 288
gmatarrubia 0:820a69dfd200 289 This function assigns the given value to the Coprocessor Access Control register.
gmatarrubia 0:820a69dfd200 290
gmatarrubia 0:820a69dfd200 291 \param [in] ttbr0 Translation Table Base Register 0 value to set
gmatarrubia 0:820a69dfd200 292 */
gmatarrubia 0:820a69dfd200 293 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
gmatarrubia 0:820a69dfd200 294 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
gmatarrubia 0:820a69dfd200 295 __regTTBR0 = ttbr0;
gmatarrubia 0:820a69dfd200 296 __ISB();
gmatarrubia 0:820a69dfd200 297 }
gmatarrubia 0:820a69dfd200 298
gmatarrubia 0:820a69dfd200 299 /** \brief Get DACR
gmatarrubia 0:820a69dfd200 300
gmatarrubia 0:820a69dfd200 301 This function returns the value of the Domain Access Control Register.
gmatarrubia 0:820a69dfd200 302
gmatarrubia 0:820a69dfd200 303 \return Domain Access Control Register value
gmatarrubia 0:820a69dfd200 304 */
gmatarrubia 0:820a69dfd200 305 __STATIC_INLINE uint32_t __get_DACR() {
gmatarrubia 0:820a69dfd200 306 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
gmatarrubia 0:820a69dfd200 307 return(__regDACR);
gmatarrubia 0:820a69dfd200 308 }
gmatarrubia 0:820a69dfd200 309
gmatarrubia 0:820a69dfd200 310 /** \brief Set DACR
gmatarrubia 0:820a69dfd200 311
gmatarrubia 0:820a69dfd200 312 This function assigns the given value to the Coprocessor Access Control register.
gmatarrubia 0:820a69dfd200 313
gmatarrubia 0:820a69dfd200 314 \param [in] dacr Domain Access Control Register value to set
gmatarrubia 0:820a69dfd200 315 */
gmatarrubia 0:820a69dfd200 316 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
gmatarrubia 0:820a69dfd200 317 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
gmatarrubia 0:820a69dfd200 318 __regDACR = dacr;
gmatarrubia 0:820a69dfd200 319 __ISB();
gmatarrubia 0:820a69dfd200 320 }
gmatarrubia 0:820a69dfd200 321
gmatarrubia 0:820a69dfd200 322 /******************************** Cache and BTAC enable ****************************************************/
gmatarrubia 0:820a69dfd200 323
gmatarrubia 0:820a69dfd200 324 /** \brief Set SCTLR
gmatarrubia 0:820a69dfd200 325
gmatarrubia 0:820a69dfd200 326 This function assigns the given value to the System Control Register.
gmatarrubia 0:820a69dfd200 327
gmatarrubia 0:820a69dfd200 328 \param [in] sctlr System Control Register, value to set
gmatarrubia 0:820a69dfd200 329 */
gmatarrubia 0:820a69dfd200 330 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
gmatarrubia 0:820a69dfd200 331 {
gmatarrubia 0:820a69dfd200 332 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
gmatarrubia 0:820a69dfd200 333 __regSCTLR = sctlr;
gmatarrubia 0:820a69dfd200 334 }
gmatarrubia 0:820a69dfd200 335
gmatarrubia 0:820a69dfd200 336 /** \brief Get SCTLR
gmatarrubia 0:820a69dfd200 337
gmatarrubia 0:820a69dfd200 338 This function returns the value of the System Control Register.
gmatarrubia 0:820a69dfd200 339
gmatarrubia 0:820a69dfd200 340 \return System Control Register value
gmatarrubia 0:820a69dfd200 341 */
gmatarrubia 0:820a69dfd200 342 __STATIC_INLINE uint32_t __get_SCTLR() {
gmatarrubia 0:820a69dfd200 343 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
gmatarrubia 0:820a69dfd200 344 return(__regSCTLR);
gmatarrubia 0:820a69dfd200 345 }
gmatarrubia 0:820a69dfd200 346
gmatarrubia 0:820a69dfd200 347 /** \brief Enable Caches
gmatarrubia 0:820a69dfd200 348
gmatarrubia 0:820a69dfd200 349 Enable Caches
gmatarrubia 0:820a69dfd200 350 */
gmatarrubia 0:820a69dfd200 351 __STATIC_INLINE void __enable_caches(void) {
gmatarrubia 0:820a69dfd200 352 // Set I bit 12 to enable I Cache
gmatarrubia 0:820a69dfd200 353 // Set C bit 2 to enable D Cache
gmatarrubia 0:820a69dfd200 354 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
gmatarrubia 0:820a69dfd200 355 }
gmatarrubia 0:820a69dfd200 356
gmatarrubia 0:820a69dfd200 357 /** \brief Disable Caches
gmatarrubia 0:820a69dfd200 358
gmatarrubia 0:820a69dfd200 359 Disable Caches
gmatarrubia 0:820a69dfd200 360 */
gmatarrubia 0:820a69dfd200 361 __STATIC_INLINE void __disable_caches(void) {
gmatarrubia 0:820a69dfd200 362 // Clear I bit 12 to disable I Cache
gmatarrubia 0:820a69dfd200 363 // Clear C bit 2 to disable D Cache
gmatarrubia 0:820a69dfd200 364 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
gmatarrubia 0:820a69dfd200 365 __ISB();
gmatarrubia 0:820a69dfd200 366 }
gmatarrubia 0:820a69dfd200 367
gmatarrubia 0:820a69dfd200 368 /** \brief Enable BTAC
gmatarrubia 0:820a69dfd200 369
gmatarrubia 0:820a69dfd200 370 Enable BTAC
gmatarrubia 0:820a69dfd200 371 */
gmatarrubia 0:820a69dfd200 372 __STATIC_INLINE void __enable_btac(void) {
gmatarrubia 0:820a69dfd200 373 // Set Z bit 11 to enable branch prediction
gmatarrubia 0:820a69dfd200 374 __set_SCTLR( __get_SCTLR() | (1 << 11));
gmatarrubia 0:820a69dfd200 375 __ISB();
gmatarrubia 0:820a69dfd200 376 }
gmatarrubia 0:820a69dfd200 377
gmatarrubia 0:820a69dfd200 378 /** \brief Disable BTAC
gmatarrubia 0:820a69dfd200 379
gmatarrubia 0:820a69dfd200 380 Disable BTAC
gmatarrubia 0:820a69dfd200 381 */
gmatarrubia 0:820a69dfd200 382 __STATIC_INLINE void __disable_btac(void) {
gmatarrubia 0:820a69dfd200 383 // Clear Z bit 11 to disable branch prediction
gmatarrubia 0:820a69dfd200 384 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
gmatarrubia 0:820a69dfd200 385 }
gmatarrubia 0:820a69dfd200 386
gmatarrubia 0:820a69dfd200 387
gmatarrubia 0:820a69dfd200 388 /** \brief Enable MMU
gmatarrubia 0:820a69dfd200 389
gmatarrubia 0:820a69dfd200 390 Enable MMU
gmatarrubia 0:820a69dfd200 391 */
gmatarrubia 0:820a69dfd200 392 __STATIC_INLINE void __enable_mmu(void) {
gmatarrubia 0:820a69dfd200 393 // Set M bit 0 to enable the MMU
gmatarrubia 0:820a69dfd200 394 // Set AFE bit to enable simplified access permissions model
gmatarrubia 0:820a69dfd200 395 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
gmatarrubia 0:820a69dfd200 396 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
gmatarrubia 0:820a69dfd200 397 __ISB();
gmatarrubia 0:820a69dfd200 398 }
gmatarrubia 0:820a69dfd200 399
gmatarrubia 0:820a69dfd200 400 /** \brief Enable MMU
gmatarrubia 0:820a69dfd200 401
gmatarrubia 0:820a69dfd200 402 Enable MMU
gmatarrubia 0:820a69dfd200 403 */
gmatarrubia 0:820a69dfd200 404 __STATIC_INLINE void __disable_mmu(void) {
gmatarrubia 0:820a69dfd200 405 // Clear M bit 0 to disable the MMU
gmatarrubia 0:820a69dfd200 406 __set_SCTLR( __get_SCTLR() & ~1);
gmatarrubia 0:820a69dfd200 407 __ISB();
gmatarrubia 0:820a69dfd200 408 }
gmatarrubia 0:820a69dfd200 409
gmatarrubia 0:820a69dfd200 410 /******************************** TLB maintenance operations ************************************************/
gmatarrubia 0:820a69dfd200 411 /** \brief Invalidate the whole tlb
gmatarrubia 0:820a69dfd200 412
gmatarrubia 0:820a69dfd200 413 TLBIALL. Invalidate the whole tlb
gmatarrubia 0:820a69dfd200 414 */
gmatarrubia 0:820a69dfd200 415
gmatarrubia 0:820a69dfd200 416 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
gmatarrubia 0:820a69dfd200 417 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
gmatarrubia 0:820a69dfd200 418 __TLBIALL = 0;
gmatarrubia 0:820a69dfd200 419 __DSB();
gmatarrubia 0:820a69dfd200 420 __ISB();
gmatarrubia 0:820a69dfd200 421 }
gmatarrubia 0:820a69dfd200 422
gmatarrubia 0:820a69dfd200 423 /******************************** BTB maintenance operations ************************************************/
gmatarrubia 0:820a69dfd200 424 /** \brief Invalidate entire branch predictor array
gmatarrubia 0:820a69dfd200 425
gmatarrubia 0:820a69dfd200 426 BPIALL. Branch Predictor Invalidate All.
gmatarrubia 0:820a69dfd200 427 */
gmatarrubia 0:820a69dfd200 428
gmatarrubia 0:820a69dfd200 429 __STATIC_INLINE void __v7_inv_btac(void) {
gmatarrubia 0:820a69dfd200 430 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
gmatarrubia 0:820a69dfd200 431 __BPIALL = 0;
gmatarrubia 0:820a69dfd200 432 __DSB(); //ensure completion of the invalidation
gmatarrubia 0:820a69dfd200 433 __ISB(); //ensure instruction fetch path sees new state
gmatarrubia 0:820a69dfd200 434 }
gmatarrubia 0:820a69dfd200 435
gmatarrubia 0:820a69dfd200 436
gmatarrubia 0:820a69dfd200 437 /******************************** L1 cache operations ******************************************************/
gmatarrubia 0:820a69dfd200 438
gmatarrubia 0:820a69dfd200 439 /** \brief Invalidate the whole I$
gmatarrubia 0:820a69dfd200 440
gmatarrubia 0:820a69dfd200 441 ICIALLU. Instruction Cache Invalidate All to PoU
gmatarrubia 0:820a69dfd200 442 */
gmatarrubia 0:820a69dfd200 443 __STATIC_INLINE void __v7_inv_icache_all(void) {
gmatarrubia 0:820a69dfd200 444 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
gmatarrubia 0:820a69dfd200 445 __ICIALLU = 0;
gmatarrubia 0:820a69dfd200 446 __DSB(); //ensure completion of the invalidation
gmatarrubia 0:820a69dfd200 447 __ISB(); //ensure instruction fetch path sees new I cache state
gmatarrubia 0:820a69dfd200 448 }
gmatarrubia 0:820a69dfd200 449
gmatarrubia 0:820a69dfd200 450 /** \brief Clean D$ by MVA
gmatarrubia 0:820a69dfd200 451
gmatarrubia 0:820a69dfd200 452 DCCMVAC. Data cache clean by MVA to PoC
gmatarrubia 0:820a69dfd200 453 */
gmatarrubia 0:820a69dfd200 454 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
gmatarrubia 0:820a69dfd200 455 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
gmatarrubia 0:820a69dfd200 456 __DCCMVAC = (uint32_t)va;
gmatarrubia 0:820a69dfd200 457 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
gmatarrubia 0:820a69dfd200 458 }
gmatarrubia 0:820a69dfd200 459
gmatarrubia 0:820a69dfd200 460 /** \brief Invalidate D$ by MVA
gmatarrubia 0:820a69dfd200 461
gmatarrubia 0:820a69dfd200 462 DCIMVAC. Data cache invalidate by MVA to PoC
gmatarrubia 0:820a69dfd200 463 */
gmatarrubia 0:820a69dfd200 464 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
gmatarrubia 0:820a69dfd200 465 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
gmatarrubia 0:820a69dfd200 466 __DCIMVAC = (uint32_t)va;
gmatarrubia 0:820a69dfd200 467 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
gmatarrubia 0:820a69dfd200 468 }
gmatarrubia 0:820a69dfd200 469
gmatarrubia 0:820a69dfd200 470 /** \brief Clean and Invalidate D$ by MVA
gmatarrubia 0:820a69dfd200 471
gmatarrubia 0:820a69dfd200 472 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
gmatarrubia 0:820a69dfd200 473 */
gmatarrubia 0:820a69dfd200 474 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
gmatarrubia 0:820a69dfd200 475 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
gmatarrubia 0:820a69dfd200 476 __DCCIMVAC = (uint32_t)va;
gmatarrubia 0:820a69dfd200 477 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
gmatarrubia 0:820a69dfd200 478 }
gmatarrubia 0:820a69dfd200 479
gmatarrubia 0:820a69dfd200 480 /** \brief
gmatarrubia 0:820a69dfd200 481 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
gmatarrubia 0:820a69dfd200 482 */
gmatarrubia 0:820a69dfd200 483 #pragma push
gmatarrubia 0:820a69dfd200 484 #pragma arm
gmatarrubia 0:820a69dfd200 485 __STATIC_ASM void __v7_all_cache(uint32_t op) {
gmatarrubia 0:820a69dfd200 486 ARM
gmatarrubia 0:820a69dfd200 487
gmatarrubia 0:820a69dfd200 488 PUSH {R4-R11}
gmatarrubia 0:820a69dfd200 489
gmatarrubia 0:820a69dfd200 490 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
gmatarrubia 0:820a69dfd200 491 ANDS R3, R6, #0x07000000 // Extract coherency level
gmatarrubia 0:820a69dfd200 492 MOV R3, R3, LSR #23 // Total cache levels << 1
gmatarrubia 0:820a69dfd200 493 BEQ Finished // If 0, no need to clean
gmatarrubia 0:820a69dfd200 494
gmatarrubia 0:820a69dfd200 495 MOV R10, #0 // R10 holds current cache level << 1
gmatarrubia 0:820a69dfd200 496 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
gmatarrubia 0:820a69dfd200 497 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
gmatarrubia 0:820a69dfd200 498 AND R1, R1, #7 // Isolate those lower 3 bits
gmatarrubia 0:820a69dfd200 499 CMP R1, #2
gmatarrubia 0:820a69dfd200 500 BLT Skip // No cache or only instruction cache at this level
gmatarrubia 0:820a69dfd200 501
gmatarrubia 0:820a69dfd200 502 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
gmatarrubia 0:820a69dfd200 503 ISB // ISB to sync the change to the CacheSizeID reg
gmatarrubia 0:820a69dfd200 504 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
gmatarrubia 0:820a69dfd200 505 AND R2, R1, #7 // Extract the line length field
gmatarrubia 0:820a69dfd200 506 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
gmatarrubia 0:820a69dfd200 507 LDR R4, =0x3FF
gmatarrubia 0:820a69dfd200 508 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
gmatarrubia 0:820a69dfd200 509 CLZ R5, R4 // R5 is the bit position of the way size increment
gmatarrubia 0:820a69dfd200 510 LDR R7, =0x7FFF
gmatarrubia 0:820a69dfd200 511 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
gmatarrubia 0:820a69dfd200 512
gmatarrubia 0:820a69dfd200 513 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
gmatarrubia 0:820a69dfd200 514
gmatarrubia 0:820a69dfd200 515 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
gmatarrubia 0:820a69dfd200 516 ORR R11, R11, R7, LSL R2 // Factor in the Set number
gmatarrubia 0:820a69dfd200 517 CMP R0, #0
gmatarrubia 0:820a69dfd200 518 BNE Dccsw
gmatarrubia 0:820a69dfd200 519 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
gmatarrubia 0:820a69dfd200 520 B cont
gmatarrubia 0:820a69dfd200 521 Dccsw CMP R0, #1
gmatarrubia 0:820a69dfd200 522 BNE Dccisw
gmatarrubia 0:820a69dfd200 523 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
gmatarrubia 0:820a69dfd200 524 B cont
gmatarrubia 0:820a69dfd200 525 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW, Clean and Invalidate by Set/Way
gmatarrubia 0:820a69dfd200 526 cont SUBS R9, R9, #1 // Decrement the Way number
gmatarrubia 0:820a69dfd200 527 BGE Loop3
gmatarrubia 0:820a69dfd200 528 SUBS R7, R7, #1 // Decrement the Set number
gmatarrubia 0:820a69dfd200 529 BGE Loop2
gmatarrubia 0:820a69dfd200 530 Skip ADD R10, R10, #2 // increment the cache number
gmatarrubia 0:820a69dfd200 531 CMP R3, R10
gmatarrubia 0:820a69dfd200 532 BGT Loop1
gmatarrubia 0:820a69dfd200 533
gmatarrubia 0:820a69dfd200 534 Finished
gmatarrubia 0:820a69dfd200 535 DSB
gmatarrubia 0:820a69dfd200 536 POP {R4-R11}
gmatarrubia 0:820a69dfd200 537 BX lr
gmatarrubia 0:820a69dfd200 538
gmatarrubia 0:820a69dfd200 539 }
gmatarrubia 0:820a69dfd200 540 #pragma pop
gmatarrubia 0:820a69dfd200 541
gmatarrubia 0:820a69dfd200 542 /** \brief __v7_all_cache - helper function
gmatarrubia 0:820a69dfd200 543
gmatarrubia 0:820a69dfd200 544 */
gmatarrubia 0:820a69dfd200 545
gmatarrubia 0:820a69dfd200 546 /** \brief Invalidate the whole D$
gmatarrubia 0:820a69dfd200 547
gmatarrubia 0:820a69dfd200 548 DCISW. Invalidate by Set/Way
gmatarrubia 0:820a69dfd200 549 */
gmatarrubia 0:820a69dfd200 550
gmatarrubia 0:820a69dfd200 551 __STATIC_INLINE void __v7_inv_dcache_all(void) {
gmatarrubia 0:820a69dfd200 552 __v7_all_cache(0);
gmatarrubia 0:820a69dfd200 553 }
gmatarrubia 0:820a69dfd200 554
gmatarrubia 0:820a69dfd200 555 /** \brief Clean the whole D$
gmatarrubia 0:820a69dfd200 556
gmatarrubia 0:820a69dfd200 557 DCCSW. Clean by Set/Way
gmatarrubia 0:820a69dfd200 558 */
gmatarrubia 0:820a69dfd200 559
gmatarrubia 0:820a69dfd200 560 __STATIC_INLINE void __v7_clean_dcache_all(void) {
gmatarrubia 0:820a69dfd200 561 __v7_all_cache(1);
gmatarrubia 0:820a69dfd200 562 }
gmatarrubia 0:820a69dfd200 563
gmatarrubia 0:820a69dfd200 564 /** \brief Clean and invalidate the whole D$
gmatarrubia 0:820a69dfd200 565
gmatarrubia 0:820a69dfd200 566 DCCISW. Clean and Invalidate by Set/Way
gmatarrubia 0:820a69dfd200 567 */
gmatarrubia 0:820a69dfd200 568
gmatarrubia 0:820a69dfd200 569 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
gmatarrubia 0:820a69dfd200 570 __v7_all_cache(2);
gmatarrubia 0:820a69dfd200 571 }
gmatarrubia 0:820a69dfd200 572
gmatarrubia 0:820a69dfd200 573 #include "core_ca_mmu.h"
gmatarrubia 0:820a69dfd200 574
gmatarrubia 0:820a69dfd200 575 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
gmatarrubia 0:820a69dfd200 576
gmatarrubia 0:820a69dfd200 577 #error IAR Compiler support not implemented for Cortex-A
gmatarrubia 0:820a69dfd200 578
gmatarrubia 0:820a69dfd200 579 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
gmatarrubia 0:820a69dfd200 580
gmatarrubia 0:820a69dfd200 581 //#error GNU Compiler support not implemented for Cortex-A
gmatarrubia 0:820a69dfd200 582
gmatarrubia 0:820a69dfd200 583 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
gmatarrubia 0:820a69dfd200 584
gmatarrubia 0:820a69dfd200 585 #error TASKING Compiler support not implemented for Cortex-A
gmatarrubia 0:820a69dfd200 586
gmatarrubia 0:820a69dfd200 587 #endif
gmatarrubia 0:820a69dfd200 588
gmatarrubia 0:820a69dfd200 589 /*@} end of CMSIS_Core_RegAccFunctions */
gmatarrubia 0:820a69dfd200 590
gmatarrubia 0:820a69dfd200 591
gmatarrubia 0:820a69dfd200 592 #endif /* __CORE_CAFUNC_H__ */