Gonzalo Matarrubia / Mbed LPC1549 mod

This repo contains the libraries of Mbed for LPC1549 with following changes: - IAP commands. - EEPROM write and read. - UART write and read (public) - CAN can_s -> LPC_C_CAN0_Type *can

mbed/TARGET_LPC1549/core_ca9.h@0:820a69dfd200, 2015-04-14 (annotated)

Committer:
gmatarrubia
Date:
Tue Apr 14 15:00:13 2015 +0200
Revision:
0:820a69dfd200
Initial repo. IAP commands, EEPROM write/read, UART write/read, CAN

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gmatarrubia 0:820a69dfd200 1 /**************************************************************************//**
gmatarrubia 0:820a69dfd200 2 * @file core_ca9.h
gmatarrubia 0:820a69dfd200 3 * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
gmatarrubia 0:820a69dfd200 4 * @version
gmatarrubia 0:820a69dfd200 5 * @date 25 March 2013
gmatarrubia 0:820a69dfd200 6 *
gmatarrubia 0:820a69dfd200 7 * @note
gmatarrubia 0:820a69dfd200 8 *
gmatarrubia 0:820a69dfd200 9 ******************************************************************************/
gmatarrubia 0:820a69dfd200 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
gmatarrubia 0:820a69dfd200 11
gmatarrubia 0:820a69dfd200 12 All rights reserved.
gmatarrubia 0:820a69dfd200 13 Redistribution and use in source and binary forms, with or without
gmatarrubia 0:820a69dfd200 14 modification, are permitted provided that the following conditions are met:
gmatarrubia 0:820a69dfd200 15 - Redistributions of source code must retain the above copyright
gmatarrubia 0:820a69dfd200 16 notice, this list of conditions and the following disclaimer.
gmatarrubia 0:820a69dfd200 17 - Redistributions in binary form must reproduce the above copyright
gmatarrubia 0:820a69dfd200 18 notice, this list of conditions and the following disclaimer in the
gmatarrubia 0:820a69dfd200 19 documentation and/or other materials provided with the distribution.
gmatarrubia 0:820a69dfd200 20 - Neither the name of ARM nor the names of its contributors may be used
gmatarrubia 0:820a69dfd200 21 to endorse or promote products derived from this software without
gmatarrubia 0:820a69dfd200 22 specific prior written permission.
gmatarrubia 0:820a69dfd200 23 *
gmatarrubia 0:820a69dfd200 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
gmatarrubia 0:820a69dfd200 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
gmatarrubia 0:820a69dfd200 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
gmatarrubia 0:820a69dfd200 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
gmatarrubia 0:820a69dfd200 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
gmatarrubia 0:820a69dfd200 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
gmatarrubia 0:820a69dfd200 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
gmatarrubia 0:820a69dfd200 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
gmatarrubia 0:820a69dfd200 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
gmatarrubia 0:820a69dfd200 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
gmatarrubia 0:820a69dfd200 34 POSSIBILITY OF SUCH DAMAGE.
gmatarrubia 0:820a69dfd200 35 ---------------------------------------------------------------------------*/
gmatarrubia 0:820a69dfd200 36
gmatarrubia 0:820a69dfd200 37
gmatarrubia 0:820a69dfd200 38 #if defined ( __ICCARM__ )
gmatarrubia 0:820a69dfd200 39 #pragma system_include /* treat file as system include file for MISRA check */
gmatarrubia 0:820a69dfd200 40 #endif
gmatarrubia 0:820a69dfd200 41
gmatarrubia 0:820a69dfd200 42 #ifdef __cplusplus
gmatarrubia 0:820a69dfd200 43 extern "C" {
gmatarrubia 0:820a69dfd200 44 #endif
gmatarrubia 0:820a69dfd200 45
gmatarrubia 0:820a69dfd200 46 #ifndef __CORE_CA9_H_GENERIC
gmatarrubia 0:820a69dfd200 47 #define __CORE_CA9_H_GENERIC
gmatarrubia 0:820a69dfd200 48
gmatarrubia 0:820a69dfd200 49
gmatarrubia 0:820a69dfd200 50 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
gmatarrubia 0:820a69dfd200 51 CMSIS violates the following MISRA-C:2004 rules:
gmatarrubia 0:820a69dfd200 52
gmatarrubia 0:820a69dfd200 53 \li Required Rule 8.5, object/function definition in header file.<br>
gmatarrubia 0:820a69dfd200 54 Function definitions in header files are used to allow 'inlining'.
gmatarrubia 0:820a69dfd200 55
gmatarrubia 0:820a69dfd200 56 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
gmatarrubia 0:820a69dfd200 57 Unions are used for effective representation of core registers.
gmatarrubia 0:820a69dfd200 58
gmatarrubia 0:820a69dfd200 59 \li Advisory Rule 19.7, Function-like macro defined.<br>
gmatarrubia 0:820a69dfd200 60 Function-like macros are used to allow more efficient code.
gmatarrubia 0:820a69dfd200 61 */
gmatarrubia 0:820a69dfd200 62
gmatarrubia 0:820a69dfd200 63
gmatarrubia 0:820a69dfd200 64 /*******************************************************************************
gmatarrubia 0:820a69dfd200 65 * CMSIS definitions
gmatarrubia 0:820a69dfd200 66 ******************************************************************************/
gmatarrubia 0:820a69dfd200 67 /** \ingroup Cortex_A9
gmatarrubia 0:820a69dfd200 68 @{
gmatarrubia 0:820a69dfd200 69 */
gmatarrubia 0:820a69dfd200 70
gmatarrubia 0:820a69dfd200 71 /* CMSIS CA9 definitions */
gmatarrubia 0:820a69dfd200 72 #define __CA9_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
gmatarrubia 0:820a69dfd200 73 #define __CA9_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
gmatarrubia 0:820a69dfd200 74 #define __CA9_CMSIS_VERSION ((__CA9_CMSIS_VERSION_MAIN << 16) | \
gmatarrubia 0:820a69dfd200 75 __CA9_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
gmatarrubia 0:820a69dfd200 76
gmatarrubia 0:820a69dfd200 77 #define __CORTEX_A (0x09) /*!< Cortex-A Core */
gmatarrubia 0:820a69dfd200 78
gmatarrubia 0:820a69dfd200 79
gmatarrubia 0:820a69dfd200 80 #if defined ( __CC_ARM )
gmatarrubia 0:820a69dfd200 81 #define __ASM __asm /*!< asm keyword for ARM Compiler */
gmatarrubia 0:820a69dfd200 82 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
gmatarrubia 0:820a69dfd200 83 #define __STATIC_INLINE static __inline
gmatarrubia 0:820a69dfd200 84 #define __STATIC_ASM static __asm
gmatarrubia 0:820a69dfd200 85
gmatarrubia 0:820a69dfd200 86 #elif defined ( __ICCARM__ )
gmatarrubia 0:820a69dfd200 87 #define __ASM __asm /*!< asm keyword for IAR Compiler */
gmatarrubia 0:820a69dfd200 88 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
gmatarrubia 0:820a69dfd200 89 #define __STATIC_INLINE static inline
gmatarrubia 0:820a69dfd200 90 #define __STATIC_ASM static __asm
gmatarrubia 0:820a69dfd200 91
gmatarrubia 0:820a69dfd200 92 #elif defined ( __TMS470__ )
gmatarrubia 0:820a69dfd200 93 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
gmatarrubia 0:820a69dfd200 94 #define __STATIC_INLINE static inline
gmatarrubia 0:820a69dfd200 95 #define __STATIC_ASM static __asm
gmatarrubia 0:820a69dfd200 96
gmatarrubia 0:820a69dfd200 97 #elif defined ( __GNUC__ )
gmatarrubia 0:820a69dfd200 98 #define __ASM __asm /*!< asm keyword for GNU Compiler */
gmatarrubia 0:820a69dfd200 99 #define __INLINE inline /*!< inline keyword for GNU Compiler */
gmatarrubia 0:820a69dfd200 100 #define __STATIC_INLINE static inline
gmatarrubia 0:820a69dfd200 101 #define __STATIC_ASM static __asm
gmatarrubia 0:820a69dfd200 102
gmatarrubia 0:820a69dfd200 103 #elif defined ( __TASKING__ )
gmatarrubia 0:820a69dfd200 104 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
gmatarrubia 0:820a69dfd200 105 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
gmatarrubia 0:820a69dfd200 106 #define __STATIC_INLINE static inline
gmatarrubia 0:820a69dfd200 107 #define __STATIC_ASM static __asm
gmatarrubia 0:820a69dfd200 108
gmatarrubia 0:820a69dfd200 109 #endif
gmatarrubia 0:820a69dfd200 110
gmatarrubia 0:820a69dfd200 111 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
gmatarrubia 0:820a69dfd200 112 */
gmatarrubia 0:820a69dfd200 113 #if defined ( __CC_ARM )
gmatarrubia 0:820a69dfd200 114 #if defined __TARGET_FPU_VFP
gmatarrubia 0:820a69dfd200 115 #if (__FPU_PRESENT == 1)
gmatarrubia 0:820a69dfd200 116 #define __FPU_USED 1
gmatarrubia 0:820a69dfd200 117 #else
gmatarrubia 0:820a69dfd200 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
gmatarrubia 0:820a69dfd200 119 #define __FPU_USED 0
gmatarrubia 0:820a69dfd200 120 #endif
gmatarrubia 0:820a69dfd200 121 #else
gmatarrubia 0:820a69dfd200 122 #define __FPU_USED 0
gmatarrubia 0:820a69dfd200 123 #endif
gmatarrubia 0:820a69dfd200 124
gmatarrubia 0:820a69dfd200 125 #elif defined ( __ICCARM__ )
gmatarrubia 0:820a69dfd200 126 #if defined __ARMVFP__
gmatarrubia 0:820a69dfd200 127 #if (__FPU_PRESENT == 1)
gmatarrubia 0:820a69dfd200 128 #define __FPU_USED 1
gmatarrubia 0:820a69dfd200 129 #else
gmatarrubia 0:820a69dfd200 130 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
gmatarrubia 0:820a69dfd200 131 #define __FPU_USED 0
gmatarrubia 0:820a69dfd200 132 #endif
gmatarrubia 0:820a69dfd200 133 #else
gmatarrubia 0:820a69dfd200 134 #define __FPU_USED 0
gmatarrubia 0:820a69dfd200 135 #endif
gmatarrubia 0:820a69dfd200 136
gmatarrubia 0:820a69dfd200 137 #elif defined ( __TMS470__ )
gmatarrubia 0:820a69dfd200 138 #if defined __TI_VFP_SUPPORT__
gmatarrubia 0:820a69dfd200 139 #if (__FPU_PRESENT == 1)
gmatarrubia 0:820a69dfd200 140 #define __FPU_USED 1
gmatarrubia 0:820a69dfd200 141 #else
gmatarrubia 0:820a69dfd200 142 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
gmatarrubia 0:820a69dfd200 143 #define __FPU_USED 0
gmatarrubia 0:820a69dfd200 144 #endif
gmatarrubia 0:820a69dfd200 145 #else
gmatarrubia 0:820a69dfd200 146 #define __FPU_USED 0
gmatarrubia 0:820a69dfd200 147 #endif
gmatarrubia 0:820a69dfd200 148
gmatarrubia 0:820a69dfd200 149 #elif defined ( __GNUC__ )
gmatarrubia 0:820a69dfd200 150 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
gmatarrubia 0:820a69dfd200 151 #if (__FPU_PRESENT == 1)
gmatarrubia 0:820a69dfd200 152 #define __FPU_USED 1
gmatarrubia 0:820a69dfd200 153 #else
gmatarrubia 0:820a69dfd200 154 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
gmatarrubia 0:820a69dfd200 155 #define __FPU_USED 0
gmatarrubia 0:820a69dfd200 156 #endif
gmatarrubia 0:820a69dfd200 157 #else
gmatarrubia 0:820a69dfd200 158 #define __FPU_USED 0
gmatarrubia 0:820a69dfd200 159 #endif
gmatarrubia 0:820a69dfd200 160
gmatarrubia 0:820a69dfd200 161 #elif defined ( __TASKING__ )
gmatarrubia 0:820a69dfd200 162 #if defined __FPU_VFP__
gmatarrubia 0:820a69dfd200 163 #if (__FPU_PRESENT == 1)
gmatarrubia 0:820a69dfd200 164 #define __FPU_USED 1
gmatarrubia 0:820a69dfd200 165 #else
gmatarrubia 0:820a69dfd200 166 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
gmatarrubia 0:820a69dfd200 167 #define __FPU_USED 0
gmatarrubia 0:820a69dfd200 168 #endif
gmatarrubia 0:820a69dfd200 169 #else
gmatarrubia 0:820a69dfd200 170 #define __FPU_USED 0
gmatarrubia 0:820a69dfd200 171 #endif
gmatarrubia 0:820a69dfd200 172 #endif
gmatarrubia 0:820a69dfd200 173
gmatarrubia 0:820a69dfd200 174 #include <stdint.h> /*!< standard types definitions */
gmatarrubia 0:820a69dfd200 175 #include "core_caInstr.h" /*!< Core Instruction Access */
gmatarrubia 0:820a69dfd200 176 #include "core_caFunc.h" /*!< Core Function Access */
gmatarrubia 0:820a69dfd200 177 #include "core_cm4_simd.h" /*!< Compiler specific SIMD Intrinsics */
gmatarrubia 0:820a69dfd200 178
gmatarrubia 0:820a69dfd200 179 #endif /* __CORE_CA9_H_GENERIC */
gmatarrubia 0:820a69dfd200 180
gmatarrubia 0:820a69dfd200 181 #ifndef __CMSIS_GENERIC
gmatarrubia 0:820a69dfd200 182
gmatarrubia 0:820a69dfd200 183 #ifndef __CORE_CA9_H_DEPENDANT
gmatarrubia 0:820a69dfd200 184 #define __CORE_CA9_H_DEPENDANT
gmatarrubia 0:820a69dfd200 185
gmatarrubia 0:820a69dfd200 186 /* check device defines and use defaults */
gmatarrubia 0:820a69dfd200 187 #if defined __CHECK_DEVICE_DEFINES
gmatarrubia 0:820a69dfd200 188 #ifndef __CA9_REV
gmatarrubia 0:820a69dfd200 189 #define __CA9_REV 0x0000
gmatarrubia 0:820a69dfd200 190 #warning "__CA9_REV not defined in device header file; using default!"
gmatarrubia 0:820a69dfd200 191 #endif
gmatarrubia 0:820a69dfd200 192
gmatarrubia 0:820a69dfd200 193 #ifndef __FPU_PRESENT
gmatarrubia 0:820a69dfd200 194 #define __FPU_PRESENT 1
gmatarrubia 0:820a69dfd200 195 #warning "__FPU_PRESENT not defined in device header file; using default!"
gmatarrubia 0:820a69dfd200 196 #endif
gmatarrubia 0:820a69dfd200 197
gmatarrubia 0:820a69dfd200 198 #ifndef __Vendor_SysTickConfig
gmatarrubia 0:820a69dfd200 199 #define __Vendor_SysTickConfig 1
gmatarrubia 0:820a69dfd200 200 #endif
gmatarrubia 0:820a69dfd200 201
gmatarrubia 0:820a69dfd200 202 #if __Vendor_SysTickConfig == 0
gmatarrubia 0:820a69dfd200 203 #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
gmatarrubia 0:820a69dfd200 204 #endif
gmatarrubia 0:820a69dfd200 205 #endif
gmatarrubia 0:820a69dfd200 206
gmatarrubia 0:820a69dfd200 207 /* IO definitions (access restrictions to peripheral registers) */
gmatarrubia 0:820a69dfd200 208 /**
gmatarrubia 0:820a69dfd200 209 \defgroup CMSIS_glob_defs CMSIS Global Defines
gmatarrubia 0:820a69dfd200 210
gmatarrubia 0:820a69dfd200 211 <strong>IO Type Qualifiers</strong> are used
gmatarrubia 0:820a69dfd200 212 \li to specify the access to peripheral variables.
gmatarrubia 0:820a69dfd200 213 \li for automatic generation of peripheral register debug information.
gmatarrubia 0:820a69dfd200 214 */
gmatarrubia 0:820a69dfd200 215 #ifdef __cplusplus
gmatarrubia 0:820a69dfd200 216 #define __I volatile /*!< Defines 'read only' permissions */
gmatarrubia 0:820a69dfd200 217 #else
gmatarrubia 0:820a69dfd200 218 #define __I volatile const /*!< Defines 'read only' permissions */
gmatarrubia 0:820a69dfd200 219 #endif
gmatarrubia 0:820a69dfd200 220 #define __O volatile /*!< Defines 'write only' permissions */
gmatarrubia 0:820a69dfd200 221 #define __IO volatile /*!< Defines 'read / write' permissions */
gmatarrubia 0:820a69dfd200 222
gmatarrubia 0:820a69dfd200 223 /*@} end of group Cortex_A9 */
gmatarrubia 0:820a69dfd200 224
gmatarrubia 0:820a69dfd200 225
gmatarrubia 0:820a69dfd200 226 /*******************************************************************************
gmatarrubia 0:820a69dfd200 227 * Register Abstraction
gmatarrubia 0:820a69dfd200 228 ******************************************************************************/
gmatarrubia 0:820a69dfd200 229 /** \defgroup CMSIS_core_register Defines and Type Definitions
gmatarrubia 0:820a69dfd200 230 \brief Type definitions and defines for Cortex-A processor based devices.
gmatarrubia 0:820a69dfd200 231 */
gmatarrubia 0:820a69dfd200 232
gmatarrubia 0:820a69dfd200 233 /** \ingroup CMSIS_core_register
gmatarrubia 0:820a69dfd200 234 \defgroup CMSIS_CORE Status and Control Registers
gmatarrubia 0:820a69dfd200 235 \brief Core Register type definitions.
gmatarrubia 0:820a69dfd200 236 @{
gmatarrubia 0:820a69dfd200 237 */
gmatarrubia 0:820a69dfd200 238
gmatarrubia 0:820a69dfd200 239 /** \brief Union type to access the Application Program Status Register (APSR).
gmatarrubia 0:820a69dfd200 240 */
gmatarrubia 0:820a69dfd200 241 typedef union
gmatarrubia 0:820a69dfd200 242 {
gmatarrubia 0:820a69dfd200 243 struct
gmatarrubia 0:820a69dfd200 244 {
gmatarrubia 0:820a69dfd200 245 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
gmatarrubia 0:820a69dfd200 246 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
gmatarrubia 0:820a69dfd200 247 uint32_t reserved1:7; /*!< bit: 20..23 Reserved */
gmatarrubia 0:820a69dfd200 248 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
gmatarrubia 0:820a69dfd200 249 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
gmatarrubia 0:820a69dfd200 250 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
gmatarrubia 0:820a69dfd200 251 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
gmatarrubia 0:820a69dfd200 252 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
gmatarrubia 0:820a69dfd200 253 } b; /*!< Structure used for bit access */
gmatarrubia 0:820a69dfd200 254 uint32_t w; /*!< Type used for word access */
gmatarrubia 0:820a69dfd200 255 } APSR_Type;
gmatarrubia 0:820a69dfd200 256
gmatarrubia 0:820a69dfd200 257
gmatarrubia 0:820a69dfd200 258 /*@} end of group CMSIS_CORE */
gmatarrubia 0:820a69dfd200 259
gmatarrubia 0:820a69dfd200 260 /*@} end of CMSIS_Core_FPUFunctions */
gmatarrubia 0:820a69dfd200 261
gmatarrubia 0:820a69dfd200 262
gmatarrubia 0:820a69dfd200 263 #endif /* __CORE_CA9_H_GENERIC */
gmatarrubia 0:820a69dfd200 264
gmatarrubia 0:820a69dfd200 265 #endif /* __CMSIS_GENERIC */
gmatarrubia 0:820a69dfd200 266
gmatarrubia 0:820a69dfd200 267 #ifdef __cplusplus
gmatarrubia 0:820a69dfd200 268 }
gmatarrubia 0:820a69dfd200 269
gmatarrubia 0:820a69dfd200 270
gmatarrubia 0:820a69dfd200 271 #endif