Mbed LPC1549 mod - This repo contains the libraries of Mbed for LPC1…

Users » Gmatarrubia » Code » Mbed LPC1549 mod

This repo contains the libraries of Mbed for LPC1549 with following changes: - IAP commands. - EEPROM write and read. - UART write and read (public) - CAN can_s -> LPC_C_CAN0_Type *can

mbed/TARGET_LPC1549/LPC15xx.h@0:820a69dfd200, 2015-04-14 (annotated)

Committer:: gmatarrubia
Date:: Tue Apr 14 15:00:13 2015 +0200
Revision:: 0:820a69dfd200

Initial repo. IAP commands, EEPROM write/read, UART write/read, CAN

Who changed what in which revision?

User	Revision	Line number	New contents of line
gmatarrubia	0:820a69dfd200	1
gmatarrubia	0:820a69dfd200	2	/**************************************************************************************************//
gmatarrubia	0:820a69dfd200	3	* @file LPC15xx.h
gmatarrubia	0:820a69dfd200	4	*
gmatarrubia	0:820a69dfd200	5	* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File for
gmatarrubia	0:820a69dfd200	6	* LPC15xx from .
gmatarrubia	0:820a69dfd200	7	*
gmatarrubia	0:820a69dfd200	8	* @version V0.3
gmatarrubia	0:820a69dfd200	9	* @date 17. July 2013
gmatarrubia	0:820a69dfd200	10	*
gmatarrubia	0:820a69dfd200	11	* @note Generated with SVDConv V2.80
gmatarrubia	0:820a69dfd200	12	* from CMSIS SVD File 'H2_v0.3.svd' Version 0.3,
gmatarrubia	0:820a69dfd200	13	*
gmatarrubia	0:820a69dfd200	14	* modified by Keil
gmatarrubia	0:820a69dfd200	15	* modified by ytsuboi
gmatarrubia	0:820a69dfd200	16	*******************************************************************************************************/
gmatarrubia	0:820a69dfd200	17
gmatarrubia	0:820a69dfd200	18
gmatarrubia	0:820a69dfd200	19
gmatarrubia	0:820a69dfd200	20	/** @addtogroup (null)
gmatarrubia	0:820a69dfd200	21	* @{
gmatarrubia	0:820a69dfd200	22	*/
gmatarrubia	0:820a69dfd200	23
gmatarrubia	0:820a69dfd200	24	/** @addtogroup LPC15xx
gmatarrubia	0:820a69dfd200	25	* @{
gmatarrubia	0:820a69dfd200	26	*/
gmatarrubia	0:820a69dfd200	27
gmatarrubia	0:820a69dfd200	28	#ifndef LPC15XX_H
gmatarrubia	0:820a69dfd200	29	#define LPC15XX_H
gmatarrubia	0:820a69dfd200	30
gmatarrubia	0:820a69dfd200	31	#ifdef __cplusplus
gmatarrubia	0:820a69dfd200	32	extern "C" {
gmatarrubia	0:820a69dfd200	33	#endif
gmatarrubia	0:820a69dfd200	34
gmatarrubia	0:820a69dfd200	35
gmatarrubia	0:820a69dfd200	36	/* ------------------------- Interrupt Number Definition ------------------------ */
gmatarrubia	0:820a69dfd200	37
gmatarrubia	0:820a69dfd200	38	typedef enum {
gmatarrubia	0:820a69dfd200	39	/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
gmatarrubia	0:820a69dfd200	40	Reset_IRQn = -15, /!< 1 Reset Vector, invoked on Power up and warm reset /
gmatarrubia	0:820a69dfd200	41	NonMaskableInt_IRQn = -14, /!< 2 Non maskable Interrupt, cannot be stopped or preempted /
gmatarrubia	0:820a69dfd200	42	HardFault_IRQn = -13, /!< 3 Hard Fault, all classes of Fault /
gmatarrubia	0:820a69dfd200	43	MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation
gmatarrubia	0:820a69dfd200	44	and No Match */
gmatarrubia	0:820a69dfd200	45	BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
gmatarrubia	0:820a69dfd200	46	related Fault */
gmatarrubia	0:820a69dfd200	47	UsageFault_IRQn = -10, /!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition /
gmatarrubia	0:820a69dfd200	48	SVCall_IRQn = -5, /!< 11 System Service Call via SVC instruction /
gmatarrubia	0:820a69dfd200	49	DebugMonitor_IRQn = -4, /!< 12 Debug Monitor /
gmatarrubia	0:820a69dfd200	50	PendSV_IRQn = -2, /!< 14 Pendable request for system service /
gmatarrubia	0:820a69dfd200	51	SysTick_IRQn = -1, /!< 15 System Tick Timer /
gmatarrubia	0:820a69dfd200	52	/* --------------------- LPC15xx Specific Interrupt Numbers --------------------- */
gmatarrubia	0:820a69dfd200	53	WDT_IRQn = 0, /!< 0 WDT /
gmatarrubia	0:820a69dfd200	54	BOD_IRQn = 1, /!< 1 BOD /
gmatarrubia	0:820a69dfd200	55	FLASH_IRQn = 2, /!< 2 FLASH /
gmatarrubia	0:820a69dfd200	56	EE_IRQn = 3, /!< 3 EE /
gmatarrubia	0:820a69dfd200	57	DMA_IRQn = 4, /!< 4 DMA /
gmatarrubia	0:820a69dfd200	58	GINT0_IRQn = 5, /!< 5 GINT0 /
gmatarrubia	0:820a69dfd200	59	GINT1_IRQn = 6, /!< 6 GINT1 /
gmatarrubia	0:820a69dfd200	60	PIN_INT0_IRQn = 7, /!< 7 PIN_INT0 /
gmatarrubia	0:820a69dfd200	61	PIN_INT1_IRQn = 8, /!< 8 PIN_INT1 /
gmatarrubia	0:820a69dfd200	62	PIN_INT2_IRQn = 9, /!< 9 PIN_INT2 /
gmatarrubia	0:820a69dfd200	63	PIN_INT3_IRQn = 10, /!< 10 PIN_INT3 /
gmatarrubia	0:820a69dfd200	64	PIN_INT4_IRQn = 11, /!< 11 PIN_INT4 /
gmatarrubia	0:820a69dfd200	65	PIN_INT5_IRQn = 12, /!< 12 PIN_INT5 /
gmatarrubia	0:820a69dfd200	66	PIN_INT6_IRQn = 13, /!< 13 PIN_INT6 /
gmatarrubia	0:820a69dfd200	67	PIN_INT7_IRQn = 14, /!< 14 PIN_INT7 /
gmatarrubia	0:820a69dfd200	68	RIT_IRQn = 15, /!< 15 RIT /
gmatarrubia	0:820a69dfd200	69	SCT0_IRQn = 16, /!< 16 SCT0 /
gmatarrubia	0:820a69dfd200	70	SCT1_IRQn = 17, /!< 17 SCT1 /
gmatarrubia	0:820a69dfd200	71	SCT2_IRQn = 18, /!< 18 SCT2 /
gmatarrubia	0:820a69dfd200	72	SCT3_IRQn = 19, /!< 19 SCT3 /
gmatarrubia	0:820a69dfd200	73	MRT_IRQn = 20, /!< 20 MRT /
gmatarrubia	0:820a69dfd200	74	UART0_IRQn = 21, /!< 21 UART0 /
gmatarrubia	0:820a69dfd200	75	UART1_IRQn = 22, /!< 22 UART1 /
gmatarrubia	0:820a69dfd200	76	UART2_IRQn = 23, /!< 23 UART2 /
gmatarrubia	0:820a69dfd200	77	I2C0_IRQn = 24, /!< 24 I2C0 /
gmatarrubia	0:820a69dfd200	78	SPI0_IRQn = 25, /!< 25 SPI0 /
gmatarrubia	0:820a69dfd200	79	SPI1_IRQn = 26, /!< 26 SPI1 /
gmatarrubia	0:820a69dfd200	80	C_CAN0_IRQn = 27, /!< 27 C_CAN0 /
gmatarrubia	0:820a69dfd200	81	USB_IRQ_IRQn = 28, /!< 28 USB_IRQ /
gmatarrubia	0:820a69dfd200	82	USB_FIQ_IRQn = 29, /!< 29 USB_FIQ /
gmatarrubia	0:820a69dfd200	83	USBWAKEUP_IRQn = 30, /!< 30 USBWAKEUP /
gmatarrubia	0:820a69dfd200	84	ADC0_SEQA_IRQn = 31, /!< 31 ADC0_SEQA /
gmatarrubia	0:820a69dfd200	85	ADC0_SEQB_IRQn = 32, /!< 32 ADC0_SEQB /
gmatarrubia	0:820a69dfd200	86	ADC0_THCMP_IRQn = 33, /!< 33 ADC0_THCMP /
gmatarrubia	0:820a69dfd200	87	ADC0_OVR_IRQn = 34, /!< 34 ADC0_OVR /
gmatarrubia	0:820a69dfd200	88	ADC1_SEQA_IRQn = 35, /!< 35 ADC1_SEQA /
gmatarrubia	0:820a69dfd200	89	ADC1_SEQB_IRQn = 36, /!< 36 ADC1_SEQB /
gmatarrubia	0:820a69dfd200	90	ADC1_THCMP_IRQn = 37, /!< 37 ADC1_THCMP /
gmatarrubia	0:820a69dfd200	91	ADC1_OVR_IRQn = 38, /!< 38 ADC1_OVR /
gmatarrubia	0:820a69dfd200	92	DAC_IRQn = 39, /!< 39 DAC /
gmatarrubia	0:820a69dfd200	93	CMP0_IRQn = 40, /!< 40 CMP0 /
gmatarrubia	0:820a69dfd200	94	CMP1_IRQn = 41, /!< 41 CMP1 /
gmatarrubia	0:820a69dfd200	95	CMP2_IRQn = 42, /!< 42 CMP2 /
gmatarrubia	0:820a69dfd200	96	CMP3_IRQn = 43, /!< 43 CMP3 /
gmatarrubia	0:820a69dfd200	97	QEI_IRQn = 44, /!< 44 QEI /
gmatarrubia	0:820a69dfd200	98	RTC_ALARM_IRQn = 45, /!< 45 RTC_ALARM /
gmatarrubia	0:820a69dfd200	99	RTC_WAKE_IRQn = 46 /!< 46 RTC_WAKE /
gmatarrubia	0:820a69dfd200	100	} IRQn_Type;
gmatarrubia	0:820a69dfd200	101
gmatarrubia	0:820a69dfd200	102
gmatarrubia	0:820a69dfd200	103	/** @addtogroup Configuration_of_CMSIS
gmatarrubia	0:820a69dfd200	104	* @{
gmatarrubia	0:820a69dfd200	105	*/
gmatarrubia	0:820a69dfd200	106
gmatarrubia	0:820a69dfd200	107
gmatarrubia	0:820a69dfd200	108	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	109	/* ================ Processor and Core Peripheral Section ================ */
gmatarrubia	0:820a69dfd200	110	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	111
gmatarrubia	0:820a69dfd200	112	/* ----------------Configuration of the Cortex-M3 Processor and Core Peripherals---------------- */
gmatarrubia	0:820a69dfd200	113	#define __CM3_REV 0x0201 /!< Cortex-M3 Core Revision /
gmatarrubia	0:820a69dfd200	114	#define __MPU_PRESENT 0 /!< MPU present or not /
gmatarrubia	0:820a69dfd200	115	#define __NVIC_PRIO_BITS 3 /!< Number of Bits used for Priority Levels /
gmatarrubia	0:820a69dfd200	116	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
gmatarrubia	0:820a69dfd200	117	/** @} / / End of group Configuration_of_CMSIS */
gmatarrubia	0:820a69dfd200	118
gmatarrubia	0:820a69dfd200	119	#include "core_cm3.h" /!< Cortex-M3 processor and core peripherals /
gmatarrubia	0:820a69dfd200	120	#include "system_LPC15xx.h" /!< LPC15xx System /
gmatarrubia	0:820a69dfd200	121
gmatarrubia	0:820a69dfd200	122
gmatarrubia	0:820a69dfd200	123	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	124	/* ================ Device Specific Peripheral Section ================ */
gmatarrubia	0:820a69dfd200	125	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	126
gmatarrubia	0:820a69dfd200	127
gmatarrubia	0:820a69dfd200	128	/** @addtogroup Device_Peripheral_Registers
gmatarrubia	0:820a69dfd200	129	* @{
gmatarrubia	0:820a69dfd200	130	*/
gmatarrubia	0:820a69dfd200	131
gmatarrubia	0:820a69dfd200	132
gmatarrubia	0:820a69dfd200	133	/* ------------------- Start of section using anonymous unions ------------------ */
gmatarrubia	0:820a69dfd200	134	#if defined(__CC_ARM)
gmatarrubia	0:820a69dfd200	135	#pragma push
gmatarrubia	0:820a69dfd200	136	#pragma anon_unions
gmatarrubia	0:820a69dfd200	137	#elif defined(__ICCARM__)
gmatarrubia	0:820a69dfd200	138	#pragma language=extended
gmatarrubia	0:820a69dfd200	139	#elif defined(__GNUC__)
gmatarrubia	0:820a69dfd200	140	/* anonymous unions are enabled by default */
gmatarrubia	0:820a69dfd200	141	#elif defined(__TMS470__)
gmatarrubia	0:820a69dfd200	142	/* anonymous unions are enabled by default */
gmatarrubia	0:820a69dfd200	143	#elif defined(__TASKING__)
gmatarrubia	0:820a69dfd200	144	#pragma warning 586
gmatarrubia	0:820a69dfd200	145	#else
gmatarrubia	0:820a69dfd200	146	#warning Not supported compiler type
gmatarrubia	0:820a69dfd200	147	#endif
gmatarrubia	0:820a69dfd200	148
gmatarrubia	0:820a69dfd200	149
gmatarrubia	0:820a69dfd200	150
gmatarrubia	0:820a69dfd200	151	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	152	/* ================ GPIO_PORT ================ */
gmatarrubia	0:820a69dfd200	153	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	154
gmatarrubia	0:820a69dfd200	155
gmatarrubia	0:820a69dfd200	156	/**
gmatarrubia	0:820a69dfd200	157	* @brief General Purpose I/O (GPIO) (GPIO_PORT)
gmatarrubia	0:820a69dfd200	158	*/
gmatarrubia	0:820a69dfd200	159
gmatarrubia	0:820a69dfd200	160	typedef struct { /!< GPIO_PORT Structure /
gmatarrubia	0:820a69dfd200	161	__IO uint8_t B[76]; /!< Byte pin registers /
gmatarrubia	0:820a69dfd200	162	__I uint32_t RESERVED0[45];
gmatarrubia	0:820a69dfd200	163	__IO uint32_t W[76]; /!< Word pin registers /
gmatarrubia	0:820a69dfd200	164	__I uint32_t RESERVED1[1908];
gmatarrubia	0:820a69dfd200	165	__IO uint32_t DIR[3]; /!< Port Direction registers /
gmatarrubia	0:820a69dfd200	166	__I uint32_t RESERVED2[29];
gmatarrubia	0:820a69dfd200	167	__IO uint32_t MASK[3]; /!< Port Mask register /
gmatarrubia	0:820a69dfd200	168	__I uint32_t RESERVED3[29];
gmatarrubia	0:820a69dfd200	169	__IO uint32_t PIN[3]; /!< Port pin register /
gmatarrubia	0:820a69dfd200	170	__I uint32_t RESERVED4[29];
gmatarrubia	0:820a69dfd200	171	__IO uint32_t MPIN[3]; /!< Masked port register /
gmatarrubia	0:820a69dfd200	172	__I uint32_t RESERVED5[29];
gmatarrubia	0:820a69dfd200	173	__IO uint32_t SET[3]; /!< Write: Set port register Read: port output bits /
gmatarrubia	0:820a69dfd200	174	__I uint32_t RESERVED6[29];
gmatarrubia	0:820a69dfd200	175	__O uint32_t CLR[3]; /!< Clear port /
gmatarrubia	0:820a69dfd200	176	__I uint32_t RESERVED7[29];
gmatarrubia	0:820a69dfd200	177	__O uint32_t NOT[3]; /!< Toggle port /
gmatarrubia	0:820a69dfd200	178	} LPC_GPIO_PORT_Type;
gmatarrubia	0:820a69dfd200	179
gmatarrubia	0:820a69dfd200	180
gmatarrubia	0:820a69dfd200	181	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	182	/* ================ DMA ================ */
gmatarrubia	0:820a69dfd200	183	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	184
gmatarrubia	0:820a69dfd200	185
gmatarrubia	0:820a69dfd200	186	/**
gmatarrubia	0:820a69dfd200	187	* @brief DMA controller (DMA)
gmatarrubia	0:820a69dfd200	188	*/
gmatarrubia	0:820a69dfd200	189
gmatarrubia	0:820a69dfd200	190	typedef struct { /!< DMA Structure /
gmatarrubia	0:820a69dfd200	191	__IO uint32_t CTRL; /!< DMA control. /
gmatarrubia	0:820a69dfd200	192	__I uint32_t INTSTAT; /!< Interrupt status. /
gmatarrubia	0:820a69dfd200	193	__IO uint32_t SRAMBASE; /!< SRAM address of the channel configuration table. /
gmatarrubia	0:820a69dfd200	194	__I uint32_t RESERVED0[5];
gmatarrubia	0:820a69dfd200	195	__IO uint32_t ENABLESET0; /!< Channel Enable read and Set for all DMA channels. /
gmatarrubia	0:820a69dfd200	196	__I uint32_t RESERVED1;
gmatarrubia	0:820a69dfd200	197	__O uint32_t ENABLECLR0; /!< Channel Enable Clear for all DMA channels. /
gmatarrubia	0:820a69dfd200	198	__I uint32_t RESERVED2;
gmatarrubia	0:820a69dfd200	199	__I uint32_t ACTIVE0; /!< Channel Active status for all DMA channels. /
gmatarrubia	0:820a69dfd200	200	__I uint32_t RESERVED3;
gmatarrubia	0:820a69dfd200	201	__I uint32_t BUSY0; /!< Channel Busy status for all DMA channels. /
gmatarrubia	0:820a69dfd200	202	__I uint32_t RESERVED4;
gmatarrubia	0:820a69dfd200	203	__IO uint32_t ERRINT0; /!< Error Interrupt status for all DMA channels. /
gmatarrubia	0:820a69dfd200	204	__I uint32_t RESERVED5;
gmatarrubia	0:820a69dfd200	205	__IO uint32_t INTENSET0; /!< Interrupt Enable read and Set for all DMA channels. /
gmatarrubia	0:820a69dfd200	206	__I uint32_t RESERVED6;
gmatarrubia	0:820a69dfd200	207	__O uint32_t INTENCLR0; /!< Interrupt Enable Clear for all DMA channels. /
gmatarrubia	0:820a69dfd200	208	__I uint32_t RESERVED7;
gmatarrubia	0:820a69dfd200	209	__IO uint32_t INTA0; /!< Interrupt A status for all DMA channels. /
gmatarrubia	0:820a69dfd200	210	__I uint32_t RESERVED8;
gmatarrubia	0:820a69dfd200	211	__IO uint32_t INTB0; /!< Interrupt B status for all DMA channels. /
gmatarrubia	0:820a69dfd200	212	__I uint32_t RESERVED9;
gmatarrubia	0:820a69dfd200	213	__O uint32_t SETVALID0; /!< Set ValidPending control bits for all DMA channels. /
gmatarrubia	0:820a69dfd200	214	__I uint32_t RESERVED10;
gmatarrubia	0:820a69dfd200	215	__O uint32_t SETTRIG0; /!< Set Trigger control bits for all DMA channels. /
gmatarrubia	0:820a69dfd200	216	__I uint32_t RESERVED11;
gmatarrubia	0:820a69dfd200	217	__O uint32_t ABORT0; /!< Channel Abort control for all DMA channels. /
gmatarrubia	0:820a69dfd200	218	__I uint32_t RESERVED12[225];
gmatarrubia	0:820a69dfd200	219	__IO uint32_t CFG0; /!< Configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	220	__I uint32_t CTLSTAT0; /!< Control and status register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	221	__IO uint32_t XFERCFG0; /!< Transfer configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	222	__I uint32_t RESERVED13;
gmatarrubia	0:820a69dfd200	223	__IO uint32_t CFG1; /!< Configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	224	__I uint32_t CTLSTAT1; /!< Control and status register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	225	__IO uint32_t XFERCFG1; /!< Transfer configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	226	__I uint32_t RESERVED14;
gmatarrubia	0:820a69dfd200	227	__IO uint32_t CFG2; /!< Configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	228	__I uint32_t CTLSTAT2; /!< Control and status register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	229	__IO uint32_t XFERCFG2; /!< Transfer configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	230	__I uint32_t RESERVED15;
gmatarrubia	0:820a69dfd200	231	__IO uint32_t CFG3; /!< Configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	232	__I uint32_t CTLSTAT3; /!< Control and status register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	233	__IO uint32_t XFERCFG3; /!< Transfer configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	234	__I uint32_t RESERVED16;
gmatarrubia	0:820a69dfd200	235	__IO uint32_t CFG4; /!< Configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	236	__I uint32_t CTLSTAT4; /!< Control and status register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	237	__IO uint32_t XFERCFG4; /!< Transfer configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	238	__I uint32_t RESERVED17;
gmatarrubia	0:820a69dfd200	239	__IO uint32_t CFG5; /!< Configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	240	__I uint32_t CTLSTAT5; /!< Control and status register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	241	__IO uint32_t XFERCFG5; /!< Transfer configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	242	__I uint32_t RESERVED18;
gmatarrubia	0:820a69dfd200	243	__IO uint32_t CFG6; /!< Configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	244	__I uint32_t CTLSTAT6; /!< Control and status register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	245	__IO uint32_t XFERCFG6; /!< Transfer configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	246	__I uint32_t RESERVED19;
gmatarrubia	0:820a69dfd200	247	__IO uint32_t CFG7; /!< Configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	248	__I uint32_t CTLSTAT7; /!< Control and status register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	249	__IO uint32_t XFERCFG7; /!< Transfer configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	250	__I uint32_t RESERVED20;
gmatarrubia	0:820a69dfd200	251	__IO uint32_t CFG8; /!< Configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	252	__I uint32_t CTLSTAT8; /!< Control and status register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	253	__IO uint32_t XFERCFG8; /!< Transfer configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	254	__I uint32_t RESERVED21;
gmatarrubia	0:820a69dfd200	255	__IO uint32_t CFG9; /!< Configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	256	__I uint32_t CTLSTAT9; /!< Control and status register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	257	__IO uint32_t XFERCFG9; /!< Transfer configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	258	__I uint32_t RESERVED22;
gmatarrubia	0:820a69dfd200	259	__IO uint32_t CFG10; /!< Configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	260	__I uint32_t CTLSTAT10; /!< Control and status register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	261	__IO uint32_t XFERCFG10; /!< Transfer configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	262	__I uint32_t RESERVED23;
gmatarrubia	0:820a69dfd200	263	__IO uint32_t CFG11; /!< Configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	264	__I uint32_t CTLSTAT11; /!< Control and status register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	265	__IO uint32_t XFERCFG11; /!< Transfer configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	266	__I uint32_t RESERVED24;
gmatarrubia	0:820a69dfd200	267	__IO uint32_t CFG12; /!< Configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	268	__I uint32_t CTLSTAT12; /!< Control and status register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	269	__IO uint32_t XFERCFG12; /!< Transfer configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	270	__I uint32_t RESERVED25;
gmatarrubia	0:820a69dfd200	271	__IO uint32_t CFG13; /!< Configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	272	__I uint32_t CTLSTAT13; /!< Control and status register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	273	__IO uint32_t XFERCFG13; /!< Transfer configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	274	__I uint32_t RESERVED26;
gmatarrubia	0:820a69dfd200	275	__IO uint32_t CFG14; /!< Configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	276	__I uint32_t CTLSTAT14; /!< Control and status register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	277	__IO uint32_t XFERCFG14; /!< Transfer configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	278	__I uint32_t RESERVED27;
gmatarrubia	0:820a69dfd200	279	__IO uint32_t CFG15; /!< Configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	280	__I uint32_t CTLSTAT15; /!< Control and status register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	281	__IO uint32_t XFERCFG15; /!< Transfer configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	282	__I uint32_t RESERVED28;
gmatarrubia	0:820a69dfd200	283	__IO uint32_t CFG16; /!< Configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	284	__I uint32_t CTLSTAT16; /!< Control and status register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	285	__IO uint32_t XFERCFG16; /!< Transfer configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	286	__I uint32_t RESERVED29;
gmatarrubia	0:820a69dfd200	287	__IO uint32_t CFG17; /!< Configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	288	__I uint32_t CTLSTAT17; /!< Control and status register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	289	__IO uint32_t XFERCFG17; /!< Transfer configuration register for DMA channel 0. /
gmatarrubia	0:820a69dfd200	290	} LPC_DMA_Type;
gmatarrubia	0:820a69dfd200	291
gmatarrubia	0:820a69dfd200	292
gmatarrubia	0:820a69dfd200	293	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	294	/* ================ USB ================ */
gmatarrubia	0:820a69dfd200	295	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	296
gmatarrubia	0:820a69dfd200	297
gmatarrubia	0:820a69dfd200	298	/**
gmatarrubia	0:820a69dfd200	299	* @brief USB device controller (USB)
gmatarrubia	0:820a69dfd200	300	*/
gmatarrubia	0:820a69dfd200	301
gmatarrubia	0:820a69dfd200	302	typedef struct { /!< USB Structure /
gmatarrubia	0:820a69dfd200	303	__IO uint32_t DEVCMDSTAT; /!< USB Device Command/Status register /
gmatarrubia	0:820a69dfd200	304	__IO uint32_t INFO; /!< USB Info register /
gmatarrubia	0:820a69dfd200	305	__IO uint32_t EPLISTSTART; /!< USB EP Command/Status List start address /
gmatarrubia	0:820a69dfd200	306	__IO uint32_t DATABUFSTART; /!< USB Data buffer start address /
gmatarrubia	0:820a69dfd200	307	__IO uint32_t LPM; /!< Link Power Management register /
gmatarrubia	0:820a69dfd200	308	__IO uint32_t EPSKIP; /!< USB Endpoint skip /
gmatarrubia	0:820a69dfd200	309	__IO uint32_t EPINUSE; /!< USB Endpoint Buffer in use /
gmatarrubia	0:820a69dfd200	310	__IO uint32_t EPBUFCFG; /!< USB Endpoint Buffer Configuration register /
gmatarrubia	0:820a69dfd200	311	__IO uint32_t INTSTAT; /!< USB interrupt status register /
gmatarrubia	0:820a69dfd200	312	__IO uint32_t INTEN; /!< USB interrupt enable register /
gmatarrubia	0:820a69dfd200	313	__IO uint32_t INTSETSTAT; /!< USB set interrupt status register /
gmatarrubia	0:820a69dfd200	314	__IO uint32_t INTROUTING; /!< USB interrupt routing register /
gmatarrubia	0:820a69dfd200	315	__I uint32_t RESERVED0;
gmatarrubia	0:820a69dfd200	316	__I uint32_t EPTOGGLE; /!< USB Endpoint toggle register /
gmatarrubia	0:820a69dfd200	317	} LPC_USB_Type;
gmatarrubia	0:820a69dfd200	318
gmatarrubia	0:820a69dfd200	319
gmatarrubia	0:820a69dfd200	320	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	321	/* ================ CRC ================ */
gmatarrubia	0:820a69dfd200	322	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	323
gmatarrubia	0:820a69dfd200	324
gmatarrubia	0:820a69dfd200	325	/**
gmatarrubia	0:820a69dfd200	326	* @brief Cyclic Redundancy Check (CRC) engine (CRC)
gmatarrubia	0:820a69dfd200	327	*/
gmatarrubia	0:820a69dfd200	328
gmatarrubia	0:820a69dfd200	329	typedef struct { /!< CRC Structure /
gmatarrubia	0:820a69dfd200	330	__IO uint32_t MODE; /!< CRC mode register /
gmatarrubia	0:820a69dfd200	331	__IO uint32_t SEED; /!< CRC seed register /
gmatarrubia	0:820a69dfd200	332
gmatarrubia	0:820a69dfd200	333	union {
gmatarrubia	0:820a69dfd200	334	__O uint32_t WR_DATA; /!< CRC data register /
gmatarrubia	0:820a69dfd200	335	__I uint32_t SUM; /!< CRC checksum register /
gmatarrubia	0:820a69dfd200	336	};
gmatarrubia	0:820a69dfd200	337	} LPC_CRC_Type;
gmatarrubia	0:820a69dfd200	338
gmatarrubia	0:820a69dfd200	339
gmatarrubia	0:820a69dfd200	340	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	341	/* ================ SCT0 ================ */
gmatarrubia	0:820a69dfd200	342	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	343
gmatarrubia	0:820a69dfd200	344
gmatarrubia	0:820a69dfd200	345	/**
gmatarrubia	0:820a69dfd200	346	* @brief Large State Configurable Timers 0/1 (SCT0/1) (SCT0)
gmatarrubia	0:820a69dfd200	347	*/
gmatarrubia	0:820a69dfd200	348
gmatarrubia	0:820a69dfd200	349	typedef struct { /!< SCT0 Structure /
gmatarrubia	0:820a69dfd200	350	__IO uint32_t CONFIG; /!< SCT configuration register /
gmatarrubia	0:820a69dfd200	351	__IO uint32_t CTRL; /!< SCT control register /
gmatarrubia	0:820a69dfd200	352	__IO uint32_t LIMIT; /!< SCT limit register /
gmatarrubia	0:820a69dfd200	353	__IO uint32_t HALT; /!< SCT halt condition register /
gmatarrubia	0:820a69dfd200	354	__IO uint32_t STOP; /!< SCT stop condition register /
gmatarrubia	0:820a69dfd200	355	__IO uint32_t START; /!< SCT start condition register /
gmatarrubia	0:820a69dfd200	356	__IO uint32_t DITHER; /!< SCT dither condition register /
gmatarrubia	0:820a69dfd200	357	__I uint32_t RESERVED0[9];
gmatarrubia	0:820a69dfd200	358	__IO uint32_t COUNT; /!< SCT counter register /
gmatarrubia	0:820a69dfd200	359	__IO uint32_t STATE; /!< SCT state register /
gmatarrubia	0:820a69dfd200	360	__I uint32_t INPUT; /!< SCT input register /
gmatarrubia	0:820a69dfd200	361	__IO uint32_t REGMODE; /!< SCT match/capture registers mode register /
gmatarrubia	0:820a69dfd200	362	__IO uint32_t OUTPUT; /!< SCT output register /
gmatarrubia	0:820a69dfd200	363	__IO uint32_t OUTPUTDIRCTRL; /!< SCT output counter direction control register /
gmatarrubia	0:820a69dfd200	364	__IO uint32_t RES; /!< SCT conflict resolution register /
gmatarrubia	0:820a69dfd200	365	__IO uint32_t DMAREQ0; /!< SCT DMA request 0 register /
gmatarrubia	0:820a69dfd200	366	__IO uint32_t DMAREQ1; /!< SCT DMA request 1 register /
gmatarrubia	0:820a69dfd200	367	__I uint32_t RESERVED1[35];
gmatarrubia	0:820a69dfd200	368	__IO uint32_t EVEN; /!< SCT event enable register /
gmatarrubia	0:820a69dfd200	369	__IO uint32_t EVFLAG; /!< SCT event flag register /
gmatarrubia	0:820a69dfd200	370	__IO uint32_t CONEN; /!< SCT conflict enable register /
gmatarrubia	0:820a69dfd200	371	__IO uint32_t CONFLAG; /!< SCT conflict flag register /
gmatarrubia	0:820a69dfd200	372
gmatarrubia	0:820a69dfd200	373	union {
gmatarrubia	0:820a69dfd200	374	__I uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
gmatarrubia	0:820a69dfd200	375	REGMODE15 = 1 */
gmatarrubia	0:820a69dfd200	376	__IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 15; REGMOD0
gmatarrubia	0:820a69dfd200	377	to REGMODE15 = 0 */
gmatarrubia	0:820a69dfd200	378	};
gmatarrubia	0:820a69dfd200	379
gmatarrubia	0:820a69dfd200	380	union {
gmatarrubia	0:820a69dfd200	381	__I uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
gmatarrubia	0:820a69dfd200	382	REGMODE15 = 1 */
gmatarrubia	0:820a69dfd200	383	__IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 15; REGMOD0
gmatarrubia	0:820a69dfd200	384	to REGMODE15 = 0 */
gmatarrubia	0:820a69dfd200	385	};
gmatarrubia	0:820a69dfd200	386
gmatarrubia	0:820a69dfd200	387	union {
gmatarrubia	0:820a69dfd200	388	__I uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
gmatarrubia	0:820a69dfd200	389	REGMODE15 = 1 */
gmatarrubia	0:820a69dfd200	390	__IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 15; REGMOD0
gmatarrubia	0:820a69dfd200	391	to REGMODE15 = 0 */
gmatarrubia	0:820a69dfd200	392	};
gmatarrubia	0:820a69dfd200	393
gmatarrubia	0:820a69dfd200	394	union {
gmatarrubia	0:820a69dfd200	395	__I uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
gmatarrubia	0:820a69dfd200	396	REGMODE15 = 1 */
gmatarrubia	0:820a69dfd200	397	__IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 15; REGMOD0
gmatarrubia	0:820a69dfd200	398	to REGMODE15 = 0 */
gmatarrubia	0:820a69dfd200	399	};
gmatarrubia	0:820a69dfd200	400
gmatarrubia	0:820a69dfd200	401	union {
gmatarrubia	0:820a69dfd200	402	__I uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
gmatarrubia	0:820a69dfd200	403	REGMODE15 = 1 */
gmatarrubia	0:820a69dfd200	404	__IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 15; REGMOD0
gmatarrubia	0:820a69dfd200	405	to REGMODE15 = 0 */
gmatarrubia	0:820a69dfd200	406	};
gmatarrubia	0:820a69dfd200	407
gmatarrubia	0:820a69dfd200	408	union {
gmatarrubia	0:820a69dfd200	409	__I uint32_t CAP5; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
gmatarrubia	0:820a69dfd200	410	REGMODE15 = 1 */
gmatarrubia	0:820a69dfd200	411	__IO uint32_t MATCH5; /*!< SCT match value register of match channels 0 to 15; REGMOD0
gmatarrubia	0:820a69dfd200	412	to REGMODE15 = 0 */
gmatarrubia	0:820a69dfd200	413	};
gmatarrubia	0:820a69dfd200	414
gmatarrubia	0:820a69dfd200	415	union {
gmatarrubia	0:820a69dfd200	416	__I uint32_t CAP6; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
gmatarrubia	0:820a69dfd200	417	REGMODE15 = 1 */
gmatarrubia	0:820a69dfd200	418	__IO uint32_t MATCH6; /*!< SCT match value register of match channels 0 to 15; REGMOD0
gmatarrubia	0:820a69dfd200	419	to REGMODE15 = 0 */
gmatarrubia	0:820a69dfd200	420	};
gmatarrubia	0:820a69dfd200	421
gmatarrubia	0:820a69dfd200	422	union {
gmatarrubia	0:820a69dfd200	423	__IO uint32_t MATCH7; /*!< SCT match value register of match channels 0 to 15; REGMOD0
gmatarrubia	0:820a69dfd200	424	to REGMODE15 = 0 */
gmatarrubia	0:820a69dfd200	425	__I uint32_t CAP7; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
gmatarrubia	0:820a69dfd200	426	REGMODE15 = 1 */
gmatarrubia	0:820a69dfd200	427	};
gmatarrubia	0:820a69dfd200	428
gmatarrubia	0:820a69dfd200	429	union {
gmatarrubia	0:820a69dfd200	430	__I uint32_t CAP8; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
gmatarrubia	0:820a69dfd200	431	REGMODE15 = 1 */
gmatarrubia	0:820a69dfd200	432	__IO uint32_t MATCH8; /*!< SCT match value register of match channels 0 to 15; REGMOD0
gmatarrubia	0:820a69dfd200	433	to REGMODE15 = 0 */
gmatarrubia	0:820a69dfd200	434	};
gmatarrubia	0:820a69dfd200	435
gmatarrubia	0:820a69dfd200	436	union {
gmatarrubia	0:820a69dfd200	437	__IO uint32_t MATCH9; /*!< SCT match value register of match channels 0 to 15; REGMOD0
gmatarrubia	0:820a69dfd200	438	to REGMODE15 = 0 */
gmatarrubia	0:820a69dfd200	439	__I uint32_t CAP9; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
gmatarrubia	0:820a69dfd200	440	REGMODE15 = 1 */
gmatarrubia	0:820a69dfd200	441	};
gmatarrubia	0:820a69dfd200	442
gmatarrubia	0:820a69dfd200	443	union {
gmatarrubia	0:820a69dfd200	444	__IO uint32_t MATCH10; /*!< SCT match value register of match channels 0 to 15; REGMOD0
gmatarrubia	0:820a69dfd200	445	to REGMODE15 = 0 */
gmatarrubia	0:820a69dfd200	446	__I uint32_t CAP10; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
gmatarrubia	0:820a69dfd200	447	REGMODE15 = 1 */
gmatarrubia	0:820a69dfd200	448	};
gmatarrubia	0:820a69dfd200	449
gmatarrubia	0:820a69dfd200	450	union {
gmatarrubia	0:820a69dfd200	451	__IO uint32_t MATCH11; /*!< SCT match value register of match channels 0 to 15; REGMOD0
gmatarrubia	0:820a69dfd200	452	to REGMODE15 = 0 */
gmatarrubia	0:820a69dfd200	453	__I uint32_t CAP11; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
gmatarrubia	0:820a69dfd200	454	REGMODE15 = 1 */
gmatarrubia	0:820a69dfd200	455	};
gmatarrubia	0:820a69dfd200	456
gmatarrubia	0:820a69dfd200	457	union {
gmatarrubia	0:820a69dfd200	458	__IO uint32_t MATCH12; /*!< SCT match value register of match channels 0 to 15; REGMOD0
gmatarrubia	0:820a69dfd200	459	to REGMODE15 = 0 */
gmatarrubia	0:820a69dfd200	460	__I uint32_t CAP12; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
gmatarrubia	0:820a69dfd200	461	REGMODE15 = 1 */
gmatarrubia	0:820a69dfd200	462	};
gmatarrubia	0:820a69dfd200	463
gmatarrubia	0:820a69dfd200	464	union {
gmatarrubia	0:820a69dfd200	465	__IO uint32_t MATCH13; /*!< SCT match value register of match channels 0 to 15; REGMOD0
gmatarrubia	0:820a69dfd200	466	to REGMODE15 = 0 */
gmatarrubia	0:820a69dfd200	467	__I uint32_t CAP13; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
gmatarrubia	0:820a69dfd200	468	REGMODE15 = 1 */
gmatarrubia	0:820a69dfd200	469	};
gmatarrubia	0:820a69dfd200	470
gmatarrubia	0:820a69dfd200	471	union {
gmatarrubia	0:820a69dfd200	472	__I uint32_t CAP14; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
gmatarrubia	0:820a69dfd200	473	REGMODE15 = 1 */
gmatarrubia	0:820a69dfd200	474	__IO uint32_t MATCH14; /*!< SCT match value register of match channels 0 to 15; REGMOD0
gmatarrubia	0:820a69dfd200	475	to REGMODE15 = 0 */
gmatarrubia	0:820a69dfd200	476	};
gmatarrubia	0:820a69dfd200	477
gmatarrubia	0:820a69dfd200	478	union {
gmatarrubia	0:820a69dfd200	479	__IO uint32_t MATCH15; /*!< SCT match value register of match channels 0 to 15; REGMOD0
gmatarrubia	0:820a69dfd200	480	to REGMODE15 = 0 */
gmatarrubia	0:820a69dfd200	481	__I uint32_t CAP15; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
gmatarrubia	0:820a69dfd200	482	REGMODE15 = 1 */
gmatarrubia	0:820a69dfd200	483	};
gmatarrubia	0:820a69dfd200	484	__IO uint32_t FRACMAT0; /*!< Fractional match registers 0 to 5 for SCT match value registers
gmatarrubia	0:820a69dfd200	485	0 to 5. */
gmatarrubia	0:820a69dfd200	486	__IO uint32_t FRACMAT1; /*!< Fractional match registers 0 to 5 for SCT match value registers
gmatarrubia	0:820a69dfd200	487	0 to 5. */
gmatarrubia	0:820a69dfd200	488	__IO uint32_t FRACMAT2; /*!< Fractional match registers 0 to 5 for SCT match value registers
gmatarrubia	0:820a69dfd200	489	0 to 5. */
gmatarrubia	0:820a69dfd200	490	__IO uint32_t FRACMAT3; /*!< Fractional match registers 0 to 5 for SCT match value registers
gmatarrubia	0:820a69dfd200	491	0 to 5. */
gmatarrubia	0:820a69dfd200	492	__IO uint32_t FRACMAT4; /*!< Fractional match registers 0 to 5 for SCT match value registers
gmatarrubia	0:820a69dfd200	493	0 to 5. */
gmatarrubia	0:820a69dfd200	494	__IO uint32_t FRACMAT5; /*!< Fractional match registers 0 to 5 for SCT match value registers
gmatarrubia	0:820a69dfd200	495	0 to 5. */
gmatarrubia	0:820a69dfd200	496	__I uint32_t RESERVED2[42];
gmatarrubia	0:820a69dfd200	497
gmatarrubia	0:820a69dfd200	498	union {
gmatarrubia	0:820a69dfd200	499	__IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
gmatarrubia	0:820a69dfd200	500	= 1 */
gmatarrubia	0:820a69dfd200	501	__IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
gmatarrubia	0:820a69dfd200	502	= 0 */
gmatarrubia	0:820a69dfd200	503	};
gmatarrubia	0:820a69dfd200	504
gmatarrubia	0:820a69dfd200	505	union {
gmatarrubia	0:820a69dfd200	506	__IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
gmatarrubia	0:820a69dfd200	507	= 0 */
gmatarrubia	0:820a69dfd200	508	__IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
gmatarrubia	0:820a69dfd200	509	= 1 */
gmatarrubia	0:820a69dfd200	510	};
gmatarrubia	0:820a69dfd200	511
gmatarrubia	0:820a69dfd200	512	union {
gmatarrubia	0:820a69dfd200	513	__IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
gmatarrubia	0:820a69dfd200	514	= 0 */
gmatarrubia	0:820a69dfd200	515	__IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
gmatarrubia	0:820a69dfd200	516	= 1 */
gmatarrubia	0:820a69dfd200	517	};
gmatarrubia	0:820a69dfd200	518
gmatarrubia	0:820a69dfd200	519	union {
gmatarrubia	0:820a69dfd200	520	__IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
gmatarrubia	0:820a69dfd200	521	= 1 */
gmatarrubia	0:820a69dfd200	522	__IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
gmatarrubia	0:820a69dfd200	523	= 0 */
gmatarrubia	0:820a69dfd200	524	};
gmatarrubia	0:820a69dfd200	525
gmatarrubia	0:820a69dfd200	526	union {
gmatarrubia	0:820a69dfd200	527	__IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
gmatarrubia	0:820a69dfd200	528	= 1 */
gmatarrubia	0:820a69dfd200	529	__IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
gmatarrubia	0:820a69dfd200	530	= 0 */
gmatarrubia	0:820a69dfd200	531	};
gmatarrubia	0:820a69dfd200	532
gmatarrubia	0:820a69dfd200	533	union {
gmatarrubia	0:820a69dfd200	534	__IO uint32_t CAPCTRL5; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
gmatarrubia	0:820a69dfd200	535	= 1 */
gmatarrubia	0:820a69dfd200	536	__IO uint32_t MATCHREL5; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
gmatarrubia	0:820a69dfd200	537	= 0 */
gmatarrubia	0:820a69dfd200	538	};
gmatarrubia	0:820a69dfd200	539
gmatarrubia	0:820a69dfd200	540	union {
gmatarrubia	0:820a69dfd200	541	__IO uint32_t MATCHREL6; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
gmatarrubia	0:820a69dfd200	542	= 0 */
gmatarrubia	0:820a69dfd200	543	__IO uint32_t CAPCTRL6; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
gmatarrubia	0:820a69dfd200	544	= 1 */
gmatarrubia	0:820a69dfd200	545	};
gmatarrubia	0:820a69dfd200	546
gmatarrubia	0:820a69dfd200	547	union {
gmatarrubia	0:820a69dfd200	548	__IO uint32_t MATCHREL7; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
gmatarrubia	0:820a69dfd200	549	= 0 */
gmatarrubia	0:820a69dfd200	550	__IO uint32_t CAPCTRL7; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
gmatarrubia	0:820a69dfd200	551	= 1 */
gmatarrubia	0:820a69dfd200	552	};
gmatarrubia	0:820a69dfd200	553
gmatarrubia	0:820a69dfd200	554	union {
gmatarrubia	0:820a69dfd200	555	__IO uint32_t CAPCTRL8; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
gmatarrubia	0:820a69dfd200	556	= 1 */
gmatarrubia	0:820a69dfd200	557	__IO uint32_t MATCHREL8; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
gmatarrubia	0:820a69dfd200	558	= 0 */
gmatarrubia	0:820a69dfd200	559	};
gmatarrubia	0:820a69dfd200	560
gmatarrubia	0:820a69dfd200	561	union {
gmatarrubia	0:820a69dfd200	562	__IO uint32_t CAPCTRL9; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
gmatarrubia	0:820a69dfd200	563	= 1 */
gmatarrubia	0:820a69dfd200	564	__IO uint32_t MATCHREL9; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
gmatarrubia	0:820a69dfd200	565	= 0 */
gmatarrubia	0:820a69dfd200	566	};
gmatarrubia	0:820a69dfd200	567
gmatarrubia	0:820a69dfd200	568	union {
gmatarrubia	0:820a69dfd200	569	__IO uint32_t CAPCTRL10; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
gmatarrubia	0:820a69dfd200	570	= 1 */
gmatarrubia	0:820a69dfd200	571	__IO uint32_t MATCHREL10; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
gmatarrubia	0:820a69dfd200	572	= 0 */
gmatarrubia	0:820a69dfd200	573	};
gmatarrubia	0:820a69dfd200	574
gmatarrubia	0:820a69dfd200	575	union {
gmatarrubia	0:820a69dfd200	576	__IO uint32_t CAPCTRL11; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
gmatarrubia	0:820a69dfd200	577	= 1 */
gmatarrubia	0:820a69dfd200	578	__IO uint32_t MATCHREL11; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
gmatarrubia	0:820a69dfd200	579	= 0 */
gmatarrubia	0:820a69dfd200	580	};
gmatarrubia	0:820a69dfd200	581
gmatarrubia	0:820a69dfd200	582	union {
gmatarrubia	0:820a69dfd200	583	__IO uint32_t MATCHREL12; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
gmatarrubia	0:820a69dfd200	584	= 0 */
gmatarrubia	0:820a69dfd200	585	__IO uint32_t CAPCTRL12; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
gmatarrubia	0:820a69dfd200	586	= 1 */
gmatarrubia	0:820a69dfd200	587	};
gmatarrubia	0:820a69dfd200	588
gmatarrubia	0:820a69dfd200	589	union {
gmatarrubia	0:820a69dfd200	590	__IO uint32_t MATCHREL13; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
gmatarrubia	0:820a69dfd200	591	= 0 */
gmatarrubia	0:820a69dfd200	592	__IO uint32_t CAPCTRL13; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
gmatarrubia	0:820a69dfd200	593	= 1 */
gmatarrubia	0:820a69dfd200	594	};
gmatarrubia	0:820a69dfd200	595
gmatarrubia	0:820a69dfd200	596	union {
gmatarrubia	0:820a69dfd200	597	__IO uint32_t CAPCTRL14; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
gmatarrubia	0:820a69dfd200	598	= 1 */
gmatarrubia	0:820a69dfd200	599	__IO uint32_t MATCHREL14; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
gmatarrubia	0:820a69dfd200	600	= 0 */
gmatarrubia	0:820a69dfd200	601	};
gmatarrubia	0:820a69dfd200	602
gmatarrubia	0:820a69dfd200	603	union {
gmatarrubia	0:820a69dfd200	604	__IO uint32_t CAPCTRL15; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
gmatarrubia	0:820a69dfd200	605	= 1 */
gmatarrubia	0:820a69dfd200	606	__IO uint32_t MATCHREL15; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
gmatarrubia	0:820a69dfd200	607	= 0 */
gmatarrubia	0:820a69dfd200	608	};
gmatarrubia	0:820a69dfd200	609	__IO uint32_t FRACMATREL0; /*!< Fractional match reload registers 0 to 5 for SCT match value
gmatarrubia	0:820a69dfd200	610	registers 0 to 5. */
gmatarrubia	0:820a69dfd200	611	__IO uint32_t FRACMATREL1; /*!< Fractional match reload registers 0 to 5 for SCT match value
gmatarrubia	0:820a69dfd200	612	registers 0 to 5. */
gmatarrubia	0:820a69dfd200	613	__IO uint32_t FRACMATREL2; /*!< Fractional match reload registers 0 to 5 for SCT match value
gmatarrubia	0:820a69dfd200	614	registers 0 to 5. */
gmatarrubia	0:820a69dfd200	615	__IO uint32_t FRACMATREL3; /*!< Fractional match reload registers 0 to 5 for SCT match value
gmatarrubia	0:820a69dfd200	616	registers 0 to 5. */
gmatarrubia	0:820a69dfd200	617	__IO uint32_t FRACMATREL4; /*!< Fractional match reload registers 0 to 5 for SCT match value
gmatarrubia	0:820a69dfd200	618	registers 0 to 5. */
gmatarrubia	0:820a69dfd200	619	__IO uint32_t FRACMATREL5; /*!< Fractional match reload registers 0 to 5 for SCT match value
gmatarrubia	0:820a69dfd200	620	registers 0 to 5. */
gmatarrubia	0:820a69dfd200	621	__I uint32_t RESERVED3[42];
gmatarrubia	0:820a69dfd200	622	__IO uint32_t EV0_STATE; /!< SCT event state register 0 /
gmatarrubia	0:820a69dfd200	623	__IO uint32_t EV0_CTRL; /!< SCT event control register 0 /
gmatarrubia	0:820a69dfd200	624	__IO uint32_t EV1_STATE; /!< SCT event state register 0 /
gmatarrubia	0:820a69dfd200	625	__IO uint32_t EV1_CTRL; /!< SCT event control register 0 /
gmatarrubia	0:820a69dfd200	626	__IO uint32_t EV2_STATE; /!< SCT event state register 0 /
gmatarrubia	0:820a69dfd200	627	__IO uint32_t EV2_CTRL; /!< SCT event control register 0 /
gmatarrubia	0:820a69dfd200	628	__IO uint32_t EV3_STATE; /!< SCT event state register 0 /
gmatarrubia	0:820a69dfd200	629	__IO uint32_t EV3_CTRL; /!< SCT event control register 0 /
gmatarrubia	0:820a69dfd200	630	__IO uint32_t EV4_STATE; /!< SCT event state register 0 /
gmatarrubia	0:820a69dfd200	631	__IO uint32_t EV4_CTRL; /!< SCT event control register 0 /
gmatarrubia	0:820a69dfd200	632	__IO uint32_t EV5_STATE; /!< SCT event state register 0 /
gmatarrubia	0:820a69dfd200	633	__IO uint32_t EV5_CTRL; /!< SCT event control register 0 /
gmatarrubia	0:820a69dfd200	634	__IO uint32_t EV6_STATE; /!< SCT event state register 0 /
gmatarrubia	0:820a69dfd200	635	__IO uint32_t EV6_CTRL; /!< SCT event control register 0 /
gmatarrubia	0:820a69dfd200	636	__IO uint32_t EV7_STATE; /!< SCT event state register 0 /
gmatarrubia	0:820a69dfd200	637	__IO uint32_t EV7_CTRL; /!< SCT event control register 0 /
gmatarrubia	0:820a69dfd200	638	__IO uint32_t EV8_STATE; /!< SCT event state register 0 /
gmatarrubia	0:820a69dfd200	639	__IO uint32_t EV8_CTRL; /!< SCT event control register 0 /
gmatarrubia	0:820a69dfd200	640	__IO uint32_t EV9_STATE; /!< SCT event state register 0 /
gmatarrubia	0:820a69dfd200	641	__IO uint32_t EV9_CTRL; /!< SCT event control register 0 /
gmatarrubia	0:820a69dfd200	642	__IO uint32_t EV10_STATE; /!< SCT event state register 0 /
gmatarrubia	0:820a69dfd200	643	__IO uint32_t EV10_CTRL; /!< SCT event control register 0 /
gmatarrubia	0:820a69dfd200	644	__IO uint32_t EV11_STATE; /!< SCT event state register 0 /
gmatarrubia	0:820a69dfd200	645	__IO uint32_t EV11_CTRL; /!< SCT event control register 0 /
gmatarrubia	0:820a69dfd200	646	__IO uint32_t EV12_STATE; /!< SCT event state register 0 /
gmatarrubia	0:820a69dfd200	647	__IO uint32_t EV12_CTRL; /!< SCT event control register 0 /
gmatarrubia	0:820a69dfd200	648	__IO uint32_t EV13_STATE; /!< SCT event state register 0 /
gmatarrubia	0:820a69dfd200	649	__IO uint32_t EV13_CTRL; /!< SCT event control register 0 /
gmatarrubia	0:820a69dfd200	650	__IO uint32_t EV14_STATE; /!< SCT event state register 0 /
gmatarrubia	0:820a69dfd200	651	__IO uint32_t EV14_CTRL; /!< SCT event control register 0 /
gmatarrubia	0:820a69dfd200	652	__IO uint32_t EV15_STATE; /!< SCT event state register 0 /
gmatarrubia	0:820a69dfd200	653	__IO uint32_t EV15_CTRL; /!< SCT event control register 0 /
gmatarrubia	0:820a69dfd200	654	__I uint32_t RESERVED4[96];
gmatarrubia	0:820a69dfd200	655	__IO uint32_t OUT0_SET; /!< SCT output 0 set register /
gmatarrubia	0:820a69dfd200	656	__IO uint32_t OUT0_CLR; /!< SCT output 0 clear register /
gmatarrubia	0:820a69dfd200	657	__IO uint32_t OUT1_SET; /!< SCT output 0 set register /
gmatarrubia	0:820a69dfd200	658	__IO uint32_t OUT1_CLR; /!< SCT output 0 clear register /
gmatarrubia	0:820a69dfd200	659	__IO uint32_t OUT2_SET; /!< SCT output 0 set register /
gmatarrubia	0:820a69dfd200	660	__IO uint32_t OUT2_CLR; /!< SCT output 0 clear register /
gmatarrubia	0:820a69dfd200	661	__IO uint32_t OUT3_SET; /!< SCT output 0 set register /
gmatarrubia	0:820a69dfd200	662	__IO uint32_t OUT3_CLR; /!< SCT output 0 clear register /
gmatarrubia	0:820a69dfd200	663	__IO uint32_t OUT4_SET; /!< SCT output 0 set register /
gmatarrubia	0:820a69dfd200	664	__IO uint32_t OUT4_CLR; /!< SCT output 0 clear register /
gmatarrubia	0:820a69dfd200	665	__IO uint32_t OUT5_SET; /!< SCT output 0 set register /
gmatarrubia	0:820a69dfd200	666	__IO uint32_t OUT5_CLR; /!< SCT output 0 clear register /
gmatarrubia	0:820a69dfd200	667	__IO uint32_t OUT6_SET; /!< SCT output 0 set register /
gmatarrubia	0:820a69dfd200	668	__IO uint32_t OUT6_CLR; /!< SCT output 0 clear register /
gmatarrubia	0:820a69dfd200	669	__IO uint32_t OUT7_SET; /!< SCT output 0 set register /
gmatarrubia	0:820a69dfd200	670	__IO uint32_t OUT7_CLR; /!< SCT output 0 clear register /
gmatarrubia	0:820a69dfd200	671	__IO uint32_t OUT8_SET; /!< SCT output 0 set register /
gmatarrubia	0:820a69dfd200	672	__IO uint32_t OUT8_CLR; /!< SCT output 0 clear register /
gmatarrubia	0:820a69dfd200	673	__IO uint32_t OUT9_SET; /!< SCT output 0 set register /
gmatarrubia	0:820a69dfd200	674	__IO uint32_t OUT9_CLR; /!< SCT output 0 clear register /
gmatarrubia	0:820a69dfd200	675	} LPC_SCT0_Type;
gmatarrubia	0:820a69dfd200	676
gmatarrubia	0:820a69dfd200	677
gmatarrubia	0:820a69dfd200	678	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	679	/* ================ SCT2 ================ */
gmatarrubia	0:820a69dfd200	680	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	681
gmatarrubia	0:820a69dfd200	682
gmatarrubia	0:820a69dfd200	683	/**
gmatarrubia	0:820a69dfd200	684	* @brief Small State Configurable Timers 2/3 (SCT2/3) (SCT2)
gmatarrubia	0:820a69dfd200	685	*/
gmatarrubia	0:820a69dfd200	686
gmatarrubia	0:820a69dfd200	687	typedef struct { /!< SCT2 Structure /
gmatarrubia	0:820a69dfd200	688	__IO uint32_t CONFIG; /!< SCT configuration register /
gmatarrubia	0:820a69dfd200	689	__IO uint32_t CTRL; /!< SCT control register /
gmatarrubia	0:820a69dfd200	690	__IO uint32_t LIMIT; /!< SCT limit register /
gmatarrubia	0:820a69dfd200	691	__IO uint32_t HALT; /!< SCT halt condition register /
gmatarrubia	0:820a69dfd200	692	__IO uint32_t STOP; /!< SCT stop condition register /
gmatarrubia	0:820a69dfd200	693	__IO uint32_t START; /!< SCT start condition register /
gmatarrubia	0:820a69dfd200	694	__I uint32_t RESERVED0[10];
gmatarrubia	0:820a69dfd200	695	__IO uint32_t COUNT; /!< SCT counter register /
gmatarrubia	0:820a69dfd200	696	__IO uint32_t STATE; /!< SCT state register /
gmatarrubia	0:820a69dfd200	697	__I uint32_t INPUT; /!< SCT input register /
gmatarrubia	0:820a69dfd200	698	__IO uint32_t REGMODE; /!< SCT match/capture registers mode register /
gmatarrubia	0:820a69dfd200	699	__IO uint32_t OUTPUT; /!< SCT output register /
gmatarrubia	0:820a69dfd200	700	__IO uint32_t OUTPUTDIRCTRL; /!< SCT output counter direction control register /
gmatarrubia	0:820a69dfd200	701	__IO uint32_t RES; /!< SCT conflict resolution register /
gmatarrubia	0:820a69dfd200	702	__IO uint32_t DMAREQ0; /!< SCT DMA request 0 register /
gmatarrubia	0:820a69dfd200	703	__IO uint32_t DMAREQ1; /!< SCT DMA request 1 register /
gmatarrubia	0:820a69dfd200	704	__I uint32_t RESERVED1[35];
gmatarrubia	0:820a69dfd200	705	__IO uint32_t EVEN; /!< SCT event enable register /
gmatarrubia	0:820a69dfd200	706	__IO uint32_t EVFLAG; /!< SCT event flag register /
gmatarrubia	0:820a69dfd200	707	__IO uint32_t CONEN; /!< SCT conflict enable register /
gmatarrubia	0:820a69dfd200	708	__IO uint32_t CONFLAG; /!< SCT conflict flag register /
gmatarrubia	0:820a69dfd200	709
gmatarrubia	0:820a69dfd200	710	union {
gmatarrubia	0:820a69dfd200	711	__I uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
gmatarrubia	0:820a69dfd200	712	= 1 */
gmatarrubia	0:820a69dfd200	713	__IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
gmatarrubia	0:820a69dfd200	714	REGMODE7 = 0 */
gmatarrubia	0:820a69dfd200	715	};
gmatarrubia	0:820a69dfd200	716
gmatarrubia	0:820a69dfd200	717	union {
gmatarrubia	0:820a69dfd200	718	__I uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
gmatarrubia	0:820a69dfd200	719	= 1 */
gmatarrubia	0:820a69dfd200	720	__IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
gmatarrubia	0:820a69dfd200	721	REGMODE7 = 0 */
gmatarrubia	0:820a69dfd200	722	};
gmatarrubia	0:820a69dfd200	723
gmatarrubia	0:820a69dfd200	724	union {
gmatarrubia	0:820a69dfd200	725	__I uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
gmatarrubia	0:820a69dfd200	726	= 1 */
gmatarrubia	0:820a69dfd200	727	__IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
gmatarrubia	0:820a69dfd200	728	REGMODE7 = 0 */
gmatarrubia	0:820a69dfd200	729	};
gmatarrubia	0:820a69dfd200	730
gmatarrubia	0:820a69dfd200	731	union {
gmatarrubia	0:820a69dfd200	732	__IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
gmatarrubia	0:820a69dfd200	733	REGMODE7 = 0 */
gmatarrubia	0:820a69dfd200	734	__I uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
gmatarrubia	0:820a69dfd200	735	= 1 */
gmatarrubia	0:820a69dfd200	736	};
gmatarrubia	0:820a69dfd200	737
gmatarrubia	0:820a69dfd200	738	union {
gmatarrubia	0:820a69dfd200	739	__I uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
gmatarrubia	0:820a69dfd200	740	= 1 */
gmatarrubia	0:820a69dfd200	741	__IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
gmatarrubia	0:820a69dfd200	742	REGMODE7 = 0 */
gmatarrubia	0:820a69dfd200	743	};
gmatarrubia	0:820a69dfd200	744
gmatarrubia	0:820a69dfd200	745	union {
gmatarrubia	0:820a69dfd200	746	__IO uint32_t MATCH5; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
gmatarrubia	0:820a69dfd200	747	REGMODE7 = 0 */
gmatarrubia	0:820a69dfd200	748	__I uint32_t CAP5; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
gmatarrubia	0:820a69dfd200	749	= 1 */
gmatarrubia	0:820a69dfd200	750	};
gmatarrubia	0:820a69dfd200	751
gmatarrubia	0:820a69dfd200	752	union {
gmatarrubia	0:820a69dfd200	753	__I uint32_t CAP6; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
gmatarrubia	0:820a69dfd200	754	= 1 */
gmatarrubia	0:820a69dfd200	755	__IO uint32_t MATCH6; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
gmatarrubia	0:820a69dfd200	756	REGMODE7 = 0 */
gmatarrubia	0:820a69dfd200	757	};
gmatarrubia	0:820a69dfd200	758
gmatarrubia	0:820a69dfd200	759	union {
gmatarrubia	0:820a69dfd200	760	__I uint32_t CAP7; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
gmatarrubia	0:820a69dfd200	761	= 1 */
gmatarrubia	0:820a69dfd200	762	__IO uint32_t MATCH7; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
gmatarrubia	0:820a69dfd200	763	REGMODE7 = 0 */
gmatarrubia	0:820a69dfd200	764	};
gmatarrubia	0:820a69dfd200	765	__I uint32_t RESERVED2[56];
gmatarrubia	0:820a69dfd200	766
gmatarrubia	0:820a69dfd200	767	union {
gmatarrubia	0:820a69dfd200	768	__IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
gmatarrubia	0:820a69dfd200	769	= 1 */
gmatarrubia	0:820a69dfd200	770	__IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
gmatarrubia	0:820a69dfd200	771	= 0 */
gmatarrubia	0:820a69dfd200	772	};
gmatarrubia	0:820a69dfd200	773
gmatarrubia	0:820a69dfd200	774	union {
gmatarrubia	0:820a69dfd200	775	__IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
gmatarrubia	0:820a69dfd200	776	= 1 */
gmatarrubia	0:820a69dfd200	777	__IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
gmatarrubia	0:820a69dfd200	778	= 0 */
gmatarrubia	0:820a69dfd200	779	};
gmatarrubia	0:820a69dfd200	780
gmatarrubia	0:820a69dfd200	781	union {
gmatarrubia	0:820a69dfd200	782	__IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
gmatarrubia	0:820a69dfd200	783	= 1 */
gmatarrubia	0:820a69dfd200	784	__IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
gmatarrubia	0:820a69dfd200	785	= 0 */
gmatarrubia	0:820a69dfd200	786	};
gmatarrubia	0:820a69dfd200	787
gmatarrubia	0:820a69dfd200	788	union {
gmatarrubia	0:820a69dfd200	789	__IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
gmatarrubia	0:820a69dfd200	790	= 0 */
gmatarrubia	0:820a69dfd200	791	__IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
gmatarrubia	0:820a69dfd200	792	= 1 */
gmatarrubia	0:820a69dfd200	793	};
gmatarrubia	0:820a69dfd200	794
gmatarrubia	0:820a69dfd200	795	union {
gmatarrubia	0:820a69dfd200	796	__IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
gmatarrubia	0:820a69dfd200	797	= 1 */
gmatarrubia	0:820a69dfd200	798	__IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
gmatarrubia	0:820a69dfd200	799	= 0 */
gmatarrubia	0:820a69dfd200	800	};
gmatarrubia	0:820a69dfd200	801
gmatarrubia	0:820a69dfd200	802	union {
gmatarrubia	0:820a69dfd200	803	__IO uint32_t MATCHREL5; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
gmatarrubia	0:820a69dfd200	804	= 0 */
gmatarrubia	0:820a69dfd200	805	__IO uint32_t CAPCTRL5; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
gmatarrubia	0:820a69dfd200	806	= 1 */
gmatarrubia	0:820a69dfd200	807	};
gmatarrubia	0:820a69dfd200	808
gmatarrubia	0:820a69dfd200	809	union {
gmatarrubia	0:820a69dfd200	810	__IO uint32_t CAPCTRL6; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
gmatarrubia	0:820a69dfd200	811	= 1 */
gmatarrubia	0:820a69dfd200	812	__IO uint32_t MATCHREL6; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
gmatarrubia	0:820a69dfd200	813	= 0 */
gmatarrubia	0:820a69dfd200	814	};
gmatarrubia	0:820a69dfd200	815
gmatarrubia	0:820a69dfd200	816	union {
gmatarrubia	0:820a69dfd200	817	__IO uint32_t CAPCTRL7; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
gmatarrubia	0:820a69dfd200	818	= 1 */
gmatarrubia	0:820a69dfd200	819	__IO uint32_t MATCHREL7; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
gmatarrubia	0:820a69dfd200	820	= 0 */
gmatarrubia	0:820a69dfd200	821	};
gmatarrubia	0:820a69dfd200	822	__I uint32_t RESERVED3[56];
gmatarrubia	0:820a69dfd200	823	__IO uint32_t EV0_STATE; /!< SCT event state register 0 /
gmatarrubia	0:820a69dfd200	824	__IO uint32_t EV0_CTRL; /!< SCT event control register 0 /
gmatarrubia	0:820a69dfd200	825	__IO uint32_t EV1_STATE; /!< SCT event state register 0 /
gmatarrubia	0:820a69dfd200	826	__IO uint32_t EV1_CTRL; /!< SCT event control register 0 /
gmatarrubia	0:820a69dfd200	827	__IO uint32_t EV2_STATE; /!< SCT event state register 0 /
gmatarrubia	0:820a69dfd200	828	__IO uint32_t EV2_CTRL; /!< SCT event control register 0 /
gmatarrubia	0:820a69dfd200	829	__IO uint32_t EV3_STATE; /!< SCT event state register 0 /
gmatarrubia	0:820a69dfd200	830	__IO uint32_t EV3_CTRL; /!< SCT event control register 0 /
gmatarrubia	0:820a69dfd200	831	__IO uint32_t EV4_STATE; /!< SCT event state register 0 /
gmatarrubia	0:820a69dfd200	832	__IO uint32_t EV4_CTRL; /!< SCT event control register 0 /
gmatarrubia	0:820a69dfd200	833	__IO uint32_t EV5_STATE; /!< SCT event state register 0 /
gmatarrubia	0:820a69dfd200	834	__IO uint32_t EV5_CTRL; /!< SCT event control register 0 /
gmatarrubia	0:820a69dfd200	835	__IO uint32_t EV6_STATE; /!< SCT event state register 0 /
gmatarrubia	0:820a69dfd200	836	__IO uint32_t EV6_CTRL; /!< SCT event control register 0 /
gmatarrubia	0:820a69dfd200	837	__IO uint32_t EV7_STATE; /!< SCT event state register 0 /
gmatarrubia	0:820a69dfd200	838	__IO uint32_t EV7_CTRL; /!< SCT event control register 0 /
gmatarrubia	0:820a69dfd200	839	__IO uint32_t EV8_STATE; /!< SCT event state register 0 /
gmatarrubia	0:820a69dfd200	840	__IO uint32_t EV8_CTRL; /!< SCT event control register 0 /
gmatarrubia	0:820a69dfd200	841	__IO uint32_t EV9_STATE; /!< SCT event state register 0 /
gmatarrubia	0:820a69dfd200	842	__IO uint32_t EV9_CTRL; /!< SCT event control register 0 /
gmatarrubia	0:820a69dfd200	843	__I uint32_t RESERVED4[108];
gmatarrubia	0:820a69dfd200	844	__IO uint32_t OUT0_SET; /!< SCT output 0 set register /
gmatarrubia	0:820a69dfd200	845	__IO uint32_t OUT0_CLR; /!< SCT output 0 clear register /
gmatarrubia	0:820a69dfd200	846	__IO uint32_t OUT1_SET; /!< SCT output 0 set register /
gmatarrubia	0:820a69dfd200	847	__IO uint32_t OUT1_CLR; /!< SCT output 0 clear register /
gmatarrubia	0:820a69dfd200	848	__IO uint32_t OUT2_SET; /!< SCT output 0 set register /
gmatarrubia	0:820a69dfd200	849	__IO uint32_t OUT2_CLR; /!< SCT output 0 clear register /
gmatarrubia	0:820a69dfd200	850	__IO uint32_t OUT3_SET; /!< SCT output 0 set register /
gmatarrubia	0:820a69dfd200	851	__IO uint32_t OUT3_CLR; /!< SCT output 0 clear register /
gmatarrubia	0:820a69dfd200	852	__IO uint32_t OUT4_SET; /!< SCT output 0 set register /
gmatarrubia	0:820a69dfd200	853	__IO uint32_t OUT4_CLR; /!< SCT output 0 clear register /
gmatarrubia	0:820a69dfd200	854	__IO uint32_t OUT5_SET; /!< SCT output 0 set register /
gmatarrubia	0:820a69dfd200	855	__IO uint32_t OUT5_CLR; /!< SCT output 0 clear register /
gmatarrubia	0:820a69dfd200	856	} LPC_SCT2_Type;
gmatarrubia	0:820a69dfd200	857
gmatarrubia	0:820a69dfd200	858
gmatarrubia	0:820a69dfd200	859	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	860	/* ================ ADC0 ================ */
gmatarrubia	0:820a69dfd200	861	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	862
gmatarrubia	0:820a69dfd200	863
gmatarrubia	0:820a69dfd200	864	/**
gmatarrubia	0:820a69dfd200	865	* @brief 12-bit ADC controller ADC0/1 (ADC0)
gmatarrubia	0:820a69dfd200	866	*/
gmatarrubia	0:820a69dfd200	867
gmatarrubia	0:820a69dfd200	868	typedef struct { /!< ADC0 Structure /
gmatarrubia	0:820a69dfd200	869	__IO uint32_t CTRL; /*!< A/D Control Register. Contains the clock divide value, enable
gmatarrubia	0:820a69dfd200	870	bits for each sequence and the A/D power-down bit. */
gmatarrubia	0:820a69dfd200	871	__IO uint32_t INSEL; /*!< A/D Input Select Register: Selects between external pin and
gmatarrubia	0:820a69dfd200	872	internal source for various channels */
gmatarrubia	0:820a69dfd200	873	__IO uint32_t SEQA_CTRL; /*!< A/D Conversion Sequence-A control Register: Controls triggering
gmatarrubia	0:820a69dfd200	874	and channel selection for conversion sequence-A. Also specifies
gmatarrubia	0:820a69dfd200	875	interrupt mode for sequence-A. */
gmatarrubia	0:820a69dfd200	876	__IO uint32_t SEQB_CTRL; /*!< A/D Conversion Sequence-B Control Register: Controls triggering
gmatarrubia	0:820a69dfd200	877	and channel selection for conversion sequence-B. Also specifies
gmatarrubia	0:820a69dfd200	878	interrupt mode for sequence-B. */
gmatarrubia	0:820a69dfd200	879	__IO uint32_t SEQA_GDAT; /*!< A/D Sequence-A Global Data Register. This register contains
gmatarrubia	0:820a69dfd200	880	the result of the most recent A/D conversion performed under
gmatarrubia	0:820a69dfd200	881	sequence-A */
gmatarrubia	0:820a69dfd200	882	__IO uint32_t SEQB_GDAT; /*!< A/D Sequence-B Global Data Register. This register contains
gmatarrubia	0:820a69dfd200	883	the result of the most recent A/D conversion performed under
gmatarrubia	0:820a69dfd200	884	sequence-B */
gmatarrubia	0:820a69dfd200	885	__I uint32_t RESERVED0[2];
gmatarrubia	0:820a69dfd200	886	__I uint32_t DAT[12]; /*!< A/D Channel 0 Data Register. This register contains the result
gmatarrubia	0:820a69dfd200	887	of the most recent conversion completed on channel 0. */
gmatarrubia	0:820a69dfd200	888	__IO uint32_t THR0_LOW; /*!< A/D Low Compare Threshold Register 0 : Contains the lower threshold
gmatarrubia	0:820a69dfd200	889	level for automatic threshold comparison for any channels linked
gmatarrubia	0:820a69dfd200	890	to threshold pair 0. */
gmatarrubia	0:820a69dfd200	891	__IO uint32_t THR1_LOW; /*!< A/D Low Compare Threshold Register 1: Contains the lower threshold
gmatarrubia	0:820a69dfd200	892	level for automatic threshold comparison for any channels linked
gmatarrubia	0:820a69dfd200	893	to threshold pair 1. */
gmatarrubia	0:820a69dfd200	894	__IO uint32_t THR0_HIGH; /*!< A/D High Compare Threshold Register 0: Contains the upper threshold
gmatarrubia	0:820a69dfd200	895	level for automatic threshold comparison for any channels linked
gmatarrubia	0:820a69dfd200	896	to threshold pair 0. */
gmatarrubia	0:820a69dfd200	897	__IO uint32_t THR1_HIGH; /*!< A/D High Compare Threshold Register 1: Contains the upper threshold
gmatarrubia	0:820a69dfd200	898	level for automatic threshold comparison for any channels linked
gmatarrubia	0:820a69dfd200	899	to threshold pair 1. */
gmatarrubia	0:820a69dfd200	900	__I uint32_t CHAN_THRSEL; /*!< A/D Channel-Threshold Select Register. Specifies which set of
gmatarrubia	0:820a69dfd200	901	threshold compare registers are to be used for each channel */
gmatarrubia	0:820a69dfd200	902	__IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable
gmatarrubia	0:820a69dfd200	903	bits that enable the sequence-A, sequence-B, threshold compare
gmatarrubia	0:820a69dfd200	904	and data overrun interrupts to be generated. */
gmatarrubia	0:820a69dfd200	905	__I uint32_t FLAGS; /*!< A/D Flags Register. Contains the four interrupt request flags
gmatarrubia	0:820a69dfd200	906	and the individual component overrun and threshold-compare flags.
gmatarrubia	0:820a69dfd200	907	(The overrun bits replicate information stored in the result
gmatarrubia	0:820a69dfd200	908	registers). */
gmatarrubia	0:820a69dfd200	909	__IO uint32_t TRM; /!< ADC trim register. /
gmatarrubia	0:820a69dfd200	910	} LPC_ADC0_Type;
gmatarrubia	0:820a69dfd200	911
gmatarrubia	0:820a69dfd200	912
gmatarrubia	0:820a69dfd200	913	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	914	/* ================ DAC ================ */
gmatarrubia	0:820a69dfd200	915	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	916
gmatarrubia	0:820a69dfd200	917
gmatarrubia	0:820a69dfd200	918	/**
gmatarrubia	0:820a69dfd200	919	* @brief 12-bit DAC Modification (DAC)
gmatarrubia	0:820a69dfd200	920	*/
gmatarrubia	0:820a69dfd200	921
gmatarrubia	0:820a69dfd200	922	typedef struct { /!< DAC Structure /
gmatarrubia	0:820a69dfd200	923	__IO uint32_t VAL; /*!< D/A Converter Value Register. This register contains the digital
gmatarrubia	0:820a69dfd200	924	value to be converted to analog. */
gmatarrubia	0:820a69dfd200	925	__IO uint32_t CTRL; /*!< DAC Control register. This register contains bits to configure
gmatarrubia	0:820a69dfd200	926	DAC operation and the interrupt/dma request flag. */
gmatarrubia	0:820a69dfd200	927	__IO uint32_t CNTVAL; /*!< DAC Counter Value register. This register contains the reload
gmatarrubia	0:820a69dfd200	928	value for the internal DAC DMA/Interrupt timer. */
gmatarrubia	0:820a69dfd200	929	} LPC_DAC_Type;
gmatarrubia	0:820a69dfd200	930
gmatarrubia	0:820a69dfd200	931
gmatarrubia	0:820a69dfd200	932	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	933	/* ================ ACMP ================ */
gmatarrubia	0:820a69dfd200	934	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	935
gmatarrubia	0:820a69dfd200	936
gmatarrubia	0:820a69dfd200	937	/**
gmatarrubia	0:820a69dfd200	938	* @brief Analog comparators ACMP0/1/2/3 (ACMP)
gmatarrubia	0:820a69dfd200	939	*/
gmatarrubia	0:820a69dfd200	940
gmatarrubia	0:820a69dfd200	941	typedef struct { /!< ACMP Structure /
gmatarrubia	0:820a69dfd200	942	__IO uint32_t CTRL; /!< Comparator block control register /
gmatarrubia	0:820a69dfd200	943	__IO uint32_t CMP0; /!< Comparator 0 source control /
gmatarrubia	0:820a69dfd200	944	__IO uint32_t CMPFILTR0; /!< Comparator 0 pin filter set-up /
gmatarrubia	0:820a69dfd200	945	__IO uint32_t CMP1; /!< Comparator 1 source control /
gmatarrubia	0:820a69dfd200	946	__IO uint32_t CMPFILTR1; /!< Comparator 0 pin filter set-up /
gmatarrubia	0:820a69dfd200	947	__IO uint32_t CMP2; /!< Comparator 2 source control /
gmatarrubia	0:820a69dfd200	948	__IO uint32_t CMPFILTR2; /!< Comparator 0 pin filter set-up /
gmatarrubia	0:820a69dfd200	949	__IO uint32_t CMP3; /!< Comparator 3 source control /
gmatarrubia	0:820a69dfd200	950	__IO uint32_t CMPFILTR3; /!< Comparator 0 pin filter set-up /
gmatarrubia	0:820a69dfd200	951	} LPC_ACMP_Type;
gmatarrubia	0:820a69dfd200	952
gmatarrubia	0:820a69dfd200	953
gmatarrubia	0:820a69dfd200	954	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	955	/* ================ INMUX ================ */
gmatarrubia	0:820a69dfd200	956	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	957
gmatarrubia	0:820a69dfd200	958
gmatarrubia	0:820a69dfd200	959	/**
gmatarrubia	0:820a69dfd200	960	* @brief Input multiplexing (INMUX) (INMUX)
gmatarrubia	0:820a69dfd200	961	*/
gmatarrubia	0:820a69dfd200	962
gmatarrubia	0:820a69dfd200	963	typedef struct { /!< INMUX Structure /
gmatarrubia	0:820a69dfd200	964	__IO uint32_t SCT0_INMUX[7]; /!< Pinmux register for SCT0 input 0 /
gmatarrubia	0:820a69dfd200	965	__I uint32_t RESERVED0;
gmatarrubia	0:820a69dfd200	966	__IO uint32_t SCT1_INMUX[7]; /!< Pinmux register for SCT1 input 0 /
gmatarrubia	0:820a69dfd200	967	__I uint32_t RESERVED1;
gmatarrubia	0:820a69dfd200	968	__IO uint32_t SCT2_INMUX[3]; /!< Pinmux register for SCT2 input 0 /
gmatarrubia	0:820a69dfd200	969	__I uint32_t RESERVED2[5];
gmatarrubia	0:820a69dfd200	970	__IO uint32_t SCT3_INMUX[3]; /!< Pinmux register for SCT3 input 0 /
gmatarrubia	0:820a69dfd200	971	__I uint32_t RESERVED3[21];
gmatarrubia	0:820a69dfd200	972	__IO uint32_t PINTSEL[8]; /!< Pin interrupt select register 0 /
gmatarrubia	0:820a69dfd200	973	__IO uint32_t DMA_ITRIG_INMUX[18]; /!< Trigger input for DMA channel 0 select register. /
gmatarrubia	0:820a69dfd200	974	__I uint32_t RESERVED4[14];
gmatarrubia	0:820a69dfd200	975	__IO uint32_t FREQMEAS_REF; /*!< Clock selection for frequency measurement function reference
gmatarrubia	0:820a69dfd200	976	clock */
gmatarrubia	0:820a69dfd200	977	__IO uint32_t FREQMEAS_TARGET; /!< Clock selection for frequency measurement function target clock /
gmatarrubia	0:820a69dfd200	978	} LPC_INMUX_Type;
gmatarrubia	0:820a69dfd200	979
gmatarrubia	0:820a69dfd200	980
gmatarrubia	0:820a69dfd200	981	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	982	/* ================ RTC ================ */
gmatarrubia	0:820a69dfd200	983	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	984
gmatarrubia	0:820a69dfd200	985
gmatarrubia	0:820a69dfd200	986	/**
gmatarrubia	0:820a69dfd200	987	* @brief Real-Time Clock (RTC) (RTC)
gmatarrubia	0:820a69dfd200	988	*/
gmatarrubia	0:820a69dfd200	989
gmatarrubia	0:820a69dfd200	990	typedef struct { /!< RTC Structure /
gmatarrubia	0:820a69dfd200	991	__IO uint32_t CTRL; /!< RTC control register /
gmatarrubia	0:820a69dfd200	992	__IO uint32_t MATCH; /!< RTC match register /
gmatarrubia	0:820a69dfd200	993	__IO uint32_t COUNT; /!< RTC counter register /
gmatarrubia	0:820a69dfd200	994	__IO uint32_t WAKE; /!< RTC high-resolution/wake-up timer control register /
gmatarrubia	0:820a69dfd200	995	} LPC_RTC_Type;
gmatarrubia	0:820a69dfd200	996
gmatarrubia	0:820a69dfd200	997
gmatarrubia	0:820a69dfd200	998	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	999	/* ================ WWDT ================ */
gmatarrubia	0:820a69dfd200	1000	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1001
gmatarrubia	0:820a69dfd200	1002
gmatarrubia	0:820a69dfd200	1003	/**
gmatarrubia	0:820a69dfd200	1004	* @brief Windowed Watchdog Timer (WWDT) (WWDT)
gmatarrubia	0:820a69dfd200	1005	*/
gmatarrubia	0:820a69dfd200	1006
gmatarrubia	0:820a69dfd200	1007	typedef struct { /!< WWDT Structure /
gmatarrubia	0:820a69dfd200	1008	__IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode
gmatarrubia	0:820a69dfd200	1009	and status of the Watchdog Timer. */
gmatarrubia	0:820a69dfd200	1010	__IO uint32_t TC; /*!< Watchdog timer constant register. This 24-bit register determines
gmatarrubia	0:820a69dfd200	1011	the time-out value. */
gmatarrubia	0:820a69dfd200	1012	__O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55
gmatarrubia	0:820a69dfd200	1013	to this register reloads the Watchdog timer with the value contained
gmatarrubia	0:820a69dfd200	1014	in WDTC. */
gmatarrubia	0:820a69dfd200	1015	__I uint32_t TV; /*!< Watchdog timer value register. This 24-bit register reads out
gmatarrubia	0:820a69dfd200	1016	the current value of the Watchdog timer. */
gmatarrubia	0:820a69dfd200	1017	__I uint32_t RESERVED0;
gmatarrubia	0:820a69dfd200	1018	__IO uint32_t WARNINT; /!< Watchdog Warning Interrupt compare value. /
gmatarrubia	0:820a69dfd200	1019	__IO uint32_t WINDOW; /!< Watchdog Window compare value. /
gmatarrubia	0:820a69dfd200	1020	} LPC_WWDT_Type;
gmatarrubia	0:820a69dfd200	1021
gmatarrubia	0:820a69dfd200	1022
gmatarrubia	0:820a69dfd200	1023	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1024	/* ================ SWM ================ */
gmatarrubia	0:820a69dfd200	1025	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1026
gmatarrubia	0:820a69dfd200	1027
gmatarrubia	0:820a69dfd200	1028	/**
gmatarrubia	0:820a69dfd200	1029	* @brief Switch Matrix (SWM) (SWM)
gmatarrubia	0:820a69dfd200	1030	*/
gmatarrubia	0:820a69dfd200	1031
gmatarrubia	0:820a69dfd200	1032	typedef struct { /!< SWM Structure /
gmatarrubia	0:820a69dfd200	1033	union {
gmatarrubia	0:820a69dfd200	1034	__IO uint32_t PINASSIGN[16];
gmatarrubia	0:820a69dfd200	1035	struct {
gmatarrubia	0:820a69dfd200	1036	__IO uint32_t PINASSIGN0; /*!< Pin assign register 0. Assign movable functions U0_TXD, U0_RXD,
gmatarrubia	0:820a69dfd200	1037	U0_RTS, U0_CTS. */
gmatarrubia	0:820a69dfd200	1038	__IO uint32_t PINASSIGN1; /*!< Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD,
gmatarrubia	0:820a69dfd200	1039	U1_RXD, U1_RTS. */
gmatarrubia	0:820a69dfd200	1040	__IO uint32_t PINASSIGN2; /*!< Pin assign register 2. Assign movable functions U1_CTS, U1_SCLK,
gmatarrubia	0:820a69dfd200	1041	U2_TXD, U2_RXD. */
gmatarrubia	0:820a69dfd200	1042	__IO uint32_t PINASSIGN3; /!< Pin assign register 3. Assign movable function . /
gmatarrubia	0:820a69dfd200	1043	__IO uint32_t PINASSIGN4; /!< Pin assign register 4. Assign movable functions /
gmatarrubia	0:820a69dfd200	1044	__IO uint32_t PINASSIGN5; /!< Pin assign register 5. Assign movable functions /
gmatarrubia	0:820a69dfd200	1045	__IO uint32_t PINASSIGN6; /!< Pin assign register 6. Assign movable functions /
gmatarrubia	0:820a69dfd200	1046	__IO uint32_t PINASSIGN7; /!< Pin assign register 7. Assign movable functions /
gmatarrubia	0:820a69dfd200	1047	__IO uint32_t PINASSIGN8; /!< Pin assign register 8. Assign movable functions /
gmatarrubia	0:820a69dfd200	1048	__IO uint32_t PINASSIGN9; /!< Pin assign register 9. Assign movable functions /
gmatarrubia	0:820a69dfd200	1049	__IO uint32_t PINASSIGN10; /!< Pin assign register 10. Assign movable functions /
gmatarrubia	0:820a69dfd200	1050	__IO uint32_t PINASSIGN11; /!< Pin assign register 11. Assign movable functions /
gmatarrubia	0:820a69dfd200	1051	__IO uint32_t PINASSIGN12; /!< Pin assign register 12. Assign movable functions /
gmatarrubia	0:820a69dfd200	1052	__IO uint32_t PINASSIGN13; /!< Pin assign register 13. Assign movable functions /
gmatarrubia	0:820a69dfd200	1053	__IO uint32_t PINASSIGN14; /!< Pin assign register 14. Assign movable functions /
gmatarrubia	0:820a69dfd200	1054	__IO uint32_t PINASSIGN15; /!< Pin assign register 15. Assign movable functions /
gmatarrubia	0:820a69dfd200	1055	};
gmatarrubia	0:820a69dfd200	1056	};
gmatarrubia	0:820a69dfd200	1057	__I uint32_t RESERVED0[96];
gmatarrubia	0:820a69dfd200	1058	__IO uint32_t PINENABLE0; /!< Pin enable register 0. Enables fixed-pin functions /
gmatarrubia	0:820a69dfd200	1059	__IO uint32_t PINENABLE1; /!< Pin enable register 0. Enables fixed-pin functions /
gmatarrubia	0:820a69dfd200	1060	} LPC_SWM_Type;
gmatarrubia	0:820a69dfd200	1061
gmatarrubia	0:820a69dfd200	1062
gmatarrubia	0:820a69dfd200	1063	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1064	/* ================ PMU ================ */
gmatarrubia	0:820a69dfd200	1065	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1066
gmatarrubia	0:820a69dfd200	1067
gmatarrubia	0:820a69dfd200	1068	/**
gmatarrubia	0:820a69dfd200	1069	* @brief Power Management Unit (PMU) (PMU)
gmatarrubia	0:820a69dfd200	1070	*/
gmatarrubia	0:820a69dfd200	1071
gmatarrubia	0:820a69dfd200	1072	typedef struct { /!< PMU Structure /
gmatarrubia	0:820a69dfd200	1073	__IO uint32_t PCON; /!< Power control register /
gmatarrubia	0:820a69dfd200	1074	__IO uint32_t GPREG0; /!< General purpose register 0 /
gmatarrubia	0:820a69dfd200	1075	__IO uint32_t GPREG1; /!< General purpose register 0 /
gmatarrubia	0:820a69dfd200	1076	__IO uint32_t GPREG2; /!< General purpose register 0 /
gmatarrubia	0:820a69dfd200	1077	__IO uint32_t GPREG3; /!< General purpose register 0 /
gmatarrubia	0:820a69dfd200	1078	__IO uint32_t DPDCTRL; /!< Deep power-down control register /
gmatarrubia	0:820a69dfd200	1079	} LPC_PMU_Type;
gmatarrubia	0:820a69dfd200	1080
gmatarrubia	0:820a69dfd200	1081
gmatarrubia	0:820a69dfd200	1082	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1083	/* ================ USART0 ================ */
gmatarrubia	0:820a69dfd200	1084	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1085
gmatarrubia	0:820a69dfd200	1086
gmatarrubia	0:820a69dfd200	1087	/**
gmatarrubia	0:820a69dfd200	1088	* @brief USART0 (USART0)
gmatarrubia	0:820a69dfd200	1089	*/
gmatarrubia	0:820a69dfd200	1090
gmatarrubia	0:820a69dfd200	1091	typedef struct { /!< USART0 Structure /
gmatarrubia	0:820a69dfd200	1092	__IO uint32_t CFG; /*!< USART Configuration register. Basic USART configuration settings
gmatarrubia	0:820a69dfd200	1093	that typically are not changed during operation. */
gmatarrubia	0:820a69dfd200	1094	__IO uint32_t CTRL; /*!< USART Control register. USART control settings that are more
gmatarrubia	0:820a69dfd200	1095	likely to change during operation. */
gmatarrubia	0:820a69dfd200	1096	__IO uint32_t STAT; /*!< USART Status register. The complete status value can be read
gmatarrubia	0:820a69dfd200	1097	here. Writing ones clears some bits in the register. Some bits
gmatarrubia	0:820a69dfd200	1098	can be cleared by writing a 1 to them. */
gmatarrubia	0:820a69dfd200	1099	__IO uint32_t INTENSET; /*!< Interrupt Enable read and Set register. Contains an individual
gmatarrubia	0:820a69dfd200	1100	interrupt enable bit for each potential USART interrupt. A complete
gmatarrubia	0:820a69dfd200	1101	value may be read from this register. Writing a 1 to any implemented
gmatarrubia	0:820a69dfd200	1102	bit position causes that bit to be set. */
gmatarrubia	0:820a69dfd200	1103	__O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. Allows clearing any combination
gmatarrubia	0:820a69dfd200	1104	of bits in the INTENSET register. Writing a 1 to any implemented
gmatarrubia	0:820a69dfd200	1105	bit position causes the corresponding bit to be cleared. */
gmatarrubia	0:820a69dfd200	1106	__I uint32_t RXDATA; /!< Receiver Data register. Contains the last character received. /
gmatarrubia	0:820a69dfd200	1107	__I uint32_t RXDATASTAT; /*!< Receiver Data with Status register. Combines the last character
gmatarrubia	0:820a69dfd200	1108	received with the current USART receive status. Allows DMA or
gmatarrubia	0:820a69dfd200	1109	software to recover incoming data and status together. */
gmatarrubia	0:820a69dfd200	1110	__IO uint32_t TXDATA; /!< Transmit Data register. Data to be transmitted is written here. /
gmatarrubia	0:820a69dfd200	1111	__IO uint32_t BRG; /*!< Baud Rate Generator register. 16-bit integer baud rate divisor
gmatarrubia	0:820a69dfd200	1112	value. */
gmatarrubia	0:820a69dfd200	1113	__I uint32_t INTSTAT; /*!< Interrupt status register. Reflects interrupts that are currently
gmatarrubia	0:820a69dfd200	1114	enabled. */
gmatarrubia	0:820a69dfd200	1115	} LPC_USART0_Type;
gmatarrubia	0:820a69dfd200	1116
gmatarrubia	0:820a69dfd200	1117
gmatarrubia	0:820a69dfd200	1118	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1119	/* ================ SPI0 ================ */
gmatarrubia	0:820a69dfd200	1120	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1121
gmatarrubia	0:820a69dfd200	1122
gmatarrubia	0:820a69dfd200	1123	/**
gmatarrubia	0:820a69dfd200	1124	* @brief SPI0 (SPI0)
gmatarrubia	0:820a69dfd200	1125	*/
gmatarrubia	0:820a69dfd200	1126
gmatarrubia	0:820a69dfd200	1127	typedef struct { /!< SPI0 Structure /
gmatarrubia	0:820a69dfd200	1128	__IO uint32_t CFG; /!< SPI Configuration register /
gmatarrubia	0:820a69dfd200	1129	__IO uint32_t DLY; /!< SPI Delay register /
gmatarrubia	0:820a69dfd200	1130	__IO uint32_t STAT; /*!< SPI Status. Some status flags can be cleared by writing a 1
gmatarrubia	0:820a69dfd200	1131	to that bit position */
gmatarrubia	0:820a69dfd200	1132	__IO uint32_t INTENSET; /*!< SPI Interrupt Enable read and Set. A complete value may be read
gmatarrubia	0:820a69dfd200	1133	from this register. Writing a 1 to any implemented bit position
gmatarrubia	0:820a69dfd200	1134	causes that bit to be set. */
gmatarrubia	0:820a69dfd200	1135	__O uint32_t INTENCLR; /*!< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit
gmatarrubia	0:820a69dfd200	1136	position causes the corresponding bit in INTENSET to be cleared. */
gmatarrubia	0:820a69dfd200	1137	__I uint32_t RXDAT; /!< SPI Receive Data /
gmatarrubia	0:820a69dfd200	1138	__IO uint32_t TXDATCTL; /!< SPI Transmit Data with Control /
gmatarrubia	0:820a69dfd200	1139	__IO uint32_t TXDAT; /!< SPI Transmit Data with Control /
gmatarrubia	0:820a69dfd200	1140	__IO uint32_t TXCTL; /!< SPI Transmit Control /
gmatarrubia	0:820a69dfd200	1141	__IO uint32_t DIV; /!< SPI clock Divider /
gmatarrubia	0:820a69dfd200	1142	__I uint32_t INTSTAT; /!< SPI Interrupt Status /
gmatarrubia	0:820a69dfd200	1143	} LPC_SPI0_Type;
gmatarrubia	0:820a69dfd200	1144
gmatarrubia	0:820a69dfd200	1145
gmatarrubia	0:820a69dfd200	1146	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1147	/* ================ I2C0 ================ */
gmatarrubia	0:820a69dfd200	1148	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1149
gmatarrubia	0:820a69dfd200	1150
gmatarrubia	0:820a69dfd200	1151	/**
gmatarrubia	0:820a69dfd200	1152	* @brief I2C-bus interface (I2C0)
gmatarrubia	0:820a69dfd200	1153	*/
gmatarrubia	0:820a69dfd200	1154
gmatarrubia	0:820a69dfd200	1155	typedef struct { /!< I2C0 Structure /
gmatarrubia	0:820a69dfd200	1156	__IO uint32_t CFG; /!< Configuration for shared functions. /
gmatarrubia	0:820a69dfd200	1157	__IO uint32_t STAT; /!< Status register for Master, Slave, and Monitor functions. /
gmatarrubia	0:820a69dfd200	1158	__IO uint32_t INTENSET; /!< Interrupt Enable Set and read register. /
gmatarrubia	0:820a69dfd200	1159	__O uint32_t INTENCLR; /!< Interrupt Enable Clear register. /
gmatarrubia	0:820a69dfd200	1160	__IO uint32_t TIMEOUT; /!< Time-out value register. /
gmatarrubia	0:820a69dfd200	1161	__IO uint32_t DIV; /*!< Clock pre-divider for the entire I2C block. This determines
gmatarrubia	0:820a69dfd200	1162	what time increments are used for the MSTTIME and SLVTIME registers. */
gmatarrubia	0:820a69dfd200	1163	__I uint32_t INTSTAT; /!< Interrupt Status register for Master, Slave, and Monitor functions. /
gmatarrubia	0:820a69dfd200	1164	__I uint32_t RESERVED0;
gmatarrubia	0:820a69dfd200	1165	__IO uint32_t MSTCTL; /!< Master control register. /
gmatarrubia	0:820a69dfd200	1166	__IO uint32_t MSTTIME; /!< Master timing configuration. /
gmatarrubia	0:820a69dfd200	1167	__IO uint32_t MSTDAT; /!< Combined Master receiver and transmitter data register. /
gmatarrubia	0:820a69dfd200	1168	__I uint32_t RESERVED1[5];
gmatarrubia	0:820a69dfd200	1169	__IO uint32_t SLVCTL; /!< Slave control register. /
gmatarrubia	0:820a69dfd200	1170	__IO uint32_t SLVDAT; /!< Combined Slave receiver and transmitter data register. /
gmatarrubia	0:820a69dfd200	1171	__IO uint32_t SLVADR0; /!< Slave address 0. /
gmatarrubia	0:820a69dfd200	1172	__IO uint32_t SLVADR1; /!< Slave address 0. /
gmatarrubia	0:820a69dfd200	1173	__IO uint32_t SLVADR2; /!< Slave address 0. /
gmatarrubia	0:820a69dfd200	1174	__IO uint32_t SLVADR3; /!< Slave address 0. /
gmatarrubia	0:820a69dfd200	1175	__IO uint32_t SLVQUAL0; /!< Slave Qualification for address 0. /
gmatarrubia	0:820a69dfd200	1176	__I uint32_t RESERVED2[9];
gmatarrubia	0:820a69dfd200	1177	__I uint32_t MONRXDAT; /!< Monitor receiver data register. /
gmatarrubia	0:820a69dfd200	1178	} LPC_I2C0_Type;
gmatarrubia	0:820a69dfd200	1179
gmatarrubia	0:820a69dfd200	1180
gmatarrubia	0:820a69dfd200	1181	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1182	/* ================ QEI ================ */
gmatarrubia	0:820a69dfd200	1183	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1184
gmatarrubia	0:820a69dfd200	1185
gmatarrubia	0:820a69dfd200	1186	/**
gmatarrubia	0:820a69dfd200	1187	* @brief Quadrature Encoder Interface (QEI) (QEI)
gmatarrubia	0:820a69dfd200	1188	*/
gmatarrubia	0:820a69dfd200	1189
gmatarrubia	0:820a69dfd200	1190	typedef struct { /!< QEI Structure /
gmatarrubia	0:820a69dfd200	1191	__O uint32_t CON; /!< Control register /
gmatarrubia	0:820a69dfd200	1192	__I uint32_t STAT; /!< Encoder status register /
gmatarrubia	0:820a69dfd200	1193	__IO uint32_t CONF; /!< Configuration register /
gmatarrubia	0:820a69dfd200	1194	__I uint32_t POS; /!< Position register /
gmatarrubia	0:820a69dfd200	1195	__IO uint32_t MAXPOS; /!< Maximum position register /
gmatarrubia	0:820a69dfd200	1196	__IO uint32_t CMPOS0; /!< position compare register 0 /
gmatarrubia	0:820a69dfd200	1197	__IO uint32_t CMPOS1; /!< position compare register 1 /
gmatarrubia	0:820a69dfd200	1198	__IO uint32_t CMPOS2; /!< position compare register 2 /
gmatarrubia	0:820a69dfd200	1199	__I uint32_t INXCNT; /!< Index count register /
gmatarrubia	0:820a69dfd200	1200	__IO uint32_t INXCMP0; /!< Index compare register 0 /
gmatarrubia	0:820a69dfd200	1201	__IO uint32_t LOAD; /!< Velocity timer reload register /
gmatarrubia	0:820a69dfd200	1202	__I uint32_t TIME; /!< Velocity timer register /
gmatarrubia	0:820a69dfd200	1203	__I uint32_t VEL; /!< Velocity counter register /
gmatarrubia	0:820a69dfd200	1204	__I uint32_t CAP; /!< Velocity capture register /
gmatarrubia	0:820a69dfd200	1205	__IO uint32_t VELCOMP; /!< Velocity compare register /
gmatarrubia	0:820a69dfd200	1206	__IO uint32_t FILTERPHA; /!< Digital filter register on input phase A (QEI_A) /
gmatarrubia	0:820a69dfd200	1207	__IO uint32_t FILTERPHB; /!< Digital filter register on input phase B (QEI_B) /
gmatarrubia	0:820a69dfd200	1208	__IO uint32_t FILTERINX; /!< Digital filter register on input index (QEI_IDX) /
gmatarrubia	0:820a69dfd200	1209	__IO uint32_t WINDOW; /!< Index acceptance window register /
gmatarrubia	0:820a69dfd200	1210	__IO uint32_t INXCMP1; /!< Index compare register 1 /
gmatarrubia	0:820a69dfd200	1211	__IO uint32_t INXCMP2; /!< Index compare register 2 /
gmatarrubia	0:820a69dfd200	1212	__I uint32_t RESERVED0[993];
gmatarrubia	0:820a69dfd200	1213	__O uint32_t IEC; /!< Interrupt enable clear register /
gmatarrubia	0:820a69dfd200	1214	__O uint32_t IES; /!< Interrupt enable set register /
gmatarrubia	0:820a69dfd200	1215	__I uint32_t INTSTAT; /!< Interrupt status register /
gmatarrubia	0:820a69dfd200	1216	__O uint32_t IE; /!< Interrupt enable clear register /
gmatarrubia	0:820a69dfd200	1217	__O uint32_t CLR; /!< Interrupt status clear register /
gmatarrubia	0:820a69dfd200	1218	__O uint32_t SET; /!< Interrupt status set register /
gmatarrubia	0:820a69dfd200	1219	} LPC_QEI_Type;
gmatarrubia	0:820a69dfd200	1220
gmatarrubia	0:820a69dfd200	1221
gmatarrubia	0:820a69dfd200	1222	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1223	/* ================ SYSCON ================ */
gmatarrubia	0:820a69dfd200	1224	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1225
gmatarrubia	0:820a69dfd200	1226
gmatarrubia	0:820a69dfd200	1227	/**
gmatarrubia	0:820a69dfd200	1228	* @brief System configuration (SYSCON) (SYSCON)
gmatarrubia	0:820a69dfd200	1229	*/
gmatarrubia	0:820a69dfd200	1230
gmatarrubia	0:820a69dfd200	1231	typedef struct { /!< SYSCON Structure /
gmatarrubia	0:820a69dfd200	1232	__IO uint32_t SYSMEMREMAP; /!< System memory remap /
gmatarrubia	0:820a69dfd200	1233	__I uint32_t RESERVED0[4];
gmatarrubia	0:820a69dfd200	1234	__IO uint32_t SYSTCKCAL; /!< System tick counter calibration /
gmatarrubia	0:820a69dfd200	1235	__I uint32_t RESERVED1;
gmatarrubia	0:820a69dfd200	1236	__IO uint32_t NMISRC; /!< NMI Source Control /
gmatarrubia	0:820a69dfd200	1237	__I uint32_t RESERVED2[8];
gmatarrubia	0:820a69dfd200	1238	__IO uint32_t SYSRSTSTAT; /!< System reset status register /
gmatarrubia	0:820a69dfd200	1239	__IO uint32_t PRESETCTRL0; /!< Peripheral reset control 0 /
gmatarrubia	0:820a69dfd200	1240	__IO uint32_t PRESETCTRL1; /!< Peripheral reset control 1 /
gmatarrubia	0:820a69dfd200	1241	__I uint32_t PIOPORCAP0; /!< POR captured PIO status 0 /
gmatarrubia	0:820a69dfd200	1242	__I uint32_t PIOPORCAP1; /!< POR captured PIO status 1 /
gmatarrubia	0:820a69dfd200	1243	__I uint32_t PIOPORCAP2; /!< POR captured PIO status 2 /
gmatarrubia	0:820a69dfd200	1244	__I uint32_t RESERVED3[10];
gmatarrubia	0:820a69dfd200	1245	__IO uint32_t MAINCLKSELA; /!< Main clock source select A /
gmatarrubia	0:820a69dfd200	1246	__IO uint32_t MAINCLKSELB; /!< Main clock source select B /
gmatarrubia	0:820a69dfd200	1247	__IO uint32_t USBCLKSEL; /!< USB clock source select /
gmatarrubia	0:820a69dfd200	1248	__IO uint32_t ADCASYNCCLKSEL; /!< ADC asynchronous clock source select /
gmatarrubia	0:820a69dfd200	1249	__I uint32_t RESERVED4;
gmatarrubia	0:820a69dfd200	1250	__IO uint32_t CLKOUTSELA; /!< CLKOUT clock source select A /
gmatarrubia	0:820a69dfd200	1251	__IO uint32_t CLKOUTSELB; /!< CLKOUT clock source select B /
gmatarrubia	0:820a69dfd200	1252	__I uint32_t RESERVED5;
gmatarrubia	0:820a69dfd200	1253	__IO uint32_t SYSPLLCLKSEL; /!< System PLL clock source select /
gmatarrubia	0:820a69dfd200	1254	__IO uint32_t USBPLLCLKSEL; /!< USB PLL clock source select /
gmatarrubia	0:820a69dfd200	1255	__IO uint32_t SCTPLLCLKSEL; /!< SCT PLL clock source select /
gmatarrubia	0:820a69dfd200	1256	__I uint32_t RESERVED6[5];
gmatarrubia	0:820a69dfd200	1257	__IO uint32_t SYSAHBCLKDIV; /!< System clock divider /
gmatarrubia	0:820a69dfd200	1258	__IO uint32_t SYSAHBCLKCTRL0; /!< System clock control 0 /
gmatarrubia	0:820a69dfd200	1259	__IO uint32_t SYSAHBCLKCTRL1; /!< System clock control 1 /
gmatarrubia	0:820a69dfd200	1260	__IO uint32_t SYSTICKCLKDIV; /!< SYSTICK clock divider /
gmatarrubia	0:820a69dfd200	1261	__IO uint32_t UARTCLKDIV; /*!< USART clock divider. Clock divider for the USART fractional
gmatarrubia	0:820a69dfd200	1262	baud rate generator. */
gmatarrubia	0:820a69dfd200	1263	__IO uint32_t IOCONCLKDIV; /*!< Peripheral clock to the IOCON block for programmable glitch
gmatarrubia	0:820a69dfd200	1264	filter */
gmatarrubia	0:820a69dfd200	1265	__IO uint32_t TRACECLKDIV; /!< ARM trace clock divider /
gmatarrubia	0:820a69dfd200	1266	__I uint32_t RESERVED7[4];
gmatarrubia	0:820a69dfd200	1267	__IO uint32_t USBCLKDIV; /!< USB clock divider /
gmatarrubia	0:820a69dfd200	1268	__IO uint32_t ADCASYNCCLKDIV; /!< Asynchronous ADC clock divider /
gmatarrubia	0:820a69dfd200	1269	__I uint32_t RESERVED8;
gmatarrubia	0:820a69dfd200	1270	__IO uint32_t CLKOUTDIV; /!< CLKOUT clock divider /
gmatarrubia	0:820a69dfd200	1271	__I uint32_t RESERVED9[11];
gmatarrubia	0:820a69dfd200	1272	__IO uint32_t FRGCTRL; /!< USART fractional baud rate generator control /
gmatarrubia	0:820a69dfd200	1273	__IO uint32_t USBCLKCTRL; /!< USB clock control /
gmatarrubia	0:820a69dfd200	1274	__IO uint32_t USBCLKST; /!< USB clock status /
gmatarrubia	0:820a69dfd200	1275	__I uint32_t RESERVED10[19];
gmatarrubia	0:820a69dfd200	1276	__IO uint32_t BODCTRL; /!< Brown-Out Detect /
gmatarrubia	0:820a69dfd200	1277	__I uint32_t RESERVED11;
gmatarrubia	0:820a69dfd200	1278	__IO uint32_t SYSOSCCTRL; /!< System oscillator control /
gmatarrubia	0:820a69dfd200	1279	__I uint32_t RESERVED12;
gmatarrubia	0:820a69dfd200	1280	__IO uint32_t RTCOSCCTRL; /!< RTC oscillator control /
gmatarrubia	0:820a69dfd200	1281	__I uint32_t RESERVED13;
gmatarrubia	0:820a69dfd200	1282	__IO uint32_t SYSPLLCTRL; /!< System PLL control /
gmatarrubia	0:820a69dfd200	1283	__I uint32_t SYSPLLSTAT; /!< System PLL status /
gmatarrubia	0:820a69dfd200	1284	__IO uint32_t USBPLLCTRL; /!< USB PLL control /
gmatarrubia	0:820a69dfd200	1285	__I uint32_t USBPLLSTAT; /!< USB PLL status /
gmatarrubia	0:820a69dfd200	1286	__IO uint32_t SCTPLLCTRL; /!< SCT PLL control /
gmatarrubia	0:820a69dfd200	1287	__I uint32_t SCTPLLSTAT; /!< SCT PLL status /
gmatarrubia	0:820a69dfd200	1288	__I uint32_t RESERVED14[21];
gmatarrubia	0:820a69dfd200	1289	__IO uint32_t PDAWAKECFG; /!< Power-down states for wake-up from deep-sleep /
gmatarrubia	0:820a69dfd200	1290	__IO uint32_t PDRUNCFG; /!< Power configuration register /
gmatarrubia	0:820a69dfd200	1291	__I uint32_t RESERVED15[3];
gmatarrubia	0:820a69dfd200	1292	__IO uint32_t STARTERP0; /!< Start logic 0 wake-up enable register /
gmatarrubia	0:820a69dfd200	1293	__IO uint32_t STARTERP1; /!< Start logic 1 wake-up enable register /
gmatarrubia	0:820a69dfd200	1294	} LPC_SYSCON_Type;
gmatarrubia	0:820a69dfd200	1295
gmatarrubia	0:820a69dfd200	1296
gmatarrubia	0:820a69dfd200	1297	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1298	/* ================ MRT ================ */
gmatarrubia	0:820a69dfd200	1299	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1300
gmatarrubia	0:820a69dfd200	1301
gmatarrubia	0:820a69dfd200	1302	/**
gmatarrubia	0:820a69dfd200	1303	* @brief Multi-Rate Timer (MRT) (MRT)
gmatarrubia	0:820a69dfd200	1304	*/
gmatarrubia	0:820a69dfd200	1305
gmatarrubia	0:820a69dfd200	1306	typedef struct { /!< MRT Structure /
gmatarrubia	0:820a69dfd200	1307	__IO uint32_t INTVAL0; /*!< MRT0 Time interval value register. This value is loaded into
gmatarrubia	0:820a69dfd200	1308	the TIMER0 register. */
gmatarrubia	0:820a69dfd200	1309	__I uint32_t TIMER0; /!< MRT0 Timer register. This register reads the value of the down-counter. /
gmatarrubia	0:820a69dfd200	1310	__IO uint32_t CTRL0; /!< MRT0 Control register. This register controls the MRT0 modes. /
gmatarrubia	0:820a69dfd200	1311	__IO uint32_t STAT0; /!< MRT0 Status register. /
gmatarrubia	0:820a69dfd200	1312	__IO uint32_t INTVAL1; /*!< MRT0 Time interval value register. This value is loaded into
gmatarrubia	0:820a69dfd200	1313	the TIMER0 register. */
gmatarrubia	0:820a69dfd200	1314	__I uint32_t TIMER1; /!< MRT0 Timer register. This register reads the value of the down-counter. /
gmatarrubia	0:820a69dfd200	1315	__IO uint32_t CTRL1; /!< MRT0 Control register. This register controls the MRT0 modes. /
gmatarrubia	0:820a69dfd200	1316	__IO uint32_t STAT1; /!< MRT0 Status register. /
gmatarrubia	0:820a69dfd200	1317	__IO uint32_t INTVAL2; /*!< MRT0 Time interval value register. This value is loaded into
gmatarrubia	0:820a69dfd200	1318	the TIMER0 register. */
gmatarrubia	0:820a69dfd200	1319	__I uint32_t TIMER2; /!< MRT0 Timer register. This register reads the value of the down-counter. /
gmatarrubia	0:820a69dfd200	1320	__IO uint32_t CTRL2; /!< MRT0 Control register. This register controls the MRT0 modes. /
gmatarrubia	0:820a69dfd200	1321	__IO uint32_t STAT2; /!< MRT0 Status register. /
gmatarrubia	0:820a69dfd200	1322	__IO uint32_t INTVAL3; /*!< MRT0 Time interval value register. This value is loaded into
gmatarrubia	0:820a69dfd200	1323	the TIMER0 register. */
gmatarrubia	0:820a69dfd200	1324	__I uint32_t TIMER3; /!< MRT0 Timer register. This register reads the value of the down-counter. /
gmatarrubia	0:820a69dfd200	1325	__IO uint32_t CTRL3; /!< MRT0 Control register. This register controls the MRT0 modes. /
gmatarrubia	0:820a69dfd200	1326	__IO uint32_t STAT3; /!< MRT0 Status register. /
gmatarrubia	0:820a69dfd200	1327	__I uint32_t RESERVED0[45];
gmatarrubia	0:820a69dfd200	1328	__I uint32_t IDLE_CH; /*!< Idle channel register. This register returns the number of the
gmatarrubia	0:820a69dfd200	1329	first idle channel. */
gmatarrubia	0:820a69dfd200	1330	__IO uint32_t IRQ_FLAG; /!< Global interrupt flag register /
gmatarrubia	0:820a69dfd200	1331	} LPC_MRT_Type;
gmatarrubia	0:820a69dfd200	1332
gmatarrubia	0:820a69dfd200	1333
gmatarrubia	0:820a69dfd200	1334	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1335	/* ================ PINT ================ */
gmatarrubia	0:820a69dfd200	1336	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1337
gmatarrubia	0:820a69dfd200	1338
gmatarrubia	0:820a69dfd200	1339	/**
gmatarrubia	0:820a69dfd200	1340	* @brief Pin interruptand pattern match (PINT) (PINT)
gmatarrubia	0:820a69dfd200	1341	*/
gmatarrubia	0:820a69dfd200	1342
gmatarrubia	0:820a69dfd200	1343	typedef struct { /!< PINT Structure /
gmatarrubia	0:820a69dfd200	1344	__IO uint32_t ISEL; /!< Pin Interrupt Mode register /
gmatarrubia	0:820a69dfd200	1345	__IO uint32_t IENR; /!< Pin interrupt level or rising edge interrupt enable register /
gmatarrubia	0:820a69dfd200	1346	__O uint32_t SIENR; /!< Pin interrupt level or rising edge interrupt set register /
gmatarrubia	0:820a69dfd200	1347	__O uint32_t CIENR; /!< Pin interrupt level (rising edge interrupt) clear register /
gmatarrubia	0:820a69dfd200	1348	__IO uint32_t IENF; /*!< Pin interrupt active level or falling edge interrupt enable
gmatarrubia	0:820a69dfd200	1349	register */
gmatarrubia	0:820a69dfd200	1350	__O uint32_t SIENF; /!< Pin interrupt active level or falling edge interrupt set register /
gmatarrubia	0:820a69dfd200	1351	__O uint32_t CIENF; /!< Pin interrupt active level or falling edge interrupt clear register /
gmatarrubia	0:820a69dfd200	1352	__IO uint32_t RISE; /!< Pin interrupt rising edge register /
gmatarrubia	0:820a69dfd200	1353	__IO uint32_t FALL; /!< Pin interrupt falling edge register /
gmatarrubia	0:820a69dfd200	1354	__IO uint32_t IST; /!< Pin interrupt status register /
gmatarrubia	0:820a69dfd200	1355	__IO uint32_t PMCTRL; /!< Pattern match interrupt control register /
gmatarrubia	0:820a69dfd200	1356	__IO uint32_t PMSRC; /!< Pattern match interrupt bit-slice source register /
gmatarrubia	0:820a69dfd200	1357	__IO uint32_t PMCFG; /!< Pattern match interrupt bit slice configuration register /
gmatarrubia	0:820a69dfd200	1358	} LPC_PINT_Type;
gmatarrubia	0:820a69dfd200	1359
gmatarrubia	0:820a69dfd200	1360
gmatarrubia	0:820a69dfd200	1361	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1362	/* ================ GINT0 ================ */
gmatarrubia	0:820a69dfd200	1363	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1364
gmatarrubia	0:820a69dfd200	1365
gmatarrubia	0:820a69dfd200	1366	/**
gmatarrubia	0:820a69dfd200	1367	* @brief Group interrupt 0/1 (GINT0/1) (GINT0)
gmatarrubia	0:820a69dfd200	1368	*/
gmatarrubia	0:820a69dfd200	1369
gmatarrubia	0:820a69dfd200	1370	typedef struct { /!< GINT0 Structure /
gmatarrubia	0:820a69dfd200	1371	__IO uint32_t CTRL; /!< GPIO grouped interrupt control register /
gmatarrubia	0:820a69dfd200	1372	__I uint32_t RESERVED0[7];
gmatarrubia	0:820a69dfd200	1373	__IO uint32_t PORT_POL[3]; /!< GPIO grouped interrupt port 0 polarity register /
gmatarrubia	0:820a69dfd200	1374	__I uint32_t RESERVED1[5];
gmatarrubia	0:820a69dfd200	1375	__IO uint32_t PORT_ENA[3]; /!< GPIO grouped interrupt port 0 enable register /
gmatarrubia	0:820a69dfd200	1376	} LPC_GINT0_Type;
gmatarrubia	0:820a69dfd200	1377
gmatarrubia	0:820a69dfd200	1378
gmatarrubia	0:820a69dfd200	1379	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1380	/* ================ RIT ================ */
gmatarrubia	0:820a69dfd200	1381	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1382
gmatarrubia	0:820a69dfd200	1383
gmatarrubia	0:820a69dfd200	1384	/**
gmatarrubia	0:820a69dfd200	1385	* @brief Repetitive Interrupt Timer (RIT) (RIT)
gmatarrubia	0:820a69dfd200	1386	*/
gmatarrubia	0:820a69dfd200	1387
gmatarrubia	0:820a69dfd200	1388	typedef struct { /!< RIT Structure /
gmatarrubia	0:820a69dfd200	1389	__IO uint32_t COMPVAL; /*!< Compare value LSB register. Holds the 32 LSBs of the compare
gmatarrubia	0:820a69dfd200	1390	value. */
gmatarrubia	0:820a69dfd200	1391	__IO uint32_t MASK; /*!< Mask LSB register. This register holds the 32 LSB s of the mask
gmatarrubia	0:820a69dfd200	1392	value. A 1 written to any bit will force a compare on the corresponding
gmatarrubia	0:820a69dfd200	1393	bit of the counter and compare register. */
gmatarrubia	0:820a69dfd200	1394	__IO uint32_t CTRL; /!< Control register. /
gmatarrubia	0:820a69dfd200	1395	__IO uint32_t COUNTER; /!< Counter LSB register. 32 LSBs of the counter. /
gmatarrubia	0:820a69dfd200	1396	__IO uint32_t COMPVAL_H; /*!< Compare value MSB register. Holds the 16 MSBs of the compare
gmatarrubia	0:820a69dfd200	1397	value. */
gmatarrubia	0:820a69dfd200	1398	__IO uint32_t MASK_H; /*!< Mask MSB register. This register holds the 16 MSBs of the mask
gmatarrubia	0:820a69dfd200	1399	value. A 1 written to any bit will force a compare on the corresponding
gmatarrubia	0:820a69dfd200	1400	bit of the counter and compare register. */
gmatarrubia	0:820a69dfd200	1401	__I uint32_t RESERVED0;
gmatarrubia	0:820a69dfd200	1402	__IO uint32_t COUNTER_H; /!< Counter MSB register. 16 MSBs of the counter. /
gmatarrubia	0:820a69dfd200	1403	} LPC_RIT_Type;
gmatarrubia	0:820a69dfd200	1404
gmatarrubia	0:820a69dfd200	1405
gmatarrubia	0:820a69dfd200	1406	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1407	/* ================ SCTIPU ================ */
gmatarrubia	0:820a69dfd200	1408	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1409
gmatarrubia	0:820a69dfd200	1410
gmatarrubia	0:820a69dfd200	1411	/**
gmatarrubia	0:820a69dfd200	1412	* @brief SCT Input Processing Unit (IPU) (SCTIPU)
gmatarrubia	0:820a69dfd200	1413	*/
gmatarrubia	0:820a69dfd200	1414
gmatarrubia	0:820a69dfd200	1415	typedef struct { /!< SCTIPU Structure /
gmatarrubia	0:820a69dfd200	1416	__IO uint32_t SAMPLE_CTRL; /*!< SCT IPU sample control register. Contains the input mux selects,
gmatarrubia	0:820a69dfd200	1417	latch/sample-enable mux selects, and sample overrride bits for
gmatarrubia	0:820a69dfd200	1418	the SAMPLE module. */
gmatarrubia	0:820a69dfd200	1419	__I uint32_t RESERVED0[7];
gmatarrubia	0:820a69dfd200	1420	__IO uint32_t ABORT_ENABLE0; /*!< SCT IPU abort enable register: Selects which input source contributes
gmatarrubia	0:820a69dfd200	1421	to ORed Abort Output 0. */
gmatarrubia	0:820a69dfd200	1422	__IO uint32_t ABORT_SOURCE0; /*!< SCT IPU abort source register: Status register indicating which
gmatarrubia	0:820a69dfd200	1423	input source caused abort output 0. */
gmatarrubia	0:820a69dfd200	1424	__I uint32_t RESERVED1[6];
gmatarrubia	0:820a69dfd200	1425	__IO uint32_t ABORT_ENABLE1; /*!< SCT IPU abort enable register: Selects which input source contributes
gmatarrubia	0:820a69dfd200	1426	to ORed Abort Output 0. */
gmatarrubia	0:820a69dfd200	1427	__IO uint32_t ABORT_SOURCE1; /*!< SCT IPU abort source register: Status register indicating which
gmatarrubia	0:820a69dfd200	1428	input source caused abort output 0. */
gmatarrubia	0:820a69dfd200	1429	__I uint32_t RESERVED2[6];
gmatarrubia	0:820a69dfd200	1430	__IO uint32_t ABORT_ENABLE2; /*!< SCT IPU abort enable register: Selects which input source contributes
gmatarrubia	0:820a69dfd200	1431	to ORed Abort Output 0. */
gmatarrubia	0:820a69dfd200	1432	__IO uint32_t ABORT_SOURCE2; /*!< SCT IPU abort source register: Status register indicating which
gmatarrubia	0:820a69dfd200	1433	input source caused abort output 0. */
gmatarrubia	0:820a69dfd200	1434	__I uint32_t RESERVED3[6];
gmatarrubia	0:820a69dfd200	1435	__IO uint32_t ABORT_ENABLE3; /*!< SCT IPU abort enable register: Selects which input source contributes
gmatarrubia	0:820a69dfd200	1436	to ORed Abort Output 0. */
gmatarrubia	0:820a69dfd200	1437	__IO uint32_t ABORT_SOURCE3; /*!< SCT IPU abort source register: Status register indicating which
gmatarrubia	0:820a69dfd200	1438	input source caused abort output 0. */
gmatarrubia	0:820a69dfd200	1439	} LPC_SCTIPU_Type;
gmatarrubia	0:820a69dfd200	1440
gmatarrubia	0:820a69dfd200	1441
gmatarrubia	0:820a69dfd200	1442	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1443	/* ================ FLASHCTRL ================ */
gmatarrubia	0:820a69dfd200	1444	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1445
gmatarrubia	0:820a69dfd200	1446
gmatarrubia	0:820a69dfd200	1447	/**
gmatarrubia	0:820a69dfd200	1448	* @brief Flash controller (FLASHCTRL)
gmatarrubia	0:820a69dfd200	1449	*/
gmatarrubia	0:820a69dfd200	1450
gmatarrubia	0:820a69dfd200	1451	typedef struct { /!< FLASHCTRL Structure /
gmatarrubia	0:820a69dfd200	1452	__I uint32_t RESERVED0[8];
gmatarrubia	0:820a69dfd200	1453	__IO uint32_t FMSSTART; /!< Signature start address register /
gmatarrubia	0:820a69dfd200	1454	__IO uint32_t FMSSTOP; /!< Signature stop-address register /
gmatarrubia	0:820a69dfd200	1455	__I uint32_t RESERVED1;
gmatarrubia	0:820a69dfd200	1456	__I uint32_t FMSW0; /!< Signature word /
gmatarrubia	0:820a69dfd200	1457	} LPC_FLASHCTRL_Type;
gmatarrubia	0:820a69dfd200	1458
gmatarrubia	0:820a69dfd200	1459
gmatarrubia	0:820a69dfd200	1460	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1461	/* ================ C_CAN0 ================ */
gmatarrubia	0:820a69dfd200	1462	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1463
gmatarrubia	0:820a69dfd200	1464
gmatarrubia	0:820a69dfd200	1465	/**
gmatarrubia	0:820a69dfd200	1466	* @brief Controller Area Network C_CAN0 (C_CAN0)
gmatarrubia	0:820a69dfd200	1467	*/
gmatarrubia	0:820a69dfd200	1468
gmatarrubia	0:820a69dfd200	1469	typedef struct { /!< C_CAN0 Structure /
gmatarrubia	0:820a69dfd200	1470	__IO uint32_t CANCNTL; /!< CAN control /
gmatarrubia	0:820a69dfd200	1471	__IO uint32_t CANSTAT; /!< Status register /
gmatarrubia	0:820a69dfd200	1472	__I uint32_t CANEC; /!< Error counter /
gmatarrubia	0:820a69dfd200	1473	__IO uint32_t CANBT; /!< Bit timing register /
gmatarrubia	0:820a69dfd200	1474	__I uint32_t CANINT; /!< Interrupt register /
gmatarrubia	0:820a69dfd200	1475	__IO uint32_t CANTEST; /!< Test register /
gmatarrubia	0:820a69dfd200	1476	__IO uint32_t CANBRPE; /!< Baud rate prescaler extension register /
gmatarrubia	0:820a69dfd200	1477	__I uint32_t RESERVED0;
gmatarrubia	0:820a69dfd200	1478	__IO uint32_t CANIF1_CMDREQ; /!< Message interface 1 command request /
gmatarrubia	0:820a69dfd200	1479
gmatarrubia	0:820a69dfd200	1480	union {
gmatarrubia	0:820a69dfd200	1481	__IO uint32_t CANIF1_CMDMSK_R; /!< Message interface 1 command mask (read direction) /
gmatarrubia	0:820a69dfd200	1482	__IO uint32_t CANIF1_CMDMSK_W; /!< Message interface 1 command mask (write direction) /
gmatarrubia	0:820a69dfd200	1483	};
gmatarrubia	0:820a69dfd200	1484	__IO uint32_t CANIF1_MSK1; /!< Message interface 1 mask 1 /
gmatarrubia	0:820a69dfd200	1485	__IO uint32_t CANIF1_MSK2; /!< Message interface 1 mask 2 /
gmatarrubia	0:820a69dfd200	1486	__IO uint32_t CANIF1_ARB1; /!< Message interface 1 arbitration 1 /
gmatarrubia	0:820a69dfd200	1487	__IO uint32_t CANIF1_ARB2; /!< Message interface 1 arbitration 2 /
gmatarrubia	0:820a69dfd200	1488	__IO uint32_t CANIF1_MCTRL; /!< Message interface 1 message control /
gmatarrubia	0:820a69dfd200	1489	__IO uint32_t CANIF1_DA1; /!< Message interface 1 data A1 /
gmatarrubia	0:820a69dfd200	1490	__IO uint32_t CANIF1_DA2; /!< Message interface 1 data A2 /
gmatarrubia	0:820a69dfd200	1491	__IO uint32_t CANIF1_DB1; /!< Message interface 1 data B1 /
gmatarrubia	0:820a69dfd200	1492	__IO uint32_t CANIF1_DB2; /!< Message interface 1 data B2 /
gmatarrubia	0:820a69dfd200	1493	__I uint32_t RESERVED1[13];
gmatarrubia	0:820a69dfd200	1494	__IO uint32_t CANIF2_CMDREQ; /!< Message interface 1 command request /
gmatarrubia	0:820a69dfd200	1495
gmatarrubia	0:820a69dfd200	1496	union {
gmatarrubia	0:820a69dfd200	1497	__IO uint32_t CANIF2_CMDMSK_W; /!< Message interface 1 command mask (write direction) /
gmatarrubia	0:820a69dfd200	1498	__IO uint32_t CANIF2_CMDMSK_R; /!< Message interface 1 command mask (read direction) /
gmatarrubia	0:820a69dfd200	1499	};
gmatarrubia	0:820a69dfd200	1500	__IO uint32_t CANIF2_MSK1; /!< Message interface 1 mask 1 /
gmatarrubia	0:820a69dfd200	1501	__IO uint32_t CANIF2_MSK2; /!< Message interface 1 mask 2 /
gmatarrubia	0:820a69dfd200	1502	__IO uint32_t CANIF2_ARB1; /!< Message interface 1 arbitration 1 /
gmatarrubia	0:820a69dfd200	1503	__IO uint32_t CANIF2_ARB2; /!< Message interface 1 arbitration 2 /
gmatarrubia	0:820a69dfd200	1504	__IO uint32_t CANIF2_MCTRL; /!< Message interface 1 message control /
gmatarrubia	0:820a69dfd200	1505	__IO uint32_t CANIF2_DA1; /!< Message interface 2 data A1 /
gmatarrubia	0:820a69dfd200	1506	__IO uint32_t CANIF2_DA2; /!< Message interface 2 data A2 /
gmatarrubia	0:820a69dfd200	1507	__IO uint32_t CANIF2_DB1; /!< Message interface 2 data B1 /
gmatarrubia	0:820a69dfd200	1508	__IO uint32_t CANIF2_DB2; /!< Message interface 2 data B2 /
gmatarrubia	0:820a69dfd200	1509	__I uint32_t RESERVED2[21];
gmatarrubia	0:820a69dfd200	1510	__I uint32_t CANTXREQ1; /!< Transmission request 1 /
gmatarrubia	0:820a69dfd200	1511	__I uint32_t CANTXREQ2; /!< Transmission request 2 /
gmatarrubia	0:820a69dfd200	1512	__I uint32_t RESERVED3[6];
gmatarrubia	0:820a69dfd200	1513	__I uint32_t CANND1; /!< New data 1 /
gmatarrubia	0:820a69dfd200	1514	__I uint32_t CANND2; /!< New data 2 /
gmatarrubia	0:820a69dfd200	1515	__I uint32_t RESERVED4[6];
gmatarrubia	0:820a69dfd200	1516	__I uint32_t CANIR1; /!< Interrupt pending 1 /
gmatarrubia	0:820a69dfd200	1517	__I uint32_t CANIR2; /!< Interrupt pending 2 /
gmatarrubia	0:820a69dfd200	1518	__I uint32_t RESERVED5[6];
gmatarrubia	0:820a69dfd200	1519	__I uint32_t CANMSGV1; /!< Message valid 1 /
gmatarrubia	0:820a69dfd200	1520	__I uint32_t CANMSGV2; /!< Message valid 2 /
gmatarrubia	0:820a69dfd200	1521	__I uint32_t RESERVED6[6];
gmatarrubia	0:820a69dfd200	1522	__IO uint32_t CANCLKDIV; /!< Can clock divider register /
gmatarrubia	0:820a69dfd200	1523	} LPC_C_CAN0_Type;
gmatarrubia	0:820a69dfd200	1524
gmatarrubia	0:820a69dfd200	1525
gmatarrubia	0:820a69dfd200	1526	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1527	/* ================ SYSCTL ================ */
gmatarrubia	0:820a69dfd200	1528	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1529
gmatarrubia	0:820a69dfd200	1530	/**
gmatarrubia	0:820a69dfd200	1531	* @brief LPC15XX System Control block structure
gmatarrubia	0:820a69dfd200	1532	*/
gmatarrubia	0:820a69dfd200	1533	typedef struct { /!< SYSCTL Structure /
gmatarrubia	0:820a69dfd200	1534	__IO uint32_t SYSMEMREMAP; /!< System Memory remap register /
gmatarrubia	0:820a69dfd200	1535	__I uint32_t RESERVED0[2];
gmatarrubia	0:820a69dfd200	1536	__IO uint32_t AHBBUFEN0;
gmatarrubia	0:820a69dfd200	1537	__IO uint32_t AHBBUFEN1;
gmatarrubia	0:820a69dfd200	1538	__IO uint32_t SYSTCKCAL; /!< System tick counter calibration register /
gmatarrubia	0:820a69dfd200	1539	__I uint32_t RESERVED1[1];
gmatarrubia	0:820a69dfd200	1540	__IO uint32_t NMISRC; /!< NMI source control register /
gmatarrubia	0:820a69dfd200	1541	__I uint32_t RESERVED2[8];
gmatarrubia	0:820a69dfd200	1542	__IO uint32_t SYSRSTSTAT; /!< System Reset Status register /
gmatarrubia	0:820a69dfd200	1543	__IO uint32_t PRESETCTRL[2]; /!< Peripheral reset Control registers /
gmatarrubia	0:820a69dfd200	1544	__I uint32_t PIOPORCAP[3]; /!< POR captured PIO status registers /
gmatarrubia	0:820a69dfd200	1545	__I uint32_t RESERVED3[10];
gmatarrubia	0:820a69dfd200	1546	__IO uint32_t MAINCLKSELA; /!< Main clock source A select register /
gmatarrubia	0:820a69dfd200	1547	__IO uint32_t MAINCLKSELB; /!< Main clock source B select register /
gmatarrubia	0:820a69dfd200	1548	__IO uint32_t USBCLKSEL; /!< USB clock source select register /
gmatarrubia	0:820a69dfd200	1549	__IO uint32_t ADCASYNCCLKSEL; /!< ADC asynchronous clock source select register /
gmatarrubia	0:820a69dfd200	1550	__I uint32_t RESERVED4[1];
gmatarrubia	0:820a69dfd200	1551	__IO uint32_t CLKOUTSEL[2]; /!< Clock out source select registers /
gmatarrubia	0:820a69dfd200	1552	__I uint32_t RESERVED5[1];
gmatarrubia	0:820a69dfd200	1553	__IO uint32_t SYSPLLCLKSEL; /!< System PLL clock source select register /
gmatarrubia	0:820a69dfd200	1554	__IO uint32_t USBPLLCLKSEL; /!< USB PLL clock source select register /
gmatarrubia	0:820a69dfd200	1555	__IO uint32_t SCTPLLCLKSEL; /!< SCT PLL clock source select register /
gmatarrubia	0:820a69dfd200	1556	__I uint32_t RESERVED6[5];
gmatarrubia	0:820a69dfd200	1557	__IO uint32_t SYSAHBCLKDIV; /!< System Clock divider register /
gmatarrubia	0:820a69dfd200	1558	__IO uint32_t SYSAHBCLKCTRL[2];/!< System clock control registers /
gmatarrubia	0:820a69dfd200	1559	__IO uint32_t SYSTICKCLKDIV; /!< SYSTICK clock divider /
gmatarrubia	0:820a69dfd200	1560	__IO uint32_t UARTCLKDIV; /!< UART clock divider register /
gmatarrubia	0:820a69dfd200	1561	__IO uint32_t IOCONCLKDIV; /!< programmable glitch filter divider registers for IOCON /
gmatarrubia	0:820a69dfd200	1562	__IO uint32_t TRACECLKDIV; /!< ARM trace clock divider register /
gmatarrubia	0:820a69dfd200	1563	__I uint32_t RESERVED7[4];
gmatarrubia	0:820a69dfd200	1564	__IO uint32_t USBCLKDIV; /!< USB clock source divider register /
gmatarrubia	0:820a69dfd200	1565	__IO uint32_t ADCASYNCCLKDIV; /!< Asynchronous ADC clock divider /
gmatarrubia	0:820a69dfd200	1566	__I uint32_t RESERVED8[1];
gmatarrubia	0:820a69dfd200	1567	__IO uint32_t CLKOUTDIV; /!< Clock out divider register /
gmatarrubia	0:820a69dfd200	1568	__I uint32_t RESERVED9[9];
gmatarrubia	0:820a69dfd200	1569	__IO uint32_t FREQMECTRL; /!< Frequency measure register /
gmatarrubia	0:820a69dfd200	1570	__IO uint32_t FLASHCFG; /!< Flash configuration register /
gmatarrubia	0:820a69dfd200	1571	__IO uint32_t FRGCTRL; /!< USART fractional baud rate generator control register /
gmatarrubia	0:820a69dfd200	1572	__IO uint32_t USBCLKCTRL; /!< USB clock control register /
gmatarrubia	0:820a69dfd200	1573	__I uint32_t USBCLKST; /!< USB clock status register /
gmatarrubia	0:820a69dfd200	1574	__I uint32_t RESERVED10[19];
gmatarrubia	0:820a69dfd200	1575	__IO uint32_t BODCTRL; /!< Brown Out Detect register /
gmatarrubia	0:820a69dfd200	1576	__I uint32_t IRCCTRL;
gmatarrubia	0:820a69dfd200	1577	__IO uint32_t SYSOSCCTRL; /!< System Oscillator control register /
gmatarrubia	0:820a69dfd200	1578	__I uint32_t RESERVED11[1];
gmatarrubia	0:820a69dfd200	1579	__IO uint32_t RTCOSCCTRL; /!< RTC Oscillator control register /
gmatarrubia	0:820a69dfd200	1580	__I uint32_t RESERVED12[1];
gmatarrubia	0:820a69dfd200	1581	__IO uint32_t SYSPLLCTRL; /!< System PLL control register /
gmatarrubia	0:820a69dfd200	1582	__I uint32_t SYSPLLSTAT; /!< System PLL status register /
gmatarrubia	0:820a69dfd200	1583	__IO uint32_t USBPLLCTRL; /!< USB PLL control register /
gmatarrubia	0:820a69dfd200	1584	__I uint32_t USBPLLSTAT; /!< USB PLL status register /
gmatarrubia	0:820a69dfd200	1585	__IO uint32_t SCTPLLCTRL; /!< SCT PLL control register /
gmatarrubia	0:820a69dfd200	1586	__I uint32_t SCTPLLSTAT; /!< SCT PLL status register /
gmatarrubia	0:820a69dfd200	1587	__I uint32_t RESERVED13[21];
gmatarrubia	0:820a69dfd200	1588	__IO uint32_t PDWAKECFG; /!< Power down states in wake up from deep sleep register /
gmatarrubia	0:820a69dfd200	1589	__IO uint32_t PDRUNCFG; /!< Power configuration register/
gmatarrubia	0:820a69dfd200	1590	__I uint32_t RESERVED14[3];
gmatarrubia	0:820a69dfd200	1591	__IO uint32_t STARTERP[2]; /!< Start logic interrupt wake-up enable registers /
gmatarrubia	0:820a69dfd200	1592	__I uint32_t RESERVED15[117];
gmatarrubia	0:820a69dfd200	1593	__I uint32_t JTAG_IDCODE; /!< JTAG ID code register /
gmatarrubia	0:820a69dfd200	1594	__I uint32_t DEVICEID[2]; /!< Device ID registers /
gmatarrubia	0:820a69dfd200	1595	} LPC_SYSCTL_Type;
gmatarrubia	0:820a69dfd200	1596
gmatarrubia	0:820a69dfd200	1597
gmatarrubia	0:820a69dfd200	1598	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1599	/* ================ IOCON ================ */
gmatarrubia	0:820a69dfd200	1600	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1601
gmatarrubia	0:820a69dfd200	1602
gmatarrubia	0:820a69dfd200	1603	/**
gmatarrubia	0:820a69dfd200	1604	* @brief I/O pin configuration (IOCON) (IOCON)
gmatarrubia	0:820a69dfd200	1605	*/
gmatarrubia	0:820a69dfd200	1606
gmatarrubia	0:820a69dfd200	1607	typedef struct { /!< IOCON Structure /
gmatarrubia	0:820a69dfd200	1608	__IO uint32_t PIO0_0; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
gmatarrubia	0:820a69dfd200	1609	__IO uint32_t PIO0_1; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
gmatarrubia	0:820a69dfd200	1610	__IO uint32_t PIO0_2; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
gmatarrubia	0:820a69dfd200	1611	__IO uint32_t PIO0_3; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
gmatarrubia	0:820a69dfd200	1612	__IO uint32_t PIO0_4; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
gmatarrubia	0:820a69dfd200	1613	__IO uint32_t PIO0_5; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
gmatarrubia	0:820a69dfd200	1614	__IO uint32_t PIO0_6; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
gmatarrubia	0:820a69dfd200	1615	__IO uint32_t PIO0_7; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
gmatarrubia	0:820a69dfd200	1616	__IO uint32_t PIO0_8; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
gmatarrubia	0:820a69dfd200	1617	__IO uint32_t PIO0_9; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
gmatarrubia	0:820a69dfd200	1618	__IO uint32_t PIO0_10; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
gmatarrubia	0:820a69dfd200	1619	__IO uint32_t PIO0_11; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
gmatarrubia	0:820a69dfd200	1620	__IO uint32_t PIO0_12; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
gmatarrubia	0:820a69dfd200	1621	__IO uint32_t PIO0_13; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
gmatarrubia	0:820a69dfd200	1622	__IO uint32_t PIO0_14; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
gmatarrubia	0:820a69dfd200	1623	__IO uint32_t PIO0_15; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
gmatarrubia	0:820a69dfd200	1624	__IO uint32_t PIO0_16; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
gmatarrubia	0:820a69dfd200	1625	__IO uint32_t PIO0_17; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
gmatarrubia	0:820a69dfd200	1626	__IO uint32_t PIO0_18; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
gmatarrubia	0:820a69dfd200	1627	__IO uint32_t PIO0_19; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
gmatarrubia	0:820a69dfd200	1628	__IO uint32_t PIO0_20; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
gmatarrubia	0:820a69dfd200	1629	__IO uint32_t PIO0_21; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
gmatarrubia	0:820a69dfd200	1630	__IO uint32_t PIO0_22; /*!< I/O control for open-drain pin PIO0_22. This pin is used for
gmatarrubia	0:820a69dfd200	1631	the I2C-bus SCL function. */
gmatarrubia	0:820a69dfd200	1632	__IO uint32_t PIO0_23; /*!< I/O control for open-drain pin PIO0_22. This pin is used for
gmatarrubia	0:820a69dfd200	1633	the I2C-bus SCL function. */
gmatarrubia	0:820a69dfd200	1634	__IO uint32_t PIO0_24; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
gmatarrubia	0:820a69dfd200	1635	__IO uint32_t PIO0_25; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
gmatarrubia	0:820a69dfd200	1636	__IO uint32_t PIO0_26; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
gmatarrubia	0:820a69dfd200	1637	__IO uint32_t PIO0_27; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
gmatarrubia	0:820a69dfd200	1638	__IO uint32_t PIO0_28; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
gmatarrubia	0:820a69dfd200	1639	__IO uint32_t PIO0_29; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
gmatarrubia	0:820a69dfd200	1640	__IO uint32_t PIO0_30; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
gmatarrubia	0:820a69dfd200	1641	__IO uint32_t PIO0_31; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
gmatarrubia	0:820a69dfd200	1642	__IO uint32_t PIO1_0; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1643	__IO uint32_t PIO1_1; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1644	__IO uint32_t PIO1_2; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1645	__IO uint32_t PIO1_3; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1646	__IO uint32_t PIO1_4; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1647	__IO uint32_t PIO1_5; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1648	__IO uint32_t PIO1_6; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1649	__IO uint32_t PIO1_7; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1650	__IO uint32_t PIO1_8; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1651	__IO uint32_t PIO1_9; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1652	__IO uint32_t PIO1_10; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1653	__IO uint32_t PIO1_11; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1654	__IO uint32_t PIO1_12; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1655	__IO uint32_t PIO1_13; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1656	__IO uint32_t PIO1_14; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1657	__IO uint32_t PIO1_15; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1658	__IO uint32_t PIO1_16; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1659	__IO uint32_t PIO1_17; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1660	__IO uint32_t PIO1_18; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1661	__IO uint32_t PIO1_19; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1662	__IO uint32_t PIO1_20; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1663	__IO uint32_t PIO1_21; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1664	__IO uint32_t PIO1_22; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1665	__IO uint32_t PIO1_23; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1666	__IO uint32_t PIO1_24; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1667	__IO uint32_t PIO1_25; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1668	__IO uint32_t PIO1_26; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1669	__IO uint32_t PIO1_27; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1670	__IO uint32_t PIO1_28; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1671	__IO uint32_t PIO1_29; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1672	__IO uint32_t PIO1_30; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1673	__IO uint32_t PIO1_31; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
gmatarrubia	0:820a69dfd200	1674	__IO uint32_t PIO2_0; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
gmatarrubia	0:820a69dfd200	1675	__IO uint32_t PIO2_1; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
gmatarrubia	0:820a69dfd200	1676	__IO uint32_t PIO2_2; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
gmatarrubia	0:820a69dfd200	1677	__IO uint32_t PIO2_3; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
gmatarrubia	0:820a69dfd200	1678	__IO uint32_t PIO2_4; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
gmatarrubia	0:820a69dfd200	1679	__IO uint32_t PIO2_5; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
gmatarrubia	0:820a69dfd200	1680	__IO uint32_t PIO2_6; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
gmatarrubia	0:820a69dfd200	1681	__IO uint32_t PIO2_7; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
gmatarrubia	0:820a69dfd200	1682	__IO uint32_t PIO2_8; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
gmatarrubia	0:820a69dfd200	1683	__IO uint32_t PIO2_9; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
gmatarrubia	0:820a69dfd200	1684	__IO uint32_t PIO2_10; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
gmatarrubia	0:820a69dfd200	1685	__IO uint32_t PIO2_11; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
gmatarrubia	0:820a69dfd200	1686	} LPC_IOCON_Type;
gmatarrubia	0:820a69dfd200	1687
gmatarrubia	0:820a69dfd200	1688
gmatarrubia	0:820a69dfd200	1689	/* -------------------- End of section using anonymous unions ------------------- */
gmatarrubia	0:820a69dfd200	1690	#if defined(__CC_ARM)
gmatarrubia	0:820a69dfd200	1691	#pragma pop
gmatarrubia	0:820a69dfd200	1692	#elif defined(__ICCARM__)
gmatarrubia	0:820a69dfd200	1693	/* leave anonymous unions enabled */
gmatarrubia	0:820a69dfd200	1694	#elif defined(__GNUC__)
gmatarrubia	0:820a69dfd200	1695	/* anonymous unions are enabled by default */
gmatarrubia	0:820a69dfd200	1696	#elif defined(__TMS470__)
gmatarrubia	0:820a69dfd200	1697	/* anonymous unions are enabled by default */
gmatarrubia	0:820a69dfd200	1698	#elif defined(__TASKING__)
gmatarrubia	0:820a69dfd200	1699	#pragma warning restore
gmatarrubia	0:820a69dfd200	1700	#else
gmatarrubia	0:820a69dfd200	1701	#warning Not supported compiler type
gmatarrubia	0:820a69dfd200	1702	#endif
gmatarrubia	0:820a69dfd200	1703
gmatarrubia	0:820a69dfd200	1704
gmatarrubia	0:820a69dfd200	1705
gmatarrubia	0:820a69dfd200	1706
gmatarrubia	0:820a69dfd200	1707	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1708	/* ================ Peripheral memory map ================ */
gmatarrubia	0:820a69dfd200	1709	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1710
gmatarrubia	0:820a69dfd200	1711	#define LPC_GPIO_PORT_BASE 0x1C000000UL
gmatarrubia	0:820a69dfd200	1712	#define LPC_DMA_BASE 0x1C004000UL
gmatarrubia	0:820a69dfd200	1713	#define LPC_USB_BASE 0x1C00C000UL
gmatarrubia	0:820a69dfd200	1714	#define LPC_CRC_BASE 0x1C010000UL
gmatarrubia	0:820a69dfd200	1715	#define LPC_SCT0_BASE 0x1C018000UL
gmatarrubia	0:820a69dfd200	1716	#define LPC_SCT1_BASE 0x1C01C000UL
gmatarrubia	0:820a69dfd200	1717	#define LPC_SCT2_BASE 0x1C020000UL
gmatarrubia	0:820a69dfd200	1718	#define LPC_SCT3_BASE 0x1C024000UL
gmatarrubia	0:820a69dfd200	1719	#define LPC_ADC0_BASE 0x40000000UL
gmatarrubia	0:820a69dfd200	1720	#define LPC_DAC_BASE 0x40004000UL
gmatarrubia	0:820a69dfd200	1721	#define LPC_ACMP_BASE 0x40008000UL
gmatarrubia	0:820a69dfd200	1722	#define LPC_INMUX_BASE 0x40014000UL
gmatarrubia	0:820a69dfd200	1723	#define LPC_RTC_BASE 0x40028000UL
gmatarrubia	0:820a69dfd200	1724	#define LPC_WWDT_BASE 0x4002C000UL
gmatarrubia	0:820a69dfd200	1725	#define LPC_SWM_BASE 0x40038000UL
gmatarrubia	0:820a69dfd200	1726	#define LPC_PMU_BASE 0x4003C000UL
gmatarrubia	0:820a69dfd200	1727	#define LPC_USART0_BASE 0x40040000UL
gmatarrubia	0:820a69dfd200	1728	#define LPC_USART1_BASE 0x40044000UL
gmatarrubia	0:820a69dfd200	1729	#define LPC_SPI0_BASE 0x40048000UL
gmatarrubia	0:820a69dfd200	1730	#define LPC_SPI1_BASE 0x4004C000UL
gmatarrubia	0:820a69dfd200	1731	#define LPC_I2C0_BASE 0x40050000UL
gmatarrubia	0:820a69dfd200	1732	#define LPC_QEI_BASE 0x40058000UL
gmatarrubia	0:820a69dfd200	1733	#define LPC_SYSCON_BASE 0x40074000UL
gmatarrubia	0:820a69dfd200	1734	#define LPC_ADC1_BASE 0x40080000UL
gmatarrubia	0:820a69dfd200	1735	#define LPC_MRT_BASE 0x400A0000UL
gmatarrubia	0:820a69dfd200	1736	#define LPC_PINT_BASE 0x400A4000UL
gmatarrubia	0:820a69dfd200	1737	#define LPC_GINT0_BASE 0x400A8000UL
gmatarrubia	0:820a69dfd200	1738	#define LPC_GINT1_BASE 0x400AC000UL
gmatarrubia	0:820a69dfd200	1739	#define LPC_RIT_BASE 0x400B4000UL
gmatarrubia	0:820a69dfd200	1740	#define LPC_SCTIPU_BASE 0x400B8000UL
gmatarrubia	0:820a69dfd200	1741	#define LPC_FLASHCTRL_BASE 0x400BC000UL
gmatarrubia	0:820a69dfd200	1742	#define LPC_USART2_BASE 0x400C0000UL
gmatarrubia	0:820a69dfd200	1743	#define LPC_C_CAN0_BASE 0x400F0000UL
gmatarrubia	0:820a69dfd200	1744	#define LPC_IOCON_BASE 0x400F8000UL
gmatarrubia	0:820a69dfd200	1745	#define LPC_EEPROM_BASE 0x400FC000UL
gmatarrubia	0:820a69dfd200	1746	#define LPC_SYSCTL_BASE 0x40074000UL
gmatarrubia	0:820a69dfd200	1747
gmatarrubia	0:820a69dfd200	1748	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1749	/* ================ Peripheral declaration ================ */
gmatarrubia	0:820a69dfd200	1750	/* ================================================================================ */
gmatarrubia	0:820a69dfd200	1751
gmatarrubia	0:820a69dfd200	1752	#define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
gmatarrubia	0:820a69dfd200	1753	#define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
gmatarrubia	0:820a69dfd200	1754	#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
gmatarrubia	0:820a69dfd200	1755	#define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
gmatarrubia	0:820a69dfd200	1756	#define LPC_SCT0 ((LPC_SCT0_Type *) LPC_SCT0_BASE)
gmatarrubia	0:820a69dfd200	1757	#define LPC_SCT1 ((LPC_SCT0_Type *) LPC_SCT1_BASE)
gmatarrubia	0:820a69dfd200	1758	#define LPC_SCT2 ((LPC_SCT2_Type *) LPC_SCT2_BASE)
gmatarrubia	0:820a69dfd200	1759	#define LPC_SCT3 ((LPC_SCT2_Type *) LPC_SCT3_BASE)
gmatarrubia	0:820a69dfd200	1760	#define LPC_ADC0 ((LPC_ADC0_Type *) LPC_ADC0_BASE)
gmatarrubia	0:820a69dfd200	1761	#define LPC_DAC ((LPC_DAC_Type *) LPC_DAC_BASE)
gmatarrubia	0:820a69dfd200	1762	#define LPC_ACMP ((LPC_ACMP_Type *) LPC_ACMP_BASE)
gmatarrubia	0:820a69dfd200	1763	#define LPC_INMUX ((LPC_INMUX_Type *) LPC_INMUX_BASE)
gmatarrubia	0:820a69dfd200	1764	#define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE)
gmatarrubia	0:820a69dfd200	1765	#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
gmatarrubia	0:820a69dfd200	1766	#define LPC_SWM ((LPC_SWM_Type *) LPC_SWM_BASE)
gmatarrubia	0:820a69dfd200	1767	#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
gmatarrubia	0:820a69dfd200	1768	#define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
gmatarrubia	0:820a69dfd200	1769	#define LPC_USART1 ((LPC_USART0_Type *) LPC_USART1_BASE)
gmatarrubia	0:820a69dfd200	1770	#define LPC_SPI0 ((LPC_SPI0_Type *) LPC_SPI0_BASE)
gmatarrubia	0:820a69dfd200	1771	#define LPC_SPI1 ((LPC_SPI0_Type *) LPC_SPI1_BASE)
gmatarrubia	0:820a69dfd200	1772	#define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
gmatarrubia	0:820a69dfd200	1773	#define LPC_QEI ((LPC_QEI_Type *) LPC_QEI_BASE)
gmatarrubia	0:820a69dfd200	1774	#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
gmatarrubia	0:820a69dfd200	1775	#define LPC_ADC1 ((LPC_ADC0_Type *) LPC_ADC1_BASE)
gmatarrubia	0:820a69dfd200	1776	#define LPC_MRT ((LPC_MRT_Type *) LPC_MRT_BASE)
gmatarrubia	0:820a69dfd200	1777	#define LPC_PINT ((LPC_PINT_Type *) LPC_PINT_BASE)
gmatarrubia	0:820a69dfd200	1778	#define LPC_GINT0 ((LPC_GINT0_Type *) LPC_GINT0_BASE)
gmatarrubia	0:820a69dfd200	1779	#define LPC_GINT1 ((LPC_GINT0_Type *) LPC_GINT1_BASE)
gmatarrubia	0:820a69dfd200	1780	#define LPC_RIT ((LPC_RIT_Type *) LPC_RIT_BASE)
gmatarrubia	0:820a69dfd200	1781	#define LPC_SCTIPU ((LPC_SCTIPU_Type *) LPC_SCTIPU_BASE)
gmatarrubia	0:820a69dfd200	1782	#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
gmatarrubia	0:820a69dfd200	1783	#define LPC_USART2 ((LPC_USART0_Type *) LPC_USART2_BASE)
gmatarrubia	0:820a69dfd200	1784	#define LPC_C_CAN0 ((LPC_C_CAN0_Type *) LPC_C_CAN0_BASE)
gmatarrubia	0:820a69dfd200	1785	#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
gmatarrubia	0:820a69dfd200	1786	#define LPC_SYSCTL ((LPC_SYSCTL_Type *) LPC_SYSCTL_BASE)
gmatarrubia	0:820a69dfd200	1787
gmatarrubia	0:820a69dfd200	1788	/** @} / / End of group Device_Peripheral_Registers */
gmatarrubia	0:820a69dfd200	1789	/** @} / / End of group LPC15xx */
gmatarrubia	0:820a69dfd200	1790	/** @} / / End of group (null) */
gmatarrubia	0:820a69dfd200	1791
gmatarrubia	0:820a69dfd200	1792	#ifdef __cplusplus
gmatarrubia	0:820a69dfd200	1793	}
gmatarrubia	0:820a69dfd200	1794	#endif
gmatarrubia	0:820a69dfd200	1795
gmatarrubia	0:820a69dfd200	1796
gmatarrubia	0:820a69dfd200	1797	#endif /* LPC15XX_H */
gmatarrubia	0:820a69dfd200	1798

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Type:	Library
Created:	14 Apr 2015
Imports:	10
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	0
Followers:	2

mbed/TARGET_LPC1549/LPC15xx.h@0:820a69dfd200, 2015-04-14 (annotated)

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