try15_flash_write_register - flash

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Kim GiJeong / Mbed 2 deprecated try15_flash_write_register

flash

stm32f4xx_flash.c@0:d885866e7cbf, 2019-08-12 (annotated)

Committer:: GiJeongKim
Date:: Mon Aug 12 09:16:40 2019 +0000
Revision:: 0:d885866e7cbf

flash memory;

Who changed what in which revision?

User	Revision	Line number	New contents of line
GiJeongKim	0:d885866e7cbf	1	/**
GiJeongKim	0:d885866e7cbf	2	******************************************************************************
GiJeongKim	0:d885866e7cbf	3	* @file stm32f4xx_flash.c
GiJeongKim	0:d885866e7cbf	4	* @author MCD Application Team
GiJeongKim	0:d885866e7cbf	5	* @version V1.7.1
GiJeongKim	0:d885866e7cbf	6	* @date 20-May-2016
GiJeongKim	0:d885866e7cbf	7	* @brief This file provides firmware functions to manage the following
GiJeongKim	0:d885866e7cbf	8	* functionalities of the FLASH peripheral:
GiJeongKim	0:d885866e7cbf	9	* + FLASH Interface configuration
GiJeongKim	0:d885866e7cbf	10	* + FLASH Memory Programming
GiJeongKim	0:d885866e7cbf	11	* + Option Bytes Programming
GiJeongKim	0:d885866e7cbf	12	* + Interrupts and flags management
GiJeongKim	0:d885866e7cbf	13	*
GiJeongKim	0:d885866e7cbf	14	@verbatim
GiJeongKim	0:d885866e7cbf	15	===============================================================================
GiJeongKim	0:d885866e7cbf	16	##### How to use this driver #####
GiJeongKim	0:d885866e7cbf	17	===============================================================================
GiJeongKim	0:d885866e7cbf	18	[..]
GiJeongKim	0:d885866e7cbf	19	This driver provides functions to configure and program the FLASH memory
GiJeongKim	0:d885866e7cbf	20	of all STM32F4xx devices. These functions are split in 4 groups:
GiJeongKim	0:d885866e7cbf	21
GiJeongKim	0:d885866e7cbf	22	(#) FLASH Interface configuration functions: this group includes the
GiJeongKim	0:d885866e7cbf	23	management of the following features:
GiJeongKim	0:d885866e7cbf	24	(++) Set the latency
GiJeongKim	0:d885866e7cbf	25	(++) Enable/Disable the prefetch buffer
GiJeongKim	0:d885866e7cbf	26	(++) Enable/Disable the Instruction cache and the Data cache
GiJeongKim	0:d885866e7cbf	27	(++) Reset the Instruction cache and the Data cache
GiJeongKim	0:d885866e7cbf	28
GiJeongKim	0:d885866e7cbf	29	(#) FLASH Memory Programming functions: this group includes all needed
GiJeongKim	0:d885866e7cbf	30	functions to erase and program the main memory:
GiJeongKim	0:d885866e7cbf	31	(++) Lock and Unlock the FLASH interface
GiJeongKim	0:d885866e7cbf	32	(++) Erase function: Erase sector, erase all sectors
GiJeongKim	0:d885866e7cbf	33	(++) Program functions: byte, half word, word and double word
GiJeongKim	0:d885866e7cbf	34
GiJeongKim	0:d885866e7cbf	35	(#) Option Bytes Programming functions: this group includes all needed
GiJeongKim	0:d885866e7cbf	36	functions to manage the Option Bytes:
GiJeongKim	0:d885866e7cbf	37	(++) Set/Reset the write protection
GiJeongKim	0:d885866e7cbf	38	(++) Set the Read protection Level
GiJeongKim	0:d885866e7cbf	39	(++) Set the BOR level
GiJeongKim	0:d885866e7cbf	40	(++) Program the user Option Bytes
GiJeongKim	0:d885866e7cbf	41	(++) Launch the Option Bytes loader
GiJeongKim	0:d885866e7cbf	42
GiJeongKim	0:d885866e7cbf	43	(#) Interrupts and flags management functions: this group
GiJeongKim	0:d885866e7cbf	44	includes all needed functions to:
GiJeongKim	0:d885866e7cbf	45	(++) Enable/Disable the FLASH interrupt sources
GiJeongKim	0:d885866e7cbf	46	(++) Get flags status
GiJeongKim	0:d885866e7cbf	47	(++) Clear flags
GiJeongKim	0:d885866e7cbf	48	(++) Get FLASH operation status
GiJeongKim	0:d885866e7cbf	49	(++) Wait for last FLASH operation
GiJeongKim	0:d885866e7cbf	50	@endverbatim
GiJeongKim	0:d885866e7cbf	51	******************************************************************************
GiJeongKim	0:d885866e7cbf	52	* @attention
GiJeongKim	0:d885866e7cbf	53	*
GiJeongKim	0:d885866e7cbf	54	* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
GiJeongKim	0:d885866e7cbf	55	*
GiJeongKim	0:d885866e7cbf	56	* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
GiJeongKim	0:d885866e7cbf	57	* You may not use this file except in compliance with the License.
GiJeongKim	0:d885866e7cbf	58	* You may obtain a copy of the License at:
GiJeongKim	0:d885866e7cbf	59	*
GiJeongKim	0:d885866e7cbf	60	* http://www.st.com/software_license_agreement_liberty_v2
GiJeongKim	0:d885866e7cbf	61	*
GiJeongKim	0:d885866e7cbf	62	* Unless required by applicable law or agreed to in writing, software
GiJeongKim	0:d885866e7cbf	63	* distributed under the License is distributed on an "AS IS" BASIS,
GiJeongKim	0:d885866e7cbf	64	* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
GiJeongKim	0:d885866e7cbf	65	* See the License for the specific language governing permissions and
GiJeongKim	0:d885866e7cbf	66	* limitations under the License.
GiJeongKim	0:d885866e7cbf	67	*
GiJeongKim	0:d885866e7cbf	68	******************************************************************************
GiJeongKim	0:d885866e7cbf	69	*/
GiJeongKim	0:d885866e7cbf	70
GiJeongKim	0:d885866e7cbf	71	/* Includes ------------------------------------------------------------------*/
GiJeongKim	0:d885866e7cbf	72	#include "stm32f4xx_flash.h"
GiJeongKim	0:d885866e7cbf	73
GiJeongKim	0:d885866e7cbf	74	/** @addtogroup STM32F4xx_StdPeriph_Driver
GiJeongKim	0:d885866e7cbf	75	* @{
GiJeongKim	0:d885866e7cbf	76	*/
GiJeongKim	0:d885866e7cbf	77
GiJeongKim	0:d885866e7cbf	78	/** @defgroup FLASH
GiJeongKim	0:d885866e7cbf	79	* @brief FLASH driver modules
GiJeongKim	0:d885866e7cbf	80	* @{
GiJeongKim	0:d885866e7cbf	81	*/
GiJeongKim	0:d885866e7cbf	82
GiJeongKim	0:d885866e7cbf	83	/* Private typedef -----------------------------------------------------------*/
GiJeongKim	0:d885866e7cbf	84	/* Private define ------------------------------------------------------------*/
GiJeongKim	0:d885866e7cbf	85	#define SECTOR_MASK ((uint32_t)0xFFFFFF07)
GiJeongKim	0:d885866e7cbf	86
GiJeongKim	0:d885866e7cbf	87	/* Private macro -------------------------------------------------------------*/
GiJeongKim	0:d885866e7cbf	88	/* Private variables ---------------------------------------------------------*/
GiJeongKim	0:d885866e7cbf	89	/* Private function prototypes -----------------------------------------------*/
GiJeongKim	0:d885866e7cbf	90	/* Private functions ---------------------------------------------------------*/
GiJeongKim	0:d885866e7cbf	91
GiJeongKim	0:d885866e7cbf	92	/** @defgroup FLASH_Private_Functions
GiJeongKim	0:d885866e7cbf	93	* @{
GiJeongKim	0:d885866e7cbf	94	*/
GiJeongKim	0:d885866e7cbf	95
GiJeongKim	0:d885866e7cbf	96	/** @defgroup FLASH_Group1 FLASH Interface configuration functions
GiJeongKim	0:d885866e7cbf	97	* @brief FLASH Interface configuration functions
GiJeongKim	0:d885866e7cbf	98	*
GiJeongKim	0:d885866e7cbf	99
GiJeongKim	0:d885866e7cbf	100	@verbatim
GiJeongKim	0:d885866e7cbf	101	===============================================================================
GiJeongKim	0:d885866e7cbf	102	##### FLASH Interface configuration functions #####
GiJeongKim	0:d885866e7cbf	103	===============================================================================
GiJeongKim	0:d885866e7cbf	104	[..]
GiJeongKim	0:d885866e7cbf	105	This group includes the following functions:
GiJeongKim	0:d885866e7cbf	106	(+) void FLASH_SetLatency(uint32_t FLASH_Latency)
GiJeongKim	0:d885866e7cbf	107	To correctly read data from FLASH memory, the number of wait states (LATENCY)
GiJeongKim	0:d885866e7cbf	108	must be correctly programmed according to the frequency of the CPU clock
GiJeongKim	0:d885866e7cbf	109	(HCLK) and the supply voltage of the device.
GiJeongKim	0:d885866e7cbf	110	[..]
GiJeongKim	0:d885866e7cbf	111	For STM32F405xx/07xx and STM32F415xx/17xx devices
GiJeongKim	0:d885866e7cbf	112	+-------------------------------------------------------------------------------------+
GiJeongKim	0:d885866e7cbf	113	\| Latency \| HCLK clock frequency (MHz) \|
GiJeongKim	0:d885866e7cbf	114	\| \|---------------------------------------------------------------------\|
GiJeongKim	0:d885866e7cbf	115	\| \| voltage range \| voltage range \| voltage range \| voltage range \|
GiJeongKim	0:d885866e7cbf	116	\| \| 2.7 V - 3.6 V \| 2.4 V - 2.7 V \| 2.1 V - 2.4 V \| 1.8 V - 2.1 V \|
GiJeongKim	0:d885866e7cbf	117	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
GiJeongKim	0:d885866e7cbf	118	\|0WS(1CPU cycle)\|0 < HCLK <= 30 \|0 < HCLK <= 24 \|0 < HCLK <= 22 \|0 < HCLK <= 20 \|
GiJeongKim	0:d885866e7cbf	119	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
GiJeongKim	0:d885866e7cbf	120	\|1WS(2CPU cycle)\|30 < HCLK <= 60 \|24 < HCLK <= 48 \|22 < HCLK <= 44 \|20 < HCLK <= 40 \|
GiJeongKim	0:d885866e7cbf	121	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
GiJeongKim	0:d885866e7cbf	122	\|2WS(3CPU cycle)\|60 < HCLK <= 90 \|48 < HCLK <= 72 \|44 < HCLK <= 66 \|40 < HCLK <= 60 \|
GiJeongKim	0:d885866e7cbf	123	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
GiJeongKim	0:d885866e7cbf	124	\|3WS(4CPU cycle)\|90 < HCLK <= 120\|72 < HCLK <= 96 \|66 < HCLK <= 88 \|60 < HCLK <= 80 \|
GiJeongKim	0:d885866e7cbf	125	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
GiJeongKim	0:d885866e7cbf	126	\|4WS(5CPU cycle)\|120< HCLK <= 150\|96 < HCLK <= 120\|88 < HCLK <= 110 \|80 < HCLK <= 100 \|
GiJeongKim	0:d885866e7cbf	127	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
GiJeongKim	0:d885866e7cbf	128	\|5WS(6CPU cycle)\|150< HCLK <= 168\|120< HCLK <= 144\|110 < HCLK <= 132\|100 < HCLK <= 120\|
GiJeongKim	0:d885866e7cbf	129	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
GiJeongKim	0:d885866e7cbf	130	\|6WS(7CPU cycle)\| NA \|144< HCLK <= 168\|132 < HCLK <= 154\|120 < HCLK <= 140\|
GiJeongKim	0:d885866e7cbf	131	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
GiJeongKim	0:d885866e7cbf	132	\|7WS(8CPU cycle)\| NA \| NA \|154 < HCLK <= 168\|140 < HCLK <= 160\|
GiJeongKim	0:d885866e7cbf	133	+---------------\|----------------\|----------------\|-----------------\|-----------------+
GiJeongKim	0:d885866e7cbf	134
GiJeongKim	0:d885866e7cbf	135	[..]
GiJeongKim	0:d885866e7cbf	136	For STM32F42xxx/43xxx devices
GiJeongKim	0:d885866e7cbf	137	+-------------------------------------------------------------------------------------+
GiJeongKim	0:d885866e7cbf	138	\| Latency \| HCLK clock frequency (MHz) \|
GiJeongKim	0:d885866e7cbf	139	\| \|---------------------------------------------------------------------\|
GiJeongKim	0:d885866e7cbf	140	\| \| voltage range \| voltage range \| voltage range \| voltage range \|
GiJeongKim	0:d885866e7cbf	141	\| \| 2.7 V - 3.6 V \| 2.4 V - 2.7 V \| 2.1 V - 2.4 V \| 1.8 V - 2.1 V \|
GiJeongKim	0:d885866e7cbf	142	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
GiJeongKim	0:d885866e7cbf	143	\|0WS(1CPU cycle)\|0 < HCLK <= 30 \|0 < HCLK <= 24 \|0 < HCLK <= 22 \|0 < HCLK <= 20 \|
GiJeongKim	0:d885866e7cbf	144	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
GiJeongKim	0:d885866e7cbf	145	\|1WS(2CPU cycle)\|30 < HCLK <= 60 \|24 < HCLK <= 48 \|22 < HCLK <= 44 \|20 < HCLK <= 40 \|
GiJeongKim	0:d885866e7cbf	146	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
GiJeongKim	0:d885866e7cbf	147	\|2WS(3CPU cycle)\|60 < HCLK <= 90 \|48 < HCLK <= 72 \|44 < HCLK <= 66 \|40 < HCLK <= 60 \|
GiJeongKim	0:d885866e7cbf	148	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
GiJeongKim	0:d885866e7cbf	149	\|3WS(4CPU cycle)\|90 < HCLK <= 120\|72 < HCLK <= 96 \|66 < HCLK <= 88 \|60 < HCLK <= 80 \|
GiJeongKim	0:d885866e7cbf	150	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
GiJeongKim	0:d885866e7cbf	151	\|4WS(5CPU cycle)\|120< HCLK <= 150\|96 < HCLK <= 120\|88 < HCLK <= 110 \|80 < HCLK <= 100 \|
GiJeongKim	0:d885866e7cbf	152	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
GiJeongKim	0:d885866e7cbf	153	\|5WS(6CPU cycle)\|120< HCLK <= 180\|120< HCLK <= 144\|110 < HCLK <= 132\|100 < HCLK <= 120\|
GiJeongKim	0:d885866e7cbf	154	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
GiJeongKim	0:d885866e7cbf	155	\|6WS(7CPU cycle)\| NA \|144< HCLK <= 168\|132 < HCLK <= 154\|120 < HCLK <= 140\|
GiJeongKim	0:d885866e7cbf	156	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
GiJeongKim	0:d885866e7cbf	157	\|7WS(8CPU cycle)\| NA \|168< HCLK <= 180\|154 < HCLK <= 176\|140 < HCLK <= 160\|
GiJeongKim	0:d885866e7cbf	158	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
GiJeongKim	0:d885866e7cbf	159	\|8WS(9CPU cycle)\| NA \| NA \|176 < HCLK <= 180\|160 < HCLK <= 168\|
GiJeongKim	0:d885866e7cbf	160	+-------------------------------------------------------------------------------------+
GiJeongKim	0:d885866e7cbf	161
GiJeongKim	0:d885866e7cbf	162	[..]
GiJeongKim	0:d885866e7cbf	163	For STM32F401x devices
GiJeongKim	0:d885866e7cbf	164	+-------------------------------------------------------------------------------------+
GiJeongKim	0:d885866e7cbf	165	\| Latency \| HCLK clock frequency (MHz) \|
GiJeongKim	0:d885866e7cbf	166	\| \|---------------------------------------------------------------------\|
GiJeongKim	0:d885866e7cbf	167	\| \| voltage range \| voltage range \| voltage range \| voltage range \|
GiJeongKim	0:d885866e7cbf	168	\| \| 2.7 V - 3.6 V \| 2.4 V - 2.7 V \| 2.1 V - 2.4 V \| 1.8 V - 2.1 V \|
GiJeongKim	0:d885866e7cbf	169	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
GiJeongKim	0:d885866e7cbf	170	\|0WS(1CPU cycle)\|0 < HCLK <= 30 \|0 < HCLK <= 24 \|0 < HCLK <= 22 \|0 < HCLK <= 20 \|
GiJeongKim	0:d885866e7cbf	171	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
GiJeongKim	0:d885866e7cbf	172	\|1WS(2CPU cycle)\|30 < HCLK <= 60 \|24 < HCLK <= 48 \|22 < HCLK <= 44 \|20 < HCLK <= 40 \|
GiJeongKim	0:d885866e7cbf	173	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
GiJeongKim	0:d885866e7cbf	174	\|2WS(3CPU cycle)\|60 < HCLK <= 84 \|48 < HCLK <= 72 \|44 < HCLK <= 66 \|40 < HCLK <= 60 \|
GiJeongKim	0:d885866e7cbf	175	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
GiJeongKim	0:d885866e7cbf	176	\|3WS(4CPU cycle)\| NA \|72 < HCLK <= 84 \|66 < HCLK <= 84 \|60 < HCLK <= 80 \|
GiJeongKim	0:d885866e7cbf	177	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
GiJeongKim	0:d885866e7cbf	178	\|4WS(5CPU cycle)\| NA \| NA \| NA \|80 < HCLK <= 84 \|
GiJeongKim	0:d885866e7cbf	179	+-------------------------------------------------------------------------------------+
GiJeongKim	0:d885866e7cbf	180
GiJeongKim	0:d885866e7cbf	181	[..]
GiJeongKim	0:d885866e7cbf	182	For STM32F410xx/STM32F411xE devices
GiJeongKim	0:d885866e7cbf	183	+-------------------------------------------------------------------------------------+
GiJeongKim	0:d885866e7cbf	184	\| Latency \| HCLK clock frequency (MHz) \|
GiJeongKim	0:d885866e7cbf	185	\| \|---------------------------------------------------------------------\|
GiJeongKim	0:d885866e7cbf	186	\| \| voltage range \| voltage range \| voltage range \| voltage range \|
GiJeongKim	0:d885866e7cbf	187	\| \| 2.7 V - 3.6 V \| 2.4 V - 2.7 V \| 2.1 V - 2.4 V \| 1.8 V - 2.1 V \|
GiJeongKim	0:d885866e7cbf	188	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
GiJeongKim	0:d885866e7cbf	189	\|0WS(1CPU cycle)\|0 < HCLK <= 30 \|0 < HCLK <= 24 \|0 < HCLK <= 18 \|0 < HCLK <= 16 \|
GiJeongKim	0:d885866e7cbf	190	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
GiJeongKim	0:d885866e7cbf	191	\|1WS(2CPU cycle)\|30 < HCLK <= 64 \|24 < HCLK <= 48 \|18 < HCLK <= 36 \|16 < HCLK <= 32 \|
GiJeongKim	0:d885866e7cbf	192	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
GiJeongKim	0:d885866e7cbf	193	\|2WS(3CPU cycle)\|64 < HCLK <= 90 \|48 < HCLK <= 72 \|36 < HCLK <= 54 \|32 < HCLK <= 48 \|
GiJeongKim	0:d885866e7cbf	194	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
GiJeongKim	0:d885866e7cbf	195	\|3WS(4CPU cycle)\|90 < HCLK <= 100\|72 < HCLK <= 96 \|54 < HCLK <= 72 \|48 < HCLK <= 64 \|
GiJeongKim	0:d885866e7cbf	196	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
GiJeongKim	0:d885866e7cbf	197	\|4WS(5CPU cycle)\| NA \|96 < HCLK <= 100\|72 < HCLK <= 90 \|64 < HCLK <= 80 \|
GiJeongKim	0:d885866e7cbf	198	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
GiJeongKim	0:d885866e7cbf	199	\|5WS(6CPU cycle)\| NA \| NA \|90 < HCLK <= 100 \|80 < HCLK <= 96 \|
GiJeongKim	0:d885866e7cbf	200	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
GiJeongKim	0:d885866e7cbf	201	\|6WS(7CPU cycle)\| NA \| NA \| NA \|96 < HCLK <= 100 \|
GiJeongKim	0:d885866e7cbf	202	+-------------------------------------------------------------------------------------+
GiJeongKim	0:d885866e7cbf	203
GiJeongKim	0:d885866e7cbf	204	[..]
GiJeongKim	0:d885866e7cbf	205	+-------------------------------------------------------------------------------------------------------------------+
GiJeongKim	0:d885866e7cbf	206	\| \| voltage range \| voltage range \| voltage range \| voltage range \| voltage range 2.7 V - 3.6 V \|
GiJeongKim	0:d885866e7cbf	207	\| \| 2.7 V - 3.6 V \| 2.4 V - 2.7 V \| 2.1 V - 2.4 V \| 1.8 V - 2.1 V \| with External Vpp = 9V \|
GiJeongKim	0:d885866e7cbf	208	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|-----------------------------\|
GiJeongKim	0:d885866e7cbf	209	\|Max Parallelism\| x32 \| x16 \| x8 \| x64 \|
GiJeongKim	0:d885866e7cbf	210	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|-----------------------------\|
GiJeongKim	0:d885866e7cbf	211	\|PSIZE[1:0] \| 10 \| 01 \| 00 \| 11 \|
GiJeongKim	0:d885866e7cbf	212	+-------------------------------------------------------------------------------------------------------------------+
GiJeongKim	0:d885866e7cbf	213
GiJeongKim	0:d885866e7cbf	214	-@- On STM32F405xx/407xx and STM32F415xx/417xx devices:
GiJeongKim	0:d885866e7cbf	215	(++) when VOS = '0' Scale 2 mode, the maximum value of fHCLK = 144MHz.
GiJeongKim	0:d885866e7cbf	216	(++) when VOS = '1' Scale 1 mode, the maximum value of fHCLK = 168MHz.
GiJeongKim	0:d885866e7cbf	217	[..]
GiJeongKim	0:d885866e7cbf	218	On STM32F42xxx/43xxx devices:
GiJeongKim	0:d885866e7cbf	219	(++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 120MHz.
GiJeongKim	0:d885866e7cbf	220	(++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 144MHz if OverDrive OFF and 168MHz if OverDrive ON.
GiJeongKim	0:d885866e7cbf	221	(++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 168MHz if OverDrive OFF and 180MHz if OverDrive ON.
GiJeongKim	0:d885866e7cbf	222	[..]
GiJeongKim	0:d885866e7cbf	223	On STM32F401x devices:
GiJeongKim	0:d885866e7cbf	224	(++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 60MHz.
GiJeongKim	0:d885866e7cbf	225	(++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz.
GiJeongKim	0:d885866e7cbf	226	[..]
GiJeongKim	0:d885866e7cbf	227	On STM32F410xx/STM32F411xE devices:
GiJeongKim	0:d885866e7cbf	228	(++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 64MHz.
GiJeongKim	0:d885866e7cbf	229	(++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz.
GiJeongKim	0:d885866e7cbf	230	(++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 100MHz.
GiJeongKim	0:d885866e7cbf	231
GiJeongKim	0:d885866e7cbf	232	For more details please refer product DataSheet
GiJeongKim	0:d885866e7cbf	233	You can use PWR_MainRegulatorModeConfig() function to control VOS bits.
GiJeongKim	0:d885866e7cbf	234
GiJeongKim	0:d885866e7cbf	235	(+) void FLASH_PrefetchBufferCmd(FunctionalState NewState)
GiJeongKim	0:d885866e7cbf	236	(+) void FLASH_InstructionCacheCmd(FunctionalState NewState)
GiJeongKim	0:d885866e7cbf	237	(+) void FLASH_DataCacheCmd(FunctionalState NewState)
GiJeongKim	0:d885866e7cbf	238	(+) void FLASH_InstructionCacheReset(void)
GiJeongKim	0:d885866e7cbf	239	(+) void FLASH_DataCacheReset(void)
GiJeongKim	0:d885866e7cbf	240
GiJeongKim	0:d885866e7cbf	241	[..]
GiJeongKim	0:d885866e7cbf	242	The unlock sequence is not needed for these functions.
GiJeongKim	0:d885866e7cbf	243
GiJeongKim	0:d885866e7cbf	244	@endverbatim
GiJeongKim	0:d885866e7cbf	245	* @{
GiJeongKim	0:d885866e7cbf	246	*/
GiJeongKim	0:d885866e7cbf	247
GiJeongKim	0:d885866e7cbf	248	/**
GiJeongKim	0:d885866e7cbf	249	* @brief Sets the code latency value.
GiJeongKim	0:d885866e7cbf	250	* @param FLASH_Latency: specifies the FLASH Latency value.
GiJeongKim	0:d885866e7cbf	251	* This parameter can be one of the following values:
GiJeongKim	0:d885866e7cbf	252	* @arg FLASH_Latency_0: FLASH Zero Latency cycle
GiJeongKim	0:d885866e7cbf	253	* @arg FLASH_Latency_1: FLASH One Latency cycle
GiJeongKim	0:d885866e7cbf	254	* @arg FLASH_Latency_2: FLASH Two Latency cycles
GiJeongKim	0:d885866e7cbf	255	* @arg FLASH_Latency_3: FLASH Three Latency cycles
GiJeongKim	0:d885866e7cbf	256	* @arg FLASH_Latency_4: FLASH Four Latency cycles
GiJeongKim	0:d885866e7cbf	257	* @arg FLASH_Latency_5: FLASH Five Latency cycles
GiJeongKim	0:d885866e7cbf	258	* @arg FLASH_Latency_6: FLASH Six Latency cycles
GiJeongKim	0:d885866e7cbf	259	* @arg FLASH_Latency_7: FLASH Seven Latency cycles
GiJeongKim	0:d885866e7cbf	260	* @arg FLASH_Latency_8: FLASH Eight Latency cycles
GiJeongKim	0:d885866e7cbf	261	* @arg FLASH_Latency_9: FLASH Nine Latency cycles
GiJeongKim	0:d885866e7cbf	262	* @arg FLASH_Latency_10: FLASH Teen Latency cycles
GiJeongKim	0:d885866e7cbf	263	* @arg FLASH_Latency_11: FLASH Eleven Latency cycles
GiJeongKim	0:d885866e7cbf	264	* @arg FLASH_Latency_12: FLASH Twelve Latency cycles
GiJeongKim	0:d885866e7cbf	265	* @arg FLASH_Latency_13: FLASH Thirteen Latency cycles
GiJeongKim	0:d885866e7cbf	266	* @arg FLASH_Latency_14: FLASH Fourteen Latency cycles
GiJeongKim	0:d885866e7cbf	267	* @arg FLASH_Latency_15: FLASH Fifteen Latency cycles
GiJeongKim	0:d885866e7cbf	268	*
GiJeongKim	0:d885866e7cbf	269	* @note For STM32F405xx/407xx, STM32F415xx/417xx, STM32F401xx/411xE and STM32F412xG devices
GiJeongKim	0:d885866e7cbf	270	* this parameter can be a value between FLASH_Latency_0 and FLASH_Latency_7.
GiJeongKim	0:d885866e7cbf	271	*
GiJeongKim	0:d885866e7cbf	272	* @note For STM32F42xxx/43xxx devices this parameter can be a value between
GiJeongKim	0:d885866e7cbf	273	* FLASH_Latency_0 and FLASH_Latency_15.
GiJeongKim	0:d885866e7cbf	274	*
GiJeongKim	0:d885866e7cbf	275	* @retval None
GiJeongKim	0:d885866e7cbf	276	*/
GiJeongKim	0:d885866e7cbf	277	void FLASH_SetLatency(uint32_t FLASH_Latency)
GiJeongKim	0:d885866e7cbf	278	{
GiJeongKim	0:d885866e7cbf	279	/* Check the parameters */
GiJeongKim	0:d885866e7cbf	280	assert_param(IS_FLASH_LATENCY(FLASH_Latency));
GiJeongKim	0:d885866e7cbf	281
GiJeongKim	0:d885866e7cbf	282	/* Perform Byte access to FLASH_ACR[8:0] to set the Latency value */
GiJeongKim	0:d885866e7cbf	283	(__IO uint8_t )ACR_BYTE0_ADDRESS = (uint8_t)FLASH_Latency;
GiJeongKim	0:d885866e7cbf	284	}
GiJeongKim	0:d885866e7cbf	285
GiJeongKim	0:d885866e7cbf	286	/**
GiJeongKim	0:d885866e7cbf	287	* @brief Enables or disables the Prefetch Buffer.
GiJeongKim	0:d885866e7cbf	288	* @param NewState: new state of the Prefetch Buffer.
GiJeongKim	0:d885866e7cbf	289	* This parameter can be: ENABLE or DISABLE.
GiJeongKim	0:d885866e7cbf	290	* @retval None
GiJeongKim	0:d885866e7cbf	291	*/
GiJeongKim	0:d885866e7cbf	292	void FLASH_PrefetchBufferCmd(FunctionalState NewState)
GiJeongKim	0:d885866e7cbf	293	{
GiJeongKim	0:d885866e7cbf	294	/* Check the parameters */
GiJeongKim	0:d885866e7cbf	295	assert_param(IS_FUNCTIONAL_STATE(NewState));
GiJeongKim	0:d885866e7cbf	296
GiJeongKim	0:d885866e7cbf	297	/* Enable or disable the Prefetch Buffer */
GiJeongKim	0:d885866e7cbf	298	if(NewState != DISABLE)
GiJeongKim	0:d885866e7cbf	299	{
GiJeongKim	0:d885866e7cbf	300	FLASH->ACR \|= FLASH_ACR_PRFTEN;
GiJeongKim	0:d885866e7cbf	301	}
GiJeongKim	0:d885866e7cbf	302	else
GiJeongKim	0:d885866e7cbf	303	{
GiJeongKim	0:d885866e7cbf	304	FLASH->ACR &= (~FLASH_ACR_PRFTEN);
GiJeongKim	0:d885866e7cbf	305	}
GiJeongKim	0:d885866e7cbf	306	}
GiJeongKim	0:d885866e7cbf	307
GiJeongKim	0:d885866e7cbf	308	/**
GiJeongKim	0:d885866e7cbf	309	* @brief Enables or disables the Instruction Cache feature.
GiJeongKim	0:d885866e7cbf	310	* @param NewState: new state of the Instruction Cache.
GiJeongKim	0:d885866e7cbf	311	* This parameter can be: ENABLE or DISABLE.
GiJeongKim	0:d885866e7cbf	312	* @retval None
GiJeongKim	0:d885866e7cbf	313	*/
GiJeongKim	0:d885866e7cbf	314	void FLASH_InstructionCacheCmd(FunctionalState NewState)
GiJeongKim	0:d885866e7cbf	315	{
GiJeongKim	0:d885866e7cbf	316	/* Check the parameters */
GiJeongKim	0:d885866e7cbf	317	assert_param(IS_FUNCTIONAL_STATE(NewState));
GiJeongKim	0:d885866e7cbf	318
GiJeongKim	0:d885866e7cbf	319	if(NewState != DISABLE)
GiJeongKim	0:d885866e7cbf	320	{
GiJeongKim	0:d885866e7cbf	321	FLASH->ACR \|= FLASH_ACR_ICEN;
GiJeongKim	0:d885866e7cbf	322	}
GiJeongKim	0:d885866e7cbf	323	else
GiJeongKim	0:d885866e7cbf	324	{
GiJeongKim	0:d885866e7cbf	325	FLASH->ACR &= (~FLASH_ACR_ICEN);
GiJeongKim	0:d885866e7cbf	326	}
GiJeongKim	0:d885866e7cbf	327	}
GiJeongKim	0:d885866e7cbf	328
GiJeongKim	0:d885866e7cbf	329	/**
GiJeongKim	0:d885866e7cbf	330	* @brief Enables or disables the Data Cache feature.
GiJeongKim	0:d885866e7cbf	331	* @param NewState: new state of the Data Cache.
GiJeongKim	0:d885866e7cbf	332	* This parameter can be: ENABLE or DISABLE.
GiJeongKim	0:d885866e7cbf	333	* @retval None
GiJeongKim	0:d885866e7cbf	334	*/
GiJeongKim	0:d885866e7cbf	335	void FLASH_DataCacheCmd(FunctionalState NewState)
GiJeongKim	0:d885866e7cbf	336	{
GiJeongKim	0:d885866e7cbf	337	/* Check the parameters */
GiJeongKim	0:d885866e7cbf	338	assert_param(IS_FUNCTIONAL_STATE(NewState));
GiJeongKim	0:d885866e7cbf	339
GiJeongKim	0:d885866e7cbf	340	if(NewState != DISABLE)
GiJeongKim	0:d885866e7cbf	341	{
GiJeongKim	0:d885866e7cbf	342	FLASH->ACR \|= FLASH_ACR_DCEN;
GiJeongKim	0:d885866e7cbf	343	}
GiJeongKim	0:d885866e7cbf	344	else
GiJeongKim	0:d885866e7cbf	345	{
GiJeongKim	0:d885866e7cbf	346	FLASH->ACR &= (~FLASH_ACR_DCEN);
GiJeongKim	0:d885866e7cbf	347	}
GiJeongKim	0:d885866e7cbf	348	}
GiJeongKim	0:d885866e7cbf	349
GiJeongKim	0:d885866e7cbf	350	/**
GiJeongKim	0:d885866e7cbf	351	* @brief Resets the Instruction Cache.
GiJeongKim	0:d885866e7cbf	352	* @note This function must be used only when the Instruction Cache is disabled.
GiJeongKim	0:d885866e7cbf	353	* @param None
GiJeongKim	0:d885866e7cbf	354	* @retval None
GiJeongKim	0:d885866e7cbf	355	*/
GiJeongKim	0:d885866e7cbf	356	void FLASH_InstructionCacheReset(void)
GiJeongKim	0:d885866e7cbf	357	{
GiJeongKim	0:d885866e7cbf	358	FLASH->ACR \|= FLASH_ACR_ICRST;
GiJeongKim	0:d885866e7cbf	359	}
GiJeongKim	0:d885866e7cbf	360
GiJeongKim	0:d885866e7cbf	361	/**
GiJeongKim	0:d885866e7cbf	362	* @brief Resets the Data Cache.
GiJeongKim	0:d885866e7cbf	363	* @note This function must be used only when the Data Cache is disabled.
GiJeongKim	0:d885866e7cbf	364	* @param None
GiJeongKim	0:d885866e7cbf	365	* @retval None
GiJeongKim	0:d885866e7cbf	366	*/
GiJeongKim	0:d885866e7cbf	367	void FLASH_DataCacheReset(void)
GiJeongKim	0:d885866e7cbf	368	{
GiJeongKim	0:d885866e7cbf	369	FLASH->ACR \|= FLASH_ACR_DCRST;
GiJeongKim	0:d885866e7cbf	370	}
GiJeongKim	0:d885866e7cbf	371
GiJeongKim	0:d885866e7cbf	372	/**
GiJeongKim	0:d885866e7cbf	373	* @}
GiJeongKim	0:d885866e7cbf	374	*/
GiJeongKim	0:d885866e7cbf	375
GiJeongKim	0:d885866e7cbf	376	/** @defgroup FLASH_Group2 FLASH Memory Programming functions
GiJeongKim	0:d885866e7cbf	377	* @brief FLASH Memory Programming functions
GiJeongKim	0:d885866e7cbf	378	*
GiJeongKim	0:d885866e7cbf	379	@verbatim
GiJeongKim	0:d885866e7cbf	380	===============================================================================
GiJeongKim	0:d885866e7cbf	381	##### FLASH Memory Programming functions #####
GiJeongKim	0:d885866e7cbf	382	===============================================================================
GiJeongKim	0:d885866e7cbf	383	[..]
GiJeongKim	0:d885866e7cbf	384	This group includes the following functions:
GiJeongKim	0:d885866e7cbf	385	(+) void FLASH_Unlock(void)
GiJeongKim	0:d885866e7cbf	386	(+) void FLASH_Lock(void)
GiJeongKim	0:d885866e7cbf	387	(+) FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange)
GiJeongKim	0:d885866e7cbf	388	(+) FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
GiJeongKim	0:d885866e7cbf	389	(+) FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)
GiJeongKim	0:d885866e7cbf	390	(+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
GiJeongKim	0:d885866e7cbf	391	(+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
GiJeongKim	0:d885866e7cbf	392	(+) FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
GiJeongKim	0:d885866e7cbf	393	The following functions can be used only for STM32F42xxx/43xxx devices.
GiJeongKim	0:d885866e7cbf	394	(+) FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange)
GiJeongKim	0:d885866e7cbf	395	(+) FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange)
GiJeongKim	0:d885866e7cbf	396	[..]
GiJeongKim	0:d885866e7cbf	397	Any operation of erase or program should follow these steps:
GiJeongKim	0:d885866e7cbf	398	(#) Call the FLASH_Unlock() function to enable the FLASH control register access
GiJeongKim	0:d885866e7cbf	399
GiJeongKim	0:d885866e7cbf	400	(#) Call the desired function to erase sector(s) or program data
GiJeongKim	0:d885866e7cbf	401
GiJeongKim	0:d885866e7cbf	402	(#) Call the FLASH_Lock() function to disable the FLASH control register access
GiJeongKim	0:d885866e7cbf	403	(recommended to protect the FLASH memory against possible unwanted operation)
GiJeongKim	0:d885866e7cbf	404
GiJeongKim	0:d885866e7cbf	405	@endverbatim
GiJeongKim	0:d885866e7cbf	406	* @{
GiJeongKim	0:d885866e7cbf	407	*/
GiJeongKim	0:d885866e7cbf	408
GiJeongKim	0:d885866e7cbf	409	/**
GiJeongKim	0:d885866e7cbf	410	* @brief Unlocks the FLASH control register access
GiJeongKim	0:d885866e7cbf	411	* @param None
GiJeongKim	0:d885866e7cbf	412	* @retval None
GiJeongKim	0:d885866e7cbf	413	*/
GiJeongKim	0:d885866e7cbf	414	void FLASH_Unlock(void)
GiJeongKim	0:d885866e7cbf	415	{
GiJeongKim	0:d885866e7cbf	416	if((FLASH->CR & FLASH_CR_LOCK) != RESET)
GiJeongKim	0:d885866e7cbf	417	{
GiJeongKim	0:d885866e7cbf	418	/* Authorize the FLASH Registers access */
GiJeongKim	0:d885866e7cbf	419	FLASH->KEYR = FLASH_KEY1;
GiJeongKim	0:d885866e7cbf	420	FLASH->KEYR = FLASH_KEY2;
GiJeongKim	0:d885866e7cbf	421	}
GiJeongKim	0:d885866e7cbf	422	}
GiJeongKim	0:d885866e7cbf	423
GiJeongKim	0:d885866e7cbf	424	/**
GiJeongKim	0:d885866e7cbf	425	* @brief Locks the FLASH control register access
GiJeongKim	0:d885866e7cbf	426	* @param None
GiJeongKim	0:d885866e7cbf	427	* @retval None
GiJeongKim	0:d885866e7cbf	428	*/
GiJeongKim	0:d885866e7cbf	429	void FLASH_Lock(void)
GiJeongKim	0:d885866e7cbf	430	{
GiJeongKim	0:d885866e7cbf	431	/* Set the LOCK Bit to lock the FLASH Registers access */
GiJeongKim	0:d885866e7cbf	432	FLASH->CR \|= FLASH_CR_LOCK;
GiJeongKim	0:d885866e7cbf	433	}
GiJeongKim	0:d885866e7cbf	434
GiJeongKim	0:d885866e7cbf	435	/**
GiJeongKim	0:d885866e7cbf	436	* @brief Erases a specified FLASH Sector.
GiJeongKim	0:d885866e7cbf	437	*
GiJeongKim	0:d885866e7cbf	438	* @note If an erase and a program operations are requested simultaneously,
GiJeongKim	0:d885866e7cbf	439	* the erase operation is performed before the program one.
GiJeongKim	0:d885866e7cbf	440	*
GiJeongKim	0:d885866e7cbf	441	* @param FLASH_Sector: The Sector number to be erased.
GiJeongKim	0:d885866e7cbf	442	*
GiJeongKim	0:d885866e7cbf	443	* @note For STM32F405xx/407xx and STM32F415xx/417xx devices this parameter can
GiJeongKim	0:d885866e7cbf	444	* be a value between FLASH_Sector_0 and FLASH_Sector_11.
GiJeongKim	0:d885866e7cbf	445	*
GiJeongKim	0:d885866e7cbf	446	* For STM32F42xxx/43xxx devices this parameter can be a value between
GiJeongKim	0:d885866e7cbf	447	* FLASH_Sector_0 and FLASH_Sector_23.
GiJeongKim	0:d885866e7cbf	448	*
GiJeongKim	0:d885866e7cbf	449	* For STM32F401xx devices this parameter can be a value between
GiJeongKim	0:d885866e7cbf	450	* FLASH_Sector_0 and FLASH_Sector_5.
GiJeongKim	0:d885866e7cbf	451	*
GiJeongKim	0:d885866e7cbf	452	* For STM32F411xE and STM32F412xG devices this parameter can be a value between
GiJeongKim	0:d885866e7cbf	453	* FLASH_Sector_0 and FLASH_Sector_7.
GiJeongKim	0:d885866e7cbf	454	*
GiJeongKim	0:d885866e7cbf	455	* For STM32F410xx devices this parameter can be a value between
GiJeongKim	0:d885866e7cbf	456	* FLASH_Sector_0 and FLASH_Sector_4.
GiJeongKim	0:d885866e7cbf	457	*
GiJeongKim	0:d885866e7cbf	458	* @param VoltageRange: The device voltage range which defines the erase parallelism.
GiJeongKim	0:d885866e7cbf	459	* This parameter can be one of the following values:
GiJeongKim	0:d885866e7cbf	460	* @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
GiJeongKim	0:d885866e7cbf	461	* the operation will be done by byte (8-bit)
GiJeongKim	0:d885866e7cbf	462	* @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
GiJeongKim	0:d885866e7cbf	463	* the operation will be done by half word (16-bit)
GiJeongKim	0:d885866e7cbf	464	* @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
GiJeongKim	0:d885866e7cbf	465	* the operation will be done by word (32-bit)
GiJeongKim	0:d885866e7cbf	466	* @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
GiJeongKim	0:d885866e7cbf	467	* the operation will be done by double word (64-bit)
GiJeongKim	0:d885866e7cbf	468	*
GiJeongKim	0:d885866e7cbf	469	* @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
GiJeongKim	0:d885866e7cbf	470	* FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
GiJeongKim	0:d885866e7cbf	471	*/
GiJeongKim	0:d885866e7cbf	472	FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange)
GiJeongKim	0:d885866e7cbf	473	{
GiJeongKim	0:d885866e7cbf	474	uint32_t tmp_psize = 0x0;
GiJeongKim	0:d885866e7cbf	475	FLASH_Status status = FLASH_COMPLETE2;
GiJeongKim	0:d885866e7cbf	476
GiJeongKim	0:d885866e7cbf	477	/* Check the parameters */
GiJeongKim	0:d885866e7cbf	478	assert_param(IS_FLASH_SECTOR(FLASH_Sector));
GiJeongKim	0:d885866e7cbf	479	assert_param(IS_VOLTAGERANGE(VoltageRange));
GiJeongKim	0:d885866e7cbf	480
GiJeongKim	0:d885866e7cbf	481	if(VoltageRange == VoltageRange_1)
GiJeongKim	0:d885866e7cbf	482	{
GiJeongKim	0:d885866e7cbf	483	tmp_psize = FLASH_PSIZE_BYTE;
GiJeongKim	0:d885866e7cbf	484	}
GiJeongKim	0:d885866e7cbf	485	else if(VoltageRange == VoltageRange_2)
GiJeongKim	0:d885866e7cbf	486	{
GiJeongKim	0:d885866e7cbf	487	tmp_psize = FLASH_PSIZE_HALF_WORD;
GiJeongKim	0:d885866e7cbf	488	}
GiJeongKim	0:d885866e7cbf	489	else if(VoltageRange == VoltageRange_3)
GiJeongKim	0:d885866e7cbf	490	{
GiJeongKim	0:d885866e7cbf	491	tmp_psize = FLASH_PSIZE_WORD;
GiJeongKim	0:d885866e7cbf	492	}
GiJeongKim	0:d885866e7cbf	493	else
GiJeongKim	0:d885866e7cbf	494	{
GiJeongKim	0:d885866e7cbf	495	tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
GiJeongKim	0:d885866e7cbf	496	}
GiJeongKim	0:d885866e7cbf	497	/* Wait for last operation to be completed */
GiJeongKim	0:d885866e7cbf	498	status = FLASH_WaitForLastOperation2();
GiJeongKim	0:d885866e7cbf	499
GiJeongKim	0:d885866e7cbf	500	if(status == FLASH_COMPLETE2)
GiJeongKim	0:d885866e7cbf	501	{
GiJeongKim	0:d885866e7cbf	502	/* if the previous operation is completed, proceed to erase the sector */
GiJeongKim	0:d885866e7cbf	503	FLASH->CR &= CR_PSIZE_MASK;
GiJeongKim	0:d885866e7cbf	504	FLASH->CR \|= tmp_psize;
GiJeongKim	0:d885866e7cbf	505	FLASH->CR &= SECTOR_MASK;
GiJeongKim	0:d885866e7cbf	506	FLASH->CR \|= FLASH_CR_SER \| FLASH_Sector;
GiJeongKim	0:d885866e7cbf	507	FLASH->CR \|= FLASH_CR_STRT;
GiJeongKim	0:d885866e7cbf	508
GiJeongKim	0:d885866e7cbf	509	/* Wait for last operation to be completed */
GiJeongKim	0:d885866e7cbf	510	status = FLASH_WaitForLastOperation2();
GiJeongKim	0:d885866e7cbf	511
GiJeongKim	0:d885866e7cbf	512	/* if the erase operation is completed, disable the SER Bit */
GiJeongKim	0:d885866e7cbf	513	FLASH->CR &= (~FLASH_CR_SER);
GiJeongKim	0:d885866e7cbf	514	FLASH->CR &= SECTOR_MASK;
GiJeongKim	0:d885866e7cbf	515	}
GiJeongKim	0:d885866e7cbf	516	/* Return the Erase Status */
GiJeongKim	0:d885866e7cbf	517	return status;
GiJeongKim	0:d885866e7cbf	518	}
GiJeongKim	0:d885866e7cbf	519
GiJeongKim	0:d885866e7cbf	520	/**
GiJeongKim	0:d885866e7cbf	521	* @brief Erases all FLASH Sectors.
GiJeongKim	0:d885866e7cbf	522	*
GiJeongKim	0:d885866e7cbf	523	* @note If an erase and a program operations are requested simultaneously,
GiJeongKim	0:d885866e7cbf	524	* the erase operation is performed before the program one.
GiJeongKim	0:d885866e7cbf	525	*
GiJeongKim	0:d885866e7cbf	526	* @param VoltageRange: The device voltage range which defines the erase parallelism.
GiJeongKim	0:d885866e7cbf	527	* This parameter can be one of the following values:
GiJeongKim	0:d885866e7cbf	528	* @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
GiJeongKim	0:d885866e7cbf	529	* the operation will be done by byte (8-bit)
GiJeongKim	0:d885866e7cbf	530	* @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
GiJeongKim	0:d885866e7cbf	531	* the operation will be done by half word (16-bit)
GiJeongKim	0:d885866e7cbf	532	* @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
GiJeongKim	0:d885866e7cbf	533	* the operation will be done by word (32-bit)
GiJeongKim	0:d885866e7cbf	534	* @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
GiJeongKim	0:d885866e7cbf	535	* the operation will be done by double word (64-bit)
GiJeongKim	0:d885866e7cbf	536	*
GiJeongKim	0:d885866e7cbf	537	* @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
GiJeongKim	0:d885866e7cbf	538	* FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
GiJeongKim	0:d885866e7cbf	539	*/
GiJeongKim	0:d885866e7cbf	540	FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
GiJeongKim	0:d885866e7cbf	541	{
GiJeongKim	0:d885866e7cbf	542	uint32_t tmp_psize = 0x0;
GiJeongKim	0:d885866e7cbf	543	FLASH_Status status = FLASH_COMPLETE2;
GiJeongKim	0:d885866e7cbf	544
GiJeongKim	0:d885866e7cbf	545	/* Wait for last operation to be completed */
GiJeongKim	0:d885866e7cbf	546	status = FLASH_WaitForLastOperation2();
GiJeongKim	0:d885866e7cbf	547	assert_param(IS_VOLTAGERANGE(VoltageRange));
GiJeongKim	0:d885866e7cbf	548
GiJeongKim	0:d885866e7cbf	549	if(VoltageRange == VoltageRange_1)
GiJeongKim	0:d885866e7cbf	550	{
GiJeongKim	0:d885866e7cbf	551	tmp_psize = FLASH_PSIZE_BYTE;
GiJeongKim	0:d885866e7cbf	552	}
GiJeongKim	0:d885866e7cbf	553	else if(VoltageRange == VoltageRange_2)
GiJeongKim	0:d885866e7cbf	554	{
GiJeongKim	0:d885866e7cbf	555	tmp_psize = FLASH_PSIZE_HALF_WORD;
GiJeongKim	0:d885866e7cbf	556	}
GiJeongKim	0:d885866e7cbf	557	else if(VoltageRange == VoltageRange_3)
GiJeongKim	0:d885866e7cbf	558	{
GiJeongKim	0:d885866e7cbf	559	tmp_psize = FLASH_PSIZE_WORD;
GiJeongKim	0:d885866e7cbf	560	}
GiJeongKim	0:d885866e7cbf	561	else
GiJeongKim	0:d885866e7cbf	562	{
GiJeongKim	0:d885866e7cbf	563	tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
GiJeongKim	0:d885866e7cbf	564	}
GiJeongKim	0:d885866e7cbf	565	if(status == FLASH_COMPLETE2)
GiJeongKim	0:d885866e7cbf	566	{
GiJeongKim	0:d885866e7cbf	567	/* if the previous operation is completed, proceed to erase all sectors */
GiJeongKim	0:d885866e7cbf	568	#if defined(STM32F427_437xx) \|\| defined(STM32F429_439xx) \|\| defined(STM32F469_479xx)
GiJeongKim	0:d885866e7cbf	569	FLASH->CR &= CR_PSIZE_MASK;
GiJeongKim	0:d885866e7cbf	570	FLASH->CR \|= tmp_psize;
GiJeongKim	0:d885866e7cbf	571	FLASH->CR \|= (FLASH_CR_MER1 \| FLASH_CR_MER2);
GiJeongKim	0:d885866e7cbf	572	FLASH->CR \|= FLASH_CR_STRT;
GiJeongKim	0:d885866e7cbf	573
GiJeongKim	0:d885866e7cbf	574	/* Wait for last operation to be completed */
GiJeongKim	0:d885866e7cbf	575	status = FLASH_WaitForLastOperation2();
GiJeongKim	0:d885866e7cbf	576
GiJeongKim	0:d885866e7cbf	577	/* if the erase operation is completed, disable the MER Bit */
GiJeongKim	0:d885866e7cbf	578	FLASH->CR &= ~(FLASH_CR_MER1 \| FLASH_CR_MER2);
GiJeongKim	0:d885866e7cbf	579	#endif /* STM32F427_437xx \|\| STM32F429_439xx \|\| STM32F469_479xx */
GiJeongKim	0:d885866e7cbf	580
GiJeongKim	0:d885866e7cbf	581	#if defined(STM32F40_41xxx) \|\| defined(STM32F401xx) \|\| defined(STM32F410xx) \|\| defined(STM32F411xE) \|\| defined(STM32F412xG) \|\| defined(STM32F446xx)
GiJeongKim	0:d885866e7cbf	582	FLASH->CR &= CR_PSIZE_MASK;
GiJeongKim	0:d885866e7cbf	583	FLASH->CR \|= tmp_psize;
GiJeongKim	0:d885866e7cbf	584	FLASH->CR \|= FLASH_CR_MER;
GiJeongKim	0:d885866e7cbf	585	FLASH->CR \|= FLASH_CR_STRT;
GiJeongKim	0:d885866e7cbf	586
GiJeongKim	0:d885866e7cbf	587	/* Wait for last operation to be completed */
GiJeongKim	0:d885866e7cbf	588	status = FLASH_WaitForLastOperation2();
GiJeongKim	0:d885866e7cbf	589
GiJeongKim	0:d885866e7cbf	590	/* if the erase operation is completed, disable the MER Bit */
GiJeongKim	0:d885866e7cbf	591	FLASH->CR &= (~FLASH_CR_MER);
GiJeongKim	0:d885866e7cbf	592	#endif /* STM32F40_41xxx \|\| STM32F401xx \|\| STM32F410xx \|\| STM32F411xE \|\| STM32F412xG \|\| STM32F446xx */
GiJeongKim	0:d885866e7cbf	593
GiJeongKim	0:d885866e7cbf	594	}
GiJeongKim	0:d885866e7cbf	595	/* Return the Erase Status */
GiJeongKim	0:d885866e7cbf	596	return status;
GiJeongKim	0:d885866e7cbf	597	}
GiJeongKim	0:d885866e7cbf	598
GiJeongKim	0:d885866e7cbf	599	/**
GiJeongKim	0:d885866e7cbf	600	* @brief Erases all FLASH Sectors in Bank 1.
GiJeongKim	0:d885866e7cbf	601	*
GiJeongKim	0:d885866e7cbf	602	* @note This function can be used only for STM32F42xxx/43xxx devices.
GiJeongKim	0:d885866e7cbf	603	*
GiJeongKim	0:d885866e7cbf	604	* @note If an erase and a program operations are requested simultaneously,
GiJeongKim	0:d885866e7cbf	605	* the erase operation is performed before the program one.
GiJeongKim	0:d885866e7cbf	606	*
GiJeongKim	0:d885866e7cbf	607	* @param VoltageRange: The device voltage range which defines the erase parallelism.
GiJeongKim	0:d885866e7cbf	608	* This parameter can be one of the following values:
GiJeongKim	0:d885866e7cbf	609	* @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
GiJeongKim	0:d885866e7cbf	610	* the operation will be done by byte (8-bit)
GiJeongKim	0:d885866e7cbf	611	* @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
GiJeongKim	0:d885866e7cbf	612	* the operation will be done by half word (16-bit)
GiJeongKim	0:d885866e7cbf	613	* @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
GiJeongKim	0:d885866e7cbf	614	* the operation will be done by word (32-bit)
GiJeongKim	0:d885866e7cbf	615	* @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
GiJeongKim	0:d885866e7cbf	616	* the operation will be done by double word (64-bit)
GiJeongKim	0:d885866e7cbf	617	*
GiJeongKim	0:d885866e7cbf	618	* @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
GiJeongKim	0:d885866e7cbf	619	* FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
GiJeongKim	0:d885866e7cbf	620	*/
GiJeongKim	0:d885866e7cbf	621	FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange)
GiJeongKim	0:d885866e7cbf	622	{
GiJeongKim	0:d885866e7cbf	623	uint32_t tmp_psize = 0x0;
GiJeongKim	0:d885866e7cbf	624	FLASH_Status status = FLASH_COMPLETE2;
GiJeongKim	0:d885866e7cbf	625
GiJeongKim	0:d885866e7cbf	626	/* Wait for last operation to be completed */
GiJeongKim	0:d885866e7cbf	627	status = FLASH_WaitForLastOperation2();
GiJeongKim	0:d885866e7cbf	628	assert_param(IS_VOLTAGERANGE(VoltageRange));
GiJeongKim	0:d885866e7cbf	629
GiJeongKim	0:d885866e7cbf	630	if(VoltageRange == VoltageRange_1)
GiJeongKim	0:d885866e7cbf	631	{
GiJeongKim	0:d885866e7cbf	632	tmp_psize = FLASH_PSIZE_BYTE;
GiJeongKim	0:d885866e7cbf	633	}
GiJeongKim	0:d885866e7cbf	634	else if(VoltageRange == VoltageRange_2)
GiJeongKim	0:d885866e7cbf	635	{
GiJeongKim	0:d885866e7cbf	636	tmp_psize = FLASH_PSIZE_HALF_WORD;
GiJeongKim	0:d885866e7cbf	637	}
GiJeongKim	0:d885866e7cbf	638	else if(VoltageRange == VoltageRange_3)
GiJeongKim	0:d885866e7cbf	639	{
GiJeongKim	0:d885866e7cbf	640	tmp_psize = FLASH_PSIZE_WORD;
GiJeongKim	0:d885866e7cbf	641	}
GiJeongKim	0:d885866e7cbf	642	else
GiJeongKim	0:d885866e7cbf	643	{
GiJeongKim	0:d885866e7cbf	644	tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
GiJeongKim	0:d885866e7cbf	645	}
GiJeongKim	0:d885866e7cbf	646	if(status == FLASH_COMPLETE2)
GiJeongKim	0:d885866e7cbf	647	{
GiJeongKim	0:d885866e7cbf	648	/* if the previous operation is completed, proceed to erase all sectors */
GiJeongKim	0:d885866e7cbf	649	FLASH->CR &= CR_PSIZE_MASK;
GiJeongKim	0:d885866e7cbf	650	FLASH->CR \|= tmp_psize;
GiJeongKim	0:d885866e7cbf	651	FLASH->CR \|= FLASH_CR_MER1;
GiJeongKim	0:d885866e7cbf	652	FLASH->CR \|= FLASH_CR_STRT;
GiJeongKim	0:d885866e7cbf	653
GiJeongKim	0:d885866e7cbf	654	/* Wait for last operation to be completed */
GiJeongKim	0:d885866e7cbf	655	status = FLASH_WaitForLastOperation2();
GiJeongKim	0:d885866e7cbf	656
GiJeongKim	0:d885866e7cbf	657	/* if the erase operation is completed, disable the MER Bit */
GiJeongKim	0:d885866e7cbf	658	FLASH->CR &= (~FLASH_CR_MER1);
GiJeongKim	0:d885866e7cbf	659
GiJeongKim	0:d885866e7cbf	660	}
GiJeongKim	0:d885866e7cbf	661	/* Return the Erase Status */
GiJeongKim	0:d885866e7cbf	662	return status;
GiJeongKim	0:d885866e7cbf	663	}
GiJeongKim	0:d885866e7cbf	664
GiJeongKim	0:d885866e7cbf	665
GiJeongKim	0:d885866e7cbf	666	/**
GiJeongKim	0:d885866e7cbf	667	* @brief Erases all FLASH Sectors in Bank 2.
GiJeongKim	0:d885866e7cbf	668	*
GiJeongKim	0:d885866e7cbf	669	* @note This function can be used only for STM32F42xxx/43xxx devices.
GiJeongKim	0:d885866e7cbf	670	*
GiJeongKim	0:d885866e7cbf	671	* @note If an erase and a program operations are requested simultaneously,
GiJeongKim	0:d885866e7cbf	672	* the erase operation is performed before the program one.
GiJeongKim	0:d885866e7cbf	673	*
GiJeongKim	0:d885866e7cbf	674	* @param VoltageRange: The device voltage range which defines the erase parallelism.
GiJeongKim	0:d885866e7cbf	675	* This parameter can be one of the following values:
GiJeongKim	0:d885866e7cbf	676	* @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
GiJeongKim	0:d885866e7cbf	677	* the operation will be done by byte (8-bit)
GiJeongKim	0:d885866e7cbf	678	* @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
GiJeongKim	0:d885866e7cbf	679	* the operation will be done by half word (16-bit)
GiJeongKim	0:d885866e7cbf	680	* @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
GiJeongKim	0:d885866e7cbf	681	* the operation will be done by word (32-bit)
GiJeongKim	0:d885866e7cbf	682	* @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
GiJeongKim	0:d885866e7cbf	683	* the operation will be done by double word (64-bit)
GiJeongKim	0:d885866e7cbf	684	*
GiJeongKim	0:d885866e7cbf	685	* @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
GiJeongKim	0:d885866e7cbf	686	* FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
GiJeongKim	0:d885866e7cbf	687	*/
GiJeongKim	0:d885866e7cbf	688	FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange)
GiJeongKim	0:d885866e7cbf	689	{
GiJeongKim	0:d885866e7cbf	690	uint32_t tmp_psize = 0x0;
GiJeongKim	0:d885866e7cbf	691	FLASH_Status status = FLASH_COMPLETE2;
GiJeongKim	0:d885866e7cbf	692
GiJeongKim	0:d885866e7cbf	693	/* Wait for last operation to be completed */
GiJeongKim	0:d885866e7cbf	694	status = FLASH_WaitForLastOperation2();
GiJeongKim	0:d885866e7cbf	695	assert_param(IS_VOLTAGERANGE(VoltageRange));
GiJeongKim	0:d885866e7cbf	696
GiJeongKim	0:d885866e7cbf	697	if(VoltageRange == VoltageRange_1)
GiJeongKim	0:d885866e7cbf	698	{
GiJeongKim	0:d885866e7cbf	699	tmp_psize = FLASH_PSIZE_BYTE;
GiJeongKim	0:d885866e7cbf	700	}
GiJeongKim	0:d885866e7cbf	701	else if(VoltageRange == VoltageRange_2)
GiJeongKim	0:d885866e7cbf	702	{
GiJeongKim	0:d885866e7cbf	703	tmp_psize = FLASH_PSIZE_HALF_WORD;
GiJeongKim	0:d885866e7cbf	704	}
GiJeongKim	0:d885866e7cbf	705	else if(VoltageRange == VoltageRange_3)
GiJeongKim	0:d885866e7cbf	706	{
GiJeongKim	0:d885866e7cbf	707	tmp_psize = FLASH_PSIZE_WORD;
GiJeongKim	0:d885866e7cbf	708	}
GiJeongKim	0:d885866e7cbf	709	else
GiJeongKim	0:d885866e7cbf	710	{
GiJeongKim	0:d885866e7cbf	711	tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
GiJeongKim	0:d885866e7cbf	712	}
GiJeongKim	0:d885866e7cbf	713	if(status == FLASH_COMPLETE2)
GiJeongKim	0:d885866e7cbf	714	{
GiJeongKim	0:d885866e7cbf	715	/* if the previous operation is completed, proceed to erase all sectors */
GiJeongKim	0:d885866e7cbf	716	FLASH->CR &= CR_PSIZE_MASK;
GiJeongKim	0:d885866e7cbf	717	FLASH->CR \|= tmp_psize;
GiJeongKim	0:d885866e7cbf	718	FLASH->CR \|= FLASH_CR_MER2;
GiJeongKim	0:d885866e7cbf	719	FLASH->CR \|= FLASH_CR_STRT;
GiJeongKim	0:d885866e7cbf	720
GiJeongKim	0:d885866e7cbf	721	/* Wait for last operation to be completed */
GiJeongKim	0:d885866e7cbf	722	status = FLASH_WaitForLastOperation2();
GiJeongKim	0:d885866e7cbf	723
GiJeongKim	0:d885866e7cbf	724	/* if the erase operation is completed, disable the MER Bit */
GiJeongKim	0:d885866e7cbf	725	FLASH->CR &= (~FLASH_CR_MER2);
GiJeongKim	0:d885866e7cbf	726
GiJeongKim	0:d885866e7cbf	727	}
GiJeongKim	0:d885866e7cbf	728	/* Return the Erase Status */
GiJeongKim	0:d885866e7cbf	729	return status;
GiJeongKim	0:d885866e7cbf	730	}
GiJeongKim	0:d885866e7cbf	731
GiJeongKim	0:d885866e7cbf	732	/**
GiJeongKim	0:d885866e7cbf	733	* @brief Programs a double word (64-bit) at a specified address.
GiJeongKim	0:d885866e7cbf	734	* @note This function must be used when the device voltage range is from
GiJeongKim	0:d885866e7cbf	735	* 2.7V to 3.6V and an External Vpp is present.
GiJeongKim	0:d885866e7cbf	736	*
GiJeongKim	0:d885866e7cbf	737	* @note If an erase and a program operations are requested simultaneously,
GiJeongKim	0:d885866e7cbf	738	* the erase operation is performed before the program one.
GiJeongKim	0:d885866e7cbf	739	*
GiJeongKim	0:d885866e7cbf	740	* @param Address: specifies the address to be programmed.
GiJeongKim	0:d885866e7cbf	741	* @param Data: specifies the data to be programmed.
GiJeongKim	0:d885866e7cbf	742	* @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
GiJeongKim	0:d885866e7cbf	743	* FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
GiJeongKim	0:d885866e7cbf	744	*/
GiJeongKim	0:d885866e7cbf	745	FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)
GiJeongKim	0:d885866e7cbf	746	{
GiJeongKim	0:d885866e7cbf	747	FLASH_Status status = FLASH_COMPLETE2;
GiJeongKim	0:d885866e7cbf	748
GiJeongKim	0:d885866e7cbf	749	/* Check the parameters */
GiJeongKim	0:d885866e7cbf	750	assert_param(IS_FLASH_ADDRESS(Address));
GiJeongKim	0:d885866e7cbf	751
GiJeongKim	0:d885866e7cbf	752	/* Wait for last operation to be completed */
GiJeongKim	0:d885866e7cbf	753	status = FLASH_WaitForLastOperation2();
GiJeongKim	0:d885866e7cbf	754
GiJeongKim	0:d885866e7cbf	755	if(status == FLASH_COMPLETE2)
GiJeongKim	0:d885866e7cbf	756	{
GiJeongKim	0:d885866e7cbf	757	/* if the previous operation is completed, proceed to program the new data */
GiJeongKim	0:d885866e7cbf	758	FLASH->CR &= CR_PSIZE_MASK;
GiJeongKim	0:d885866e7cbf	759	FLASH->CR \|= FLASH_PSIZE_DOUBLE_WORD;
GiJeongKim	0:d885866e7cbf	760	FLASH->CR \|= FLASH_CR_PG;
GiJeongKim	0:d885866e7cbf	761
GiJeongKim	0:d885866e7cbf	762	(__IO uint64_t)Address = Data;
GiJeongKim	0:d885866e7cbf	763
GiJeongKim	0:d885866e7cbf	764	/* Wait for last operation to be completed */
GiJeongKim	0:d885866e7cbf	765	status = FLASH_WaitForLastOperation2();
GiJeongKim	0:d885866e7cbf	766
GiJeongKim	0:d885866e7cbf	767	/* if the program operation is completed, disable the PG Bit */
GiJeongKim	0:d885866e7cbf	768	FLASH->CR &= (~FLASH_CR_PG);
GiJeongKim	0:d885866e7cbf	769	}
GiJeongKim	0:d885866e7cbf	770	/* Return the Program Status */
GiJeongKim	0:d885866e7cbf	771	return status;
GiJeongKim	0:d885866e7cbf	772	}
GiJeongKim	0:d885866e7cbf	773
GiJeongKim	0:d885866e7cbf	774	/**
GiJeongKim	0:d885866e7cbf	775	* @brief Programs a word (32-bit) at a specified address.
GiJeongKim	0:d885866e7cbf	776	*
GiJeongKim	0:d885866e7cbf	777	* @note This function must be used when the device voltage range is from 2.7V to 3.6V.
GiJeongKim	0:d885866e7cbf	778	*
GiJeongKim	0:d885866e7cbf	779	* @note If an erase and a program operations are requested simultaneously,
GiJeongKim	0:d885866e7cbf	780	* the erase operation is performed before the program one.
GiJeongKim	0:d885866e7cbf	781	*
GiJeongKim	0:d885866e7cbf	782	* @param Address: specifies the address to be programmed.
GiJeongKim	0:d885866e7cbf	783	* This parameter can be any address in Program memory zone or in OTP zone.
GiJeongKim	0:d885866e7cbf	784	* @param Data: specifies the data to be programmed.
GiJeongKim	0:d885866e7cbf	785	* @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
GiJeongKim	0:d885866e7cbf	786	* FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
GiJeongKim	0:d885866e7cbf	787	*/
GiJeongKim	0:d885866e7cbf	788	FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
GiJeongKim	0:d885866e7cbf	789	{
GiJeongKim	0:d885866e7cbf	790	FLASH_Status status = FLASH_COMPLETE2;
GiJeongKim	0:d885866e7cbf	791
GiJeongKim	0:d885866e7cbf	792	/* Check the parameters */
GiJeongKim	0:d885866e7cbf	793	assert_param(IS_FLASH_ADDRESS(Address));
GiJeongKim	0:d885866e7cbf	794
GiJeongKim	0:d885866e7cbf	795	/* Wait for last operation to be completed */
GiJeongKim	0:d885866e7cbf	796	status = FLASH_WaitForLastOperation2();
GiJeongKim	0:d885866e7cbf	797
GiJeongKim	0:d885866e7cbf	798	if(status == FLASH_COMPLETE2)
GiJeongKim	0:d885866e7cbf	799	{
GiJeongKim	0:d885866e7cbf	800	/* if the previous operation is completed, proceed to program the new data */
GiJeongKim	0:d885866e7cbf	801	FLASH->CR &= CR_PSIZE_MASK;
GiJeongKim	0:d885866e7cbf	802	FLASH->CR \|= FLASH_PSIZE_WORD;
GiJeongKim	0:d885866e7cbf	803	FLASH->CR \|= FLASH_CR_PG;
GiJeongKim	0:d885866e7cbf	804
GiJeongKim	0:d885866e7cbf	805	(__IO uint32_t)Address = Data;
GiJeongKim	0:d885866e7cbf	806
GiJeongKim	0:d885866e7cbf	807	/* Wait for last operation to be completed */
GiJeongKim	0:d885866e7cbf	808	status = FLASH_WaitForLastOperation2();
GiJeongKim	0:d885866e7cbf	809
GiJeongKim	0:d885866e7cbf	810	/* if the program operation is completed, disable the PG Bit */
GiJeongKim	0:d885866e7cbf	811	FLASH->CR &= (~FLASH_CR_PG);
GiJeongKim	0:d885866e7cbf	812	}
GiJeongKim	0:d885866e7cbf	813	/* Return the Program Status */
GiJeongKim	0:d885866e7cbf	814	return status;
GiJeongKim	0:d885866e7cbf	815	}
GiJeongKim	0:d885866e7cbf	816
GiJeongKim	0:d885866e7cbf	817	/**
GiJeongKim	0:d885866e7cbf	818	* @brief Programs a half word (16-bit) at a specified address.
GiJeongKim	0:d885866e7cbf	819	* @note This function must be used when the device voltage range is from 2.1V to 3.6V.
GiJeongKim	0:d885866e7cbf	820	*
GiJeongKim	0:d885866e7cbf	821	* @note If an erase and a program operations are requested simultaneously,
GiJeongKim	0:d885866e7cbf	822	* the erase operation is performed before the program one.
GiJeongKim	0:d885866e7cbf	823	*
GiJeongKim	0:d885866e7cbf	824	* @param Address: specifies the address to be programmed.
GiJeongKim	0:d885866e7cbf	825	* This parameter can be any address in Program memory zone or in OTP zone.
GiJeongKim	0:d885866e7cbf	826	* @param Data: specifies the data to be programmed.
GiJeongKim	0:d885866e7cbf	827	* @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
GiJeongKim	0:d885866e7cbf	828	* FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
GiJeongKim	0:d885866e7cbf	829	*/
GiJeongKim	0:d885866e7cbf	830	FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
GiJeongKim	0:d885866e7cbf	831	{
GiJeongKim	0:d885866e7cbf	832	FLASH_Status status = FLASH_COMPLETE2;
GiJeongKim	0:d885866e7cbf	833
GiJeongKim	0:d885866e7cbf	834	/* Check the parameters */
GiJeongKim	0:d885866e7cbf	835	assert_param(IS_FLASH_ADDRESS(Address));
GiJeongKim	0:d885866e7cbf	836
GiJeongKim	0:d885866e7cbf	837	/* Wait for last operation to be completed */
GiJeongKim	0:d885866e7cbf	838	status = FLASH_WaitForLastOperation2();
GiJeongKim	0:d885866e7cbf	839
GiJeongKim	0:d885866e7cbf	840	if(status == FLASH_COMPLETE2)
GiJeongKim	0:d885866e7cbf	841	{
GiJeongKim	0:d885866e7cbf	842	/* if the previous operation is completed, proceed to program the new data */
GiJeongKim	0:d885866e7cbf	843	FLASH->CR &= CR_PSIZE_MASK;
GiJeongKim	0:d885866e7cbf	844	FLASH->CR \|= FLASH_PSIZE_HALF_WORD;
GiJeongKim	0:d885866e7cbf	845	FLASH->CR \|= FLASH_CR_PG;
GiJeongKim	0:d885866e7cbf	846
GiJeongKim	0:d885866e7cbf	847	(__IO uint16_t)Address = Data;
GiJeongKim	0:d885866e7cbf	848
GiJeongKim	0:d885866e7cbf	849	/* Wait for last operation to be completed */
GiJeongKim	0:d885866e7cbf	850	status = FLASH_WaitForLastOperation2();
GiJeongKim	0:d885866e7cbf	851
GiJeongKim	0:d885866e7cbf	852	/* if the program operation is completed, disable the PG Bit */
GiJeongKim	0:d885866e7cbf	853	FLASH->CR &= (~FLASH_CR_PG);
GiJeongKim	0:d885866e7cbf	854	}
GiJeongKim	0:d885866e7cbf	855	/* Return the Program Status */
GiJeongKim	0:d885866e7cbf	856	return status;
GiJeongKim	0:d885866e7cbf	857	}
GiJeongKim	0:d885866e7cbf	858
GiJeongKim	0:d885866e7cbf	859	/**
GiJeongKim	0:d885866e7cbf	860	* @brief Programs a byte (8-bit) at a specified address.
GiJeongKim	0:d885866e7cbf	861	* @note This function can be used within all the device supply voltage ranges.
GiJeongKim	0:d885866e7cbf	862	*
GiJeongKim	0:d885866e7cbf	863	* @note If an erase and a program operations are requested simultaneously,
GiJeongKim	0:d885866e7cbf	864	* the erase operation is performed before the program one.
GiJeongKim	0:d885866e7cbf	865	*
GiJeongKim	0:d885866e7cbf	866	* @param Address: specifies the address to be programmed.
GiJeongKim	0:d885866e7cbf	867	* This parameter can be any address in Program memory zone or in OTP zone.
GiJeongKim	0:d885866e7cbf	868	* @param Data: specifies the data to be programmed.
GiJeongKim	0:d885866e7cbf	869	* @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
GiJeongKim	0:d885866e7cbf	870	* FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
GiJeongKim	0:d885866e7cbf	871	*/
GiJeongKim	0:d885866e7cbf	872	FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
GiJeongKim	0:d885866e7cbf	873	{
GiJeongKim	0:d885866e7cbf	874	FLASH_Status status = FLASH_COMPLETE2;
GiJeongKim	0:d885866e7cbf	875
GiJeongKim	0:d885866e7cbf	876	/* Check the parameters */
GiJeongKim	0:d885866e7cbf	877	assert_param(IS_FLASH_ADDRESS(Address));
GiJeongKim	0:d885866e7cbf	878
GiJeongKim	0:d885866e7cbf	879	/* Wait for last operation to be completed */
GiJeongKim	0:d885866e7cbf	880	status = FLASH_WaitForLastOperation2();
GiJeongKim	0:d885866e7cbf	881
GiJeongKim	0:d885866e7cbf	882	if(status == FLASH_COMPLETE2)
GiJeongKim	0:d885866e7cbf	883	{
GiJeongKim	0:d885866e7cbf	884	/* if the previous operation is completed, proceed to program the new data */
GiJeongKim	0:d885866e7cbf	885	FLASH->CR &= CR_PSIZE_MASK;
GiJeongKim	0:d885866e7cbf	886	FLASH->CR \|= FLASH_PSIZE_BYTE;
GiJeongKim	0:d885866e7cbf	887	FLASH->CR \|= FLASH_CR_PG;
GiJeongKim	0:d885866e7cbf	888
GiJeongKim	0:d885866e7cbf	889	(__IO uint8_t)Address = Data;
GiJeongKim	0:d885866e7cbf	890
GiJeongKim	0:d885866e7cbf	891	/* Wait for last operation to be completed */
GiJeongKim	0:d885866e7cbf	892	status = FLASH_WaitForLastOperation2();
GiJeongKim	0:d885866e7cbf	893
GiJeongKim	0:d885866e7cbf	894	/* if the program operation is completed, disable the PG Bit */
GiJeongKim	0:d885866e7cbf	895	FLASH->CR &= (~FLASH_CR_PG);
GiJeongKim	0:d885866e7cbf	896	}
GiJeongKim	0:d885866e7cbf	897
GiJeongKim	0:d885866e7cbf	898	/* Return the Program Status */
GiJeongKim	0:d885866e7cbf	899	return status;
GiJeongKim	0:d885866e7cbf	900	}
GiJeongKim	0:d885866e7cbf	901
GiJeongKim	0:d885866e7cbf	902	/**
GiJeongKim	0:d885866e7cbf	903	* @}
GiJeongKim	0:d885866e7cbf	904	*/
GiJeongKim	0:d885866e7cbf	905
GiJeongKim	0:d885866e7cbf	906	/** @defgroup FLASH_Group3 Option Bytes Programming functions
GiJeongKim	0:d885866e7cbf	907	* @brief Option Bytes Programming functions
GiJeongKim	0:d885866e7cbf	908	*
GiJeongKim	0:d885866e7cbf	909	@verbatim
GiJeongKim	0:d885866e7cbf	910	===============================================================================
GiJeongKim	0:d885866e7cbf	911	##### Option Bytes Programming functions #####
GiJeongKim	0:d885866e7cbf	912	===============================================================================
GiJeongKim	0:d885866e7cbf	913	[..]
GiJeongKim	0:d885866e7cbf	914	This group includes the following functions:
GiJeongKim	0:d885866e7cbf	915	(+) void FLASH_OB_Unlock(void)
GiJeongKim	0:d885866e7cbf	916	(+) void FLASH_OB_Lock(void)
GiJeongKim	0:d885866e7cbf	917	(+) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
GiJeongKim	0:d885866e7cbf	918	(+) void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState)
GiJeongKim	0:d885866e7cbf	919	(+) void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PCROPSelect)
GiJeongKim	0:d885866e7cbf	920	(+) void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState)
GiJeongKim	0:d885866e7cbf	921	(+) void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState)
GiJeongKim	0:d885866e7cbf	922	(+) void FLASH_OB_RDPConfig(uint8_t OB_RDP)
GiJeongKim	0:d885866e7cbf	923	(+) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
GiJeongKim	0:d885866e7cbf	924	(+) void FLASH_OB_BORConfig(uint8_t OB_BOR)
GiJeongKim	0:d885866e7cbf	925	(+) FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data)
GiJeongKim	0:d885866e7cbf	926	(+) FLASH_Status FLASH_OB_Launch(void)
GiJeongKim	0:d885866e7cbf	927	(+) uint32_t FLASH_OB_GetUser(void)
GiJeongKim	0:d885866e7cbf	928	(+) uint8_t FLASH_OB_GetWRP(void)
GiJeongKim	0:d885866e7cbf	929	(+) uint8_t FLASH_OB_GetWRP1(void)
GiJeongKim	0:d885866e7cbf	930	(+) uint8_t FLASH_OB_GetPCROP(void)
GiJeongKim	0:d885866e7cbf	931	(+) uint8_t FLASH_OB_GetPCROP1(void)
GiJeongKim	0:d885866e7cbf	932	(+) uint8_t FLASH_OB_GetRDP(void)
GiJeongKim	0:d885866e7cbf	933	(+) uint8_t FLASH_OB_GetBOR(void)
GiJeongKim	0:d885866e7cbf	934	[..]
GiJeongKim	0:d885866e7cbf	935	The following function can be used only for STM32F42xxx/43xxx devices.
GiJeongKim	0:d885866e7cbf	936	(+) void FLASH_OB_BootConfig(uint8_t OB_BOOT)
GiJeongKim	0:d885866e7cbf	937	[..]
GiJeongKim	0:d885866e7cbf	938	Any operation of erase or program should follow these steps:
GiJeongKim	0:d885866e7cbf	939	(#) Call the FLASH_OB_Unlock() function to enable the FLASH option control
GiJeongKim	0:d885866e7cbf	940	register access
GiJeongKim	0:d885866e7cbf	941
GiJeongKim	0:d885866e7cbf	942	(#) Call one or several functions to program the desired Option Bytes:
GiJeongKim	0:d885866e7cbf	943	(++) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
GiJeongKim	0:d885866e7cbf	944	=> to Enable/Disable the desired sector write protection
GiJeongKim	0:d885866e7cbf	945	(++) void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read
GiJeongKim	0:d885866e7cbf	946	Protection Level
GiJeongKim	0:d885866e7cbf	947	(++) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
GiJeongKim	0:d885866e7cbf	948	=> to configure the user Option Bytes.
GiJeongKim	0:d885866e7cbf	949	(++) void FLASH_OB_BORConfig(uint8_t OB_BOR) => to set the BOR Level
GiJeongKim	0:d885866e7cbf	950
GiJeongKim	0:d885866e7cbf	951	(#) Once all needed Option Bytes to be programmed are correctly written,
GiJeongKim	0:d885866e7cbf	952	call the FLASH_OB_Launch() function to launch the Option Bytes
GiJeongKim	0:d885866e7cbf	953	programming process.
GiJeongKim	0:d885866e7cbf	954
GiJeongKim	0:d885866e7cbf	955	-@- When changing the IWDG mode from HW to SW or from SW to HW, a system
GiJeongKim	0:d885866e7cbf	956	reset is needed to make the change effective.
GiJeongKim	0:d885866e7cbf	957
GiJeongKim	0:d885866e7cbf	958	(#) Call the FLASH_OB_Lock() function to disable the FLASH option control
GiJeongKim	0:d885866e7cbf	959	register access (recommended to protect the Option Bytes against
GiJeongKim	0:d885866e7cbf	960	possible unwanted operations)
GiJeongKim	0:d885866e7cbf	961
GiJeongKim	0:d885866e7cbf	962	@endverbatim
GiJeongKim	0:d885866e7cbf	963	* @{
GiJeongKim	0:d885866e7cbf	964	*/
GiJeongKim	0:d885866e7cbf	965
GiJeongKim	0:d885866e7cbf	966	/**
GiJeongKim	0:d885866e7cbf	967	* @brief Unlocks the FLASH Option Control Registers access.
GiJeongKim	0:d885866e7cbf	968	* @param None
GiJeongKim	0:d885866e7cbf	969	* @retval None
GiJeongKim	0:d885866e7cbf	970	*/
GiJeongKim	0:d885866e7cbf	971	void FLASH_OB_Unlock(void)
GiJeongKim	0:d885866e7cbf	972	{
GiJeongKim	0:d885866e7cbf	973	if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
GiJeongKim	0:d885866e7cbf	974	{
GiJeongKim	0:d885866e7cbf	975	/* Authorizes the Option Byte register programming */
GiJeongKim	0:d885866e7cbf	976	FLASH->OPTKEYR = FLASH_OPT_KEY1;
GiJeongKim	0:d885866e7cbf	977	FLASH->OPTKEYR = FLASH_OPT_KEY2;
GiJeongKim	0:d885866e7cbf	978	}
GiJeongKim	0:d885866e7cbf	979	}
GiJeongKim	0:d885866e7cbf	980
GiJeongKim	0:d885866e7cbf	981	/**
GiJeongKim	0:d885866e7cbf	982	* @brief Locks the FLASH Option Control Registers access.
GiJeongKim	0:d885866e7cbf	983	* @param None
GiJeongKim	0:d885866e7cbf	984	* @retval None
GiJeongKim	0:d885866e7cbf	985	*/
GiJeongKim	0:d885866e7cbf	986	void FLASH_OB_Lock(void)
GiJeongKim	0:d885866e7cbf	987	{
GiJeongKim	0:d885866e7cbf	988	/* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
GiJeongKim	0:d885866e7cbf	989	FLASH->OPTCR \|= FLASH_OPTCR_OPTLOCK;
GiJeongKim	0:d885866e7cbf	990	}
GiJeongKim	0:d885866e7cbf	991
GiJeongKim	0:d885866e7cbf	992	/**
GiJeongKim	0:d885866e7cbf	993	* @brief Enables or disables the write protection of the desired sectors, for the first
GiJeongKim	0:d885866e7cbf	994	* 1 Mb of the Flash
GiJeongKim	0:d885866e7cbf	995	*
GiJeongKim	0:d885866e7cbf	996	* @note When the memory read protection level is selected (RDP level = 1),
GiJeongKim	0:d885866e7cbf	997	* it is not possible to program or erase the flash sector i if CortexM4
GiJeongKim	0:d885866e7cbf	998	* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
GiJeongKim	0:d885866e7cbf	999	* @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
GiJeongKim	0:d885866e7cbf	1000	*
GiJeongKim	0:d885866e7cbf	1001	* @param OB_WRP: specifies the sector(s) to be write protected or unprotected.
GiJeongKim	0:d885866e7cbf	1002	* This parameter can be one of the following values:
GiJeongKim	0:d885866e7cbf	1003	* @arg OB_WRP: A value between OB_WRP_Sector0 and OB_WRP_Sector11
GiJeongKim	0:d885866e7cbf	1004	* @arg OB_WRP_Sector_All
GiJeongKim	0:d885866e7cbf	1005	* @param Newstate: new state of the Write Protection.
GiJeongKim	0:d885866e7cbf	1006	* This parameter can be: ENABLE or DISABLE.
GiJeongKim	0:d885866e7cbf	1007	* @retval None
GiJeongKim	0:d885866e7cbf	1008	*/
GiJeongKim	0:d885866e7cbf	1009	void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
GiJeongKim	0:d885866e7cbf	1010	{
GiJeongKim	0:d885866e7cbf	1011	FLASH_Status status = FLASH_COMPLETE2;
GiJeongKim	0:d885866e7cbf	1012
GiJeongKim	0:d885866e7cbf	1013	/* Check the parameters */
GiJeongKim	0:d885866e7cbf	1014	assert_param(IS_OB_WRP(OB_WRP));
GiJeongKim	0:d885866e7cbf	1015	assert_param(IS_FUNCTIONAL_STATE(NewState));
GiJeongKim	0:d885866e7cbf	1016
GiJeongKim	0:d885866e7cbf	1017	status = FLASH_WaitForLastOperation2();
GiJeongKim	0:d885866e7cbf	1018
GiJeongKim	0:d885866e7cbf	1019	if(status == FLASH_COMPLETE2)
GiJeongKim	0:d885866e7cbf	1020	{
GiJeongKim	0:d885866e7cbf	1021	if(NewState != DISABLE)
GiJeongKim	0:d885866e7cbf	1022	{
GiJeongKim	0:d885866e7cbf	1023	(__IO uint16_t)OPTCR_BYTE2_ADDRESS &= (~OB_WRP);
GiJeongKim	0:d885866e7cbf	1024	}
GiJeongKim	0:d885866e7cbf	1025	else
GiJeongKim	0:d885866e7cbf	1026	{
GiJeongKim	0:d885866e7cbf	1027	(__IO uint16_t)OPTCR_BYTE2_ADDRESS \|= (uint16_t)OB_WRP;
GiJeongKim	0:d885866e7cbf	1028	}
GiJeongKim	0:d885866e7cbf	1029	}
GiJeongKim	0:d885866e7cbf	1030	}
GiJeongKim	0:d885866e7cbf	1031
GiJeongKim	0:d885866e7cbf	1032	/**
GiJeongKim	0:d885866e7cbf	1033	* @brief Enables or disables the write protection of the desired sectors, for the second
GiJeongKim	0:d885866e7cbf	1034	* 1 Mb of the Flash
GiJeongKim	0:d885866e7cbf	1035	*
GiJeongKim	0:d885866e7cbf	1036	* @note This function can be used only for STM32F42xxx/43xxx devices.
GiJeongKim	0:d885866e7cbf	1037	*
GiJeongKim	0:d885866e7cbf	1038	* @note When the memory read out protection is selected (RDP level = 1),
GiJeongKim	0:d885866e7cbf	1039	* it is not possible to program or erase the flash sector i if CortexM4
GiJeongKim	0:d885866e7cbf	1040	* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
GiJeongKim	0:d885866e7cbf	1041	* @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
GiJeongKim	0:d885866e7cbf	1042	*
GiJeongKim	0:d885866e7cbf	1043	* @param OB_WRP: specifies the sector(s) to be write protected or unprotected.
GiJeongKim	0:d885866e7cbf	1044	* This parameter can be one of the following values:
GiJeongKim	0:d885866e7cbf	1045	* @arg OB_WRP: A value between OB_WRP_Sector12 and OB_WRP_Sector23
GiJeongKim	0:d885866e7cbf	1046	* @arg OB_WRP_Sector_All
GiJeongKim	0:d885866e7cbf	1047	* @param Newstate: new state of the Write Protection.
GiJeongKim	0:d885866e7cbf	1048	* This parameter can be: ENABLE or DISABLE.
GiJeongKim	0:d885866e7cbf	1049	* @retval None
GiJeongKim	0:d885866e7cbf	1050	*/
GiJeongKim	0:d885866e7cbf	1051	void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState)
GiJeongKim	0:d885866e7cbf	1052	{
GiJeongKim	0:d885866e7cbf	1053	FLASH_Status status = FLASH_COMPLETE2;
GiJeongKim	0:d885866e7cbf	1054
GiJeongKim	0:d885866e7cbf	1055	/* Check the parameters */
GiJeongKim	0:d885866e7cbf	1056	assert_param(IS_OB_WRP(OB_WRP));
GiJeongKim	0:d885866e7cbf	1057	assert_param(IS_FUNCTIONAL_STATE(NewState));
GiJeongKim	0:d885866e7cbf	1058
GiJeongKim	0:d885866e7cbf	1059	status = FLASH_WaitForLastOperation2();
GiJeongKim	0:d885866e7cbf	1060
GiJeongKim	0:d885866e7cbf	1061	if(status == FLASH_COMPLETE2)
GiJeongKim	0:d885866e7cbf	1062	{
GiJeongKim	0:d885866e7cbf	1063	if(NewState != DISABLE)
GiJeongKim	0:d885866e7cbf	1064	{
GiJeongKim	0:d885866e7cbf	1065	(__IO uint16_t)OPTCR1_BYTE2_ADDRESS &= (~OB_WRP);
GiJeongKim	0:d885866e7cbf	1066	}
GiJeongKim	0:d885866e7cbf	1067	else
GiJeongKim	0:d885866e7cbf	1068	{
GiJeongKim	0:d885866e7cbf	1069	(__IO uint16_t)OPTCR1_BYTE2_ADDRESS \|= (uint16_t)OB_WRP;
GiJeongKim	0:d885866e7cbf	1070	}
GiJeongKim	0:d885866e7cbf	1071	}
GiJeongKim	0:d885866e7cbf	1072	}
GiJeongKim	0:d885866e7cbf	1073
GiJeongKim	0:d885866e7cbf	1074	/**
GiJeongKim	0:d885866e7cbf	1075	* @brief Select the Protection Mode (SPRMOD).
GiJeongKim	0:d885866e7cbf	1076	*
GiJeongKim	0:d885866e7cbf	1077	* @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices.
GiJeongKim	0:d885866e7cbf	1078	*
GiJeongKim	0:d885866e7cbf	1079	* @note After PCROP activation, Option Byte modification is not possible.
GiJeongKim	0:d885866e7cbf	1080	* Exception made for the global Read Out Protection modification level (level1 to level0)
GiJeongKim	0:d885866e7cbf	1081	* @note Once SPRMOD bit is active unprotection of a protected sector is not possible
GiJeongKim	0:d885866e7cbf	1082	*
GiJeongKim	0:d885866e7cbf	1083	* @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
GiJeongKim	0:d885866e7cbf	1084	*
GiJeongKim	0:d885866e7cbf	1085	* @note Some Precautions should be taken when activating the PCROP feature :
GiJeongKim	0:d885866e7cbf	1086	* The active value of nWRPi bits is inverted when PCROP mode is active, this means if SPRMOD = 1
GiJeongKim	0:d885866e7cbf	1087	* and WRPi = 1 (default value), then the user sector i is read/write protected.
GiJeongKim	0:d885866e7cbf	1088	* In order to avoid activation of PCROP Mode for undesired sectors, please follow the
GiJeongKim	0:d885866e7cbf	1089	* below safety sequence :
GiJeongKim	0:d885866e7cbf	1090	* - Disable PCROP for all Sectors using FLASH_OB_PCROPConfig(OB_PCROP_Sector_All, DISABLE) function
GiJeongKim	0:d885866e7cbf	1091	* for Bank1 or FLASH_OB_PCROP1Config(OB_PCROP_Sector_All, DISABLE) function for Bank2
GiJeongKim	0:d885866e7cbf	1092	* - Enable PCROP for the desired Sector i using FLASH_OB_PCROPConfig(Sector i, ENABLE) function
GiJeongKim	0:d885866e7cbf	1093	* - Activate the PCROP Mode FLASH_OB_PCROPSelectionConfig() function.
GiJeongKim	0:d885866e7cbf	1094	*
GiJeongKim	0:d885866e7cbf	1095	* @param OB_PCROP: Select the Protection Mode of nWPRi bits
GiJeongKim	0:d885866e7cbf	1096	* This parameter can be one of the following values:
GiJeongKim	0:d885866e7cbf	1097	* @arg OB_PcROP_Disable: nWRPi control the write protection of respective user sectors.
GiJeongKim	0:d885866e7cbf	1098	* @arg OB_PcROP_Enable: nWRPi control the read&write protection (PCROP) of respective user sectors.
GiJeongKim	0:d885866e7cbf	1099	* @retval None
GiJeongKim	0:d885866e7cbf	1100	*/
GiJeongKim	0:d885866e7cbf	1101	void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP)
GiJeongKim	0:d885866e7cbf	1102	{
GiJeongKim	0:d885866e7cbf	1103	uint8_t optiontmp = 0xFF;
GiJeongKim	0:d885866e7cbf	1104
GiJeongKim	0:d885866e7cbf	1105	/* Check the parameters */
GiJeongKim	0:d885866e7cbf	1106	assert_param(IS_OB_PCROP_SELECT(OB_PcROP));
GiJeongKim	0:d885866e7cbf	1107
GiJeongKim	0:d885866e7cbf	1108	/* Mask SPRMOD bit */
GiJeongKim	0:d885866e7cbf	1109	optiontmp = (uint8_t)(((__IO uint8_t )OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F);
GiJeongKim	0:d885866e7cbf	1110	/* Update Option Byte */
GiJeongKim	0:d885866e7cbf	1111	(__IO uint8_t )OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PcROP \| optiontmp);
GiJeongKim	0:d885866e7cbf	1112
GiJeongKim	0:d885866e7cbf	1113	}
GiJeongKim	0:d885866e7cbf	1114
GiJeongKim	0:d885866e7cbf	1115	/**
GiJeongKim	0:d885866e7cbf	1116	* @brief Enables or disables the read/write protection (PCROP) of the desired
GiJeongKim	0:d885866e7cbf	1117	* sectors, for the first 1 MB of the Flash.
GiJeongKim	0:d885866e7cbf	1118	*
GiJeongKim	0:d885866e7cbf	1119	* @note This function can be used only for STM32F42xxx/43xxx , STM32F401xx/411xE
GiJeongKim	0:d885866e7cbf	1120	* and STM32F412xG devices.
GiJeongKim	0:d885866e7cbf	1121	*
GiJeongKim	0:d885866e7cbf	1122	* @param OB_PCROP: specifies the sector(s) to be read/write protected or unprotected.
GiJeongKim	0:d885866e7cbf	1123	* This parameter can be one of the following values:
GiJeongKim	0:d885866e7cbf	1124	* @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector11 for
GiJeongKim	0:d885866e7cbf	1125	* STM32F42xxx/43xxx devices and between OB_PCROP_Sector0 and
GiJeongKim	0:d885866e7cbf	1126	* OB_PCROP_Sector5 for STM32F401xx/411xE devices.
GiJeongKim	0:d885866e7cbf	1127	* @arg OB_PCROP_Sector_All
GiJeongKim	0:d885866e7cbf	1128	* @param Newstate: new state of the Write Protection.
GiJeongKim	0:d885866e7cbf	1129	* This parameter can be: ENABLE or DISABLE.
GiJeongKim	0:d885866e7cbf	1130	* @retval None
GiJeongKim	0:d885866e7cbf	1131	*/
GiJeongKim	0:d885866e7cbf	1132	void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState)
GiJeongKim	0:d885866e7cbf	1133	{
GiJeongKim	0:d885866e7cbf	1134	FLASH_Status status = FLASH_COMPLETE2;
GiJeongKim	0:d885866e7cbf	1135
GiJeongKim	0:d885866e7cbf	1136	/* Check the parameters */
GiJeongKim	0:d885866e7cbf	1137	assert_param(IS_OB_PCROP(OB_PCROP));
GiJeongKim	0:d885866e7cbf	1138	assert_param(IS_FUNCTIONAL_STATE(NewState));
GiJeongKim	0:d885866e7cbf	1139
GiJeongKim	0:d885866e7cbf	1140	status = FLASH_WaitForLastOperation2();
GiJeongKim	0:d885866e7cbf	1141
GiJeongKim	0:d885866e7cbf	1142	if(status == FLASH_COMPLETE2)
GiJeongKim	0:d885866e7cbf	1143	{
GiJeongKim	0:d885866e7cbf	1144	if(NewState != DISABLE)
GiJeongKim	0:d885866e7cbf	1145	{
GiJeongKim	0:d885866e7cbf	1146	(__IO uint16_t)OPTCR_BYTE2_ADDRESS \|= (uint16_t)OB_PCROP;
GiJeongKim	0:d885866e7cbf	1147	}
GiJeongKim	0:d885866e7cbf	1148	else
GiJeongKim	0:d885866e7cbf	1149	{
GiJeongKim	0:d885866e7cbf	1150	(__IO uint16_t)OPTCR_BYTE2_ADDRESS &= (~OB_PCROP);
GiJeongKim	0:d885866e7cbf	1151	}
GiJeongKim	0:d885866e7cbf	1152	}
GiJeongKim	0:d885866e7cbf	1153	}
GiJeongKim	0:d885866e7cbf	1154
GiJeongKim	0:d885866e7cbf	1155	/**
GiJeongKim	0:d885866e7cbf	1156	* @brief Enables or disables the read/write protection (PCROP) of the desired
GiJeongKim	0:d885866e7cbf	1157	* sectors
GiJeongKim	0:d885866e7cbf	1158	*
GiJeongKim	0:d885866e7cbf	1159	* @note This function can be used only for STM32F42xxx/43xxx devices.
GiJeongKim	0:d885866e7cbf	1160	*
GiJeongKim	0:d885866e7cbf	1161	* @param OB_PCROP: specifies the sector(s) to be read/write protected or unprotected.
GiJeongKim	0:d885866e7cbf	1162	* This parameter can be one of the following values:
GiJeongKim	0:d885866e7cbf	1163	* @arg OB_PCROP: A value between OB_PCROP_Sector12 and OB_PCROP_Sector23
GiJeongKim	0:d885866e7cbf	1164	* @arg OB_PCROP_Sector_All
GiJeongKim	0:d885866e7cbf	1165	* @param Newstate: new state of the Write Protection.
GiJeongKim	0:d885866e7cbf	1166	* This parameter can be: ENABLE or DISABLE.
GiJeongKim	0:d885866e7cbf	1167	* @retval None
GiJeongKim	0:d885866e7cbf	1168	*/
GiJeongKim	0:d885866e7cbf	1169	void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState)
GiJeongKim	0:d885866e7cbf	1170	{
GiJeongKim	0:d885866e7cbf	1171	FLASH_Status status = FLASH_COMPLETE2;
GiJeongKim	0:d885866e7cbf	1172
GiJeongKim	0:d885866e7cbf	1173	/* Check the parameters */
GiJeongKim	0:d885866e7cbf	1174	assert_param(IS_OB_PCROP(OB_PCROP));
GiJeongKim	0:d885866e7cbf	1175	assert_param(IS_FUNCTIONAL_STATE(NewState));
GiJeongKim	0:d885866e7cbf	1176
GiJeongKim	0:d885866e7cbf	1177	status = FLASH_WaitForLastOperation2();
GiJeongKim	0:d885866e7cbf	1178
GiJeongKim	0:d885866e7cbf	1179	if(status == FLASH_COMPLETE2)
GiJeongKim	0:d885866e7cbf	1180	{
GiJeongKim	0:d885866e7cbf	1181	if(NewState != DISABLE)
GiJeongKim	0:d885866e7cbf	1182	{
GiJeongKim	0:d885866e7cbf	1183	(__IO uint16_t)OPTCR1_BYTE2_ADDRESS \|= (uint16_t)OB_PCROP;
GiJeongKim	0:d885866e7cbf	1184	}
GiJeongKim	0:d885866e7cbf	1185	else
GiJeongKim	0:d885866e7cbf	1186	{
GiJeongKim	0:d885866e7cbf	1187	(__IO uint16_t)OPTCR1_BYTE2_ADDRESS &= (~OB_PCROP);
GiJeongKim	0:d885866e7cbf	1188	}
GiJeongKim	0:d885866e7cbf	1189	}
GiJeongKim	0:d885866e7cbf	1190	}
GiJeongKim	0:d885866e7cbf	1191
GiJeongKim	0:d885866e7cbf	1192
GiJeongKim	0:d885866e7cbf	1193	/**
GiJeongKim	0:d885866e7cbf	1194	* @brief Sets the read protection level.
GiJeongKim	0:d885866e7cbf	1195	* @param OB_RDP: specifies the read protection level.
GiJeongKim	0:d885866e7cbf	1196	* This parameter can be one of the following values:
GiJeongKim	0:d885866e7cbf	1197	* @arg OB_RDP_Level_0: No protection
GiJeongKim	0:d885866e7cbf	1198	* @arg OB_RDP_Level_1: Read protection of the memory
GiJeongKim	0:d885866e7cbf	1199	* @arg OB_RDP_Level_2: Full chip protection
GiJeongKim	0:d885866e7cbf	1200	*
GiJeongKim	0:d885866e7cbf	1201	* /!\ Warning /!\ When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
GiJeongKim	0:d885866e7cbf	1202	*
GiJeongKim	0:d885866e7cbf	1203	* @retval None
GiJeongKim	0:d885866e7cbf	1204	*/
GiJeongKim	0:d885866e7cbf	1205	void FLASH_OB_RDPConfig(uint8_t OB_RDP)
GiJeongKim	0:d885866e7cbf	1206	{
GiJeongKim	0:d885866e7cbf	1207	FLASH_Status status = FLASH_COMPLETE2;
GiJeongKim	0:d885866e7cbf	1208
GiJeongKim	0:d885866e7cbf	1209	/* Check the parameters */
GiJeongKim	0:d885866e7cbf	1210	assert_param(IS_OB_RDP(OB_RDP));
GiJeongKim	0:d885866e7cbf	1211
GiJeongKim	0:d885866e7cbf	1212	status = FLASH_WaitForLastOperation2();
GiJeongKim	0:d885866e7cbf	1213
GiJeongKim	0:d885866e7cbf	1214	if(status == FLASH_COMPLETE2)
GiJeongKim	0:d885866e7cbf	1215	{
GiJeongKim	0:d885866e7cbf	1216	(__IO uint8_t)OPTCR_BYTE1_ADDRESS = OB_RDP;
GiJeongKim	0:d885866e7cbf	1217
GiJeongKim	0:d885866e7cbf	1218	}
GiJeongKim	0:d885866e7cbf	1219	}
GiJeongKim	0:d885866e7cbf	1220
GiJeongKim	0:d885866e7cbf	1221	/**
GiJeongKim	0:d885866e7cbf	1222	* @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
GiJeongKim	0:d885866e7cbf	1223	* @param OB_IWDG: Selects the IWDG mode
GiJeongKim	0:d885866e7cbf	1224	* This parameter can be one of the following values:
GiJeongKim	0:d885866e7cbf	1225	* @arg OB_IWDG_SW: Software IWDG selected
GiJeongKim	0:d885866e7cbf	1226	* @arg OB_IWDG_HW: Hardware IWDG selected
GiJeongKim	0:d885866e7cbf	1227	* @param OB_STOP: Reset event when entering STOP mode.
GiJeongKim	0:d885866e7cbf	1228	* This parameter can be one of the following values:
GiJeongKim	0:d885866e7cbf	1229	* @arg OB_STOP_NoRST: No reset generated when entering in STOP
GiJeongKim	0:d885866e7cbf	1230	* @arg OB_STOP_RST: Reset generated when entering in STOP
GiJeongKim	0:d885866e7cbf	1231	* @param OB_STDBY: Reset event when entering Standby mode.
GiJeongKim	0:d885866e7cbf	1232	* This parameter can be one of the following values:
GiJeongKim	0:d885866e7cbf	1233	* @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
GiJeongKim	0:d885866e7cbf	1234	* @arg OB_STDBY_RST: Reset generated when entering in STANDBY
GiJeongKim	0:d885866e7cbf	1235	* @retval None
GiJeongKim	0:d885866e7cbf	1236	*/
GiJeongKim	0:d885866e7cbf	1237	void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
GiJeongKim	0:d885866e7cbf	1238	{
GiJeongKim	0:d885866e7cbf	1239	uint8_t optiontmp = 0xFF;
GiJeongKim	0:d885866e7cbf	1240	FLASH_Status status = FLASH_COMPLETE2;
GiJeongKim	0:d885866e7cbf	1241
GiJeongKim	0:d885866e7cbf	1242	/* Check the parameters */
GiJeongKim	0:d885866e7cbf	1243	assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
GiJeongKim	0:d885866e7cbf	1244	assert_param(IS_OB_STOP_SOURCE(OB_STOP));
GiJeongKim	0:d885866e7cbf	1245	assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
GiJeongKim	0:d885866e7cbf	1246
GiJeongKim	0:d885866e7cbf	1247	/* Wait for last operation to be completed */
GiJeongKim	0:d885866e7cbf	1248	status = FLASH_WaitForLastOperation2();
GiJeongKim	0:d885866e7cbf	1249
GiJeongKim	0:d885866e7cbf	1250	if(status == FLASH_COMPLETE2)
GiJeongKim	0:d885866e7cbf	1251	{
GiJeongKim	0:d885866e7cbf	1252	#if defined(STM32F427_437xx) \|\| defined(STM32F429_439xx) \|\| defined(STM32F469_479xx)
GiJeongKim	0:d885866e7cbf	1253	/* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */
GiJeongKim	0:d885866e7cbf	1254	optiontmp = (uint8_t)(((__IO uint8_t )OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F);
GiJeongKim	0:d885866e7cbf	1255	#endif /* STM32F427_437xx \|\| STM32F429_439xx \|\| STM32F469_479xx */
GiJeongKim	0:d885866e7cbf	1256
GiJeongKim	0:d885866e7cbf	1257	#if defined(STM32F40_41xxx) \|\| defined(STM32F401xx) \|\| defined(STM32F410xx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx)
GiJeongKim	0:d885866e7cbf	1258	/* Mask OPTLOCK, OPTSTRT and BOR_LEV bits */
GiJeongKim	0:d885866e7cbf	1259	optiontmp = (uint8_t)(((__IO uint8_t )OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0F);
GiJeongKim	0:d885866e7cbf	1260	#endif /* STM32F40_41xxx \|\| STM32F401xx \|\| STM32F410xx \|\| STM32F411xE \|\| STM32F446xx */
GiJeongKim	0:d885866e7cbf	1261
GiJeongKim	0:d885866e7cbf	1262	/* Update User Option Byte */
GiJeongKim	0:d885866e7cbf	1263	(__IO uint8_t )OPTCR_BYTE0_ADDRESS = OB_IWDG \| (uint8_t)(OB_STDBY \| (uint8_t)(OB_STOP \| ((uint8_t)optiontmp)));
GiJeongKim	0:d885866e7cbf	1264	}
GiJeongKim	0:d885866e7cbf	1265	}
GiJeongKim	0:d885866e7cbf	1266
GiJeongKim	0:d885866e7cbf	1267	/**
GiJeongKim	0:d885866e7cbf	1268	* @brief Configure the Dual Bank Boot.
GiJeongKim	0:d885866e7cbf	1269	*
GiJeongKim	0:d885866e7cbf	1270	* @note This function can be used only for STM32F42xxx/43xxx devices.
GiJeongKim	0:d885866e7cbf	1271	*
GiJeongKim	0:d885866e7cbf	1272	* @param OB_BOOT: specifies the Dual Bank Boot Option byte.
GiJeongKim	0:d885866e7cbf	1273	* This parameter can be one of the following values:
GiJeongKim	0:d885866e7cbf	1274	* @arg OB_Dual_BootEnabled: Dual Bank Boot Enable
GiJeongKim	0:d885866e7cbf	1275	* @arg OB_Dual_BootDisabled: Dual Bank Boot Disabled
GiJeongKim	0:d885866e7cbf	1276	* @retval None
GiJeongKim	0:d885866e7cbf	1277	*/
GiJeongKim	0:d885866e7cbf	1278	void FLASH_OB_BootConfig(uint8_t OB_BOOT)
GiJeongKim	0:d885866e7cbf	1279	{
GiJeongKim	0:d885866e7cbf	1280	/* Check the parameters */
GiJeongKim	0:d885866e7cbf	1281	assert_param(IS_OB_BOOT(OB_BOOT));
GiJeongKim	0:d885866e7cbf	1282
GiJeongKim	0:d885866e7cbf	1283	/* Set Dual Bank Boot */
GiJeongKim	0:d885866e7cbf	1284	(__IO uint8_t )OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2);
GiJeongKim	0:d885866e7cbf	1285	(__IO uint8_t )OPTCR_BYTE0_ADDRESS \|= OB_BOOT;
GiJeongKim	0:d885866e7cbf	1286
GiJeongKim	0:d885866e7cbf	1287	}
GiJeongKim	0:d885866e7cbf	1288
GiJeongKim	0:d885866e7cbf	1289	/**
GiJeongKim	0:d885866e7cbf	1290	* @brief Sets the BOR Level.
GiJeongKim	0:d885866e7cbf	1291	* @param OB_BOR: specifies the Option Bytes BOR Reset Level.
GiJeongKim	0:d885866e7cbf	1292	* This parameter can be one of the following values:
GiJeongKim	0:d885866e7cbf	1293	* @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
GiJeongKim	0:d885866e7cbf	1294	* @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
GiJeongKim	0:d885866e7cbf	1295	* @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
GiJeongKim	0:d885866e7cbf	1296	* @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
GiJeongKim	0:d885866e7cbf	1297	* @retval None
GiJeongKim	0:d885866e7cbf	1298	*/
GiJeongKim	0:d885866e7cbf	1299	void FLASH_OB_BORConfig(uint8_t OB_BOR)
GiJeongKim	0:d885866e7cbf	1300	{
GiJeongKim	0:d885866e7cbf	1301	/* Check the parameters */
GiJeongKim	0:d885866e7cbf	1302	assert_param(IS_OB_BOR(OB_BOR));
GiJeongKim	0:d885866e7cbf	1303
GiJeongKim	0:d885866e7cbf	1304	/* Set the BOR Level */
GiJeongKim	0:d885866e7cbf	1305	(__IO uint8_t )OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV);
GiJeongKim	0:d885866e7cbf	1306	(__IO uint8_t )OPTCR_BYTE0_ADDRESS \|= OB_BOR;
GiJeongKim	0:d885866e7cbf	1307
GiJeongKim	0:d885866e7cbf	1308	}
GiJeongKim	0:d885866e7cbf	1309
GiJeongKim	0:d885866e7cbf	1310	/**
GiJeongKim	0:d885866e7cbf	1311	* @brief Launch the option byte loading.
GiJeongKim	0:d885866e7cbf	1312	* @param None
GiJeongKim	0:d885866e7cbf	1313	* @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
GiJeongKim	0:d885866e7cbf	1314	* FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
GiJeongKim	0:d885866e7cbf	1315	*/
GiJeongKim	0:d885866e7cbf	1316	FLASH_Status FLASH_OB_Launch(void)
GiJeongKim	0:d885866e7cbf	1317	{
GiJeongKim	0:d885866e7cbf	1318	FLASH_Status status = FLASH_COMPLETE2;
GiJeongKim	0:d885866e7cbf	1319
GiJeongKim	0:d885866e7cbf	1320	/* Set the OPTSTRT bit in OPTCR register */
GiJeongKim	0:d885866e7cbf	1321	(__IO uint8_t )OPTCR_BYTE0_ADDRESS \|= FLASH_OPTCR_OPTSTRT;
GiJeongKim	0:d885866e7cbf	1322
GiJeongKim	0:d885866e7cbf	1323	/* Wait for last operation to be completed */
GiJeongKim	0:d885866e7cbf	1324	status = FLASH_WaitForLastOperation2();
GiJeongKim	0:d885866e7cbf	1325
GiJeongKim	0:d885866e7cbf	1326	return status;
GiJeongKim	0:d885866e7cbf	1327	}
GiJeongKim	0:d885866e7cbf	1328
GiJeongKim	0:d885866e7cbf	1329	/**
GiJeongKim	0:d885866e7cbf	1330	* @brief Returns the FLASH User Option Bytes values.
GiJeongKim	0:d885866e7cbf	1331	* @param None
GiJeongKim	0:d885866e7cbf	1332	* @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)
GiJeongKim	0:d885866e7cbf	1333	* and RST_STDBY(Bit2).
GiJeongKim	0:d885866e7cbf	1334	*/
GiJeongKim	0:d885866e7cbf	1335	uint8_t FLASH_OB_GetUser(void)
GiJeongKim	0:d885866e7cbf	1336	{
GiJeongKim	0:d885866e7cbf	1337	/* Return the User Option Byte */
GiJeongKim	0:d885866e7cbf	1338	return (uint8_t)(FLASH->OPTCR >> 5);
GiJeongKim	0:d885866e7cbf	1339	}
GiJeongKim	0:d885866e7cbf	1340
GiJeongKim	0:d885866e7cbf	1341	/**
GiJeongKim	0:d885866e7cbf	1342	* @brief Returns the FLASH Write Protection Option Bytes value.
GiJeongKim	0:d885866e7cbf	1343	* @param None
GiJeongKim	0:d885866e7cbf	1344	* @retval The FLASH Write Protection Option Bytes value
GiJeongKim	0:d885866e7cbf	1345	*/
GiJeongKim	0:d885866e7cbf	1346	uint16_t FLASH_OB_GetWRP(void)
GiJeongKim	0:d885866e7cbf	1347	{
GiJeongKim	0:d885866e7cbf	1348	/* Return the FLASH write protection Register value */
GiJeongKim	0:d885866e7cbf	1349	return ((__IO uint16_t )(OPTCR_BYTE2_ADDRESS));
GiJeongKim	0:d885866e7cbf	1350	}
GiJeongKim	0:d885866e7cbf	1351
GiJeongKim	0:d885866e7cbf	1352	/**
GiJeongKim	0:d885866e7cbf	1353	* @brief Returns the FLASH Write Protection Option Bytes value.
GiJeongKim	0:d885866e7cbf	1354	*
GiJeongKim	0:d885866e7cbf	1355	* @note This function can be used only for STM32F42xxx/43xxx devices.
GiJeongKim	0:d885866e7cbf	1356	*
GiJeongKim	0:d885866e7cbf	1357	* @param None
GiJeongKim	0:d885866e7cbf	1358	* @retval The FLASH Write Protection Option Bytes value
GiJeongKim	0:d885866e7cbf	1359	*/
GiJeongKim	0:d885866e7cbf	1360	uint16_t FLASH_OB_GetWRP1(void)
GiJeongKim	0:d885866e7cbf	1361	{
GiJeongKim	0:d885866e7cbf	1362	/* Return the FLASH write protection Register value */
GiJeongKim	0:d885866e7cbf	1363	return ((__IO uint16_t )(OPTCR1_BYTE2_ADDRESS));
GiJeongKim	0:d885866e7cbf	1364	}
GiJeongKim	0:d885866e7cbf	1365
GiJeongKim	0:d885866e7cbf	1366	/**
GiJeongKim	0:d885866e7cbf	1367	* @brief Returns the FLASH PC Read/Write Protection Option Bytes value.
GiJeongKim	0:d885866e7cbf	1368	*
GiJeongKim	0:d885866e7cbf	1369	* @note This function can be used only for STM32F42xxx/43xxx devices and STM32F401xx/411xE devices.
GiJeongKim	0:d885866e7cbf	1370	*
GiJeongKim	0:d885866e7cbf	1371	* @param None
GiJeongKim	0:d885866e7cbf	1372	* @retval The FLASH PC Read/Write Protection Option Bytes value
GiJeongKim	0:d885866e7cbf	1373	*/
GiJeongKim	0:d885866e7cbf	1374	uint16_t FLASH_OB_GetPCROP(void)
GiJeongKim	0:d885866e7cbf	1375	{
GiJeongKim	0:d885866e7cbf	1376	/* Return the FLASH PC Read/write protection Register value */
GiJeongKim	0:d885866e7cbf	1377	return ((__IO uint16_t )(OPTCR_BYTE2_ADDRESS));
GiJeongKim	0:d885866e7cbf	1378	}
GiJeongKim	0:d885866e7cbf	1379
GiJeongKim	0:d885866e7cbf	1380	/**
GiJeongKim	0:d885866e7cbf	1381	* @brief Returns the FLASH PC Read/Write Protection Option Bytes value.
GiJeongKim	0:d885866e7cbf	1382	*
GiJeongKim	0:d885866e7cbf	1383	* @note This function can be used only for STM32F42xxx/43xxx devices.
GiJeongKim	0:d885866e7cbf	1384	*
GiJeongKim	0:d885866e7cbf	1385	* @param None
GiJeongKim	0:d885866e7cbf	1386	* @retval The FLASH PC Read/Write Protection Option Bytes value
GiJeongKim	0:d885866e7cbf	1387	*/
GiJeongKim	0:d885866e7cbf	1388	uint16_t FLASH_OB_GetPCROP1(void)
GiJeongKim	0:d885866e7cbf	1389	{
GiJeongKim	0:d885866e7cbf	1390	/* Return the FLASH write protection Register value */
GiJeongKim	0:d885866e7cbf	1391	return ((__IO uint16_t )(OPTCR1_BYTE2_ADDRESS));
GiJeongKim	0:d885866e7cbf	1392	}
GiJeongKim	0:d885866e7cbf	1393
GiJeongKim	0:d885866e7cbf	1394	/**
GiJeongKim	0:d885866e7cbf	1395	* @brief Returns the FLASH Read Protection level.
GiJeongKim	0:d885866e7cbf	1396	* @param None
GiJeongKim	0:d885866e7cbf	1397	* @retval FLASH ReadOut Protection Status:
GiJeongKim	0:d885866e7cbf	1398	* - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set
GiJeongKim	0:d885866e7cbf	1399	* - RESET, when OB_RDP_Level_0 is set
GiJeongKim	0:d885866e7cbf	1400	*/
GiJeongKim	0:d885866e7cbf	1401	FlagStatus FLASH_OB_GetRDP(void)
GiJeongKim	0:d885866e7cbf	1402	{
GiJeongKim	0:d885866e7cbf	1403	FlagStatus readstatus = RESET;
GiJeongKim	0:d885866e7cbf	1404
GiJeongKim	0:d885866e7cbf	1405	if (((__IO uint8_t)(OPTCR_BYTE1_ADDRESS) != (uint8_t)OB_RDP_Level_0))
GiJeongKim	0:d885866e7cbf	1406	{
GiJeongKim	0:d885866e7cbf	1407	readstatus = SET;
GiJeongKim	0:d885866e7cbf	1408	}
GiJeongKim	0:d885866e7cbf	1409	else
GiJeongKim	0:d885866e7cbf	1410	{
GiJeongKim	0:d885866e7cbf	1411	readstatus = RESET;
GiJeongKim	0:d885866e7cbf	1412	}
GiJeongKim	0:d885866e7cbf	1413	return readstatus;
GiJeongKim	0:d885866e7cbf	1414	}
GiJeongKim	0:d885866e7cbf	1415
GiJeongKim	0:d885866e7cbf	1416	/**
GiJeongKim	0:d885866e7cbf	1417	* @brief Returns the FLASH BOR level.
GiJeongKim	0:d885866e7cbf	1418	* @param None
GiJeongKim	0:d885866e7cbf	1419	* @retval The FLASH BOR level:
GiJeongKim	0:d885866e7cbf	1420	* - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
GiJeongKim	0:d885866e7cbf	1421	* - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
GiJeongKim	0:d885866e7cbf	1422	* - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
GiJeongKim	0:d885866e7cbf	1423	* - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V
GiJeongKim	0:d885866e7cbf	1424	*/
GiJeongKim	0:d885866e7cbf	1425	uint8_t FLASH_OB_GetBOR(void)
GiJeongKim	0:d885866e7cbf	1426	{
GiJeongKim	0:d885866e7cbf	1427	/* Return the FLASH BOR level */
GiJeongKim	0:d885866e7cbf	1428	return (uint8_t)((__IO uint8_t )(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C);
GiJeongKim	0:d885866e7cbf	1429	}
GiJeongKim	0:d885866e7cbf	1430
GiJeongKim	0:d885866e7cbf	1431	/**
GiJeongKim	0:d885866e7cbf	1432	* @}
GiJeongKim	0:d885866e7cbf	1433	*/
GiJeongKim	0:d885866e7cbf	1434
GiJeongKim	0:d885866e7cbf	1435	/** @defgroup FLASH_Group4 Interrupts and flags management functions
GiJeongKim	0:d885866e7cbf	1436	* @brief Interrupts and flags management functions
GiJeongKim	0:d885866e7cbf	1437	*
GiJeongKim	0:d885866e7cbf	1438	@verbatim
GiJeongKim	0:d885866e7cbf	1439	===============================================================================
GiJeongKim	0:d885866e7cbf	1440	##### Interrupts and flags management functions #####
GiJeongKim	0:d885866e7cbf	1441	===============================================================================
GiJeongKim	0:d885866e7cbf	1442	@endverbatim
GiJeongKim	0:d885866e7cbf	1443	* @{
GiJeongKim	0:d885866e7cbf	1444	*/
GiJeongKim	0:d885866e7cbf	1445
GiJeongKim	0:d885866e7cbf	1446	/**
GiJeongKim	0:d885866e7cbf	1447	* @brief Enables or disables the specified FLASH interrupts.
GiJeongKim	0:d885866e7cbf	1448	* @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.
GiJeongKim	0:d885866e7cbf	1449	* This parameter can be any combination of the following values:
GiJeongKim	0:d885866e7cbf	1450	* @arg FLASH_IT_ERR: FLASH Error Interrupt
GiJeongKim	0:d885866e7cbf	1451	* @arg FLASH_IT_EOP: FLASH end of operation Interrupt
GiJeongKim	0:d885866e7cbf	1452	* @retval None
GiJeongKim	0:d885866e7cbf	1453	*/
GiJeongKim	0:d885866e7cbf	1454	void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
GiJeongKim	0:d885866e7cbf	1455	{
GiJeongKim	0:d885866e7cbf	1456	/* Check the parameters */
GiJeongKim	0:d885866e7cbf	1457	assert_param(IS_FLASH_IT(FLASH_IT));
GiJeongKim	0:d885866e7cbf	1458	assert_param(IS_FUNCTIONAL_STATE(NewState));
GiJeongKim	0:d885866e7cbf	1459
GiJeongKim	0:d885866e7cbf	1460	if(NewState != DISABLE)
GiJeongKim	0:d885866e7cbf	1461	{
GiJeongKim	0:d885866e7cbf	1462	/* Enable the interrupt sources */
GiJeongKim	0:d885866e7cbf	1463	FLASH->CR \|= FLASH_IT;
GiJeongKim	0:d885866e7cbf	1464	}
GiJeongKim	0:d885866e7cbf	1465	else
GiJeongKim	0:d885866e7cbf	1466	{
GiJeongKim	0:d885866e7cbf	1467	/* Disable the interrupt sources */
GiJeongKim	0:d885866e7cbf	1468	FLASH->CR &= ~(uint32_t)FLASH_IT;
GiJeongKim	0:d885866e7cbf	1469	}
GiJeongKim	0:d885866e7cbf	1470	}
GiJeongKim	0:d885866e7cbf	1471
GiJeongKim	0:d885866e7cbf	1472	/**
GiJeongKim	0:d885866e7cbf	1473	* @brief Checks whether the specified FLASH flag is set or not.
GiJeongKim	0:d885866e7cbf	1474	* @param FLASH_FLAG: specifies the FLASH flag to check.
GiJeongKim	0:d885866e7cbf	1475	* This parameter can be one of the following values:
GiJeongKim	0:d885866e7cbf	1476	* @arg FLASH_FLAG_EOP: FLASH End of Operation flag
GiJeongKim	0:d885866e7cbf	1477	* @arg FLASH_FLAG_OPERR: FLASH operation Error flag
GiJeongKim	0:d885866e7cbf	1478	* @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
GiJeongKim	0:d885866e7cbf	1479	* @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
GiJeongKim	0:d885866e7cbf	1480	* @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
GiJeongKim	0:d885866e7cbf	1481	* @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
GiJeongKim	0:d885866e7cbf	1482	* @arg FLASH_FLAG_RDERR: FLASH (PCROP) Read Protection error flag (STM32F42xx/43xxx and STM32F401xx/411xE devices)
GiJeongKim	0:d885866e7cbf	1483	* @arg FLASH_FLAG_BSY: FLASH Busy flag
GiJeongKim	0:d885866e7cbf	1484	* @retval The new state of FLASH_FLAG (SET or RESET).
GiJeongKim	0:d885866e7cbf	1485	*/
GiJeongKim	0:d885866e7cbf	1486	FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
GiJeongKim	0:d885866e7cbf	1487	{
GiJeongKim	0:d885866e7cbf	1488	FlagStatus bitstatus = RESET;
GiJeongKim	0:d885866e7cbf	1489	/* Check the parameters */
GiJeongKim	0:d885866e7cbf	1490	assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));
GiJeongKim	0:d885866e7cbf	1491
GiJeongKim	0:d885866e7cbf	1492	if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
GiJeongKim	0:d885866e7cbf	1493	{
GiJeongKim	0:d885866e7cbf	1494	bitstatus = SET;
GiJeongKim	0:d885866e7cbf	1495	}
GiJeongKim	0:d885866e7cbf	1496	else
GiJeongKim	0:d885866e7cbf	1497	{
GiJeongKim	0:d885866e7cbf	1498	bitstatus = RESET;
GiJeongKim	0:d885866e7cbf	1499	}
GiJeongKim	0:d885866e7cbf	1500	/* Return the new state of FLASH_FLAG (SET or RESET) */
GiJeongKim	0:d885866e7cbf	1501	return bitstatus;
GiJeongKim	0:d885866e7cbf	1502	}
GiJeongKim	0:d885866e7cbf	1503
GiJeongKim	0:d885866e7cbf	1504	/**
GiJeongKim	0:d885866e7cbf	1505	* @brief Clears the FLASH's pending flags.
GiJeongKim	0:d885866e7cbf	1506	* @param FLASH_FLAG: specifies the FLASH flags to clear.
GiJeongKim	0:d885866e7cbf	1507	* This parameter can be any combination of the following values:
GiJeongKim	0:d885866e7cbf	1508	* @arg FLASH_FLAG_EOP: FLASH End of Operation flag
GiJeongKim	0:d885866e7cbf	1509	* @arg FLASH_FLAG_OPERR: FLASH operation Error flag
GiJeongKim	0:d885866e7cbf	1510	* @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
GiJeongKim	0:d885866e7cbf	1511	* @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
GiJeongKim	0:d885866e7cbf	1512	* @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
GiJeongKim	0:d885866e7cbf	1513	* @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
GiJeongKim	0:d885866e7cbf	1514	* @arg FLASH_FLAG_RDERR: FLASH Read Protection error flag (STM32F42xx/43xxx and STM32F401xx/411xE devices)
GiJeongKim	0:d885866e7cbf	1515	* @retval None
GiJeongKim	0:d885866e7cbf	1516	*/
GiJeongKim	0:d885866e7cbf	1517	void FLASH_ClearFlag(uint32_t FLASH_FLAG)
GiJeongKim	0:d885866e7cbf	1518	{
GiJeongKim	0:d885866e7cbf	1519	/* Check the parameters */
GiJeongKim	0:d885866e7cbf	1520	assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));
GiJeongKim	0:d885866e7cbf	1521
GiJeongKim	0:d885866e7cbf	1522	/* Clear the flags */
GiJeongKim	0:d885866e7cbf	1523	FLASH->SR = FLASH_FLAG;
GiJeongKim	0:d885866e7cbf	1524	}
GiJeongKim	0:d885866e7cbf	1525
GiJeongKim	0:d885866e7cbf	1526	/**
GiJeongKim	0:d885866e7cbf	1527	* @brief Returns the FLASH Status.
GiJeongKim	0:d885866e7cbf	1528	* @param None
GiJeongKim	0:d885866e7cbf	1529	* @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
GiJeongKim	0:d885866e7cbf	1530	* FLASH_ERROR_WRP2, FLASH_ERROR_RD2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
GiJeongKim	0:d885866e7cbf	1531	*/
GiJeongKim	0:d885866e7cbf	1532	FLASH_Status FLASH_GetStatus(void)
GiJeongKim	0:d885866e7cbf	1533	{
GiJeongKim	0:d885866e7cbf	1534	FLASH_Status flashstatus = FLASH_COMPLETE2;
GiJeongKim	0:d885866e7cbf	1535
GiJeongKim	0:d885866e7cbf	1536	if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
GiJeongKim	0:d885866e7cbf	1537	{
GiJeongKim	0:d885866e7cbf	1538	flashstatus = FLASH_BUSY2;
GiJeongKim	0:d885866e7cbf	1539	}
GiJeongKim	0:d885866e7cbf	1540	else
GiJeongKim	0:d885866e7cbf	1541	{
GiJeongKim	0:d885866e7cbf	1542	if((FLASH->SR & FLASH_FLAG_WRPERR) != (uint32_t)0x00)
GiJeongKim	0:d885866e7cbf	1543	{
GiJeongKim	0:d885866e7cbf	1544	flashstatus = FLASH_ERROR_WRP2;
GiJeongKim	0:d885866e7cbf	1545	}
GiJeongKim	0:d885866e7cbf	1546	else
GiJeongKim	0:d885866e7cbf	1547	{
GiJeongKim	0:d885866e7cbf	1548	if((FLASH->SR & FLASH_FLAG_RDERR) != (uint32_t)0x00)
GiJeongKim	0:d885866e7cbf	1549	{
GiJeongKim	0:d885866e7cbf	1550	flashstatus = FLASH_ERROR_RD2;
GiJeongKim	0:d885866e7cbf	1551	}
GiJeongKim	0:d885866e7cbf	1552	else
GiJeongKim	0:d885866e7cbf	1553	{
GiJeongKim	0:d885866e7cbf	1554	if((FLASH->SR & (uint32_t)0xE0) != (uint32_t)0x00)
GiJeongKim	0:d885866e7cbf	1555	{
GiJeongKim	0:d885866e7cbf	1556	flashstatus = FLASH_ERROR_PROGRAM2;
GiJeongKim	0:d885866e7cbf	1557	}
GiJeongKim	0:d885866e7cbf	1558	else
GiJeongKim	0:d885866e7cbf	1559	{
GiJeongKim	0:d885866e7cbf	1560	if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00)
GiJeongKim	0:d885866e7cbf	1561	{
GiJeongKim	0:d885866e7cbf	1562	flashstatus = FLASH_ERROR_OPERATION2;
GiJeongKim	0:d885866e7cbf	1563	}
GiJeongKim	0:d885866e7cbf	1564	else
GiJeongKim	0:d885866e7cbf	1565	{
GiJeongKim	0:d885866e7cbf	1566	flashstatus = FLASH_COMPLETE2;
GiJeongKim	0:d885866e7cbf	1567	}
GiJeongKim	0:d885866e7cbf	1568	}
GiJeongKim	0:d885866e7cbf	1569	}
GiJeongKim	0:d885866e7cbf	1570	}
GiJeongKim	0:d885866e7cbf	1571	}
GiJeongKim	0:d885866e7cbf	1572	/* Return the FLASH Status */
GiJeongKim	0:d885866e7cbf	1573	return flashstatus;
GiJeongKim	0:d885866e7cbf	1574	}
GiJeongKim	0:d885866e7cbf	1575
GiJeongKim	0:d885866e7cbf	1576	/**
GiJeongKim	0:d885866e7cbf	1577	* @brief Waits for a FLASH operation to complete.
GiJeongKim	0:d885866e7cbf	1578	* @param None
GiJeongKim	0:d885866e7cbf	1579	* @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
GiJeongKim	0:d885866e7cbf	1580	* FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
GiJeongKim	0:d885866e7cbf	1581	*/
GiJeongKim	0:d885866e7cbf	1582	FLASH_Status FLASH_WaitForLastOperation2(void)
GiJeongKim	0:d885866e7cbf	1583	{
GiJeongKim	0:d885866e7cbf	1584	__IO FLASH_Status status = FLASH_COMPLETE2;
GiJeongKim	0:d885866e7cbf	1585
GiJeongKim	0:d885866e7cbf	1586	/* Check for the FLASH Status */
GiJeongKim	0:d885866e7cbf	1587	status = FLASH_GetStatus();
GiJeongKim	0:d885866e7cbf	1588
GiJeongKim	0:d885866e7cbf	1589	/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
GiJeongKim	0:d885866e7cbf	1590	Even if the FLASH operation fails, the BUSY flag will be reset and an error
GiJeongKim	0:d885866e7cbf	1591	flag will be set */
GiJeongKim	0:d885866e7cbf	1592	while(status == FLASH_BUSY2)
GiJeongKim	0:d885866e7cbf	1593	{
GiJeongKim	0:d885866e7cbf	1594	status = FLASH_GetStatus();
GiJeongKim	0:d885866e7cbf	1595	}
GiJeongKim	0:d885866e7cbf	1596	/* Return the operation status */
GiJeongKim	0:d885866e7cbf	1597	return status;
GiJeongKim	0:d885866e7cbf	1598	}
GiJeongKim	0:d885866e7cbf	1599
GiJeongKim	0:d885866e7cbf	1600	/**
GiJeongKim	0:d885866e7cbf	1601	* @}
GiJeongKim	0:d885866e7cbf	1602	*/
GiJeongKim	0:d885866e7cbf	1603
GiJeongKim	0:d885866e7cbf	1604	/**
GiJeongKim	0:d885866e7cbf	1605	* @}
GiJeongKim	0:d885866e7cbf	1606	*/
GiJeongKim	0:d885866e7cbf	1607
GiJeongKim	0:d885866e7cbf	1608	/**
GiJeongKim	0:d885866e7cbf	1609	* @}
GiJeongKim	0:d885866e7cbf	1610	*/
GiJeongKim	0:d885866e7cbf	1611
GiJeongKim	0:d885866e7cbf	1612	/**
GiJeongKim	0:d885866e7cbf	1613	* @}
GiJeongKim	0:d885866e7cbf	1614	*/
GiJeongKim	0:d885866e7cbf	1615
GiJeongKim	0:d885866e7cbf	1616	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	12 Aug 2019
Imports:	2
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	1

stm32f4xx_flash.c@0:d885866e7cbf, 2019-08-12 (annotated)

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