Frederick Huang / mbed-STM32L452

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Dependents:   STM32L452_Nucleo_ticker

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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_irda.c@182:59ec31722650, 2017-12-15 (annotated)

Committer:
Frederick_H
Date:
Fri Dec 15 08:17:23 2017 +0000
Revision:
182:59ec31722650
Parent:
151:5eaa88a5bcc7 
Modify hal_tick.h of TARGET_STM32L476xG

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l0xx_hal_irda.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 151:5eaa88a5bcc7 5 * @version V1.7.0
<> 151:5eaa88a5bcc7 6 * @date 31-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief IRDA HAL module driver.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 10 * functionalities of the IrDA (Infrared Data Association) Peripheral
<> 144:ef7eb2e8f9f7 11 * (IRDA)
<> 144:ef7eb2e8f9f7 12 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 13 * + IO operation functions
<> 144:ef7eb2e8f9f7 14 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 *
<> 144:ef7eb2e8f9f7 17 @verbatim
<> 144:ef7eb2e8f9f7 18 ===============================================================================
<> 144:ef7eb2e8f9f7 19 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 20 ===============================================================================
<> 144:ef7eb2e8f9f7 21 [..]
<> 144:ef7eb2e8f9f7 22 The IRDA HAL driver can be used as follows:
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 (#) Declare a IRDA_HandleTypeDef handle structure.
<> 144:ef7eb2e8f9f7 26 (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API:
<> 144:ef7eb2e8f9f7 27 (##) Enable the USARTx interface clock.
<> 144:ef7eb2e8f9f7 28 (##) IRDA pins configuration:
<> 144:ef7eb2e8f9f7 29 (+) Enable the clock for the IRDA GPIOs.
<> 144:ef7eb2e8f9f7 30 (+) Configure these IRDA pins as alternate function pull-up.
<> 144:ef7eb2e8f9f7 31 (##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
<> 144:ef7eb2e8f9f7 32 and HAL_IRDA_Receive_IT() APIs):
<> 144:ef7eb2e8f9f7 33 (+) Configure the USARTx interrupt priority.
<> 144:ef7eb2e8f9f7 34 (+) Enable the NVIC USART IRQ handle.
<> 144:ef7eb2e8f9f7 35 (##) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
<> 144:ef7eb2e8f9f7 36 and HAL_IRDA_Receive_DMA() APIs):
<> 144:ef7eb2e8f9f7 37 (+) Declare a DMA handle structure for the Tx/Rx channel.
<> 144:ef7eb2e8f9f7 38 (+) Enable the DMAx interface clock.
<> 144:ef7eb2e8f9f7 39 (+) Configure the declared DMA handle structure with the required Tx/Rx parameters.
<> 144:ef7eb2e8f9f7 40 (+) Configure the DMA Tx/Rx channel.
<> 144:ef7eb2e8f9f7 41 (+) Associate the initilalized DMA handle to the IRDA DMA Tx/Rx handle.
<> 144:ef7eb2e8f9f7 42 (+) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 (#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler
<> 144:ef7eb2e8f9f7 45 and Mode(Receiver/Transmitter) in the hirda Init structure.
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
<> 144:ef7eb2e8f9f7 48 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
<> 144:ef7eb2e8f9f7 49 by calling the customed HAL_IRDA_MspInit() API.
<> 144:ef7eb2e8f9f7 50 -@@- The specific IRDA interrupts (Transmission complete interrupt,
<> 144:ef7eb2e8f9f7 51 RXNE interrupt and Error Interrupts) will be managed using the macros
<> 144:ef7eb2e8f9f7 52 __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 (#) Three operation modes are available within this driver :
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 57 =================================
<> 144:ef7eb2e8f9f7 58 [..]
<> 144:ef7eb2e8f9f7 59 (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
<> 144:ef7eb2e8f9f7 60 (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 63 ===================================
<> 144:ef7eb2e8f9f7 64 [..]
<> 144:ef7eb2e8f9f7 65 (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT()
<> 144:ef7eb2e8f9f7 66 (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 67 add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
<> 144:ef7eb2e8f9f7 68 (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT()
<> 144:ef7eb2e8f9f7 69 (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 70 add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
<> 144:ef7eb2e8f9f7 71 (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 72 add his own code by customization of function pointer HAL_IRDA_ErrorCallback
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 *** DMA mode IO operation ***
<> 144:ef7eb2e8f9f7 75 =============================
<> 144:ef7eb2e8f9f7 76 [..]
<> 144:ef7eb2e8f9f7 77 (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
<> 144:ef7eb2e8f9f7 78 (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 79 add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
<> 144:ef7eb2e8f9f7 80 (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA()
<> 144:ef7eb2e8f9f7 81 (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 82 add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
<> 144:ef7eb2e8f9f7 83 (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 84 add his own code by customization of function pointer HAL_IRDA_ErrorCallback
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 *** IRDA HAL driver macros list ***
<> 144:ef7eb2e8f9f7 87 ===================================
<> 144:ef7eb2e8f9f7 88 [..]
<> 144:ef7eb2e8f9f7 89 Below the list of most used macros in IRDA HAL driver.
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
<> 144:ef7eb2e8f9f7 92 (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
<> 144:ef7eb2e8f9f7 93 (+) __HAL_IRDA_GET_FLAG : Checks whether the specified IRDA flag is set or not
<> 144:ef7eb2e8f9f7 94 (+) __HAL_IRDA_CLEAR_FLAG : Clears the specified IRDA pending flag
<> 144:ef7eb2e8f9f7 95 (+) __HAL_IRDA_ENABLE_IT: Enables the specified IRDA interrupt
<> 144:ef7eb2e8f9f7 96 (+) __HAL_IRDA_DISABLE_IT: Disables the specified IRDA interrupt
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 (@) You can refer to the IRDA HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 @endverbatim
<> 144:ef7eb2e8f9f7 101 ******************************************************************************
<> 144:ef7eb2e8f9f7 102 * @attention
<> 144:ef7eb2e8f9f7 103 *
<> 144:ef7eb2e8f9f7 104 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 105 *
<> 144:ef7eb2e8f9f7 106 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 107 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 108 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 109 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 110 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 111 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 112 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 113 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 114 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 115 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 116 *
<> 144:ef7eb2e8f9f7 117 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 118 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 119 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 120 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 121 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 122 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 123 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 124 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 125 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 126 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 127 *
<> 144:ef7eb2e8f9f7 128 ******************************************************************************
<> 144:ef7eb2e8f9f7 129 */
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 132 #include "stm32l0xx_hal.h"
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /** @addtogroup STM32L0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 135 * @{
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 #ifdef HAL_IRDA_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 /** @addtogroup IRDA
<> 144:ef7eb2e8f9f7 141 * @brief IRDA HAL module driver
<> 144:ef7eb2e8f9f7 142 * @{
<> 144:ef7eb2e8f9f7 143 */
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 /** @addtogroup IRDA_Private
<> 144:ef7eb2e8f9f7 146 * @{
<> 144:ef7eb2e8f9f7 147 */
<> 144:ef7eb2e8f9f7 148 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 149 /* Private define ------------------------------------------------------------*/
<> 151:5eaa88a5bcc7 150 #define TEACK_REACK_TIMEOUT 1000U
<> 151:5eaa88a5bcc7 151 #define HAL_IRDA_TXDMA_TIMEOUTVALUE 22000U
<> 144:ef7eb2e8f9f7 152 #define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
<> 144:ef7eb2e8f9f7 153 | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE))
<> 144:ef7eb2e8f9f7 154 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 155 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 156 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 157 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 158 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 159 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 160 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 161 static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 162 static void IRDA_SetConfig (IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 163 static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 164 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 165 static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 166 static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 167 static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 168 /**
<> 144:ef7eb2e8f9f7 169 * @}
<> 144:ef7eb2e8f9f7 170 */
<> 144:ef7eb2e8f9f7 171 /** @addtogroup IRDA_Exported_Functions
<> 144:ef7eb2e8f9f7 172 * @{
<> 144:ef7eb2e8f9f7 173 */
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /** @addtogroup IRDA_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 176 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 177 *
<> 144:ef7eb2e8f9f7 178 @verbatim
<> 144:ef7eb2e8f9f7 179 ===============================================================================
<> 144:ef7eb2e8f9f7 180 ##### Initialization and Configuration functions #####
<> 144:ef7eb2e8f9f7 181 ===============================================================================
<> 144:ef7eb2e8f9f7 182 [..]
<> 144:ef7eb2e8f9f7 183 This subsection provides a set of functions allowing to initialize the USARTx
<> 144:ef7eb2e8f9f7 184 in asynchronous IRDA mode.
<> 144:ef7eb2e8f9f7 185 (+) For the asynchronous mode only these parameters can be configured:
<> 144:ef7eb2e8f9f7 186 (++) Baud Rate
<> 144:ef7eb2e8f9f7 187 (++) Word Length
<> 144:ef7eb2e8f9f7 188 (++) Parity: If the parity is enabled, then the MSB bit of the data written
<> 144:ef7eb2e8f9f7 189 in the data register is transmitted but is changed by the parity bit.
<> 151:5eaa88a5bcc7 190 (++) Power mode
<> 151:5eaa88a5bcc7 191 (++) Prescaler setting
<> 151:5eaa88a5bcc7 192 (++) Receiver/transmitter modes
<> 151:5eaa88a5bcc7 193
<> 151:5eaa88a5bcc7 194 [..]
<> 151:5eaa88a5bcc7 195 The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
<> 151:5eaa88a5bcc7 196 (details for the procedures are available in reference manual).
<> 151:5eaa88a5bcc7 197
<> 151:5eaa88a5bcc7 198 @endverbatim
<> 151:5eaa88a5bcc7 199
<> 151:5eaa88a5bcc7 200 Depending on the frame length defined by the M bit (8-bits or 9-bits)
<> 151:5eaa88a5bcc7 201 or by the M1 and M0 bits (7-bit, 8-bit or 9-bit),
<> 151:5eaa88a5bcc7 202 the possible IRDA frame formats are as listed in the following table:
<> 151:5eaa88a5bcc7 203
<> 151:5eaa88a5bcc7 204 Table 1. IRDA frame format.
<> 144:ef7eb2e8f9f7 205 +---------------------------------------------------------------+
<> 144:ef7eb2e8f9f7 206 | M1M0 bits | PCE bit | IRDA frame |
<> 144:ef7eb2e8f9f7 207 |-----------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 208 | 00 | 0 | | SB | 8-bit data | STB | |
<> 144:ef7eb2e8f9f7 209 |-----------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 210 | 00 | 1 | | SB | 7-bit data | PB | STB | |
<> 144:ef7eb2e8f9f7 211 |-----------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 212 | 01 | 0 | | SB | 9-bit data | STB | |
<> 144:ef7eb2e8f9f7 213 |-----------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 214 | 01 | 1 | | SB | 8-bit data | PB | STB | |
<> 144:ef7eb2e8f9f7 215 |-----------------------|---------------------------------------|
<> 144:ef7eb2e8f9f7 216 | 10 | 0 | | SB | 7-bit data | STB | |
<> 144:ef7eb2e8f9f7 217 |-----------|-----------|---------------------------------------|
<> 144:ef7eb2e8f9f7 218 | 10 | 1 | | SB | 6-bit data | PB | STB | |
<> 144:ef7eb2e8f9f7 219 +---------------------------------------------------------------+
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 * @{
<> 144:ef7eb2e8f9f7 222 */
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /**
<> 144:ef7eb2e8f9f7 225 * @brief Initializes the IRDA mode according to the specified
<> 144:ef7eb2e8f9f7 226 * parameters in the IRDA_InitTypeDef and creates the associated handle .
<> 144:ef7eb2e8f9f7 227 * @param hirda: IRDA handle
<> 144:ef7eb2e8f9f7 228 * @retval HAL status
<> 144:ef7eb2e8f9f7 229 */
<> 144:ef7eb2e8f9f7 230 HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 231 {
<> 144:ef7eb2e8f9f7 232 /* Check the IRDA handle allocation */
<> 144:ef7eb2e8f9f7 233 if(hirda == NULL)
<> 144:ef7eb2e8f9f7 234 {
<> 144:ef7eb2e8f9f7 235 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 236 }
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /* Check the USART/UART associated to the IRDA handle */
<> 144:ef7eb2e8f9f7 239 assert_param(IS_IRDA_INSTANCE(hirda->Instance));
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 if(hirda->State == HAL_IRDA_STATE_RESET)
<> 144:ef7eb2e8f9f7 242 {
<> 144:ef7eb2e8f9f7 243 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 244 hirda->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /* Init the low level hardware : GPIO, CLOCK, CORTEX */
<> 144:ef7eb2e8f9f7 247 HAL_IRDA_MspInit(hirda);
<> 144:ef7eb2e8f9f7 248 }
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 hirda->State = HAL_IRDA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /* Disable the Peripheral to update the configuration registers */
<> 144:ef7eb2e8f9f7 253 __HAL_IRDA_DISABLE(hirda);
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /* Set the IRDA Communication parameters */
<> 144:ef7eb2e8f9f7 256 IRDA_SetConfig(hirda);
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /* In IRDA mode, the following bits must be kept cleared:
<> 144:ef7eb2e8f9f7 259 - LINEN, STOP and CLKEN bits in the USART_CR2 register,
<> 144:ef7eb2e8f9f7 260 - SCEN and HDSEL bits in the USART_CR3 register.*/
<> 144:ef7eb2e8f9f7 261 hirda->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP);
<> 144:ef7eb2e8f9f7 262 hirda->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL);
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 /* set the UART/USART in IRDA mode */
<> 144:ef7eb2e8f9f7 265 hirda->Instance->CR3 |= USART_CR3_IREN;
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 268 __HAL_IRDA_ENABLE(hirda);
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /* TEACK and/or REACK to check before moving hirda->State to Ready */
<> 144:ef7eb2e8f9f7 271 return (IRDA_CheckIdleState(hirda));
<> 144:ef7eb2e8f9f7 272 }
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /**
<> 144:ef7eb2e8f9f7 275 * @brief DeInitializes the IRDA peripheral
<> 144:ef7eb2e8f9f7 276 * @param hirda: IRDA handle
<> 144:ef7eb2e8f9f7 277 * @retval HAL status
<> 144:ef7eb2e8f9f7 278 */
<> 144:ef7eb2e8f9f7 279 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 280 {
<> 144:ef7eb2e8f9f7 281 /* Check the IRDA handle allocation */
<> 144:ef7eb2e8f9f7 282 if(hirda == NULL)
<> 144:ef7eb2e8f9f7 283 {
<> 144:ef7eb2e8f9f7 284 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 285 }
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 /* Check the USART/UART associated to the IRDA handle */
<> 144:ef7eb2e8f9f7 288 assert_param(IS_IRDA_INSTANCE(hirda->Instance));
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 hirda->State = HAL_IRDA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /* DeInit the low level hardware */
<> 144:ef7eb2e8f9f7 293 HAL_IRDA_MspDeInit(hirda);
<> 144:ef7eb2e8f9f7 294 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 295 __HAL_IRDA_DISABLE(hirda);
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 298 hirda->State = HAL_IRDA_STATE_RESET;
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /* Release Lock */
<> 144:ef7eb2e8f9f7 301 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 return HAL_OK;
<> 144:ef7eb2e8f9f7 304 }
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /**
<> 144:ef7eb2e8f9f7 307 * @brief IRDA MSP Init
<> 144:ef7eb2e8f9f7 308 * @param hirda: IRDA handle
<> 144:ef7eb2e8f9f7 309 * @retval None
<> 144:ef7eb2e8f9f7 310 */
<> 144:ef7eb2e8f9f7 311 __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 312 {
<> 144:ef7eb2e8f9f7 313 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 314 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 317 the HAL_IRDA_MspInit could be implented in the user file
<> 144:ef7eb2e8f9f7 318 */
<> 144:ef7eb2e8f9f7 319 }
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 /**
<> 144:ef7eb2e8f9f7 322 * @brief IRDA MSP DeInit
<> 144:ef7eb2e8f9f7 323 * @param hirda: IRDA handle
<> 144:ef7eb2e8f9f7 324 * @retval None
<> 144:ef7eb2e8f9f7 325 */
<> 144:ef7eb2e8f9f7 326 __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 327 {
<> 144:ef7eb2e8f9f7 328 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 329 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 332 the HAL_IRDA_MspDeInit could be implented in the user file
<> 144:ef7eb2e8f9f7 333 */
<> 144:ef7eb2e8f9f7 334 }
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /**
<> 144:ef7eb2e8f9f7 337 * @}
<> 144:ef7eb2e8f9f7 338 */
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 /** @addtogroup IRDA_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 341 * @brief IRDA Transmit-Receive functions
<> 144:ef7eb2e8f9f7 342 *
<> 144:ef7eb2e8f9f7 343 @verbatim
<> 144:ef7eb2e8f9f7 344 ===============================================================================
<> 144:ef7eb2e8f9f7 345 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 346 ===============================================================================
<> 144:ef7eb2e8f9f7 347 [..]
<> 144:ef7eb2e8f9f7 348 This subsection provides a set of functions allowing to manage the IRDA asynchronous
<> 144:ef7eb2e8f9f7 349 data transfers.
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 (#) There are two modes of transfer:
<> 144:ef7eb2e8f9f7 352 (++) Blocking mode: the communication is performed in polling mode.
<> 144:ef7eb2e8f9f7 353 The HAL status of all data processing is returned by the same function
<> 144:ef7eb2e8f9f7 354 after finishing transfer.
<> 144:ef7eb2e8f9f7 355 (++) No-Blocking mode: the communication is performed using Interrupts
<> 144:ef7eb2e8f9f7 356 or DMA, these API's return the HAL status.
<> 144:ef7eb2e8f9f7 357 The end of the data processing will be indicated through the
<> 144:ef7eb2e8f9f7 358 dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
<> 144:ef7eb2e8f9f7 359 using DMA mode.
<> 144:ef7eb2e8f9f7 360 The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
<> 144:ef7eb2e8f9f7 361 will be executed respectivelly at the end of the Transmit or Receive process
<> 144:ef7eb2e8f9f7 362 The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 (#) Blocking mode API's are :
<> 144:ef7eb2e8f9f7 365 (++) HAL_IRDA_Transmit()
<> 144:ef7eb2e8f9f7 366 (++) HAL_IRDA_Receive()
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 (#) Non-Blocking mode API's with Interrupt are :
<> 144:ef7eb2e8f9f7 369 (++) HAL_IRDA_Transmit_IT()
<> 144:ef7eb2e8f9f7 370 (++) HAL_IRDA_Receive_IT()
<> 144:ef7eb2e8f9f7 371 (++) HAL_IRDA_IRQHandler()
<> 144:ef7eb2e8f9f7 372 (++) IRDA_Transmit_IT()
<> 144:ef7eb2e8f9f7 373 (++) IRDA_Receive_IT()
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 (#) Non-Blocking mode functions with DMA are :
<> 144:ef7eb2e8f9f7 376 (++) HAL_IRDA_Transmit_DMA()
<> 144:ef7eb2e8f9f7 377 (++) HAL_IRDA_Receive_DMA()
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
<> 144:ef7eb2e8f9f7 380 (++) HAL_IRDA_TxCpltCallback()
<> 144:ef7eb2e8f9f7 381 (++) HAL_IRDA_RxCpltCallback()
<> 144:ef7eb2e8f9f7 382 (++) HAL_IRDA_ErrorCallback()
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 @endverbatim
<> 144:ef7eb2e8f9f7 385 * @{
<> 144:ef7eb2e8f9f7 386 */
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /**
<> 144:ef7eb2e8f9f7 389 * @brief Send an amount of data in blocking mode
<> 144:ef7eb2e8f9f7 390 * @param hirda: IRDA handle
<> 144:ef7eb2e8f9f7 391 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 392 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 393 * @param Timeout: Duration of the timeout
<> 144:ef7eb2e8f9f7 394 * @retval HAL status
<> 144:ef7eb2e8f9f7 395 */
<> 144:ef7eb2e8f9f7 396 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 397 {
<> 144:ef7eb2e8f9f7 398 uint16_t* tmp;
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX))
<> 144:ef7eb2e8f9f7 401 {
<> 151:5eaa88a5bcc7 402 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 403 {
<> 144:ef7eb2e8f9f7 404 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 405 }
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 /* Process Locked */
<> 144:ef7eb2e8f9f7 408 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 409 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 412 {
<> 144:ef7eb2e8f9f7 413 hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 414 }
<> 144:ef7eb2e8f9f7 415 else
<> 144:ef7eb2e8f9f7 416 {
<> 144:ef7eb2e8f9f7 417 hirda->State = HAL_IRDA_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 418 }
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 hirda->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 421 hirda->TxXferCount = Size;
<> 151:5eaa88a5bcc7 422 while(hirda->TxXferCount > 0U)
<> 144:ef7eb2e8f9f7 423 {
<> 144:ef7eb2e8f9f7 424 hirda->TxXferCount--;
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 427 {
<> 144:ef7eb2e8f9f7 428 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 429 }
<> 144:ef7eb2e8f9f7 430 if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
<> 144:ef7eb2e8f9f7 431 {
<> 144:ef7eb2e8f9f7 432 tmp = (uint16_t*) pData;
<> 151:5eaa88a5bcc7 433 hirda->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
<> 144:ef7eb2e8f9f7 434 pData +=2;
<> 144:ef7eb2e8f9f7 435 }
<> 144:ef7eb2e8f9f7 436 else
<> 144:ef7eb2e8f9f7 437 {
<> 151:5eaa88a5bcc7 438 hirda->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
<> 144:ef7eb2e8f9f7 439 }
<> 144:ef7eb2e8f9f7 440 }
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 443 {
<> 144:ef7eb2e8f9f7 444 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 445 }
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 448 {
<> 144:ef7eb2e8f9f7 449 hirda->State = HAL_IRDA_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 450 }
<> 144:ef7eb2e8f9f7 451 else
<> 144:ef7eb2e8f9f7 452 {
<> 144:ef7eb2e8f9f7 453 hirda->State = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 454 }
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 457 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 return HAL_OK;
<> 144:ef7eb2e8f9f7 460 }
<> 144:ef7eb2e8f9f7 461 else
<> 144:ef7eb2e8f9f7 462 {
<> 144:ef7eb2e8f9f7 463 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 464 }
<> 144:ef7eb2e8f9f7 465 }
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 /**
<> 144:ef7eb2e8f9f7 468 * @brief Receive an amount of data in blocking mode
<> 144:ef7eb2e8f9f7 469 * @param hirda: IRDA handle
<> 144:ef7eb2e8f9f7 470 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 471 * @param Size: amount of data to be received
<> 144:ef7eb2e8f9f7 472 * @param Timeout: Duration of the timeout
<> 144:ef7eb2e8f9f7 473 * @retval HAL status
<> 144:ef7eb2e8f9f7 474 */
<> 144:ef7eb2e8f9f7 475 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 476 {
<> 144:ef7eb2e8f9f7 477 uint16_t* tmp;
<> 144:ef7eb2e8f9f7 478 uint16_t uhMask;
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX))
<> 144:ef7eb2e8f9f7 481 {
<> 151:5eaa88a5bcc7 482 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 483 {
<> 144:ef7eb2e8f9f7 484 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 485 }
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 /* Process Locked */
<> 144:ef7eb2e8f9f7 488 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 489 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 492 {
<> 144:ef7eb2e8f9f7 493 hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 494 }
<> 144:ef7eb2e8f9f7 495 else
<> 144:ef7eb2e8f9f7 496 {
<> 144:ef7eb2e8f9f7 497 hirda->State = HAL_IRDA_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 498 }
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 hirda->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 501 hirda->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /* Computation of the mask to apply to the RDR register
<> 144:ef7eb2e8f9f7 504 of the UART associated to the IRDA */
<> 144:ef7eb2e8f9f7 505 IRDA_MASK_COMPUTATION(hirda);
<> 144:ef7eb2e8f9f7 506 uhMask = hirda->Mask;
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /* Check data remaining to be received */
<> 151:5eaa88a5bcc7 509 while(hirda->RxXferCount > 0U)
<> 144:ef7eb2e8f9f7 510 {
<> 144:ef7eb2e8f9f7 511 hirda->RxXferCount--;
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 514 {
<> 144:ef7eb2e8f9f7 515 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 516 }
<> 144:ef7eb2e8f9f7 517 if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
<> 144:ef7eb2e8f9f7 518 {
<> 144:ef7eb2e8f9f7 519 tmp = (uint16_t*) pData ;
<> 144:ef7eb2e8f9f7 520 *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
<> 151:5eaa88a5bcc7 521 pData +=2U;
<> 144:ef7eb2e8f9f7 522 }
<> 144:ef7eb2e8f9f7 523 else
<> 144:ef7eb2e8f9f7 524 {
<> 144:ef7eb2e8f9f7 525 *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
<> 144:ef7eb2e8f9f7 526 }
<> 144:ef7eb2e8f9f7 527 }
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 530 {
<> 144:ef7eb2e8f9f7 531 hirda->State = HAL_IRDA_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 532 }
<> 144:ef7eb2e8f9f7 533 else
<> 144:ef7eb2e8f9f7 534 {
<> 144:ef7eb2e8f9f7 535 hirda->State = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 536 }
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 539 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 return HAL_OK;
<> 144:ef7eb2e8f9f7 542 }
<> 144:ef7eb2e8f9f7 543 else
<> 144:ef7eb2e8f9f7 544 {
<> 144:ef7eb2e8f9f7 545 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 546 }
<> 144:ef7eb2e8f9f7 547 }
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 /**
<> 144:ef7eb2e8f9f7 550 * @brief Send an amount of data in interrupt mode
<> 144:ef7eb2e8f9f7 551 * @param hirda: IRDA handle
<> 144:ef7eb2e8f9f7 552 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 553 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 554 * @retval HAL status
<> 144:ef7eb2e8f9f7 555 */
<> 144:ef7eb2e8f9f7 556 HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 557 {
<> 144:ef7eb2e8f9f7 558 if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX))
<> 144:ef7eb2e8f9f7 559 {
<> 151:5eaa88a5bcc7 560 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 561 {
<> 144:ef7eb2e8f9f7 562 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 563 }
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 /* Process Locked */
<> 144:ef7eb2e8f9f7 566 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 hirda->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 569 hirda->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 570 hirda->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 573 if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 574 {
<> 144:ef7eb2e8f9f7 575 hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 576 }
<> 144:ef7eb2e8f9f7 577 else
<> 144:ef7eb2e8f9f7 578 {
<> 144:ef7eb2e8f9f7 579 hirda->State = HAL_IRDA_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 580 }
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 583 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 /* Enable the IRDA Transmit Data Register Empty Interrupt */
<> 144:ef7eb2e8f9f7 586 __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TXE);
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 return HAL_OK;
<> 144:ef7eb2e8f9f7 589 }
<> 144:ef7eb2e8f9f7 590 else
<> 144:ef7eb2e8f9f7 591 {
<> 144:ef7eb2e8f9f7 592 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 593 }
<> 144:ef7eb2e8f9f7 594 }
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 /**
<> 144:ef7eb2e8f9f7 597 * @brief Receive an amount of data in interrupt mode
<> 144:ef7eb2e8f9f7 598 * @param hirda: IRDA handle
<> 144:ef7eb2e8f9f7 599 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 600 * @param Size: amount of data to be received
<> 144:ef7eb2e8f9f7 601 * @retval HAL status
<> 144:ef7eb2e8f9f7 602 */
<> 144:ef7eb2e8f9f7 603 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 604 {
<> 144:ef7eb2e8f9f7 605 if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX))
<> 144:ef7eb2e8f9f7 606 {
<> 151:5eaa88a5bcc7 607 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 608 {
<> 144:ef7eb2e8f9f7 609 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 610 }
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 /* Process Locked */
<> 144:ef7eb2e8f9f7 613 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 hirda->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 616 hirda->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 617 hirda->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 /* Computation of the mask to apply to the RDR register
<> 144:ef7eb2e8f9f7 620 of the UART associated to the IRDA */
<> 144:ef7eb2e8f9f7 621 IRDA_MASK_COMPUTATION(hirda);
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 624 if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 625 {
<> 144:ef7eb2e8f9f7 626 hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 627 }
<> 144:ef7eb2e8f9f7 628 else
<> 144:ef7eb2e8f9f7 629 {
<> 144:ef7eb2e8f9f7 630 hirda->State = HAL_IRDA_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 631 }
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 /* Enable the IRDA Parity Error Interrupt */
<> 144:ef7eb2e8f9f7 634 __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE);
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636 /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
<> 144:ef7eb2e8f9f7 637 __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 640 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642 /* Enable the IRDA Data Register not empty Interrupt */
<> 144:ef7eb2e8f9f7 643 __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE);
<> 144:ef7eb2e8f9f7 644
<> 144:ef7eb2e8f9f7 645 return HAL_OK;
<> 144:ef7eb2e8f9f7 646 }
<> 144:ef7eb2e8f9f7 647 else
<> 144:ef7eb2e8f9f7 648 {
<> 144:ef7eb2e8f9f7 649 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 650 }
<> 144:ef7eb2e8f9f7 651 }
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 /**
<> 144:ef7eb2e8f9f7 654 * @brief Send an amount of data in DMA mode
<> 144:ef7eb2e8f9f7 655 * @param hirda: IRDA handle
<> 144:ef7eb2e8f9f7 656 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 657 * @param Size: amount of data to be sent
<> 144:ef7eb2e8f9f7 658 * @retval HAL status
<> 144:ef7eb2e8f9f7 659 */
<> 144:ef7eb2e8f9f7 660 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 661 {
<> 144:ef7eb2e8f9f7 662 uint32_t *tmp;
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX))
<> 144:ef7eb2e8f9f7 665 {
<> 151:5eaa88a5bcc7 666 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 667 {
<> 144:ef7eb2e8f9f7 668 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 669 }
<> 144:ef7eb2e8f9f7 670
<> 144:ef7eb2e8f9f7 671 /* Process Locked */
<> 144:ef7eb2e8f9f7 672 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 hirda->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 675 hirda->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 676 hirda->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 681 {
<> 144:ef7eb2e8f9f7 682 hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 683 }
<> 144:ef7eb2e8f9f7 684 else
<> 144:ef7eb2e8f9f7 685 {
<> 144:ef7eb2e8f9f7 686 hirda->State = HAL_IRDA_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 687 }
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689 /* Set the IRDA DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 690 hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
<> 144:ef7eb2e8f9f7 691
<> 144:ef7eb2e8f9f7 692 /* Set the IRDA DMA half transfer complete callback */
<> 144:ef7eb2e8f9f7 693 hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 696 hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 /* Enable the IRDA transmit DMA channel */
<> 144:ef7eb2e8f9f7 699 tmp = (uint32_t*)&pData;
<> 144:ef7eb2e8f9f7 700 HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->TDR, Size);
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702 /* Clear the TC flag in the SR register by writing 0 to it */
<> 144:ef7eb2e8f9f7 703 __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_TC);
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 /* Enable the DMA transfer for transmit request by setting the DMAT bit
<> 144:ef7eb2e8f9f7 706 in the IRDA CR3 register */
<> 144:ef7eb2e8f9f7 707 hirda->Instance->CR3 |= USART_CR3_DMAT;
<> 144:ef7eb2e8f9f7 708
<> 144:ef7eb2e8f9f7 709 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 710 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 711
<> 144:ef7eb2e8f9f7 712 return HAL_OK;
<> 144:ef7eb2e8f9f7 713 }
<> 144:ef7eb2e8f9f7 714 else
<> 144:ef7eb2e8f9f7 715 {
<> 144:ef7eb2e8f9f7 716 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 717 }
<> 144:ef7eb2e8f9f7 718 }
<> 144:ef7eb2e8f9f7 719
<> 144:ef7eb2e8f9f7 720 /**
<> 144:ef7eb2e8f9f7 721 * @brief Receive an amount of data in DMA mode
<> 144:ef7eb2e8f9f7 722 * @param hirda: IRDA handle
<> 144:ef7eb2e8f9f7 723 * @param pData: pointer to data buffer
<> 144:ef7eb2e8f9f7 724 * @param Size: amount of data to be received
<> 144:ef7eb2e8f9f7 725 * @note When the IRDA parity is enabled (PCE = 1), the received data contain
<> 144:ef7eb2e8f9f7 726 * the parity bit (MSB position)
<> 144:ef7eb2e8f9f7 727 * @retval HAL status
<> 144:ef7eb2e8f9f7 728 */
<> 144:ef7eb2e8f9f7 729 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 730 {
<> 144:ef7eb2e8f9f7 731 uint32_t *tmp;
<> 144:ef7eb2e8f9f7 732
<> 144:ef7eb2e8f9f7 733 if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX))
<> 144:ef7eb2e8f9f7 734 {
<> 151:5eaa88a5bcc7 735 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 736 {
<> 144:ef7eb2e8f9f7 737 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 738 }
<> 144:ef7eb2e8f9f7 739
<> 144:ef7eb2e8f9f7 740 /* Process Locked */
<> 144:ef7eb2e8f9f7 741 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 742
<> 144:ef7eb2e8f9f7 743 hirda->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 744 hirda->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 745
<> 144:ef7eb2e8f9f7 746 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 747 if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 748 {
<> 144:ef7eb2e8f9f7 749 hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 750 }
<> 144:ef7eb2e8f9f7 751 else
<> 144:ef7eb2e8f9f7 752 {
<> 144:ef7eb2e8f9f7 753 hirda->State = HAL_IRDA_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 754 }
<> 144:ef7eb2e8f9f7 755
<> 144:ef7eb2e8f9f7 756 /* Set the IRDA DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 757 hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
<> 144:ef7eb2e8f9f7 758
<> 144:ef7eb2e8f9f7 759 /* Set the IRDA DMA half transfer complete callback */
<> 144:ef7eb2e8f9f7 760 hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 763 hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 766 tmp = (uint32_t*)&pData;
<> 144:ef7eb2e8f9f7 767 HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, *(uint32_t*)tmp, Size);
<> 144:ef7eb2e8f9f7 768
<> 144:ef7eb2e8f9f7 769 /* Enable the DMA transfer for the receiver request by setting the DMAR bit
<> 144:ef7eb2e8f9f7 770 in the IRDA CR3 register */
<> 144:ef7eb2e8f9f7 771 hirda->Instance->CR3 |= USART_CR3_DMAR;
<> 144:ef7eb2e8f9f7 772
<> 144:ef7eb2e8f9f7 773 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 774 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 775
<> 144:ef7eb2e8f9f7 776 return HAL_OK;
<> 144:ef7eb2e8f9f7 777 }
<> 144:ef7eb2e8f9f7 778 else
<> 144:ef7eb2e8f9f7 779 {
<> 144:ef7eb2e8f9f7 780 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 781 }
<> 144:ef7eb2e8f9f7 782 }
<> 144:ef7eb2e8f9f7 783
<> 144:ef7eb2e8f9f7 784 /**
<> 144:ef7eb2e8f9f7 785 * @brief Pauses the DMA Transfer.
<> 144:ef7eb2e8f9f7 786 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 787 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 788 * @retval HAL status
<> 144:ef7eb2e8f9f7 789 */
<> 144:ef7eb2e8f9f7 790 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 791 {
<> 144:ef7eb2e8f9f7 792 /* Process Locked */
<> 144:ef7eb2e8f9f7 793 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 794
<> 144:ef7eb2e8f9f7 795 if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 796 {
<> 144:ef7eb2e8f9f7 797 /* Disable the UART DMA Tx request */
<> 144:ef7eb2e8f9f7 798 hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 799 }
<> 144:ef7eb2e8f9f7 800 else if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 801 {
<> 144:ef7eb2e8f9f7 802 /* Disable the UART DMA Rx request */
<> 144:ef7eb2e8f9f7 803 hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 804 }
<> 144:ef7eb2e8f9f7 805 else if (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 806 {
<> 144:ef7eb2e8f9f7 807 /* Disable the UART DMA Tx & Rx requests */
<> 144:ef7eb2e8f9f7 808 hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 809 hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 810 }
<> 144:ef7eb2e8f9f7 811
<> 144:ef7eb2e8f9f7 812 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 813 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 814
<> 144:ef7eb2e8f9f7 815 return HAL_OK;
<> 144:ef7eb2e8f9f7 816 }
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 /**
<> 144:ef7eb2e8f9f7 819 * @brief Resumes the DMA Transfer.
<> 144:ef7eb2e8f9f7 820 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 821 * the configuration information for the specified UART module.
<> 144:ef7eb2e8f9f7 822 * @retval HAL status
<> 144:ef7eb2e8f9f7 823 */
<> 144:ef7eb2e8f9f7 824 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 825 {
<> 144:ef7eb2e8f9f7 826 /* Process Locked */
<> 144:ef7eb2e8f9f7 827 __HAL_LOCK(hirda);
<> 144:ef7eb2e8f9f7 828
<> 144:ef7eb2e8f9f7 829 if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 830 {
<> 144:ef7eb2e8f9f7 831 /* Enable the UART DMA Tx request */
<> 144:ef7eb2e8f9f7 832 hirda->Instance->CR3 |= USART_CR3_DMAT;
<> 144:ef7eb2e8f9f7 833 }
<> 144:ef7eb2e8f9f7 834 else if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 835 {
<> 144:ef7eb2e8f9f7 836 /* Clear the Overrun flag before resumming the Rx transfer*/
<> 144:ef7eb2e8f9f7 837 __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 /* Enable the UART DMA Rx request */
<> 144:ef7eb2e8f9f7 840 hirda->Instance->CR3 |= USART_CR3_DMAR;
<> 144:ef7eb2e8f9f7 841 }
<> 144:ef7eb2e8f9f7 842 else if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 843 {
<> 144:ef7eb2e8f9f7 844 /* Clear the Overrun flag before resumming the Rx transfer*/
<> 144:ef7eb2e8f9f7 845 __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
<> 144:ef7eb2e8f9f7 846
<> 144:ef7eb2e8f9f7 847 /* Enable the UART DMA Tx & Rx request */
<> 144:ef7eb2e8f9f7 848 hirda->Instance->CR3 |= USART_CR3_DMAT;
<> 144:ef7eb2e8f9f7 849 hirda->Instance->CR3 |= USART_CR3_DMAR;
<> 144:ef7eb2e8f9f7 850 }
<> 144:ef7eb2e8f9f7 851
<> 144:ef7eb2e8f9f7 852 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 853 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 854
<> 144:ef7eb2e8f9f7 855 return HAL_OK;
<> 144:ef7eb2e8f9f7 856 }
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858 /**
<> 144:ef7eb2e8f9f7 859 * @brief Stops the DMA Transfer.
<> 144:ef7eb2e8f9f7 860 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 861 * the configuration information for the specified UART module.
<> 144:ef7eb2e8f9f7 862 * @retval HAL status
<> 144:ef7eb2e8f9f7 863 */
<> 144:ef7eb2e8f9f7 864 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 865 {
<> 144:ef7eb2e8f9f7 866 /* The Lock is not implemented on this API to allow the user application
<> 144:ef7eb2e8f9f7 867 to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback():
<> 144:ef7eb2e8f9f7 868 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
<> 144:ef7eb2e8f9f7 869 and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback()
<> 144:ef7eb2e8f9f7 870 */
<> 144:ef7eb2e8f9f7 871
<> 144:ef7eb2e8f9f7 872 /* Disable the UART Tx/Rx DMA requests */
<> 144:ef7eb2e8f9f7 873 hirda->Instance->CR3 &= ~USART_CR3_DMAT;
<> 144:ef7eb2e8f9f7 874 hirda->Instance->CR3 &= ~USART_CR3_DMAR;
<> 144:ef7eb2e8f9f7 875
<> 144:ef7eb2e8f9f7 876 /* Abort the UART DMA tx channel */
<> 144:ef7eb2e8f9f7 877 if(hirda->hdmatx != NULL)
<> 144:ef7eb2e8f9f7 878 {
<> 144:ef7eb2e8f9f7 879 HAL_DMA_Abort(hirda->hdmatx);
<> 144:ef7eb2e8f9f7 880 }
<> 144:ef7eb2e8f9f7 881 /* Abort the UART DMA rx channel */
<> 144:ef7eb2e8f9f7 882 if(hirda->hdmarx != NULL)
<> 144:ef7eb2e8f9f7 883 {
<> 144:ef7eb2e8f9f7 884 HAL_DMA_Abort(hirda->hdmarx);
<> 144:ef7eb2e8f9f7 885 }
<> 144:ef7eb2e8f9f7 886
<> 144:ef7eb2e8f9f7 887 hirda->State = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 888
<> 144:ef7eb2e8f9f7 889 return HAL_OK;
<> 144:ef7eb2e8f9f7 890 }
<> 144:ef7eb2e8f9f7 891
<> 144:ef7eb2e8f9f7 892 /**
<> 144:ef7eb2e8f9f7 893 * @brief This function handles IRDA interrupt request.
<> 144:ef7eb2e8f9f7 894 * @param hirda: IRDA handle
<> 144:ef7eb2e8f9f7 895 * @retval None
<> 144:ef7eb2e8f9f7 896 */
<> 144:ef7eb2e8f9f7 897 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 898 {
<> 144:ef7eb2e8f9f7 899 /* IRDA parity error interrupt occurred -------------------------------------*/
<> 144:ef7eb2e8f9f7 900 if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_PE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE) != RESET))
<> 144:ef7eb2e8f9f7 901 {
<> 144:ef7eb2e8f9f7 902 __HAL_IRDA_CLEAR_PEFLAG(hirda);
<> 144:ef7eb2e8f9f7 903
<> 144:ef7eb2e8f9f7 904 hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
<> 144:ef7eb2e8f9f7 905 /* Set the IRDA state ready to be able to start again the process */
<> 144:ef7eb2e8f9f7 906 hirda->State = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 907 }
<> 144:ef7eb2e8f9f7 908
<> 144:ef7eb2e8f9f7 909 /* IRDA frame error interrupt occured --------------------------------------*/
<> 144:ef7eb2e8f9f7 910 if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_FE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET))
<> 144:ef7eb2e8f9f7 911 {
<> 144:ef7eb2e8f9f7 912 __HAL_IRDA_CLEAR_FEFLAG(hirda);
<> 144:ef7eb2e8f9f7 913
<> 144:ef7eb2e8f9f7 914 hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
<> 144:ef7eb2e8f9f7 915 /* Set the IRDA state ready to be able to start again the process */
<> 144:ef7eb2e8f9f7 916 hirda->State = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 917 }
<> 144:ef7eb2e8f9f7 918
<> 144:ef7eb2e8f9f7 919 /* IRDA noise error interrupt occured --------------------------------------*/
<> 144:ef7eb2e8f9f7 920 if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_NE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET))
<> 144:ef7eb2e8f9f7 921 {
<> 144:ef7eb2e8f9f7 922 __HAL_IRDA_CLEAR_NEFLAG(hirda);
<> 144:ef7eb2e8f9f7 923
<> 144:ef7eb2e8f9f7 924 hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
<> 144:ef7eb2e8f9f7 925 /* Set the IRDA state ready to be able to start again the process */
<> 144:ef7eb2e8f9f7 926 hirda->State = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 927 }
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 /* IRDA Over-Run interrupt occured -----------------------------------------*/
<> 144:ef7eb2e8f9f7 930 if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_ORE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET))
<> 144:ef7eb2e8f9f7 931 {
<> 144:ef7eb2e8f9f7 932 __HAL_IRDA_CLEAR_OREFLAG(hirda);
<> 144:ef7eb2e8f9f7 933
<> 144:ef7eb2e8f9f7 934 hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
<> 144:ef7eb2e8f9f7 935 /* Set the IRDA state ready to be able to start again the process */
<> 144:ef7eb2e8f9f7 936 hirda->State = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 937 }
<> 144:ef7eb2e8f9f7 938
<> 144:ef7eb2e8f9f7 939 /* Call IRDA Error Call back function if need be --------------------------*/
<> 144:ef7eb2e8f9f7 940 if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
<> 144:ef7eb2e8f9f7 941 {
<> 144:ef7eb2e8f9f7 942 HAL_IRDA_ErrorCallback(hirda);
<> 144:ef7eb2e8f9f7 943 }
<> 144:ef7eb2e8f9f7 944
<> 144:ef7eb2e8f9f7 945 /* IRDA in mode Receiver ---------------------------------------------------*/
<> 144:ef7eb2e8f9f7 946 if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_RXNE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_RXNE) != RESET))
<> 144:ef7eb2e8f9f7 947 {
<> 144:ef7eb2e8f9f7 948 IRDA_Receive_IT(hirda);
<> 144:ef7eb2e8f9f7 949 /* Clear RXNE interrupt flag */
<> 144:ef7eb2e8f9f7 950 __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
<> 144:ef7eb2e8f9f7 951 }
<> 144:ef7eb2e8f9f7 952
<> 144:ef7eb2e8f9f7 953 /* IRDA in mode Transmitter ------------------------------------------------*/
<> 144:ef7eb2e8f9f7 954 if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TXE) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TXE) != RESET))
<> 144:ef7eb2e8f9f7 955 {
<> 144:ef7eb2e8f9f7 956 IRDA_Transmit_IT(hirda);
<> 144:ef7eb2e8f9f7 957 }
<> 144:ef7eb2e8f9f7 958
<> 144:ef7eb2e8f9f7 959 /* IRDA in mode Transmitter (transmission end) -----------------------------*/
<> 144:ef7eb2e8f9f7 960 if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TC) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC) != RESET))
<> 144:ef7eb2e8f9f7 961 {
<> 144:ef7eb2e8f9f7 962 IRDA_EndTransmit_IT(hirda);
<> 144:ef7eb2e8f9f7 963 }
<> 144:ef7eb2e8f9f7 964
<> 144:ef7eb2e8f9f7 965 }
<> 144:ef7eb2e8f9f7 966
<> 144:ef7eb2e8f9f7 967 /**
<> 144:ef7eb2e8f9f7 968 * @brief Tx Half Transfer completed callback
<> 144:ef7eb2e8f9f7 969 * @param hirda: irda handle
<> 144:ef7eb2e8f9f7 970 * @retval None
<> 144:ef7eb2e8f9f7 971 */
<> 144:ef7eb2e8f9f7 972 __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 973 {
<> 144:ef7eb2e8f9f7 974 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 975 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 976
<> 144:ef7eb2e8f9f7 977 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 978 the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file
<> 144:ef7eb2e8f9f7 979 */
<> 144:ef7eb2e8f9f7 980 }
<> 144:ef7eb2e8f9f7 981
<> 144:ef7eb2e8f9f7 982 /**
<> 144:ef7eb2e8f9f7 983 * @brief Tx Transfer completed callback
<> 144:ef7eb2e8f9f7 984 * @param hirda: irda handle
<> 144:ef7eb2e8f9f7 985 * @retval None
<> 144:ef7eb2e8f9f7 986 */
<> 144:ef7eb2e8f9f7 987 __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 988 {
<> 144:ef7eb2e8f9f7 989 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 990 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 991
<> 144:ef7eb2e8f9f7 992 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 993 the HAL_IRDA_TxCpltCallback can be implemented in the user file
<> 144:ef7eb2e8f9f7 994 */
<> 144:ef7eb2e8f9f7 995 }
<> 144:ef7eb2e8f9f7 996
<> 144:ef7eb2e8f9f7 997 /**
<> 144:ef7eb2e8f9f7 998 * @brief Rx Half Transfer completed callback
<> 144:ef7eb2e8f9f7 999 * @param hirda: irda handle
<> 144:ef7eb2e8f9f7 1000 * @retval None
<> 144:ef7eb2e8f9f7 1001 */
<> 144:ef7eb2e8f9f7 1002 __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1003 {
<> 144:ef7eb2e8f9f7 1004 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1005 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 1006
<> 144:ef7eb2e8f9f7 1007 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1008 the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file
<> 144:ef7eb2e8f9f7 1009 */
<> 144:ef7eb2e8f9f7 1010 }
<> 144:ef7eb2e8f9f7 1011
<> 144:ef7eb2e8f9f7 1012 /**
<> 144:ef7eb2e8f9f7 1013 * @brief Rx Transfer completed callback
<> 144:ef7eb2e8f9f7 1014 * @param hirda: irda handle
<> 144:ef7eb2e8f9f7 1015 * @retval None
<> 144:ef7eb2e8f9f7 1016 */
<> 144:ef7eb2e8f9f7 1017 __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1018 {
<> 144:ef7eb2e8f9f7 1019 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1020 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 1021
<> 144:ef7eb2e8f9f7 1022 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1023 the HAL_IRDA_RxCpltCallback can be implemented in the user file
<> 144:ef7eb2e8f9f7 1024 */
<> 144:ef7eb2e8f9f7 1025 }
<> 144:ef7eb2e8f9f7 1026
<> 144:ef7eb2e8f9f7 1027 /**
<> 144:ef7eb2e8f9f7 1028 * @brief IRDA error callback
<> 144:ef7eb2e8f9f7 1029 * @param hirda: IRDA handle
<> 144:ef7eb2e8f9f7 1030 * @retval None
<> 144:ef7eb2e8f9f7 1031 */
<> 144:ef7eb2e8f9f7 1032 __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1033 {
<> 144:ef7eb2e8f9f7 1034 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1035 UNUSED(hirda);
<> 144:ef7eb2e8f9f7 1036
<> 144:ef7eb2e8f9f7 1037 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1038 the HAL_IRDA_ErrorCallback can be implemented in the user file
<> 144:ef7eb2e8f9f7 1039 */
<> 144:ef7eb2e8f9f7 1040 }
<> 144:ef7eb2e8f9f7 1041
<> 144:ef7eb2e8f9f7 1042 /**
<> 144:ef7eb2e8f9f7 1043 * @}
<> 144:ef7eb2e8f9f7 1044 */
<> 144:ef7eb2e8f9f7 1045
<> 144:ef7eb2e8f9f7 1046 /** @addtogroup IRDA_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 1047 * @brief IRDA control functions
<> 144:ef7eb2e8f9f7 1048 *
<> 144:ef7eb2e8f9f7 1049 @verbatim
<> 144:ef7eb2e8f9f7 1050 ===============================================================================
<> 144:ef7eb2e8f9f7 1051 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 1052 ===============================================================================
<> 144:ef7eb2e8f9f7 1053 [..]
<> 144:ef7eb2e8f9f7 1054 This subsection provides a set of functions allowing to control the IRDA.
<> 144:ef7eb2e8f9f7 1055 (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IRDA peripheral.
<> 144:ef7eb2e8f9f7 1056 (+) IRDA_SetConfig() API is used to configure the IRDA communications parameters.
<> 144:ef7eb2e8f9f7 1057 @endverbatim
<> 144:ef7eb2e8f9f7 1058 * @{
<> 144:ef7eb2e8f9f7 1059 */
<> 144:ef7eb2e8f9f7 1060
<> 144:ef7eb2e8f9f7 1061 /**
<> 144:ef7eb2e8f9f7 1062 * @brief return the IRDA state
<> 144:ef7eb2e8f9f7 1063 * @param hirda: irda handle
<> 144:ef7eb2e8f9f7 1064 * @retval HAL state
<> 144:ef7eb2e8f9f7 1065 */
<> 144:ef7eb2e8f9f7 1066 HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1067 {
<> 144:ef7eb2e8f9f7 1068 return hirda->State;
<> 144:ef7eb2e8f9f7 1069 }
<> 144:ef7eb2e8f9f7 1070
<> 144:ef7eb2e8f9f7 1071 /**
<> 144:ef7eb2e8f9f7 1072 * @brief Return the IRDA error code
<> 144:ef7eb2e8f9f7 1073 * @param hirda : pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1074 * the configuration information for the specified IRDA.
<> 144:ef7eb2e8f9f7 1075 * @retval IRDA Error Code
<> 144:ef7eb2e8f9f7 1076 */
<> 144:ef7eb2e8f9f7 1077 uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1078 {
<> 144:ef7eb2e8f9f7 1079 return hirda->ErrorCode;
<> 144:ef7eb2e8f9f7 1080 }
<> 144:ef7eb2e8f9f7 1081
<> 144:ef7eb2e8f9f7 1082 /**
<> 144:ef7eb2e8f9f7 1083 * @}
<> 144:ef7eb2e8f9f7 1084 */
<> 144:ef7eb2e8f9f7 1085
<> 144:ef7eb2e8f9f7 1086 /**
<> 144:ef7eb2e8f9f7 1087 * @}
<> 144:ef7eb2e8f9f7 1088 */
<> 144:ef7eb2e8f9f7 1089
<> 144:ef7eb2e8f9f7 1090 /** @addtogroup IRDA_Private
<> 144:ef7eb2e8f9f7 1091 * @{
<> 144:ef7eb2e8f9f7 1092 */
<> 144:ef7eb2e8f9f7 1093 /**
<> 144:ef7eb2e8f9f7 1094 * @brief Configure the IRDA peripheral
<> 144:ef7eb2e8f9f7 1095 * @param hirda: irda handle
<> 144:ef7eb2e8f9f7 1096 * @retval None
<> 144:ef7eb2e8f9f7 1097 */
<> 144:ef7eb2e8f9f7 1098 static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1099 {
<> 151:5eaa88a5bcc7 1100 uint32_t tmpreg = 0x00000000U;
<> 151:5eaa88a5bcc7 1101 uint32_t clocksource = 0x00000000U;
<> 144:ef7eb2e8f9f7 1102
<> 144:ef7eb2e8f9f7 1103 /* Check the communication parameters */
<> 144:ef7eb2e8f9f7 1104 assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
<> 144:ef7eb2e8f9f7 1105 assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
<> 144:ef7eb2e8f9f7 1106 assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
<> 144:ef7eb2e8f9f7 1107 assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));
<> 144:ef7eb2e8f9f7 1108 assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));
<> 144:ef7eb2e8f9f7 1109 assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));
<> 144:ef7eb2e8f9f7 1110 /*-------------------------- USART CR1 Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 1111 /* Configure the IRDA Word Length, Parity and transfer Mode:
<> 144:ef7eb2e8f9f7 1112 Set the M bits according to hirda->Init.WordLength value
<> 144:ef7eb2e8f9f7 1113 Set PCE and PS bits according to hirda->Init.Parity value
<> 144:ef7eb2e8f9f7 1114 Set TE and RE bits according to hirda->Init.Mode value */
<> 144:ef7eb2e8f9f7 1115 tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;
<> 144:ef7eb2e8f9f7 1116
<> 144:ef7eb2e8f9f7 1117 MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);
<> 144:ef7eb2e8f9f7 1118
<> 144:ef7eb2e8f9f7 1119 /*-------------------------- USART CR3 Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 1120 MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
<> 144:ef7eb2e8f9f7 1121
<> 144:ef7eb2e8f9f7 1122 /*-------------------------- USART GTPR Configuration ----------------------*/
<> 144:ef7eb2e8f9f7 1123 MODIFY_REG(hirda->Instance->GTPR, (uint32_t)USART_GTPR_PSC, hirda->Init.Prescaler);
<> 144:ef7eb2e8f9f7 1124
<> 144:ef7eb2e8f9f7 1125 /*-------------------------- USART BRR Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 1126 IRDA_GETCLOCKSOURCE(hirda, clocksource);
<> 144:ef7eb2e8f9f7 1127 switch (clocksource)
<> 144:ef7eb2e8f9f7 1128 {
<> 144:ef7eb2e8f9f7 1129 case IRDA_CLOCKSOURCE_PCLK1:
<> 151:5eaa88a5bcc7 1130 hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
<> 144:ef7eb2e8f9f7 1131 break;
<> 144:ef7eb2e8f9f7 1132 case IRDA_CLOCKSOURCE_PCLK2:
<> 151:5eaa88a5bcc7 1133 hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
<> 144:ef7eb2e8f9f7 1134 break;
<> 144:ef7eb2e8f9f7 1135 case IRDA_CLOCKSOURCE_HSI:
<> 151:5eaa88a5bcc7 1136 hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
<> 144:ef7eb2e8f9f7 1137 break;
<> 144:ef7eb2e8f9f7 1138 case IRDA_CLOCKSOURCE_SYSCLK:
<> 151:5eaa88a5bcc7 1139 hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
<> 144:ef7eb2e8f9f7 1140 break;
<> 144:ef7eb2e8f9f7 1141 case IRDA_CLOCKSOURCE_LSE:
<> 151:5eaa88a5bcc7 1142 hirda->Instance->BRR = (uint16_t)((LSE_VALUE + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
<> 144:ef7eb2e8f9f7 1143 break;
<> 144:ef7eb2e8f9f7 1144 default:
<> 144:ef7eb2e8f9f7 1145 break;
<> 144:ef7eb2e8f9f7 1146 }
<> 144:ef7eb2e8f9f7 1147 }
<> 144:ef7eb2e8f9f7 1148
<> 144:ef7eb2e8f9f7 1149 /**
<> 144:ef7eb2e8f9f7 1150 * @brief Check the IRDA Idle State
<> 144:ef7eb2e8f9f7 1151 * @param hirda: IRDA handle
<> 144:ef7eb2e8f9f7 1152 * @retval HAL status
<> 144:ef7eb2e8f9f7 1153 */
<> 144:ef7eb2e8f9f7 1154 static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1155 {
<> 144:ef7eb2e8f9f7 1156 /* Initialize the IRDA ErrorCode */
<> 144:ef7eb2e8f9f7 1157 hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1158
<> 144:ef7eb2e8f9f7 1159 /* Check if the Transmitter is enabled */
<> 144:ef7eb2e8f9f7 1160 if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
<> 144:ef7eb2e8f9f7 1161 {
<> 144:ef7eb2e8f9f7 1162 /* Wait until TEACK flag is set */
<> 144:ef7eb2e8f9f7 1163 if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK)
<> 144:ef7eb2e8f9f7 1164 {
<> 144:ef7eb2e8f9f7 1165 hirda->State= HAL_IRDA_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1166 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1167 }
<> 144:ef7eb2e8f9f7 1168 }
<> 144:ef7eb2e8f9f7 1169 /* Check if the Receiver is enabled */
<> 144:ef7eb2e8f9f7 1170 if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
<> 144:ef7eb2e8f9f7 1171 {
<> 144:ef7eb2e8f9f7 1172 if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK)
<> 144:ef7eb2e8f9f7 1173 {
<> 144:ef7eb2e8f9f7 1174 hirda->State= HAL_IRDA_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1175 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1176 }
<> 144:ef7eb2e8f9f7 1177 }
<> 144:ef7eb2e8f9f7 1178 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1179 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 1180
<> 144:ef7eb2e8f9f7 1181 /* Initialize the IRDA state*/
<> 144:ef7eb2e8f9f7 1182 hirda->State= HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1183
<> 144:ef7eb2e8f9f7 1184 return HAL_OK;
<> 144:ef7eb2e8f9f7 1185 }
<> 144:ef7eb2e8f9f7 1186
<> 144:ef7eb2e8f9f7 1187 /**
<> 144:ef7eb2e8f9f7 1188 * @brief Handle IRDA Communication Timeout.
<> 144:ef7eb2e8f9f7 1189 * @param hirda: IRDA handle
<> 144:ef7eb2e8f9f7 1190 * @param Flag: specifies the IRDA flag to check.
<> 144:ef7eb2e8f9f7 1191 * @param Status: the flag status (SET or RESET). The function is locked in a while loop as long as the flag remains set to Status.
<> 144:ef7eb2e8f9f7 1192 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 1193 * @retval HAL status
<> 144:ef7eb2e8f9f7 1194 */
<> 144:ef7eb2e8f9f7 1195 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1196 {
<> 151:5eaa88a5bcc7 1197 uint32_t tickstart = 0x00U;
<> 144:ef7eb2e8f9f7 1198 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1199
<> 144:ef7eb2e8f9f7 1200 /* Wait until flag is set */
<> 144:ef7eb2e8f9f7 1201 if(Status == RESET)
<> 144:ef7eb2e8f9f7 1202 {
<> 144:ef7eb2e8f9f7 1203 while(__HAL_IRDA_GET_FLAG(hirda, Flag) == RESET)
<> 144:ef7eb2e8f9f7 1204 {
<> 144:ef7eb2e8f9f7 1205 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1206 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1207 {
<> 151:5eaa88a5bcc7 1208 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1209 {
<> 144:ef7eb2e8f9f7 1210 /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
<> 144:ef7eb2e8f9f7 1211 __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
<> 144:ef7eb2e8f9f7 1212 __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
<> 144:ef7eb2e8f9f7 1213 __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
<> 144:ef7eb2e8f9f7 1214 __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
<> 144:ef7eb2e8f9f7 1215
<> 144:ef7eb2e8f9f7 1216 hirda->State= HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1217
<> 144:ef7eb2e8f9f7 1218 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1219 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 1220
<> 144:ef7eb2e8f9f7 1221 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1222 }
<> 144:ef7eb2e8f9f7 1223 }
<> 144:ef7eb2e8f9f7 1224 }
<> 144:ef7eb2e8f9f7 1225 }
<> 144:ef7eb2e8f9f7 1226 else
<> 144:ef7eb2e8f9f7 1227 {
<> 144:ef7eb2e8f9f7 1228 while(__HAL_IRDA_GET_FLAG(hirda, Flag) != RESET)
<> 144:ef7eb2e8f9f7 1229 {
<> 144:ef7eb2e8f9f7 1230 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1231 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1232 {
<> 151:5eaa88a5bcc7 1233 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1234 {
<> 144:ef7eb2e8f9f7 1235 /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
<> 144:ef7eb2e8f9f7 1236 __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
<> 144:ef7eb2e8f9f7 1237 __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
<> 144:ef7eb2e8f9f7 1238 __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
<> 144:ef7eb2e8f9f7 1239 __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
<> 144:ef7eb2e8f9f7 1240
<> 144:ef7eb2e8f9f7 1241 hirda->State= HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1242
<> 144:ef7eb2e8f9f7 1243 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1244 __HAL_UNLOCK(hirda);
<> 144:ef7eb2e8f9f7 1245
<> 144:ef7eb2e8f9f7 1246 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1247 }
<> 144:ef7eb2e8f9f7 1248 }
<> 144:ef7eb2e8f9f7 1249 }
<> 144:ef7eb2e8f9f7 1250 }
<> 144:ef7eb2e8f9f7 1251 return HAL_OK;
<> 144:ef7eb2e8f9f7 1252 }
<> 144:ef7eb2e8f9f7 1253
<> 144:ef7eb2e8f9f7 1254 /**
<> 144:ef7eb2e8f9f7 1255 * @brief Receive an amount of data in non blocking mode.
<> 144:ef7eb2e8f9f7 1256 * Function called under interruption only, once
<> 144:ef7eb2e8f9f7 1257 * interruptions have been enabled by HAL_IRDA_Transmit_IT()
<> 144:ef7eb2e8f9f7 1258 * @param hirda: IRDA handle
<> 144:ef7eb2e8f9f7 1259 * @retval HAL status
<> 144:ef7eb2e8f9f7 1260 */
<> 144:ef7eb2e8f9f7 1261 static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1262 {
<> 144:ef7eb2e8f9f7 1263 uint16_t* tmp;
<> 144:ef7eb2e8f9f7 1264
<> 144:ef7eb2e8f9f7 1265 if((hirda->State == HAL_IRDA_STATE_BUSY_TX) || (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX))
<> 144:ef7eb2e8f9f7 1266 {
<> 144:ef7eb2e8f9f7 1267
<> 151:5eaa88a5bcc7 1268 if(hirda->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 1269 {
<> 144:ef7eb2e8f9f7 1270 /* Disable the IRDA Transmit Data Register Empty Interrupt */
<> 144:ef7eb2e8f9f7 1271 __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
<> 144:ef7eb2e8f9f7 1272
<> 144:ef7eb2e8f9f7 1273 /* Enable the IRDA Transmit Complete Interrupt */
<> 144:ef7eb2e8f9f7 1274 __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
<> 144:ef7eb2e8f9f7 1275
<> 144:ef7eb2e8f9f7 1276 return HAL_OK;
<> 144:ef7eb2e8f9f7 1277 }
<> 144:ef7eb2e8f9f7 1278 else
<> 144:ef7eb2e8f9f7 1279 {
<> 144:ef7eb2e8f9f7 1280 if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
<> 144:ef7eb2e8f9f7 1281 {
<> 144:ef7eb2e8f9f7 1282 tmp = (uint16_t*) hirda->pTxBuffPtr;
<> 151:5eaa88a5bcc7 1283 hirda->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
<> 151:5eaa88a5bcc7 1284 hirda->pTxBuffPtr += 2U;
<> 144:ef7eb2e8f9f7 1285 }
<> 144:ef7eb2e8f9f7 1286 else
<> 144:ef7eb2e8f9f7 1287 {
<> 151:5eaa88a5bcc7 1288 hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFFU);
<> 144:ef7eb2e8f9f7 1289 }
<> 144:ef7eb2e8f9f7 1290 hirda->TxXferCount--;
<> 144:ef7eb2e8f9f7 1291 return HAL_OK;
<> 144:ef7eb2e8f9f7 1292 }
<> 144:ef7eb2e8f9f7 1293 }
<> 144:ef7eb2e8f9f7 1294 else
<> 144:ef7eb2e8f9f7 1295 {
<> 144:ef7eb2e8f9f7 1296 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1297 }
<> 144:ef7eb2e8f9f7 1298 }
<> 144:ef7eb2e8f9f7 1299 /**
<> 144:ef7eb2e8f9f7 1300 * @brief Wraps up transmission in non blocking mode.
<> 144:ef7eb2e8f9f7 1301 * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1302 * the configuration information for the specified IRDA module.
<> 144:ef7eb2e8f9f7 1303 * @retval HAL status
<> 144:ef7eb2e8f9f7 1304 */
<> 144:ef7eb2e8f9f7 1305 static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1306 {
<> 144:ef7eb2e8f9f7 1307 /* Disable the IRDA Transmit Complete Interrupt */
<> 144:ef7eb2e8f9f7 1308 __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC);
<> 144:ef7eb2e8f9f7 1309
<> 144:ef7eb2e8f9f7 1310 /* Check if a receive process is ongoing or not */
<> 144:ef7eb2e8f9f7 1311 if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 1312 {
<> 144:ef7eb2e8f9f7 1313 hirda->State = HAL_IRDA_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 1314 }
<> 144:ef7eb2e8f9f7 1315 else
<> 144:ef7eb2e8f9f7 1316 {
<> 144:ef7eb2e8f9f7 1317 /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
<> 144:ef7eb2e8f9f7 1318 __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
<> 144:ef7eb2e8f9f7 1319
<> 144:ef7eb2e8f9f7 1320 hirda->State = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1321 }
<> 144:ef7eb2e8f9f7 1322
<> 144:ef7eb2e8f9f7 1323 HAL_IRDA_TxCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 1324
<> 144:ef7eb2e8f9f7 1325 return HAL_OK;
<> 144:ef7eb2e8f9f7 1326 }
<> 144:ef7eb2e8f9f7 1327
<> 144:ef7eb2e8f9f7 1328 /**
<> 144:ef7eb2e8f9f7 1329 * @brief Receive an amount of data in non blocking mode.
<> 144:ef7eb2e8f9f7 1330 * Function called under interruption only, once
<> 144:ef7eb2e8f9f7 1331 * interruptions have been enabled by HAL_IRDA_Receive_IT()
<> 144:ef7eb2e8f9f7 1332 * @param hirda: IRDA handle
<> 144:ef7eb2e8f9f7 1333 * @retval HAL status
<> 144:ef7eb2e8f9f7 1334 */
<> 144:ef7eb2e8f9f7 1335 static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
<> 144:ef7eb2e8f9f7 1336 {
<> 144:ef7eb2e8f9f7 1337 uint16_t* tmp;
<> 144:ef7eb2e8f9f7 1338 uint16_t uhMask = hirda->Mask;
<> 144:ef7eb2e8f9f7 1339
<> 144:ef7eb2e8f9f7 1340 if ((hirda->State == HAL_IRDA_STATE_BUSY_RX) || (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX))
<> 144:ef7eb2e8f9f7 1341 {
<> 144:ef7eb2e8f9f7 1342 if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
<> 144:ef7eb2e8f9f7 1343 {
<> 144:ef7eb2e8f9f7 1344 tmp = (uint16_t*) hirda->pRxBuffPtr ;
<> 144:ef7eb2e8f9f7 1345 *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
<> 151:5eaa88a5bcc7 1346 hirda->pRxBuffPtr +=2U;
<> 144:ef7eb2e8f9f7 1347 }
<> 144:ef7eb2e8f9f7 1348 else
<> 144:ef7eb2e8f9f7 1349 {
<> 144:ef7eb2e8f9f7 1350 *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
<> 144:ef7eb2e8f9f7 1351 }
<> 144:ef7eb2e8f9f7 1352
<> 151:5eaa88a5bcc7 1353 if(--hirda->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 1354 {
<> 144:ef7eb2e8f9f7 1355 while(HAL_IS_BIT_SET(hirda->Instance->ISR, IRDA_FLAG_RXNE))
<> 144:ef7eb2e8f9f7 1356 {
<> 144:ef7eb2e8f9f7 1357 }
<> 144:ef7eb2e8f9f7 1358 __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
<> 151:5eaa88a5bcc7 1359
<> 151:5eaa88a5bcc7 1360 /* Disable the IRDA Parity Error Interrupt */
<> 151:5eaa88a5bcc7 1361 __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
<> 144:ef7eb2e8f9f7 1362
<> 151:5eaa88a5bcc7 1363 /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
<> 151:5eaa88a5bcc7 1364 __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
<> 151:5eaa88a5bcc7 1365
<> 144:ef7eb2e8f9f7 1366 if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 1367 {
<> 144:ef7eb2e8f9f7 1368 hirda->State = HAL_IRDA_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 1369 }
<> 144:ef7eb2e8f9f7 1370 else
<> 144:ef7eb2e8f9f7 1371 {
<> 144:ef7eb2e8f9f7 1372 hirda->State = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1373 }
<> 144:ef7eb2e8f9f7 1374
<> 144:ef7eb2e8f9f7 1375 HAL_IRDA_RxCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 1376
<> 144:ef7eb2e8f9f7 1377 return HAL_OK;
<> 144:ef7eb2e8f9f7 1378 }
<> 144:ef7eb2e8f9f7 1379
<> 144:ef7eb2e8f9f7 1380 return HAL_OK;
<> 144:ef7eb2e8f9f7 1381 }
<> 144:ef7eb2e8f9f7 1382 else
<> 144:ef7eb2e8f9f7 1383 {
<> 144:ef7eb2e8f9f7 1384 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1385 }
<> 144:ef7eb2e8f9f7 1386 }
<> 144:ef7eb2e8f9f7 1387
<> 144:ef7eb2e8f9f7 1388 /**
<> 144:ef7eb2e8f9f7 1389 * @brief DMA IRDA Tx transfer completed callback
<> 144:ef7eb2e8f9f7 1390 * @param hdma: DMA handle
<> 144:ef7eb2e8f9f7 1391 * @retval None
<> 144:ef7eb2e8f9f7 1392 */
<> 144:ef7eb2e8f9f7 1393 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1394 {
<> 144:ef7eb2e8f9f7 1395 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1396
<> 144:ef7eb2e8f9f7 1397 /* DMA Normal mode */
<> 144:ef7eb2e8f9f7 1398 if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
<> 144:ef7eb2e8f9f7 1399 {
<> 151:5eaa88a5bcc7 1400 hirda->TxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1401
<> 144:ef7eb2e8f9f7 1402 /* Disable the DMA transfer for transmit request by resetting the DMAT bit
<> 144:ef7eb2e8f9f7 1403 in the IRDA CR3 register */
<> 144:ef7eb2e8f9f7 1404 hirda->Instance->CR3 &= ~(USART_CR3_DMAT);
<> 144:ef7eb2e8f9f7 1405
<> 144:ef7eb2e8f9f7 1406 /* Enable the IRDA Transmit Complete Interrupt */
<> 144:ef7eb2e8f9f7 1407 __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
<> 144:ef7eb2e8f9f7 1408 }
<> 144:ef7eb2e8f9f7 1409 /* DMA Circular mode */
<> 144:ef7eb2e8f9f7 1410 else
<> 144:ef7eb2e8f9f7 1411 {
<> 144:ef7eb2e8f9f7 1412 HAL_IRDA_TxCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 1413 }
<> 144:ef7eb2e8f9f7 1414 }
<> 144:ef7eb2e8f9f7 1415
<> 144:ef7eb2e8f9f7 1416 /**
<> 144:ef7eb2e8f9f7 1417 * @brief DMA IRDA receive process half complete callback
<> 144:ef7eb2e8f9f7 1418 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1419 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1420 * @retval None
<> 144:ef7eb2e8f9f7 1421 */
<> 144:ef7eb2e8f9f7 1422 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1423 {
<> 144:ef7eb2e8f9f7 1424 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1425
<> 144:ef7eb2e8f9f7 1426 HAL_IRDA_TxHalfCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 1427 }
<> 144:ef7eb2e8f9f7 1428
<> 144:ef7eb2e8f9f7 1429 /**
<> 144:ef7eb2e8f9f7 1430 * @brief DMA IRDA Rx Transfer completed callback
<> 144:ef7eb2e8f9f7 1431 * @param hdma: DMA handle
<> 144:ef7eb2e8f9f7 1432 * @retval None
<> 144:ef7eb2e8f9f7 1433 */
<> 144:ef7eb2e8f9f7 1434 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1435 {
<> 144:ef7eb2e8f9f7 1436 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1437 /* DMA Normal mode */
<> 151:5eaa88a5bcc7 1438 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
<> 144:ef7eb2e8f9f7 1439 {
<> 151:5eaa88a5bcc7 1440 hirda->RxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1441
<> 144:ef7eb2e8f9f7 1442 /* Disable the DMA transfer for the receiver request by setting the DMAR bit
<> 144:ef7eb2e8f9f7 1443 in the IRDA CR3 register */
<> 144:ef7eb2e8f9f7 1444 hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAR);
<> 144:ef7eb2e8f9f7 1445
<> 144:ef7eb2e8f9f7 1446 if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 1447 {
<> 144:ef7eb2e8f9f7 1448 hirda->State = HAL_IRDA_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 1449 }
<> 144:ef7eb2e8f9f7 1450 else
<> 144:ef7eb2e8f9f7 1451 {
<> 144:ef7eb2e8f9f7 1452 hirda->State = HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1453 }
<> 144:ef7eb2e8f9f7 1454 }
<> 144:ef7eb2e8f9f7 1455
<> 144:ef7eb2e8f9f7 1456 HAL_IRDA_RxCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 1457 }
<> 144:ef7eb2e8f9f7 1458
<> 144:ef7eb2e8f9f7 1459 /**
<> 144:ef7eb2e8f9f7 1460 * @brief DMA IRDA receive process half complete callback
<> 144:ef7eb2e8f9f7 1461 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1462 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1463 * @retval None
<> 144:ef7eb2e8f9f7 1464 */
<> 144:ef7eb2e8f9f7 1465 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1466 {
<> 144:ef7eb2e8f9f7 1467 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1468
<> 144:ef7eb2e8f9f7 1469 HAL_IRDA_RxHalfCpltCallback(hirda);
<> 144:ef7eb2e8f9f7 1470 }
<> 144:ef7eb2e8f9f7 1471
<> 144:ef7eb2e8f9f7 1472 /**
<> 144:ef7eb2e8f9f7 1473 * @brief DMA IRDA communication error callback
<> 144:ef7eb2e8f9f7 1474 * @param hdma: DMA handle
<> 144:ef7eb2e8f9f7 1475 * @retval None
<> 144:ef7eb2e8f9f7 1476 */
<> 144:ef7eb2e8f9f7 1477 static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1478 {
<> 144:ef7eb2e8f9f7 1479 IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 151:5eaa88a5bcc7 1480 hirda->RxXferCount = 0U;
<> 151:5eaa88a5bcc7 1481 hirda->TxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1482 hirda->State= HAL_IRDA_STATE_READY;
<> 144:ef7eb2e8f9f7 1483 hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
<> 144:ef7eb2e8f9f7 1484 HAL_IRDA_ErrorCallback(hirda);
<> 144:ef7eb2e8f9f7 1485 }
<> 144:ef7eb2e8f9f7 1486
<> 144:ef7eb2e8f9f7 1487 /**
<> 144:ef7eb2e8f9f7 1488 * @}
<> 144:ef7eb2e8f9f7 1489 */
<> 144:ef7eb2e8f9f7 1490
<> 144:ef7eb2e8f9f7 1491 /**
<> 144:ef7eb2e8f9f7 1492 * @}
<> 144:ef7eb2e8f9f7 1493 */
<> 144:ef7eb2e8f9f7 1494
<> 144:ef7eb2e8f9f7 1495 #endif /* HAL_IRDA_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1496 /**
<> 144:ef7eb2e8f9f7 1497 * @}
<> 144:ef7eb2e8f9f7 1498 */
<> 144:ef7eb2e8f9f7 1499
<> 144:ef7eb2e8f9f7 1500 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 1501