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Dependents: STM32L452_Nucleo_ticker
Fork of mbed-dev by
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.h@167:e84263d55307, 2017-06-21 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Jun 21 17:46:44 2017 +0100
- Revision:
- 167:e84263d55307
- Parent:
- 149:156823d33999
This updates the lib to the mbed lib v 145
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file stm32l4xx_ll_fmc.h |
<> | 144:ef7eb2e8f9f7 | 4 | * @author MCD Application Team |
AnnaBridge | 167:e84263d55307 | 5 | * @version V1.7.1 |
AnnaBridge | 167:e84263d55307 | 6 | * @date 21-April-2017 |
<> | 144:ef7eb2e8f9f7 | 7 | * @brief Header file of FMC HAL module. |
<> | 144:ef7eb2e8f9f7 | 8 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 9 | * @attention |
<> | 144:ef7eb2e8f9f7 | 10 | * |
AnnaBridge | 167:e84263d55307 | 11 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
<> | 144:ef7eb2e8f9f7 | 12 | * |
<> | 144:ef7eb2e8f9f7 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 14 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 16 | * this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 18 | * this list of conditions and the following disclaimer in the documentation |
<> | 144:ef7eb2e8f9f7 | 19 | * and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 144:ef7eb2e8f9f7 | 21 | * may be used to endorse or promote products derived from this software |
<> | 144:ef7eb2e8f9f7 | 22 | * without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 23 | * |
<> | 144:ef7eb2e8f9f7 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 144:ef7eb2e8f9f7 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 144:ef7eb2e8f9f7 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 144:ef7eb2e8f9f7 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 144:ef7eb2e8f9f7 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 144:ef7eb2e8f9f7 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 144:ef7eb2e8f9f7 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 34 | * |
<> | 144:ef7eb2e8f9f7 | 35 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 36 | */ |
<> | 144:ef7eb2e8f9f7 | 37 | |
<> | 144:ef7eb2e8f9f7 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 39 | #ifndef __STM32L4xx_LL_FMC_H |
<> | 144:ef7eb2e8f9f7 | 40 | #define __STM32L4xx_LL_FMC_H |
<> | 144:ef7eb2e8f9f7 | 41 | |
<> | 144:ef7eb2e8f9f7 | 42 | #ifdef __cplusplus |
AnnaBridge | 167:e84263d55307 | 43 | extern "C" { |
<> | 144:ef7eb2e8f9f7 | 44 | #endif |
<> | 144:ef7eb2e8f9f7 | 45 | |
<> | 144:ef7eb2e8f9f7 | 46 | /* Includes ------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 47 | #include "stm32l4xx_hal_def.h" |
<> | 144:ef7eb2e8f9f7 | 48 | |
<> | 144:ef7eb2e8f9f7 | 49 | /** @addtogroup STM32L4xx_HAL_Driver |
<> | 144:ef7eb2e8f9f7 | 50 | * @{ |
<> | 144:ef7eb2e8f9f7 | 51 | */ |
<> | 144:ef7eb2e8f9f7 | 52 | |
AnnaBridge | 167:e84263d55307 | 53 | #if defined(FMC_BANK1) |
AnnaBridge | 167:e84263d55307 | 54 | |
AnnaBridge | 167:e84263d55307 | 55 | /** @addtogroup FMC_LL |
AnnaBridge | 167:e84263d55307 | 56 | * @{ |
AnnaBridge | 167:e84263d55307 | 57 | */ |
AnnaBridge | 167:e84263d55307 | 58 | |
AnnaBridge | 167:e84263d55307 | 59 | /** @addtogroup FMC_LL_Private_Macros |
<> | 144:ef7eb2e8f9f7 | 60 | * @{ |
<> | 144:ef7eb2e8f9f7 | 61 | */ |
<> | 144:ef7eb2e8f9f7 | 62 | |
AnnaBridge | 167:e84263d55307 | 63 | #define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ |
AnnaBridge | 167:e84263d55307 | 64 | ((__BANK__) == FMC_NORSRAM_BANK2) || \ |
AnnaBridge | 167:e84263d55307 | 65 | ((__BANK__) == FMC_NORSRAM_BANK3) || \ |
AnnaBridge | 167:e84263d55307 | 66 | ((__BANK__) == FMC_NORSRAM_BANK4)) |
<> | 144:ef7eb2e8f9f7 | 67 | |
AnnaBridge | 167:e84263d55307 | 68 | #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ |
AnnaBridge | 167:e84263d55307 | 69 | ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) |
<> | 144:ef7eb2e8f9f7 | 70 | |
AnnaBridge | 167:e84263d55307 | 71 | #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ |
AnnaBridge | 167:e84263d55307 | 72 | ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ |
AnnaBridge | 167:e84263d55307 | 73 | ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) |
<> | 144:ef7eb2e8f9f7 | 74 | |
<> | 144:ef7eb2e8f9f7 | 75 | #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ |
AnnaBridge | 167:e84263d55307 | 76 | ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ |
AnnaBridge | 167:e84263d55307 | 77 | ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) |
AnnaBridge | 167:e84263d55307 | 78 | |
AnnaBridge | 167:e84263d55307 | 79 | #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ |
AnnaBridge | 167:e84263d55307 | 80 | ((__BURST__) == FMC_WRITE_BURST_ENABLE)) |
<> | 144:ef7eb2e8f9f7 | 81 | |
<> | 144:ef7eb2e8f9f7 | 82 | #define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ |
<> | 144:ef7eb2e8f9f7 | 83 | ((__SIZE__) == FMC_PAGE_SIZE_128) || \ |
<> | 144:ef7eb2e8f9f7 | 84 | ((__SIZE__) == FMC_PAGE_SIZE_256) || \ |
<> | 144:ef7eb2e8f9f7 | 85 | ((__SIZE__) == FMC_PAGE_SIZE_512) || \ |
<> | 144:ef7eb2e8f9f7 | 86 | ((__SIZE__) == FMC_PAGE_SIZE_1024)) |
<> | 144:ef7eb2e8f9f7 | 87 | |
<> | 144:ef7eb2e8f9f7 | 88 | #define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ |
<> | 144:ef7eb2e8f9f7 | 89 | ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) |
<> | 144:ef7eb2e8f9f7 | 90 | |
AnnaBridge | 167:e84263d55307 | 91 | #if defined(FMC_BCR1_WFDIS) |
AnnaBridge | 167:e84263d55307 | 92 | #define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ |
AnnaBridge | 167:e84263d55307 | 93 | ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) |
AnnaBridge | 167:e84263d55307 | 94 | |
AnnaBridge | 167:e84263d55307 | 95 | #endif /* FMC_BCR1_WFDIS */ |
AnnaBridge | 167:e84263d55307 | 96 | #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ |
AnnaBridge | 167:e84263d55307 | 97 | ((__MODE__) == FMC_ACCESS_MODE_B) || \ |
AnnaBridge | 167:e84263d55307 | 98 | ((__MODE__) == FMC_ACCESS_MODE_C) || \ |
AnnaBridge | 167:e84263d55307 | 99 | ((__MODE__) == FMC_ACCESS_MODE_D)) |
AnnaBridge | 167:e84263d55307 | 100 | |
AnnaBridge | 167:e84263d55307 | 101 | #define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) |
AnnaBridge | 167:e84263d55307 | 102 | |
AnnaBridge | 167:e84263d55307 | 103 | #define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ |
AnnaBridge | 167:e84263d55307 | 104 | ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE)) |
AnnaBridge | 167:e84263d55307 | 105 | |
AnnaBridge | 167:e84263d55307 | 106 | #define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \ |
AnnaBridge | 167:e84263d55307 | 107 | ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16)) |
<> | 144:ef7eb2e8f9f7 | 108 | |
AnnaBridge | 167:e84263d55307 | 109 | #define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ |
AnnaBridge | 167:e84263d55307 | 110 | ((__STATE__) == FMC_NAND_ECC_ENABLE)) |
<> | 144:ef7eb2e8f9f7 | 111 | |
AnnaBridge | 167:e84263d55307 | 112 | #define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ |
AnnaBridge | 167:e84263d55307 | 113 | ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ |
AnnaBridge | 167:e84263d55307 | 114 | ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ |
AnnaBridge | 167:e84263d55307 | 115 | ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ |
AnnaBridge | 167:e84263d55307 | 116 | ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ |
AnnaBridge | 167:e84263d55307 | 117 | ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) |
AnnaBridge | 167:e84263d55307 | 118 | |
AnnaBridge | 167:e84263d55307 | 119 | /** @defgroup FMC_TCLR_Setup_Time FMC_TCLR_Setup_Time |
AnnaBridge | 167:e84263d55307 | 120 | * @{ |
AnnaBridge | 167:e84263d55307 | 121 | */ |
AnnaBridge | 167:e84263d55307 | 122 | #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255) |
AnnaBridge | 167:e84263d55307 | 123 | /** |
AnnaBridge | 167:e84263d55307 | 124 | * @} |
AnnaBridge | 167:e84263d55307 | 125 | */ |
<> | 144:ef7eb2e8f9f7 | 126 | |
AnnaBridge | 167:e84263d55307 | 127 | /** @defgroup FMC_TAR_Setup_Time FMC_TAR_Setup_Time |
AnnaBridge | 167:e84263d55307 | 128 | * @{ |
AnnaBridge | 167:e84263d55307 | 129 | */ |
AnnaBridge | 167:e84263d55307 | 130 | #define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255) |
AnnaBridge | 167:e84263d55307 | 131 | /** |
AnnaBridge | 167:e84263d55307 | 132 | * @} |
AnnaBridge | 167:e84263d55307 | 133 | */ |
<> | 144:ef7eb2e8f9f7 | 134 | |
AnnaBridge | 167:e84263d55307 | 135 | /** @defgroup FMC_Setup_Time FMC_Setup_Time |
AnnaBridge | 167:e84263d55307 | 136 | * @{ |
AnnaBridge | 167:e84263d55307 | 137 | */ |
AnnaBridge | 167:e84263d55307 | 138 | #define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 255) |
AnnaBridge | 167:e84263d55307 | 139 | /** |
AnnaBridge | 167:e84263d55307 | 140 | * @} |
AnnaBridge | 167:e84263d55307 | 141 | */ |
<> | 144:ef7eb2e8f9f7 | 142 | |
AnnaBridge | 167:e84263d55307 | 143 | /** @defgroup FMC_Wait_Setup_Time FMC_Wait_Setup_Time |
AnnaBridge | 167:e84263d55307 | 144 | * @{ |
AnnaBridge | 167:e84263d55307 | 145 | */ |
AnnaBridge | 167:e84263d55307 | 146 | #define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 255) |
AnnaBridge | 167:e84263d55307 | 147 | /** |
AnnaBridge | 167:e84263d55307 | 148 | * @} |
AnnaBridge | 167:e84263d55307 | 149 | */ |
<> | 144:ef7eb2e8f9f7 | 150 | |
AnnaBridge | 167:e84263d55307 | 151 | /** @defgroup FMC_Hold_Setup_Time FMC_Hold_Setup_Time |
AnnaBridge | 167:e84263d55307 | 152 | * @{ |
AnnaBridge | 167:e84263d55307 | 153 | */ |
AnnaBridge | 167:e84263d55307 | 154 | #define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 255) |
AnnaBridge | 167:e84263d55307 | 155 | /** |
AnnaBridge | 167:e84263d55307 | 156 | * @} |
AnnaBridge | 167:e84263d55307 | 157 | */ |
AnnaBridge | 167:e84263d55307 | 158 | |
AnnaBridge | 167:e84263d55307 | 159 | /** @defgroup FMC_HiZ_Setup_Time FMC_HiZ_Setup_Time |
AnnaBridge | 167:e84263d55307 | 160 | * @{ |
AnnaBridge | 167:e84263d55307 | 161 | */ |
AnnaBridge | 167:e84263d55307 | 162 | #define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 255) |
AnnaBridge | 167:e84263d55307 | 163 | /** |
AnnaBridge | 167:e84263d55307 | 164 | * @} |
AnnaBridge | 167:e84263d55307 | 165 | */ |
<> | 144:ef7eb2e8f9f7 | 166 | |
<> | 144:ef7eb2e8f9f7 | 167 | /** @defgroup FMC_NORSRAM_Device_Instance FMC NOR/SRAM Device Instance |
<> | 144:ef7eb2e8f9f7 | 168 | * @{ |
<> | 144:ef7eb2e8f9f7 | 169 | */ |
AnnaBridge | 167:e84263d55307 | 170 | |
<> | 144:ef7eb2e8f9f7 | 171 | #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) |
AnnaBridge | 167:e84263d55307 | 172 | |
<> | 144:ef7eb2e8f9f7 | 173 | /** |
<> | 144:ef7eb2e8f9f7 | 174 | * @} |
<> | 144:ef7eb2e8f9f7 | 175 | */ |
<> | 144:ef7eb2e8f9f7 | 176 | |
<> | 144:ef7eb2e8f9f7 | 177 | /** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NOR/SRAM EXTENDED Device Instance |
<> | 144:ef7eb2e8f9f7 | 178 | * @{ |
<> | 144:ef7eb2e8f9f7 | 179 | */ |
AnnaBridge | 167:e84263d55307 | 180 | |
<> | 144:ef7eb2e8f9f7 | 181 | #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) |
AnnaBridge | 167:e84263d55307 | 182 | |
<> | 144:ef7eb2e8f9f7 | 183 | /** |
<> | 144:ef7eb2e8f9f7 | 184 | * @} |
<> | 144:ef7eb2e8f9f7 | 185 | */ |
<> | 144:ef7eb2e8f9f7 | 186 | |
<> | 144:ef7eb2e8f9f7 | 187 | /** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance |
<> | 144:ef7eb2e8f9f7 | 188 | * @{ |
<> | 144:ef7eb2e8f9f7 | 189 | */ |
<> | 144:ef7eb2e8f9f7 | 190 | #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) |
<> | 144:ef7eb2e8f9f7 | 191 | /** |
<> | 144:ef7eb2e8f9f7 | 192 | * @} |
<> | 144:ef7eb2e8f9f7 | 193 | */ |
<> | 144:ef7eb2e8f9f7 | 194 | |
AnnaBridge | 167:e84263d55307 | 195 | #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ |
AnnaBridge | 167:e84263d55307 | 196 | ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) |
<> | 144:ef7eb2e8f9f7 | 197 | |
AnnaBridge | 167:e84263d55307 | 198 | #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ |
AnnaBridge | 167:e84263d55307 | 199 | ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) |
<> | 144:ef7eb2e8f9f7 | 200 | |
AnnaBridge | 167:e84263d55307 | 201 | #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ |
<> | 144:ef7eb2e8f9f7 | 202 | ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) |
<> | 144:ef7eb2e8f9f7 | 203 | |
AnnaBridge | 167:e84263d55307 | 204 | #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ |
<> | 144:ef7eb2e8f9f7 | 205 | ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) |
<> | 144:ef7eb2e8f9f7 | 206 | |
AnnaBridge | 167:e84263d55307 | 207 | #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ |
AnnaBridge | 167:e84263d55307 | 208 | ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) |
AnnaBridge | 167:e84263d55307 | 209 | |
AnnaBridge | 167:e84263d55307 | 210 | #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ |
AnnaBridge | 167:e84263d55307 | 211 | ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) |
AnnaBridge | 167:e84263d55307 | 212 | |
AnnaBridge | 167:e84263d55307 | 213 | #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ |
AnnaBridge | 167:e84263d55307 | 214 | ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) |
<> | 144:ef7eb2e8f9f7 | 215 | |
AnnaBridge | 167:e84263d55307 | 216 | #define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16)) |
<> | 144:ef7eb2e8f9f7 | 217 | |
AnnaBridge | 167:e84263d55307 | 218 | /** @defgroup FMC_Data_Latency FMC Data Latency |
AnnaBridge | 167:e84263d55307 | 219 | * @{ |
AnnaBridge | 167:e84263d55307 | 220 | */ |
AnnaBridge | 167:e84263d55307 | 221 | #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17)) |
AnnaBridge | 167:e84263d55307 | 222 | /** |
AnnaBridge | 167:e84263d55307 | 223 | * @} |
AnnaBridge | 167:e84263d55307 | 224 | */ |
<> | 144:ef7eb2e8f9f7 | 225 | |
AnnaBridge | 167:e84263d55307 | 226 | /** @defgroup FMC_Address_Setup_Time FMC Address Setup Time |
<> | 144:ef7eb2e8f9f7 | 227 | * @{ |
<> | 144:ef7eb2e8f9f7 | 228 | */ |
<> | 144:ef7eb2e8f9f7 | 229 | #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15) |
<> | 144:ef7eb2e8f9f7 | 230 | /** |
<> | 144:ef7eb2e8f9f7 | 231 | * @} |
<> | 144:ef7eb2e8f9f7 | 232 | */ |
<> | 144:ef7eb2e8f9f7 | 233 | |
AnnaBridge | 167:e84263d55307 | 234 | /** @defgroup FMC_Address_Hold_Time FMC Address Hold Time |
<> | 144:ef7eb2e8f9f7 | 235 | * @{ |
<> | 144:ef7eb2e8f9f7 | 236 | */ |
<> | 144:ef7eb2e8f9f7 | 237 | #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15)) |
<> | 144:ef7eb2e8f9f7 | 238 | /** |
<> | 144:ef7eb2e8f9f7 | 239 | * @} |
<> | 144:ef7eb2e8f9f7 | 240 | */ |
<> | 144:ef7eb2e8f9f7 | 241 | |
AnnaBridge | 167:e84263d55307 | 242 | /** @defgroup FMC_Data_Setup_Time FMC Data Setup Time |
<> | 144:ef7eb2e8f9f7 | 243 | * @{ |
<> | 144:ef7eb2e8f9f7 | 244 | */ |
<> | 144:ef7eb2e8f9f7 | 245 | #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255)) |
<> | 144:ef7eb2e8f9f7 | 246 | /** |
<> | 144:ef7eb2e8f9f7 | 247 | * @} |
<> | 144:ef7eb2e8f9f7 | 248 | */ |
<> | 144:ef7eb2e8f9f7 | 249 | |
AnnaBridge | 167:e84263d55307 | 250 | /** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration |
<> | 144:ef7eb2e8f9f7 | 251 | * @{ |
<> | 144:ef7eb2e8f9f7 | 252 | */ |
<> | 144:ef7eb2e8f9f7 | 253 | #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15) |
<> | 144:ef7eb2e8f9f7 | 254 | /** |
<> | 144:ef7eb2e8f9f7 | 255 | * @} |
<> | 144:ef7eb2e8f9f7 | 256 | */ |
<> | 144:ef7eb2e8f9f7 | 257 | |
<> | 144:ef7eb2e8f9f7 | 258 | /** |
<> | 144:ef7eb2e8f9f7 | 259 | * @} |
<> | 144:ef7eb2e8f9f7 | 260 | */ |
<> | 144:ef7eb2e8f9f7 | 261 | |
<> | 144:ef7eb2e8f9f7 | 262 | /* Exported typedef ----------------------------------------------------------*/ |
AnnaBridge | 167:e84263d55307 | 263 | |
AnnaBridge | 167:e84263d55307 | 264 | /** @defgroup FMC_NORSRAM_Exported_typedef FMC Low Layer Exported Types |
<> | 144:ef7eb2e8f9f7 | 265 | * @{ |
<> | 144:ef7eb2e8f9f7 | 266 | */ |
AnnaBridge | 167:e84263d55307 | 267 | |
<> | 144:ef7eb2e8f9f7 | 268 | #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef |
<> | 144:ef7eb2e8f9f7 | 269 | #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef |
<> | 144:ef7eb2e8f9f7 | 270 | #define FMC_NAND_TypeDef FMC_Bank3_TypeDef |
<> | 144:ef7eb2e8f9f7 | 271 | |
AnnaBridge | 167:e84263d55307 | 272 | #define FMC_NORSRAM_DEVICE FMC_Bank1_R |
AnnaBridge | 167:e84263d55307 | 273 | #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R |
AnnaBridge | 167:e84263d55307 | 274 | #define FMC_NAND_DEVICE FMC_Bank3_R |
<> | 144:ef7eb2e8f9f7 | 275 | |
<> | 144:ef7eb2e8f9f7 | 276 | /** |
<> | 144:ef7eb2e8f9f7 | 277 | * @brief FMC_NORSRAM Configuration Structure definition |
<> | 144:ef7eb2e8f9f7 | 278 | */ |
<> | 144:ef7eb2e8f9f7 | 279 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 280 | { |
<> | 144:ef7eb2e8f9f7 | 281 | uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. |
<> | 144:ef7eb2e8f9f7 | 282 | This parameter can be a value of @ref FMC_NORSRAM_Bank */ |
<> | 144:ef7eb2e8f9f7 | 283 | |
<> | 144:ef7eb2e8f9f7 | 284 | uint32_t DataAddressMux; /*!< Specifies whether the address and data values are |
<> | 144:ef7eb2e8f9f7 | 285 | multiplexed on the data bus or not. |
<> | 144:ef7eb2e8f9f7 | 286 | This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ |
<> | 144:ef7eb2e8f9f7 | 287 | |
<> | 144:ef7eb2e8f9f7 | 288 | uint32_t MemoryType; /*!< Specifies the type of external memory attached to |
<> | 144:ef7eb2e8f9f7 | 289 | the corresponding memory device. |
<> | 144:ef7eb2e8f9f7 | 290 | This parameter can be a value of @ref FMC_Memory_Type */ |
<> | 144:ef7eb2e8f9f7 | 291 | |
<> | 144:ef7eb2e8f9f7 | 292 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
<> | 144:ef7eb2e8f9f7 | 293 | This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ |
<> | 144:ef7eb2e8f9f7 | 294 | |
<> | 144:ef7eb2e8f9f7 | 295 | uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, |
<> | 144:ef7eb2e8f9f7 | 296 | valid only with synchronous burst Flash memories. |
<> | 144:ef7eb2e8f9f7 | 297 | This parameter can be a value of @ref FMC_Burst_Access_Mode */ |
<> | 144:ef7eb2e8f9f7 | 298 | |
<> | 144:ef7eb2e8f9f7 | 299 | uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing |
<> | 144:ef7eb2e8f9f7 | 300 | the Flash memory in burst mode. |
<> | 144:ef7eb2e8f9f7 | 301 | This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ |
<> | 144:ef7eb2e8f9f7 | 302 | |
<> | 144:ef7eb2e8f9f7 | 303 | uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one |
<> | 144:ef7eb2e8f9f7 | 304 | clock cycle before the wait state or during the wait state, |
<> | 144:ef7eb2e8f9f7 | 305 | valid only when accessing memories in burst mode. |
<> | 144:ef7eb2e8f9f7 | 306 | This parameter can be a value of @ref FMC_Wait_Timing */ |
<> | 144:ef7eb2e8f9f7 | 307 | |
<> | 144:ef7eb2e8f9f7 | 308 | uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. |
<> | 144:ef7eb2e8f9f7 | 309 | This parameter can be a value of @ref FMC_Write_Operation */ |
<> | 144:ef7eb2e8f9f7 | 310 | |
<> | 144:ef7eb2e8f9f7 | 311 | uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait |
<> | 144:ef7eb2e8f9f7 | 312 | signal, valid for Flash memory access in burst mode. |
<> | 144:ef7eb2e8f9f7 | 313 | This parameter can be a value of @ref FMC_Wait_Signal */ |
<> | 144:ef7eb2e8f9f7 | 314 | |
<> | 144:ef7eb2e8f9f7 | 315 | uint32_t ExtendedMode; /*!< Enables or disables the extended mode. |
<> | 144:ef7eb2e8f9f7 | 316 | This parameter can be a value of @ref FMC_Extended_Mode */ |
<> | 144:ef7eb2e8f9f7 | 317 | |
<> | 144:ef7eb2e8f9f7 | 318 | uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, |
<> | 144:ef7eb2e8f9f7 | 319 | valid only with asynchronous Flash memories. |
<> | 144:ef7eb2e8f9f7 | 320 | This parameter can be a value of @ref FMC_AsynchronousWait */ |
<> | 144:ef7eb2e8f9f7 | 321 | |
<> | 144:ef7eb2e8f9f7 | 322 | uint32_t WriteBurst; /*!< Enables or disables the write burst operation. |
<> | 144:ef7eb2e8f9f7 | 323 | This parameter can be a value of @ref FMC_Write_Burst */ |
<> | 144:ef7eb2e8f9f7 | 324 | |
<> | 144:ef7eb2e8f9f7 | 325 | uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. |
<> | 144:ef7eb2e8f9f7 | 326 | This parameter is only enabled through the FMC_BCR1 register, and don't care |
<> | 144:ef7eb2e8f9f7 | 327 | through FMC_BCR2..4 registers. |
<> | 144:ef7eb2e8f9f7 | 328 | This parameter can be a value of @ref FMC_Continous_Clock */ |
<> | 144:ef7eb2e8f9f7 | 329 | |
<> | 144:ef7eb2e8f9f7 | 330 | uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. |
<> | 144:ef7eb2e8f9f7 | 331 | This parameter is only enabled through the FMC_BCR1 register, and don't care |
<> | 144:ef7eb2e8f9f7 | 332 | through FMC_BCR2..4 registers. |
<> | 144:ef7eb2e8f9f7 | 333 | This parameter can be a value of @ref FMC_Write_FIFO. |
<> | 144:ef7eb2e8f9f7 | 334 | @note This Parameter is not available for STM32L47x/L48x devices. */ |
<> | 144:ef7eb2e8f9f7 | 335 | |
<> | 144:ef7eb2e8f9f7 | 336 | uint32_t PageSize; /*!< Specifies the memory page size. |
<> | 144:ef7eb2e8f9f7 | 337 | This parameter can be a value of @ref FMC_Page_Size */ |
<> | 144:ef7eb2e8f9f7 | 338 | }FMC_NORSRAM_InitTypeDef; |
<> | 144:ef7eb2e8f9f7 | 339 | |
<> | 144:ef7eb2e8f9f7 | 340 | /** |
<> | 144:ef7eb2e8f9f7 | 341 | * @brief FMC_NORSRAM Timing parameters structure definition |
<> | 144:ef7eb2e8f9f7 | 342 | */ |
<> | 144:ef7eb2e8f9f7 | 343 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 344 | { |
<> | 144:ef7eb2e8f9f7 | 345 | uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure |
<> | 144:ef7eb2e8f9f7 | 346 | the duration of the address setup time. |
<> | 144:ef7eb2e8f9f7 | 347 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
<> | 144:ef7eb2e8f9f7 | 348 | @note This parameter is not used with synchronous NOR Flash memories. */ |
<> | 144:ef7eb2e8f9f7 | 349 | |
<> | 144:ef7eb2e8f9f7 | 350 | uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure |
<> | 144:ef7eb2e8f9f7 | 351 | the duration of the address hold time. |
<> | 144:ef7eb2e8f9f7 | 352 | This parameter can be a value between Min_Data = 1 and Max_Data = 15. |
<> | 144:ef7eb2e8f9f7 | 353 | @note This parameter is not used with synchronous NOR Flash memories. */ |
<> | 144:ef7eb2e8f9f7 | 354 | |
<> | 144:ef7eb2e8f9f7 | 355 | uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure |
<> | 144:ef7eb2e8f9f7 | 356 | the duration of the data setup time. |
<> | 144:ef7eb2e8f9f7 | 357 | This parameter can be a value between Min_Data = 1 and Max_Data = 255. |
<> | 144:ef7eb2e8f9f7 | 358 | @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed |
<> | 144:ef7eb2e8f9f7 | 359 | NOR Flash memories. */ |
<> | 144:ef7eb2e8f9f7 | 360 | |
<> | 144:ef7eb2e8f9f7 | 361 | uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure |
<> | 144:ef7eb2e8f9f7 | 362 | the duration of the bus turnaround. |
<> | 144:ef7eb2e8f9f7 | 363 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
<> | 144:ef7eb2e8f9f7 | 364 | @note This parameter is only used for multiplexed NOR Flash memories. */ |
<> | 144:ef7eb2e8f9f7 | 365 | |
<> | 144:ef7eb2e8f9f7 | 366 | uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of |
<> | 144:ef7eb2e8f9f7 | 367 | HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. |
<> | 144:ef7eb2e8f9f7 | 368 | @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM |
<> | 144:ef7eb2e8f9f7 | 369 | accesses. */ |
<> | 144:ef7eb2e8f9f7 | 370 | |
<> | 144:ef7eb2e8f9f7 | 371 | uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue |
<> | 144:ef7eb2e8f9f7 | 372 | to the memory before getting the first data. |
<> | 144:ef7eb2e8f9f7 | 373 | The parameter value depends on the memory type as shown below: |
<> | 144:ef7eb2e8f9f7 | 374 | - It must be set to 0 in case of a CRAM |
<> | 144:ef7eb2e8f9f7 | 375 | - It is don't care in asynchronous NOR, SRAM or ROM accesses |
<> | 144:ef7eb2e8f9f7 | 376 | - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories |
<> | 144:ef7eb2e8f9f7 | 377 | with synchronous burst mode enable */ |
<> | 144:ef7eb2e8f9f7 | 378 | |
<> | 144:ef7eb2e8f9f7 | 379 | uint32_t AccessMode; /*!< Specifies the asynchronous access mode. |
<> | 144:ef7eb2e8f9f7 | 380 | This parameter can be a value of @ref FMC_Access_Mode */ |
AnnaBridge | 167:e84263d55307 | 381 | |
<> | 144:ef7eb2e8f9f7 | 382 | }FMC_NORSRAM_TimingTypeDef; |
<> | 144:ef7eb2e8f9f7 | 383 | |
<> | 144:ef7eb2e8f9f7 | 384 | /** |
<> | 144:ef7eb2e8f9f7 | 385 | * @brief FMC_NAND Configuration Structure definition |
<> | 144:ef7eb2e8f9f7 | 386 | */ |
<> | 144:ef7eb2e8f9f7 | 387 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 388 | { |
<> | 144:ef7eb2e8f9f7 | 389 | uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. |
<> | 144:ef7eb2e8f9f7 | 390 | This parameter can be a value of @ref FMC_NAND_Bank */ |
<> | 144:ef7eb2e8f9f7 | 391 | |
<> | 144:ef7eb2e8f9f7 | 392 | uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. |
<> | 144:ef7eb2e8f9f7 | 393 | This parameter can be any value of @ref FMC_Wait_feature */ |
<> | 144:ef7eb2e8f9f7 | 394 | |
<> | 144:ef7eb2e8f9f7 | 395 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
<> | 144:ef7eb2e8f9f7 | 396 | This parameter can be any value of @ref FMC_NAND_Data_Width */ |
<> | 144:ef7eb2e8f9f7 | 397 | |
<> | 144:ef7eb2e8f9f7 | 398 | uint32_t EccComputation; /*!< Enables or disables the ECC computation. |
<> | 144:ef7eb2e8f9f7 | 399 | This parameter can be any value of @ref FMC_ECC */ |
<> | 144:ef7eb2e8f9f7 | 400 | |
<> | 144:ef7eb2e8f9f7 | 401 | uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. |
<> | 144:ef7eb2e8f9f7 | 402 | This parameter can be any value of @ref FMC_ECC_Page_Size */ |
<> | 144:ef7eb2e8f9f7 | 403 | |
<> | 144:ef7eb2e8f9f7 | 404 | uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the |
<> | 144:ef7eb2e8f9f7 | 405 | delay between CLE low and RE low. |
<> | 144:ef7eb2e8f9f7 | 406 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
<> | 144:ef7eb2e8f9f7 | 407 | |
<> | 144:ef7eb2e8f9f7 | 408 | uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the |
<> | 144:ef7eb2e8f9f7 | 409 | delay between ALE low and RE low. |
<> | 144:ef7eb2e8f9f7 | 410 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
AnnaBridge | 167:e84263d55307 | 411 | |
<> | 144:ef7eb2e8f9f7 | 412 | }FMC_NAND_InitTypeDef; |
<> | 144:ef7eb2e8f9f7 | 413 | |
<> | 144:ef7eb2e8f9f7 | 414 | /** |
<> | 144:ef7eb2e8f9f7 | 415 | * @brief FMC_NAND Timing parameters structure definition |
<> | 144:ef7eb2e8f9f7 | 416 | */ |
<> | 144:ef7eb2e8f9f7 | 417 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 418 | { |
<> | 144:ef7eb2e8f9f7 | 419 | uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before |
<> | 144:ef7eb2e8f9f7 | 420 | the command assertion for NAND-Flash read or write access |
<> | 144:ef7eb2e8f9f7 | 421 | to common/Attribute or I/O memory space (depending on |
<> | 144:ef7eb2e8f9f7 | 422 | the memory space timing to be configured). |
<> | 144:ef7eb2e8f9f7 | 423 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
<> | 144:ef7eb2e8f9f7 | 424 | |
<> | 144:ef7eb2e8f9f7 | 425 | uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the |
<> | 144:ef7eb2e8f9f7 | 426 | command for NAND-Flash read or write access to |
<> | 144:ef7eb2e8f9f7 | 427 | common/Attribute or I/O memory space (depending on the |
<> | 144:ef7eb2e8f9f7 | 428 | memory space timing to be configured). |
<> | 144:ef7eb2e8f9f7 | 429 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
<> | 144:ef7eb2e8f9f7 | 430 | |
<> | 144:ef7eb2e8f9f7 | 431 | uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address |
<> | 144:ef7eb2e8f9f7 | 432 | (and data for write access) after the command de-assertion |
<> | 144:ef7eb2e8f9f7 | 433 | for NAND-Flash read or write access to common/Attribute |
<> | 144:ef7eb2e8f9f7 | 434 | or I/O memory space (depending on the memory space timing |
<> | 144:ef7eb2e8f9f7 | 435 | to be configured). |
<> | 144:ef7eb2e8f9f7 | 436 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
<> | 144:ef7eb2e8f9f7 | 437 | |
<> | 144:ef7eb2e8f9f7 | 438 | uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the |
<> | 144:ef7eb2e8f9f7 | 439 | data bus is kept in HiZ after the start of a NAND-Flash |
<> | 144:ef7eb2e8f9f7 | 440 | write access to common/Attribute or I/O memory space (depending |
<> | 144:ef7eb2e8f9f7 | 441 | on the memory space timing to be configured). |
<> | 144:ef7eb2e8f9f7 | 442 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
AnnaBridge | 167:e84263d55307 | 443 | |
<> | 144:ef7eb2e8f9f7 | 444 | }FMC_NAND_PCC_TimingTypeDef; |
<> | 144:ef7eb2e8f9f7 | 445 | |
<> | 144:ef7eb2e8f9f7 | 446 | /** |
<> | 144:ef7eb2e8f9f7 | 447 | * @} |
<> | 144:ef7eb2e8f9f7 | 448 | */ |
<> | 144:ef7eb2e8f9f7 | 449 | |
<> | 144:ef7eb2e8f9f7 | 450 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 167:e84263d55307 | 451 | |
AnnaBridge | 167:e84263d55307 | 452 | /** @defgroup FMC_Exported_Constants FMC Low Layer Exported Constants |
<> | 144:ef7eb2e8f9f7 | 453 | * @{ |
<> | 144:ef7eb2e8f9f7 | 454 | */ |
<> | 144:ef7eb2e8f9f7 | 455 | |
AnnaBridge | 167:e84263d55307 | 456 | /** @defgroup FMC_NORSRAM_Exported_constants FMC NOR/SRAM Exported constants |
<> | 144:ef7eb2e8f9f7 | 457 | * @{ |
<> | 144:ef7eb2e8f9f7 | 458 | */ |
<> | 144:ef7eb2e8f9f7 | 459 | |
<> | 144:ef7eb2e8f9f7 | 460 | /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank |
<> | 144:ef7eb2e8f9f7 | 461 | * @{ |
<> | 144:ef7eb2e8f9f7 | 462 | */ |
<> | 144:ef7eb2e8f9f7 | 463 | #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000) |
<> | 144:ef7eb2e8f9f7 | 464 | #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002) |
<> | 144:ef7eb2e8f9f7 | 465 | #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004) |
<> | 144:ef7eb2e8f9f7 | 466 | #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006) |
AnnaBridge | 167:e84263d55307 | 467 | |
<> | 144:ef7eb2e8f9f7 | 468 | /** |
<> | 144:ef7eb2e8f9f7 | 469 | * @} |
<> | 144:ef7eb2e8f9f7 | 470 | */ |
<> | 144:ef7eb2e8f9f7 | 471 | |
<> | 144:ef7eb2e8f9f7 | 472 | /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing |
<> | 144:ef7eb2e8f9f7 | 473 | * @{ |
<> | 144:ef7eb2e8f9f7 | 474 | */ |
AnnaBridge | 167:e84263d55307 | 475 | |
<> | 144:ef7eb2e8f9f7 | 476 | #define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000) |
<> | 144:ef7eb2e8f9f7 | 477 | #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FMC_BCRx_MUXEN) |
AnnaBridge | 167:e84263d55307 | 478 | |
<> | 144:ef7eb2e8f9f7 | 479 | /** |
<> | 144:ef7eb2e8f9f7 | 480 | * @} |
<> | 144:ef7eb2e8f9f7 | 481 | */ |
<> | 144:ef7eb2e8f9f7 | 482 | |
<> | 144:ef7eb2e8f9f7 | 483 | /** @defgroup FMC_Memory_Type FMC Memory Type |
<> | 144:ef7eb2e8f9f7 | 484 | * @{ |
<> | 144:ef7eb2e8f9f7 | 485 | */ |
AnnaBridge | 167:e84263d55307 | 486 | |
<> | 144:ef7eb2e8f9f7 | 487 | #define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000) |
<> | 144:ef7eb2e8f9f7 | 488 | #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)FMC_BCRx_MTYP_0) |
<> | 144:ef7eb2e8f9f7 | 489 | #define FMC_MEMORY_TYPE_NOR ((uint32_t)FMC_BCRx_MTYP_1) |
AnnaBridge | 167:e84263d55307 | 490 | |
<> | 144:ef7eb2e8f9f7 | 491 | /** |
<> | 144:ef7eb2e8f9f7 | 492 | * @} |
<> | 144:ef7eb2e8f9f7 | 493 | */ |
<> | 144:ef7eb2e8f9f7 | 494 | |
AnnaBridge | 167:e84263d55307 | 495 | /** @defgroup FMC_NORSRAM_Data_Width FMC NOR/SRAM Data Width |
<> | 144:ef7eb2e8f9f7 | 496 | * @{ |
<> | 144:ef7eb2e8f9f7 | 497 | */ |
AnnaBridge | 167:e84263d55307 | 498 | |
<> | 144:ef7eb2e8f9f7 | 499 | #define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) |
<> | 144:ef7eb2e8f9f7 | 500 | #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FMC_BCRx_MWID_0) |
<> | 144:ef7eb2e8f9f7 | 501 | #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FMC_BCRx_MWID_1) |
AnnaBridge | 167:e84263d55307 | 502 | |
<> | 144:ef7eb2e8f9f7 | 503 | /** |
<> | 144:ef7eb2e8f9f7 | 504 | * @} |
<> | 144:ef7eb2e8f9f7 | 505 | */ |
<> | 144:ef7eb2e8f9f7 | 506 | |
AnnaBridge | 167:e84263d55307 | 507 | /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access |
<> | 144:ef7eb2e8f9f7 | 508 | * @{ |
<> | 144:ef7eb2e8f9f7 | 509 | */ |
AnnaBridge | 167:e84263d55307 | 510 | |
<> | 144:ef7eb2e8f9f7 | 511 | #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FMC_BCRx_FACCEN) |
<> | 144:ef7eb2e8f9f7 | 512 | #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000) |
<> | 144:ef7eb2e8f9f7 | 513 | /** |
<> | 144:ef7eb2e8f9f7 | 514 | * @} |
<> | 144:ef7eb2e8f9f7 | 515 | */ |
<> | 144:ef7eb2e8f9f7 | 516 | |
<> | 144:ef7eb2e8f9f7 | 517 | /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode |
<> | 144:ef7eb2e8f9f7 | 518 | * @{ |
<> | 144:ef7eb2e8f9f7 | 519 | */ |
AnnaBridge | 167:e84263d55307 | 520 | |
<> | 144:ef7eb2e8f9f7 | 521 | #define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000) |
<> | 144:ef7eb2e8f9f7 | 522 | #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FMC_BCRx_BURSTEN) |
AnnaBridge | 167:e84263d55307 | 523 | |
<> | 144:ef7eb2e8f9f7 | 524 | /** |
<> | 144:ef7eb2e8f9f7 | 525 | * @} |
<> | 144:ef7eb2e8f9f7 | 526 | */ |
<> | 144:ef7eb2e8f9f7 | 527 | |
<> | 144:ef7eb2e8f9f7 | 528 | |
<> | 144:ef7eb2e8f9f7 | 529 | /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity |
<> | 144:ef7eb2e8f9f7 | 530 | * @{ |
<> | 144:ef7eb2e8f9f7 | 531 | */ |
AnnaBridge | 167:e84263d55307 | 532 | |
<> | 144:ef7eb2e8f9f7 | 533 | #define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000) |
<> | 144:ef7eb2e8f9f7 | 534 | #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FMC_BCRx_WAITPOL) |
AnnaBridge | 167:e84263d55307 | 535 | |
AnnaBridge | 167:e84263d55307 | 536 | /** |
AnnaBridge | 167:e84263d55307 | 537 | * @} |
AnnaBridge | 167:e84263d55307 | 538 | */ |
AnnaBridge | 167:e84263d55307 | 539 | |
<> | 144:ef7eb2e8f9f7 | 540 | /** |
<> | 144:ef7eb2e8f9f7 | 541 | * @} |
<> | 144:ef7eb2e8f9f7 | 542 | */ |
<> | 144:ef7eb2e8f9f7 | 543 | |
<> | 144:ef7eb2e8f9f7 | 544 | /** @defgroup FMC_Wait_Timing FMC Wait Timing |
<> | 144:ef7eb2e8f9f7 | 545 | * @{ |
<> | 144:ef7eb2e8f9f7 | 546 | */ |
AnnaBridge | 167:e84263d55307 | 547 | |
<> | 144:ef7eb2e8f9f7 | 548 | #define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000) |
<> | 144:ef7eb2e8f9f7 | 549 | #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)FMC_BCRx_WAITCFG) |
<> | 144:ef7eb2e8f9f7 | 550 | |
<> | 144:ef7eb2e8f9f7 | 551 | /** |
<> | 144:ef7eb2e8f9f7 | 552 | * @} |
<> | 144:ef7eb2e8f9f7 | 553 | */ |
<> | 144:ef7eb2e8f9f7 | 554 | |
<> | 144:ef7eb2e8f9f7 | 555 | /** @defgroup FMC_Write_Operation FMC Write Operation |
<> | 144:ef7eb2e8f9f7 | 556 | * @{ |
<> | 144:ef7eb2e8f9f7 | 557 | */ |
AnnaBridge | 167:e84263d55307 | 558 | |
<> | 144:ef7eb2e8f9f7 | 559 | #define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000) |
<> | 144:ef7eb2e8f9f7 | 560 | #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)FMC_BCRx_WREN) |
AnnaBridge | 167:e84263d55307 | 561 | |
<> | 144:ef7eb2e8f9f7 | 562 | /** |
<> | 144:ef7eb2e8f9f7 | 563 | * @} |
<> | 144:ef7eb2e8f9f7 | 564 | */ |
<> | 144:ef7eb2e8f9f7 | 565 | |
<> | 144:ef7eb2e8f9f7 | 566 | /** @defgroup FMC_Wait_Signal FMC Wait Signal |
<> | 144:ef7eb2e8f9f7 | 567 | * @{ |
<> | 144:ef7eb2e8f9f7 | 568 | */ |
AnnaBridge | 167:e84263d55307 | 569 | |
<> | 144:ef7eb2e8f9f7 | 570 | #define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000) |
<> | 144:ef7eb2e8f9f7 | 571 | #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)FMC_BCRx_WAITEN) |
AnnaBridge | 167:e84263d55307 | 572 | |
<> | 144:ef7eb2e8f9f7 | 573 | /** |
<> | 144:ef7eb2e8f9f7 | 574 | * @} |
<> | 144:ef7eb2e8f9f7 | 575 | */ |
<> | 144:ef7eb2e8f9f7 | 576 | |
<> | 144:ef7eb2e8f9f7 | 577 | /** @defgroup FMC_Extended_Mode FMC Extended Mode |
<> | 144:ef7eb2e8f9f7 | 578 | * @{ |
<> | 144:ef7eb2e8f9f7 | 579 | */ |
AnnaBridge | 167:e84263d55307 | 580 | |
<> | 144:ef7eb2e8f9f7 | 581 | #define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000) |
<> | 144:ef7eb2e8f9f7 | 582 | #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)FMC_BCRx_EXTMOD) |
AnnaBridge | 167:e84263d55307 | 583 | |
<> | 144:ef7eb2e8f9f7 | 584 | /** |
<> | 144:ef7eb2e8f9f7 | 585 | * @} |
<> | 144:ef7eb2e8f9f7 | 586 | */ |
<> | 144:ef7eb2e8f9f7 | 587 | |
<> | 144:ef7eb2e8f9f7 | 588 | /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait |
<> | 144:ef7eb2e8f9f7 | 589 | * @{ |
<> | 144:ef7eb2e8f9f7 | 590 | */ |
AnnaBridge | 167:e84263d55307 | 591 | |
<> | 144:ef7eb2e8f9f7 | 592 | #define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000) |
<> | 144:ef7eb2e8f9f7 | 593 | #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FMC_BCRx_ASYNCWAIT) |
AnnaBridge | 167:e84263d55307 | 594 | |
<> | 144:ef7eb2e8f9f7 | 595 | /** |
<> | 144:ef7eb2e8f9f7 | 596 | * @} |
<> | 144:ef7eb2e8f9f7 | 597 | */ |
<> | 144:ef7eb2e8f9f7 | 598 | |
<> | 144:ef7eb2e8f9f7 | 599 | /** @defgroup FMC_Page_Size FMC Page Size |
<> | 144:ef7eb2e8f9f7 | 600 | * @{ |
<> | 144:ef7eb2e8f9f7 | 601 | */ |
<> | 144:ef7eb2e8f9f7 | 602 | #define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000) |
<> | 144:ef7eb2e8f9f7 | 603 | #define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCRx_CPSIZE_0) |
<> | 144:ef7eb2e8f9f7 | 604 | #define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCRx_CPSIZE_1) |
<> | 144:ef7eb2e8f9f7 | 605 | #define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCRx_CPSIZE_0 | FMC_BCRx_CPSIZE_1)) |
<> | 144:ef7eb2e8f9f7 | 606 | #define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCRx_CPSIZE_2) |
<> | 144:ef7eb2e8f9f7 | 607 | /** |
<> | 144:ef7eb2e8f9f7 | 608 | * @} |
<> | 144:ef7eb2e8f9f7 | 609 | */ |
<> | 144:ef7eb2e8f9f7 | 610 | |
<> | 144:ef7eb2e8f9f7 | 611 | /** @defgroup FMC_Write_Burst FMC Write Burst |
<> | 144:ef7eb2e8f9f7 | 612 | * @{ |
<> | 144:ef7eb2e8f9f7 | 613 | */ |
AnnaBridge | 167:e84263d55307 | 614 | |
<> | 144:ef7eb2e8f9f7 | 615 | #define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000) |
<> | 144:ef7eb2e8f9f7 | 616 | #define FMC_WRITE_BURST_ENABLE ((uint32_t)FMC_BCRx_CBURSTRW) |
AnnaBridge | 167:e84263d55307 | 617 | |
<> | 144:ef7eb2e8f9f7 | 618 | /** |
<> | 144:ef7eb2e8f9f7 | 619 | * @} |
<> | 144:ef7eb2e8f9f7 | 620 | */ |
<> | 144:ef7eb2e8f9f7 | 621 | |
<> | 144:ef7eb2e8f9f7 | 622 | /** @defgroup FMC_Continous_Clock FMC Continous Clock |
<> | 144:ef7eb2e8f9f7 | 623 | * @{ |
<> | 144:ef7eb2e8f9f7 | 624 | */ |
<> | 144:ef7eb2e8f9f7 | 625 | #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000) |
<> | 144:ef7eb2e8f9f7 | 626 | #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)FMC_BCR1_CCLKEN) |
<> | 144:ef7eb2e8f9f7 | 627 | /** |
<> | 144:ef7eb2e8f9f7 | 628 | * @} |
<> | 144:ef7eb2e8f9f7 | 629 | */ |
<> | 144:ef7eb2e8f9f7 | 630 | |
AnnaBridge | 167:e84263d55307 | 631 | #if defined(FMC_BCR1_WFDIS) |
AnnaBridge | 167:e84263d55307 | 632 | /** @defgroup FMC_Write_FIFO FMC Write FIFO |
AnnaBridge | 167:e84263d55307 | 633 | * @{ |
AnnaBridge | 167:e84263d55307 | 634 | */ |
AnnaBridge | 167:e84263d55307 | 635 | #define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS) |
AnnaBridge | 167:e84263d55307 | 636 | #define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000) |
AnnaBridge | 167:e84263d55307 | 637 | /** |
AnnaBridge | 167:e84263d55307 | 638 | * @} |
AnnaBridge | 167:e84263d55307 | 639 | */ |
AnnaBridge | 167:e84263d55307 | 640 | |
AnnaBridge | 167:e84263d55307 | 641 | #endif /* FMC_BCR1_WFDIS */ |
<> | 144:ef7eb2e8f9f7 | 642 | /** @defgroup FMC_Access_Mode FMC Access Mode |
<> | 144:ef7eb2e8f9f7 | 643 | * @{ |
<> | 144:ef7eb2e8f9f7 | 644 | */ |
AnnaBridge | 167:e84263d55307 | 645 | |
AnnaBridge | 167:e84263d55307 | 646 | #define FMC_ACCESS_MODE_A ((uint32_t)0x00000000) |
AnnaBridge | 167:e84263d55307 | 647 | #define FMC_ACCESS_MODE_B ((uint32_t)FMC_BTRx_ACCMOD_0) |
AnnaBridge | 167:e84263d55307 | 648 | #define FMC_ACCESS_MODE_C ((uint32_t)FMC_BTRx_ACCMOD_1) |
AnnaBridge | 167:e84263d55307 | 649 | #define FMC_ACCESS_MODE_D ((uint32_t)(FMC_BTRx_ACCMOD_0 | FMC_BTRx_ACCMOD_1)) |
<> | 144:ef7eb2e8f9f7 | 650 | |
<> | 144:ef7eb2e8f9f7 | 651 | /** |
<> | 144:ef7eb2e8f9f7 | 652 | * @} |
<> | 144:ef7eb2e8f9f7 | 653 | */ |
<> | 144:ef7eb2e8f9f7 | 654 | |
<> | 144:ef7eb2e8f9f7 | 655 | /** |
<> | 144:ef7eb2e8f9f7 | 656 | * @} |
<> | 144:ef7eb2e8f9f7 | 657 | */ |
<> | 144:ef7eb2e8f9f7 | 658 | |
AnnaBridge | 167:e84263d55307 | 659 | /** @defgroup FMC_NAND_Controller FMC NAND and PCCARD Controller |
<> | 144:ef7eb2e8f9f7 | 660 | * @{ |
<> | 144:ef7eb2e8f9f7 | 661 | */ |
<> | 144:ef7eb2e8f9f7 | 662 | |
<> | 144:ef7eb2e8f9f7 | 663 | /** @defgroup FMC_NAND_Bank FMC NAND Bank |
<> | 144:ef7eb2e8f9f7 | 664 | * @{ |
<> | 144:ef7eb2e8f9f7 | 665 | */ |
<> | 144:ef7eb2e8f9f7 | 666 | #define FMC_NAND_BANK3 ((uint32_t)0x00000100) |
AnnaBridge | 167:e84263d55307 | 667 | |
<> | 144:ef7eb2e8f9f7 | 668 | /** |
<> | 144:ef7eb2e8f9f7 | 669 | * @} |
<> | 144:ef7eb2e8f9f7 | 670 | */ |
<> | 144:ef7eb2e8f9f7 | 671 | |
<> | 144:ef7eb2e8f9f7 | 672 | /** @defgroup FMC_Wait_feature FMC Wait feature |
<> | 144:ef7eb2e8f9f7 | 673 | * @{ |
<> | 144:ef7eb2e8f9f7 | 674 | */ |
<> | 144:ef7eb2e8f9f7 | 675 | #define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000) |
<> | 144:ef7eb2e8f9f7 | 676 | #define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)FMC_PCR_PWAITEN) |
AnnaBridge | 167:e84263d55307 | 677 | |
<> | 144:ef7eb2e8f9f7 | 678 | /** |
<> | 144:ef7eb2e8f9f7 | 679 | * @} |
<> | 144:ef7eb2e8f9f7 | 680 | */ |
<> | 144:ef7eb2e8f9f7 | 681 | |
<> | 144:ef7eb2e8f9f7 | 682 | /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type |
<> | 144:ef7eb2e8f9f7 | 683 | * @{ |
<> | 144:ef7eb2e8f9f7 | 684 | */ |
AnnaBridge | 167:e84263d55307 | 685 | #define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)FMC_PCR_PTYP) |
<> | 144:ef7eb2e8f9f7 | 686 | /** |
<> | 144:ef7eb2e8f9f7 | 687 | * @} |
<> | 144:ef7eb2e8f9f7 | 688 | */ |
<> | 144:ef7eb2e8f9f7 | 689 | |
<> | 144:ef7eb2e8f9f7 | 690 | /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width |
<> | 144:ef7eb2e8f9f7 | 691 | * @{ |
<> | 144:ef7eb2e8f9f7 | 692 | */ |
<> | 144:ef7eb2e8f9f7 | 693 | #define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) |
<> | 144:ef7eb2e8f9f7 | 694 | #define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)FMC_PCR_PWID_0) |
AnnaBridge | 167:e84263d55307 | 695 | |
<> | 144:ef7eb2e8f9f7 | 696 | /** |
<> | 144:ef7eb2e8f9f7 | 697 | * @} |
<> | 144:ef7eb2e8f9f7 | 698 | */ |
<> | 144:ef7eb2e8f9f7 | 699 | |
<> | 144:ef7eb2e8f9f7 | 700 | /** @defgroup FMC_ECC FMC NAND ECC |
<> | 144:ef7eb2e8f9f7 | 701 | * @{ |
<> | 144:ef7eb2e8f9f7 | 702 | */ |
<> | 144:ef7eb2e8f9f7 | 703 | #define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000) |
<> | 144:ef7eb2e8f9f7 | 704 | #define FMC_NAND_ECC_ENABLE ((uint32_t)FMC_PCR_ECCEN) |
AnnaBridge | 167:e84263d55307 | 705 | |
<> | 144:ef7eb2e8f9f7 | 706 | /** |
<> | 144:ef7eb2e8f9f7 | 707 | * @} |
<> | 144:ef7eb2e8f9f7 | 708 | */ |
<> | 144:ef7eb2e8f9f7 | 709 | |
AnnaBridge | 167:e84263d55307 | 710 | /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size |
<> | 144:ef7eb2e8f9f7 | 711 | * @{ |
<> | 144:ef7eb2e8f9f7 | 712 | */ |
<> | 144:ef7eb2e8f9f7 | 713 | #define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000) |
<> | 144:ef7eb2e8f9f7 | 714 | #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)FMC_PCR_ECCPS_0) |
<> | 144:ef7eb2e8f9f7 | 715 | #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)FMC_PCR_ECCPS_1) |
<> | 144:ef7eb2e8f9f7 | 716 | #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)FMC_PCR_ECCPS_0|FMC_PCR_ECCPS_1) |
<> | 144:ef7eb2e8f9f7 | 717 | #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)FMC_PCR_ECCPS_2) |
<> | 144:ef7eb2e8f9f7 | 718 | #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)FMC_PCR_ECCPS_0|FMC_PCR_ECCPS_2) |
<> | 144:ef7eb2e8f9f7 | 719 | |
<> | 144:ef7eb2e8f9f7 | 720 | /** |
<> | 144:ef7eb2e8f9f7 | 721 | * @} |
<> | 144:ef7eb2e8f9f7 | 722 | */ |
<> | 144:ef7eb2e8f9f7 | 723 | |
<> | 144:ef7eb2e8f9f7 | 724 | /** @defgroup FMC_Interrupt_definition FMC Interrupt definition |
<> | 144:ef7eb2e8f9f7 | 725 | * @brief FMC Interrupt definition |
<> | 144:ef7eb2e8f9f7 | 726 | * @{ |
<> | 144:ef7eb2e8f9f7 | 727 | */ |
AnnaBridge | 167:e84263d55307 | 728 | #define FMC_IT_RISING_EDGE ((uint32_t)FMC_SR_IREN) |
AnnaBridge | 167:e84263d55307 | 729 | #define FMC_IT_LEVEL ((uint32_t)FMC_SR_ILEN) |
AnnaBridge | 167:e84263d55307 | 730 | #define FMC_IT_FALLING_EDGE ((uint32_t)FMC_SR_IFEN) |
AnnaBridge | 167:e84263d55307 | 731 | |
<> | 144:ef7eb2e8f9f7 | 732 | /** |
<> | 144:ef7eb2e8f9f7 | 733 | * @} |
<> | 144:ef7eb2e8f9f7 | 734 | */ |
<> | 144:ef7eb2e8f9f7 | 735 | |
<> | 144:ef7eb2e8f9f7 | 736 | /** @defgroup FMC_Flag_definition FMC Flag definition |
<> | 144:ef7eb2e8f9f7 | 737 | * @brief FMC Flag definition |
<> | 144:ef7eb2e8f9f7 | 738 | * @{ |
<> | 144:ef7eb2e8f9f7 | 739 | */ |
<> | 144:ef7eb2e8f9f7 | 740 | #define FMC_FLAG_RISING_EDGE ((uint32_t)FMC_SR_IRS) |
<> | 144:ef7eb2e8f9f7 | 741 | #define FMC_FLAG_LEVEL ((uint32_t)FMC_SR_ILS) |
<> | 144:ef7eb2e8f9f7 | 742 | #define FMC_FLAG_FALLING_EDGE ((uint32_t)FMC_SR_IFS) |
<> | 144:ef7eb2e8f9f7 | 743 | #define FMC_FLAG_FEMPT ((uint32_t)FMC_SR_FEMPT) |
AnnaBridge | 167:e84263d55307 | 744 | |
AnnaBridge | 167:e84263d55307 | 745 | /** |
AnnaBridge | 167:e84263d55307 | 746 | * @} |
AnnaBridge | 167:e84263d55307 | 747 | */ |
AnnaBridge | 167:e84263d55307 | 748 | |
AnnaBridge | 167:e84263d55307 | 749 | /** |
AnnaBridge | 167:e84263d55307 | 750 | * @} |
AnnaBridge | 167:e84263d55307 | 751 | */ |
AnnaBridge | 167:e84263d55307 | 752 | |
<> | 144:ef7eb2e8f9f7 | 753 | /** |
<> | 144:ef7eb2e8f9f7 | 754 | * @} |
<> | 144:ef7eb2e8f9f7 | 755 | */ |
<> | 144:ef7eb2e8f9f7 | 756 | |
<> | 144:ef7eb2e8f9f7 | 757 | /* Exported macro ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 758 | |
<> | 144:ef7eb2e8f9f7 | 759 | /** @defgroup FMC_Exported_Macros FMC Low Layer Exported Macros |
<> | 144:ef7eb2e8f9f7 | 760 | * @{ |
<> | 144:ef7eb2e8f9f7 | 761 | */ |
<> | 144:ef7eb2e8f9f7 | 762 | |
<> | 144:ef7eb2e8f9f7 | 763 | /** @defgroup FMC_NOR_Macros FMC NOR/SRAM Exported Macros |
<> | 144:ef7eb2e8f9f7 | 764 | * @brief macros to handle NOR device enable/disable and read/write operations |
<> | 144:ef7eb2e8f9f7 | 765 | * @{ |
<> | 144:ef7eb2e8f9f7 | 766 | */ |
<> | 144:ef7eb2e8f9f7 | 767 | |
<> | 144:ef7eb2e8f9f7 | 768 | /** |
<> | 144:ef7eb2e8f9f7 | 769 | * @brief Enable the NORSRAM device access. |
AnnaBridge | 167:e84263d55307 | 770 | * @param __INSTANCE__ FMC_NORSRAM Instance |
AnnaBridge | 167:e84263d55307 | 771 | * @param __BANK__ FMC_NORSRAM Bank |
<> | 144:ef7eb2e8f9f7 | 772 | * @retval none |
<> | 144:ef7eb2e8f9f7 | 773 | */ |
<> | 144:ef7eb2e8f9f7 | 774 | #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN) |
<> | 144:ef7eb2e8f9f7 | 775 | |
<> | 144:ef7eb2e8f9f7 | 776 | /** |
<> | 144:ef7eb2e8f9f7 | 777 | * @brief Disable the NORSRAM device access. |
AnnaBridge | 167:e84263d55307 | 778 | * @param __INSTANCE__ FMC_NORSRAM Instance |
AnnaBridge | 167:e84263d55307 | 779 | * @param __BANK__ FMC_NORSRAM Bank |
<> | 144:ef7eb2e8f9f7 | 780 | * @retval none |
<> | 144:ef7eb2e8f9f7 | 781 | */ |
<> | 144:ef7eb2e8f9f7 | 782 | #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN) |
<> | 144:ef7eb2e8f9f7 | 783 | |
<> | 144:ef7eb2e8f9f7 | 784 | /** |
<> | 144:ef7eb2e8f9f7 | 785 | * @} |
<> | 144:ef7eb2e8f9f7 | 786 | */ |
<> | 144:ef7eb2e8f9f7 | 787 | |
<> | 144:ef7eb2e8f9f7 | 788 | /** @defgroup FMC_NAND_Macros FMC NAND Macros |
<> | 144:ef7eb2e8f9f7 | 789 | * @brief macros to handle NAND device enable/disable |
<> | 144:ef7eb2e8f9f7 | 790 | * @{ |
<> | 144:ef7eb2e8f9f7 | 791 | */ |
<> | 144:ef7eb2e8f9f7 | 792 | |
<> | 144:ef7eb2e8f9f7 | 793 | /** |
<> | 144:ef7eb2e8f9f7 | 794 | * @brief Enable the NAND device access. |
AnnaBridge | 167:e84263d55307 | 795 | * @param __INSTANCE__ FMC_NAND Instance |
AnnaBridge | 167:e84263d55307 | 796 | * @param __BANK__ FMC_NAND Bank |
AnnaBridge | 167:e84263d55307 | 797 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 798 | */ |
<> | 144:ef7eb2e8f9f7 | 799 | #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) |
<> | 144:ef7eb2e8f9f7 | 800 | |
<> | 144:ef7eb2e8f9f7 | 801 | /** |
<> | 144:ef7eb2e8f9f7 | 802 | * @brief Disable the NAND device access. |
AnnaBridge | 167:e84263d55307 | 803 | * @param __INSTANCE__ FMC_NAND Instance |
AnnaBridge | 167:e84263d55307 | 804 | * @param __BANK__ FMC_NAND Bank |
<> | 144:ef7eb2e8f9f7 | 805 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 806 | */ |
<> | 144:ef7eb2e8f9f7 | 807 | #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) |
<> | 144:ef7eb2e8f9f7 | 808 | |
<> | 144:ef7eb2e8f9f7 | 809 | /** |
<> | 144:ef7eb2e8f9f7 | 810 | * @} |
<> | 144:ef7eb2e8f9f7 | 811 | */ |
<> | 144:ef7eb2e8f9f7 | 812 | |
<> | 144:ef7eb2e8f9f7 | 813 | /** @defgroup FMC_Interrupt FMC Interrupt |
<> | 144:ef7eb2e8f9f7 | 814 | * @brief macros to handle FMC interrupts |
<> | 144:ef7eb2e8f9f7 | 815 | * @{ |
<> | 144:ef7eb2e8f9f7 | 816 | */ |
<> | 144:ef7eb2e8f9f7 | 817 | |
<> | 144:ef7eb2e8f9f7 | 818 | /** |
<> | 144:ef7eb2e8f9f7 | 819 | * @brief Enable the NAND device interrupt. |
AnnaBridge | 167:e84263d55307 | 820 | * @param __INSTANCE__ FMC_NAND Instance |
AnnaBridge | 167:e84263d55307 | 821 | * @param __BANK__ FMC_NAND Bank |
AnnaBridge | 167:e84263d55307 | 822 | * @param __INTERRUPT__ FMC_NAND interrupt |
<> | 144:ef7eb2e8f9f7 | 823 | * This parameter can be any combination of the following values: |
AnnaBridge | 167:e84263d55307 | 824 | * @arg FMC_IT_RISING_EDGE Interrupt rising edge. |
AnnaBridge | 167:e84263d55307 | 825 | * @arg FMC_IT_LEVEL Interrupt level. |
AnnaBridge | 167:e84263d55307 | 826 | * @arg FMC_IT_FALLING_EDGE Interrupt falling edge. |
<> | 144:ef7eb2e8f9f7 | 827 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 828 | */ |
<> | 144:ef7eb2e8f9f7 | 829 | #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) SET_BIT((__INSTANCE__)->SR, (__INTERRUPT__)) |
<> | 144:ef7eb2e8f9f7 | 830 | |
<> | 144:ef7eb2e8f9f7 | 831 | /** |
<> | 144:ef7eb2e8f9f7 | 832 | * @brief Disable the NAND device interrupt. |
AnnaBridge | 167:e84263d55307 | 833 | * @param __INSTANCE__ FMC_NAND Instance |
AnnaBridge | 167:e84263d55307 | 834 | * @param __BANK__ FMC_NAND Bank |
AnnaBridge | 167:e84263d55307 | 835 | * @param __INTERRUPT__ FMC_NAND interrupt |
<> | 144:ef7eb2e8f9f7 | 836 | * This parameter can be any combination of the following values: |
AnnaBridge | 167:e84263d55307 | 837 | * @arg FMC_IT_RISING_EDGE Interrupt rising edge. |
AnnaBridge | 167:e84263d55307 | 838 | * @arg FMC_IT_LEVEL Interrupt level. |
AnnaBridge | 167:e84263d55307 | 839 | * @arg FMC_IT_FALLING_EDGE Interrupt falling edge. |
<> | 144:ef7eb2e8f9f7 | 840 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 841 | */ |
<> | 144:ef7eb2e8f9f7 | 842 | #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->SR, (__INTERRUPT__)) |
<> | 144:ef7eb2e8f9f7 | 843 | |
<> | 144:ef7eb2e8f9f7 | 844 | /** |
<> | 144:ef7eb2e8f9f7 | 845 | * @brief Get flag status of the NAND device. |
AnnaBridge | 167:e84263d55307 | 846 | * @param __INSTANCE__ FMC_NAND Instance |
AnnaBridge | 167:e84263d55307 | 847 | * @param __BANK__ FMC_NAND Bank |
AnnaBridge | 167:e84263d55307 | 848 | * @param __FLAG__ FMC_NAND flag |
<> | 144:ef7eb2e8f9f7 | 849 | * This parameter can be any combination of the following values: |
AnnaBridge | 167:e84263d55307 | 850 | * @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag. |
AnnaBridge | 167:e84263d55307 | 851 | * @arg FMC_FLAG_LEVEL Interrupt level edge flag. |
AnnaBridge | 167:e84263d55307 | 852 | * @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag. |
AnnaBridge | 167:e84263d55307 | 853 | * @arg FMC_FLAG_FEMPT FIFO empty flag. |
<> | 144:ef7eb2e8f9f7 | 854 | * @retval The state of FLAG (SET or RESET). |
<> | 144:ef7eb2e8f9f7 | 855 | */ |
<> | 144:ef7eb2e8f9f7 | 856 | #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__)) |
<> | 144:ef7eb2e8f9f7 | 857 | |
<> | 144:ef7eb2e8f9f7 | 858 | /** |
<> | 144:ef7eb2e8f9f7 | 859 | * @brief Clear flag status of the NAND device. |
AnnaBridge | 167:e84263d55307 | 860 | * @param __INSTANCE__ FMC_NAND Instance |
AnnaBridge | 167:e84263d55307 | 861 | * @param __BANK__ FMC_NAND Bank |
AnnaBridge | 167:e84263d55307 | 862 | * @param __FLAG__ FMC_NAND flag |
<> | 144:ef7eb2e8f9f7 | 863 | * This parameter can be any combination of the following values: |
AnnaBridge | 167:e84263d55307 | 864 | * @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag. |
AnnaBridge | 167:e84263d55307 | 865 | * @arg FMC_FLAG_LEVEL Interrupt level edge flag. |
AnnaBridge | 167:e84263d55307 | 866 | * @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag. |
AnnaBridge | 167:e84263d55307 | 867 | * @arg FMC_FLAG_FEMPT FIFO empty flag. |
<> | 144:ef7eb2e8f9f7 | 868 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 869 | */ |
<> | 144:ef7eb2e8f9f7 | 870 | #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) CLEAR_BIT((__INSTANCE__)->SR, (__FLAG__)) |
<> | 144:ef7eb2e8f9f7 | 871 | |
AnnaBridge | 167:e84263d55307 | 872 | /** |
AnnaBridge | 167:e84263d55307 | 873 | * @} |
AnnaBridge | 167:e84263d55307 | 874 | */ |
AnnaBridge | 167:e84263d55307 | 875 | |
AnnaBridge | 167:e84263d55307 | 876 | |
AnnaBridge | 167:e84263d55307 | 877 | /** |
AnnaBridge | 167:e84263d55307 | 878 | * @} |
AnnaBridge | 167:e84263d55307 | 879 | */ |
<> | 144:ef7eb2e8f9f7 | 880 | |
<> | 144:ef7eb2e8f9f7 | 881 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 167:e84263d55307 | 882 | |
AnnaBridge | 167:e84263d55307 | 883 | /** @addtogroup FMC_LL_Exported_Functions |
AnnaBridge | 167:e84263d55307 | 884 | * @{ |
AnnaBridge | 167:e84263d55307 | 885 | */ |
<> | 144:ef7eb2e8f9f7 | 886 | |
AnnaBridge | 167:e84263d55307 | 887 | /** @addtogroup FMC_NORSRAM |
AnnaBridge | 167:e84263d55307 | 888 | * @{ |
AnnaBridge | 167:e84263d55307 | 889 | */ |
AnnaBridge | 167:e84263d55307 | 890 | |
AnnaBridge | 167:e84263d55307 | 891 | /** @addtogroup FMC_NORSRAM_Group1 |
AnnaBridge | 167:e84263d55307 | 892 | * @{ |
AnnaBridge | 167:e84263d55307 | 893 | */ |
AnnaBridge | 167:e84263d55307 | 894 | |
AnnaBridge | 167:e84263d55307 | 895 | /* FMC_NORSRAM Controller functions ******************************************/ |
<> | 144:ef7eb2e8f9f7 | 896 | /* Initialization/de-initialization functions */ |
<> | 144:ef7eb2e8f9f7 | 897 | HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init); |
<> | 144:ef7eb2e8f9f7 | 898 | HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); |
<> | 144:ef7eb2e8f9f7 | 899 | HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); |
<> | 144:ef7eb2e8f9f7 | 900 | HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); |
AnnaBridge | 167:e84263d55307 | 901 | |
<> | 144:ef7eb2e8f9f7 | 902 | /** |
<> | 144:ef7eb2e8f9f7 | 903 | * @} |
<> | 144:ef7eb2e8f9f7 | 904 | */ |
<> | 144:ef7eb2e8f9f7 | 905 | |
AnnaBridge | 167:e84263d55307 | 906 | /** @addtogroup FMC_NORSRAM_Group2 |
AnnaBridge | 167:e84263d55307 | 907 | * @{ |
AnnaBridge | 167:e84263d55307 | 908 | */ |
AnnaBridge | 167:e84263d55307 | 909 | |
<> | 144:ef7eb2e8f9f7 | 910 | /* FMC_NORSRAM Control functions */ |
<> | 144:ef7eb2e8f9f7 | 911 | HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
<> | 144:ef7eb2e8f9f7 | 912 | HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
AnnaBridge | 167:e84263d55307 | 913 | |
AnnaBridge | 167:e84263d55307 | 914 | /** |
AnnaBridge | 167:e84263d55307 | 915 | * @} |
AnnaBridge | 167:e84263d55307 | 916 | */ |
AnnaBridge | 167:e84263d55307 | 917 | |
<> | 144:ef7eb2e8f9f7 | 918 | /** |
<> | 144:ef7eb2e8f9f7 | 919 | * @} |
<> | 144:ef7eb2e8f9f7 | 920 | */ |
<> | 144:ef7eb2e8f9f7 | 921 | |
AnnaBridge | 167:e84263d55307 | 922 | /** @addtogroup FMC_NAND |
AnnaBridge | 167:e84263d55307 | 923 | * @{ |
AnnaBridge | 167:e84263d55307 | 924 | */ |
AnnaBridge | 167:e84263d55307 | 925 | |
<> | 144:ef7eb2e8f9f7 | 926 | /* FMC_NAND Controller functions **********************************************/ |
<> | 144:ef7eb2e8f9f7 | 927 | /* Initialization/de-initialization functions */ |
AnnaBridge | 167:e84263d55307 | 928 | /** @addtogroup FMC_NAND_Exported_Functions_Group1 |
AnnaBridge | 167:e84263d55307 | 929 | * @{ |
AnnaBridge | 167:e84263d55307 | 930 | */ |
AnnaBridge | 167:e84263d55307 | 931 | |
<> | 144:ef7eb2e8f9f7 | 932 | HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); |
<> | 144:ef7eb2e8f9f7 | 933 | HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); |
<> | 144:ef7eb2e8f9f7 | 934 | HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); |
<> | 144:ef7eb2e8f9f7 | 935 | HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); |
AnnaBridge | 167:e84263d55307 | 936 | |
<> | 144:ef7eb2e8f9f7 | 937 | /** |
<> | 144:ef7eb2e8f9f7 | 938 | * @} |
<> | 144:ef7eb2e8f9f7 | 939 | */ |
<> | 144:ef7eb2e8f9f7 | 940 | |
<> | 144:ef7eb2e8f9f7 | 941 | /* FMC_NAND Control functions */ |
AnnaBridge | 167:e84263d55307 | 942 | /** @addtogroup FMC_NAND_Exported_Functions_Group2 |
AnnaBridge | 167:e84263d55307 | 943 | * @{ |
AnnaBridge | 167:e84263d55307 | 944 | */ |
AnnaBridge | 167:e84263d55307 | 945 | |
<> | 144:ef7eb2e8f9f7 | 946 | HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); |
<> | 144:ef7eb2e8f9f7 | 947 | HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); |
<> | 144:ef7eb2e8f9f7 | 948 | HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); |
AnnaBridge | 167:e84263d55307 | 949 | |
<> | 144:ef7eb2e8f9f7 | 950 | /** |
<> | 144:ef7eb2e8f9f7 | 951 | * @} |
<> | 144:ef7eb2e8f9f7 | 952 | */ |
<> | 144:ef7eb2e8f9f7 | 953 | |
<> | 144:ef7eb2e8f9f7 | 954 | /** |
<> | 144:ef7eb2e8f9f7 | 955 | * @} |
<> | 144:ef7eb2e8f9f7 | 956 | */ |
<> | 144:ef7eb2e8f9f7 | 957 | |
<> | 144:ef7eb2e8f9f7 | 958 | /** |
<> | 144:ef7eb2e8f9f7 | 959 | * @} |
<> | 144:ef7eb2e8f9f7 | 960 | */ |
<> | 144:ef7eb2e8f9f7 | 961 | |
<> | 144:ef7eb2e8f9f7 | 962 | /** |
<> | 144:ef7eb2e8f9f7 | 963 | * @} |
<> | 144:ef7eb2e8f9f7 | 964 | */ |
<> | 144:ef7eb2e8f9f7 | 965 | |
AnnaBridge | 167:e84263d55307 | 966 | #endif /* FMC_BANK1 */ |
AnnaBridge | 167:e84263d55307 | 967 | |
AnnaBridge | 167:e84263d55307 | 968 | /** |
AnnaBridge | 167:e84263d55307 | 969 | * @} |
AnnaBridge | 167:e84263d55307 | 970 | */ |
<> | 144:ef7eb2e8f9f7 | 971 | |
<> | 144:ef7eb2e8f9f7 | 972 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 973 | } |
<> | 144:ef7eb2e8f9f7 | 974 | #endif |
<> | 144:ef7eb2e8f9f7 | 975 | |
<> | 144:ef7eb2e8f9f7 | 976 | #endif /* __STM32L4xx_LL_FMC_H */ |
<> | 144:ef7eb2e8f9f7 | 977 | |
<> | 144:ef7eb2e8f9f7 | 978 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
AnnaBridge | 167:e84263d55307 | 979 |