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targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smbus.h@0:9b334a45a8ff, 2015-10-01 (annotated)
- Committer:
- bogdanm
- Date:
- Thu Oct 01 15:25:22 2015 +0300
- Revision:
- 0:9b334a45a8ff
- Child:
- 113:b3775bf36a83
Initial commit on mbed-dev
Replaces mbed-src (now inactive)
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 0:9b334a45a8ff | 1 | /** |
| bogdanm | 0:9b334a45a8ff | 2 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 3 | * @file stm32l0xx_hal_smbus.h |
| bogdanm | 0:9b334a45a8ff | 4 | * @author MCD Application Team |
| bogdanm | 0:9b334a45a8ff | 5 | * @version V1.2.0 |
| bogdanm | 0:9b334a45a8ff | 6 | * @date 06-February-2015 |
| bogdanm | 0:9b334a45a8ff | 7 | * @brief Header file of SMBUS HAL module. |
| bogdanm | 0:9b334a45a8ff | 8 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 9 | * @attention |
| bogdanm | 0:9b334a45a8ff | 10 | * |
| bogdanm | 0:9b334a45a8ff | 11 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| bogdanm | 0:9b334a45a8ff | 12 | * |
| bogdanm | 0:9b334a45a8ff | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 0:9b334a45a8ff | 14 | * are permitted provided that the following conditions are met: |
| bogdanm | 0:9b334a45a8ff | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 16 | * this list of conditions and the following disclaimer. |
| bogdanm | 0:9b334a45a8ff | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 18 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 0:9b334a45a8ff | 19 | * and/or other materials provided with the distribution. |
| bogdanm | 0:9b334a45a8ff | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 0:9b334a45a8ff | 21 | * may be used to endorse or promote products derived from this software |
| bogdanm | 0:9b334a45a8ff | 22 | * without specific prior written permission. |
| bogdanm | 0:9b334a45a8ff | 23 | * |
| bogdanm | 0:9b334a45a8ff | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 0:9b334a45a8ff | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 0:9b334a45a8ff | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 0:9b334a45a8ff | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 0:9b334a45a8ff | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 0:9b334a45a8ff | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 0:9b334a45a8ff | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 0:9b334a45a8ff | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 0:9b334a45a8ff | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 0:9b334a45a8ff | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 0:9b334a45a8ff | 34 | * |
| bogdanm | 0:9b334a45a8ff | 35 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 36 | */ |
| bogdanm | 0:9b334a45a8ff | 37 | |
| bogdanm | 0:9b334a45a8ff | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 39 | #ifndef __STM32L0xx_HAL_SMBUS_H |
| bogdanm | 0:9b334a45a8ff | 40 | #define __STM32L0xx_HAL_SMBUS_H |
| bogdanm | 0:9b334a45a8ff | 41 | |
| bogdanm | 0:9b334a45a8ff | 42 | #ifdef __cplusplus |
| bogdanm | 0:9b334a45a8ff | 43 | extern "C" { |
| bogdanm | 0:9b334a45a8ff | 44 | #endif |
| bogdanm | 0:9b334a45a8ff | 45 | |
| bogdanm | 0:9b334a45a8ff | 46 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 47 | #include "stm32l0xx_hal_def.h" |
| bogdanm | 0:9b334a45a8ff | 48 | |
| bogdanm | 0:9b334a45a8ff | 49 | /** @addtogroup STM32L0xx_HAL_Driver |
| bogdanm | 0:9b334a45a8ff | 50 | * @{ |
| bogdanm | 0:9b334a45a8ff | 51 | */ |
| bogdanm | 0:9b334a45a8ff | 52 | |
| bogdanm | 0:9b334a45a8ff | 53 | /** @addtogroup SMBUS |
| bogdanm | 0:9b334a45a8ff | 54 | * @{ |
| bogdanm | 0:9b334a45a8ff | 55 | */ |
| bogdanm | 0:9b334a45a8ff | 56 | |
| bogdanm | 0:9b334a45a8ff | 57 | /* Exported types ------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 58 | |
| bogdanm | 0:9b334a45a8ff | 59 | /** |
| bogdanm | 0:9b334a45a8ff | 60 | * @brief SMBUS Configuration Structure definition |
| bogdanm | 0:9b334a45a8ff | 61 | */ |
| bogdanm | 0:9b334a45a8ff | 62 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 63 | { |
| bogdanm | 0:9b334a45a8ff | 64 | uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. |
| bogdanm | 0:9b334a45a8ff | 65 | This parameter calculated by referring to SMBUS initialization |
| bogdanm | 0:9b334a45a8ff | 66 | section in Reference manual */ |
| bogdanm | 0:9b334a45a8ff | 67 | |
| bogdanm | 0:9b334a45a8ff | 68 | uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. |
| bogdanm | 0:9b334a45a8ff | 69 | This parameter can be a a value of @ref SMBUS_Analog_Filter */ |
| bogdanm | 0:9b334a45a8ff | 70 | |
| bogdanm | 0:9b334a45a8ff | 71 | uint32_t OwnAddress1; /*!< Specifies the first device own address. |
| bogdanm | 0:9b334a45a8ff | 72 | This parameter can be a 7-bit or 10-bit address. */ |
| bogdanm | 0:9b334a45a8ff | 73 | |
| bogdanm | 0:9b334a45a8ff | 74 | uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected. |
| bogdanm | 0:9b334a45a8ff | 75 | This parameter can be a value of @ref SMBUS_addressing_mode */ |
| bogdanm | 0:9b334a45a8ff | 76 | |
| bogdanm | 0:9b334a45a8ff | 77 | uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. |
| bogdanm | 0:9b334a45a8ff | 78 | This parameter can be a value of @ref SMBUS_dual_addressing_mode */ |
| bogdanm | 0:9b334a45a8ff | 79 | |
| bogdanm | 0:9b334a45a8ff | 80 | uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected |
| bogdanm | 0:9b334a45a8ff | 81 | This parameter can be a 7-bit address. */ |
| bogdanm | 0:9b334a45a8ff | 82 | |
| bogdanm | 0:9b334a45a8ff | 83 | uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected |
| bogdanm | 0:9b334a45a8ff | 84 | This parameter can be a value of @ref SMBUS_own_address2_masks */ |
| bogdanm | 0:9b334a45a8ff | 85 | |
| bogdanm | 0:9b334a45a8ff | 86 | uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. |
| bogdanm | 0:9b334a45a8ff | 87 | This parameter can be a value of @ref SMBUS_general_call_addressing_mode */ |
| bogdanm | 0:9b334a45a8ff | 88 | |
| bogdanm | 0:9b334a45a8ff | 89 | uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. |
| bogdanm | 0:9b334a45a8ff | 90 | This parameter can be a value of @ref SMBUS_nostretch_mode */ |
| bogdanm | 0:9b334a45a8ff | 91 | |
| bogdanm | 0:9b334a45a8ff | 92 | uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. |
| bogdanm | 0:9b334a45a8ff | 93 | This parameter can be a value of @ref SMBUS_packet_error_check_mode */ |
| bogdanm | 0:9b334a45a8ff | 94 | |
| bogdanm | 0:9b334a45a8ff | 95 | uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. |
| bogdanm | 0:9b334a45a8ff | 96 | This parameter can be a value of @ref SMBUS_peripheral_mode */ |
| bogdanm | 0:9b334a45a8ff | 97 | |
| bogdanm | 0:9b334a45a8ff | 98 | uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. |
| bogdanm | 0:9b334a45a8ff | 99 | (Enable bits and different timeout values) |
| bogdanm | 0:9b334a45a8ff | 100 | This parameter calculated by referring to SMBUS initialization |
| bogdanm | 0:9b334a45a8ff | 101 | section in Reference manual */ |
| bogdanm | 0:9b334a45a8ff | 102 | } SMBUS_InitTypeDef; |
| bogdanm | 0:9b334a45a8ff | 103 | |
| bogdanm | 0:9b334a45a8ff | 104 | /** @defgroup SMBUS_State SMBUS State |
| bogdanm | 0:9b334a45a8ff | 105 | * @brief HAL States definition |
| bogdanm | 0:9b334a45a8ff | 106 | * @{ |
| bogdanm | 0:9b334a45a8ff | 107 | */ |
| bogdanm | 0:9b334a45a8ff | 108 | |
| bogdanm | 0:9b334a45a8ff | 109 | #define HAL_SMBUS_STATE_RESET 0x00 /*!< SMBUS not yet initialized or disabled */ |
| bogdanm | 0:9b334a45a8ff | 110 | #define HAL_SMBUS_STATE_READY 0x01 /*!< SMBUS initialized and ready for use */ |
| bogdanm | 0:9b334a45a8ff | 111 | #define HAL_SMBUS_STATE_BUSY 0x02 /*!< SMBUS internal process is ongoing */ |
| bogdanm | 0:9b334a45a8ff | 112 | #define HAL_SMBUS_STATE_MASTER_BUSY_TX 0x12 /*!< Master Data Transmission process is ongoing */ |
| bogdanm | 0:9b334a45a8ff | 113 | #define HAL_SMBUS_STATE_MASTER_BUSY_RX 0x22 /*!< Master Data Reception process is ongoing */ |
| bogdanm | 0:9b334a45a8ff | 114 | #define HAL_SMBUS_STATE_SLAVE_BUSY_TX 0x32 /*!< Slave Data Transmission process is ongoing */ |
| bogdanm | 0:9b334a45a8ff | 115 | #define HAL_SMBUS_STATE_SLAVE_BUSY_RX 0x42 /*!< Slave Data Reception process is ongoing */ |
| bogdanm | 0:9b334a45a8ff | 116 | #define HAL_SMBUS_STATE_TIMEOUT 0x03 /*!< Timeout state */ |
| bogdanm | 0:9b334a45a8ff | 117 | #define HAL_SMBUS_STATE_ERROR 0x04 /*!< Reception process is ongoing */ |
| bogdanm | 0:9b334a45a8ff | 118 | #define HAL_SMBUS_STATE_LISTEN 0x08 /*!< Address Listen Mode is ongoing */ |
| bogdanm | 0:9b334a45a8ff | 119 | /** |
| bogdanm | 0:9b334a45a8ff | 120 | * @} |
| bogdanm | 0:9b334a45a8ff | 121 | */ |
| bogdanm | 0:9b334a45a8ff | 122 | |
| bogdanm | 0:9b334a45a8ff | 123 | /** @defgroup SMBUS_Error_Code SMBUS Error Code |
| bogdanm | 0:9b334a45a8ff | 124 | * @brief SMBUS Error Code |
| bogdanm | 0:9b334a45a8ff | 125 | * @{ |
| bogdanm | 0:9b334a45a8ff | 126 | */ |
| bogdanm | 0:9b334a45a8ff | 127 | #define HAL_SMBUS_ERROR_NONE 0x00 /*!< No error */ |
| bogdanm | 0:9b334a45a8ff | 128 | #define HAL_SMBUS_ERROR_BERR 0x01 /*!< BERR error */ |
| bogdanm | 0:9b334a45a8ff | 129 | #define HAL_SMBUS_ERROR_ARLO 0x02 /*!< ARLO error */ |
| bogdanm | 0:9b334a45a8ff | 130 | #define HAL_SMBUS_ERROR_ACKF 0x04 /*!< ACKF error */ |
| bogdanm | 0:9b334a45a8ff | 131 | #define HAL_SMBUS_ERROR_OVR 0x08 /*!< OVR error */ |
| bogdanm | 0:9b334a45a8ff | 132 | #define HAL_SMBUS_ERROR_HALTIMEOUT 0x10 /*!< Timeout error */ |
| bogdanm | 0:9b334a45a8ff | 133 | #define HAL_SMBUS_ERROR_BUSTIMEOUT 0x20 /*!< Bus Timeout error */ |
| bogdanm | 0:9b334a45a8ff | 134 | #define HAL_SMBUS_ERROR_ALERT 0x40 /*!< Alert error */ |
| bogdanm | 0:9b334a45a8ff | 135 | #define HAL_SMBUS_ERROR_PECERR 0x80 /*!< PEC error */ |
| bogdanm | 0:9b334a45a8ff | 136 | /** |
| bogdanm | 0:9b334a45a8ff | 137 | * @} |
| bogdanm | 0:9b334a45a8ff | 138 | */ |
| bogdanm | 0:9b334a45a8ff | 139 | |
| bogdanm | 0:9b334a45a8ff | 140 | /** |
| bogdanm | 0:9b334a45a8ff | 141 | * @brief SMBUS handle Structure definition |
| bogdanm | 0:9b334a45a8ff | 142 | */ |
| bogdanm | 0:9b334a45a8ff | 143 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 144 | { |
| bogdanm | 0:9b334a45a8ff | 145 | I2C_TypeDef *Instance; /*!< SMBUS registers base address */ |
| bogdanm | 0:9b334a45a8ff | 146 | |
| bogdanm | 0:9b334a45a8ff | 147 | SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */ |
| bogdanm | 0:9b334a45a8ff | 148 | |
| bogdanm | 0:9b334a45a8ff | 149 | uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */ |
| bogdanm | 0:9b334a45a8ff | 150 | |
| bogdanm | 0:9b334a45a8ff | 151 | uint16_t XferSize; /*!< SMBUS transfer size */ |
| bogdanm | 0:9b334a45a8ff | 152 | |
| bogdanm | 0:9b334a45a8ff | 153 | __IO uint16_t XferCount; /*!< SMBUS transfer counter */ |
| bogdanm | 0:9b334a45a8ff | 154 | |
| bogdanm | 0:9b334a45a8ff | 155 | __IO uint32_t XferOptions; /*!< SMBUS transfer options */ |
| bogdanm | 0:9b334a45a8ff | 156 | |
| bogdanm | 0:9b334a45a8ff | 157 | __IO uint32_t PreviousState; /*!< SMBUS communication Previous tate */ |
| bogdanm | 0:9b334a45a8ff | 158 | |
| bogdanm | 0:9b334a45a8ff | 159 | HAL_LockTypeDef Lock; /*!< SMBUS locking object */ |
| bogdanm | 0:9b334a45a8ff | 160 | |
| bogdanm | 0:9b334a45a8ff | 161 | __IO uint32_t State; /*!< SMBUS communication state */ |
| bogdanm | 0:9b334a45a8ff | 162 | |
| bogdanm | 0:9b334a45a8ff | 163 | __IO uint32_t ErrorCode; /*!< SMBUS Error code , see SMBUS_Error_Code */ |
| bogdanm | 0:9b334a45a8ff | 164 | |
| bogdanm | 0:9b334a45a8ff | 165 | }SMBUS_HandleTypeDef; |
| bogdanm | 0:9b334a45a8ff | 166 | |
| bogdanm | 0:9b334a45a8ff | 167 | /* Exported constants --------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 168 | |
| bogdanm | 0:9b334a45a8ff | 169 | /** @defgroup SMBUS_Exported_Constants |
| bogdanm | 0:9b334a45a8ff | 170 | * @{ |
| bogdanm | 0:9b334a45a8ff | 171 | */ |
| bogdanm | 0:9b334a45a8ff | 172 | |
| bogdanm | 0:9b334a45a8ff | 173 | /** @defgroup SMBUS_Analog_Filter |
| bogdanm | 0:9b334a45a8ff | 174 | * @{ |
| bogdanm | 0:9b334a45a8ff | 175 | */ |
| bogdanm | 0:9b334a45a8ff | 176 | #define SMBUS_ANALOGFILTER_ENABLE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 177 | #define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF |
| bogdanm | 0:9b334a45a8ff | 178 | |
| bogdanm | 0:9b334a45a8ff | 179 | #define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 180 | ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) |
| bogdanm | 0:9b334a45a8ff | 181 | /** |
| bogdanm | 0:9b334a45a8ff | 182 | * @} |
| bogdanm | 0:9b334a45a8ff | 183 | */ |
| bogdanm | 0:9b334a45a8ff | 184 | |
| bogdanm | 0:9b334a45a8ff | 185 | /** @defgroup SMBUS_addressing_mode |
| bogdanm | 0:9b334a45a8ff | 186 | * @{ |
| bogdanm | 0:9b334a45a8ff | 187 | */ |
| bogdanm | 0:9b334a45a8ff | 188 | #define SMBUS_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001) |
| bogdanm | 0:9b334a45a8ff | 189 | #define SMBUS_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002) |
| bogdanm | 0:9b334a45a8ff | 190 | |
| bogdanm | 0:9b334a45a8ff | 191 | #define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \ |
| bogdanm | 0:9b334a45a8ff | 192 | ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) |
| bogdanm | 0:9b334a45a8ff | 193 | /** |
| bogdanm | 0:9b334a45a8ff | 194 | * @} |
| bogdanm | 0:9b334a45a8ff | 195 | */ |
| bogdanm | 0:9b334a45a8ff | 196 | |
| bogdanm | 0:9b334a45a8ff | 197 | /** @defgroup SMBUS_dual_addressing_mode |
| bogdanm | 0:9b334a45a8ff | 198 | * @{ |
| bogdanm | 0:9b334a45a8ff | 199 | */ |
| bogdanm | 0:9b334a45a8ff | 200 | |
| bogdanm | 0:9b334a45a8ff | 201 | #define SMBUS_DUALADDRESS_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 202 | #define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN |
| bogdanm | 0:9b334a45a8ff | 203 | |
| bogdanm | 0:9b334a45a8ff | 204 | #define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 205 | ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) |
| bogdanm | 0:9b334a45a8ff | 206 | /** |
| bogdanm | 0:9b334a45a8ff | 207 | * @} |
| bogdanm | 0:9b334a45a8ff | 208 | */ |
| bogdanm | 0:9b334a45a8ff | 209 | |
| bogdanm | 0:9b334a45a8ff | 210 | /** @defgroup SMBUS_own_address2_masks |
| bogdanm | 0:9b334a45a8ff | 211 | * @{ |
| bogdanm | 0:9b334a45a8ff | 212 | */ |
| bogdanm | 0:9b334a45a8ff | 213 | |
| bogdanm | 0:9b334a45a8ff | 214 | #define SMBUS_OA2_NOMASK ((uint8_t)0x00) |
| bogdanm | 0:9b334a45a8ff | 215 | #define SMBUS_OA2_MASK01 ((uint8_t)0x01) |
| bogdanm | 0:9b334a45a8ff | 216 | #define SMBUS_OA2_MASK02 ((uint8_t)0x02) |
| bogdanm | 0:9b334a45a8ff | 217 | #define SMBUS_OA2_MASK03 ((uint8_t)0x03) |
| bogdanm | 0:9b334a45a8ff | 218 | #define SMBUS_OA2_MASK04 ((uint8_t)0x04) |
| bogdanm | 0:9b334a45a8ff | 219 | #define SMBUS_OA2_MASK05 ((uint8_t)0x05) |
| bogdanm | 0:9b334a45a8ff | 220 | #define SMBUS_OA2_MASK06 ((uint8_t)0x06) |
| bogdanm | 0:9b334a45a8ff | 221 | #define SMBUS_OA2_MASK07 ((uint8_t)0x07) |
| bogdanm | 0:9b334a45a8ff | 222 | |
| bogdanm | 0:9b334a45a8ff | 223 | #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \ |
| bogdanm | 0:9b334a45a8ff | 224 | ((MASK) == SMBUS_OA2_MASK01) || \ |
| bogdanm | 0:9b334a45a8ff | 225 | ((MASK) == SMBUS_OA2_MASK02) || \ |
| bogdanm | 0:9b334a45a8ff | 226 | ((MASK) == SMBUS_OA2_MASK03) || \ |
| bogdanm | 0:9b334a45a8ff | 227 | ((MASK) == SMBUS_OA2_MASK04) || \ |
| bogdanm | 0:9b334a45a8ff | 228 | ((MASK) == SMBUS_OA2_MASK05) || \ |
| bogdanm | 0:9b334a45a8ff | 229 | ((MASK) == SMBUS_OA2_MASK06) || \ |
| bogdanm | 0:9b334a45a8ff | 230 | ((MASK) == SMBUS_OA2_MASK07)) |
| bogdanm | 0:9b334a45a8ff | 231 | /** |
| bogdanm | 0:9b334a45a8ff | 232 | * @} |
| bogdanm | 0:9b334a45a8ff | 233 | */ |
| bogdanm | 0:9b334a45a8ff | 234 | |
| bogdanm | 0:9b334a45a8ff | 235 | |
| bogdanm | 0:9b334a45a8ff | 236 | /** @defgroup SMBUS_general_call_addressing_mode |
| bogdanm | 0:9b334a45a8ff | 237 | * @{ |
| bogdanm | 0:9b334a45a8ff | 238 | */ |
| bogdanm | 0:9b334a45a8ff | 239 | #define SMBUS_GENERALCALL_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 240 | #define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN |
| bogdanm | 0:9b334a45a8ff | 241 | |
| bogdanm | 0:9b334a45a8ff | 242 | #define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 243 | ((CALL) == SMBUS_GENERALCALL_ENABLE)) |
| bogdanm | 0:9b334a45a8ff | 244 | /** |
| bogdanm | 0:9b334a45a8ff | 245 | * @} |
| bogdanm | 0:9b334a45a8ff | 246 | */ |
| bogdanm | 0:9b334a45a8ff | 247 | |
| bogdanm | 0:9b334a45a8ff | 248 | /** @defgroup SMBUS_nostretch_mode |
| bogdanm | 0:9b334a45a8ff | 249 | * @{ |
| bogdanm | 0:9b334a45a8ff | 250 | */ |
| bogdanm | 0:9b334a45a8ff | 251 | #define SMBUS_NOSTRETCH_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 252 | #define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH |
| bogdanm | 0:9b334a45a8ff | 253 | |
| bogdanm | 0:9b334a45a8ff | 254 | #define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 255 | ((STRETCH) == SMBUS_NOSTRETCH_ENABLE)) |
| bogdanm | 0:9b334a45a8ff | 256 | /** |
| bogdanm | 0:9b334a45a8ff | 257 | * @} |
| bogdanm | 0:9b334a45a8ff | 258 | */ |
| bogdanm | 0:9b334a45a8ff | 259 | |
| bogdanm | 0:9b334a45a8ff | 260 | /** @defgroup SMBUS_packet_error_check_mode |
| bogdanm | 0:9b334a45a8ff | 261 | * @{ |
| bogdanm | 0:9b334a45a8ff | 262 | */ |
| bogdanm | 0:9b334a45a8ff | 263 | #define SMBUS_PEC_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 264 | #define SMBUS_PEC_ENABLE I2C_CR1_PECEN |
| bogdanm | 0:9b334a45a8ff | 265 | |
| bogdanm | 0:9b334a45a8ff | 266 | #define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 267 | ((PEC) == SMBUS_PEC_ENABLE)) |
| bogdanm | 0:9b334a45a8ff | 268 | /** |
| bogdanm | 0:9b334a45a8ff | 269 | * @} |
| bogdanm | 0:9b334a45a8ff | 270 | */ |
| bogdanm | 0:9b334a45a8ff | 271 | |
| bogdanm | 0:9b334a45a8ff | 272 | /** @defgroup SMBUS_peripheral_mode |
| bogdanm | 0:9b334a45a8ff | 273 | * @{ |
| bogdanm | 0:9b334a45a8ff | 274 | */ |
| bogdanm | 0:9b334a45a8ff | 275 | #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBHEN) |
| bogdanm | 0:9b334a45a8ff | 276 | #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (uint32_t)(0x00000000) |
| bogdanm | 0:9b334a45a8ff | 277 | #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP (uint32_t)(I2C_CR1_SMBDEN) |
| bogdanm | 0:9b334a45a8ff | 278 | |
| bogdanm | 0:9b334a45a8ff | 279 | #define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ |
| bogdanm | 0:9b334a45a8ff | 280 | ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ |
| bogdanm | 0:9b334a45a8ff | 281 | ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) |
| bogdanm | 0:9b334a45a8ff | 282 | /** |
| bogdanm | 0:9b334a45a8ff | 283 | * @} |
| bogdanm | 0:9b334a45a8ff | 284 | */ |
| bogdanm | 0:9b334a45a8ff | 285 | |
| bogdanm | 0:9b334a45a8ff | 286 | /** @defgroup SMBUS_ReloadEndMode_definition |
| bogdanm | 0:9b334a45a8ff | 287 | * @{ |
| bogdanm | 0:9b334a45a8ff | 288 | */ |
| bogdanm | 0:9b334a45a8ff | 289 | |
| bogdanm | 0:9b334a45a8ff | 290 | #define SMBUS_SOFTEND_MODE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 291 | #define SMBUS_RELOAD_MODE I2C_CR2_RELOAD |
| bogdanm | 0:9b334a45a8ff | 292 | #define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND |
| bogdanm | 0:9b334a45a8ff | 293 | #define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE |
| bogdanm | 0:9b334a45a8ff | 294 | |
| bogdanm | 0:9b334a45a8ff | 295 | #define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ |
| bogdanm | 0:9b334a45a8ff | 296 | ((MODE) == SMBUS_AUTOEND_MODE) || \ |
| bogdanm | 0:9b334a45a8ff | 297 | ((MODE) == SMBUS_SOFTEND_MODE) || \ |
| bogdanm | 0:9b334a45a8ff | 298 | ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ |
| bogdanm | 0:9b334a45a8ff | 299 | ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ |
| bogdanm | 0:9b334a45a8ff | 300 | ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE ))) |
| bogdanm | 0:9b334a45a8ff | 301 | |
| bogdanm | 0:9b334a45a8ff | 302 | /** |
| bogdanm | 0:9b334a45a8ff | 303 | * @} |
| bogdanm | 0:9b334a45a8ff | 304 | */ |
| bogdanm | 0:9b334a45a8ff | 305 | |
| bogdanm | 0:9b334a45a8ff | 306 | /** @defgroup SMBUS_StartStopMode_definition |
| bogdanm | 0:9b334a45a8ff | 307 | * @{ |
| bogdanm | 0:9b334a45a8ff | 308 | */ |
| bogdanm | 0:9b334a45a8ff | 309 | |
| bogdanm | 0:9b334a45a8ff | 310 | #define SMBUS_NO_STARTSTOP ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 311 | #define SMBUS_GENERATE_STOP I2C_CR2_STOP |
| bogdanm | 0:9b334a45a8ff | 312 | #define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) |
| bogdanm | 0:9b334a45a8ff | 313 | #define SMBUS_GENERATE_START_WRITE I2C_CR2_START |
| bogdanm | 0:9b334a45a8ff | 314 | |
| bogdanm | 0:9b334a45a8ff | 315 | #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ |
| bogdanm | 0:9b334a45a8ff | 316 | ((REQUEST) == SMBUS_GENERATE_START_READ) || \ |
| bogdanm | 0:9b334a45a8ff | 317 | ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ |
| bogdanm | 0:9b334a45a8ff | 318 | ((REQUEST) == SMBUS_NO_STARTSTOP)) |
| bogdanm | 0:9b334a45a8ff | 319 | /** |
| bogdanm | 0:9b334a45a8ff | 320 | * @} |
| bogdanm | 0:9b334a45a8ff | 321 | */ |
| bogdanm | 0:9b334a45a8ff | 322 | |
| bogdanm | 0:9b334a45a8ff | 323 | /** @defgroup SMBUS_XferOptions_definition |
| bogdanm | 0:9b334a45a8ff | 324 | * @{ |
| bogdanm | 0:9b334a45a8ff | 325 | */ |
| bogdanm | 0:9b334a45a8ff | 326 | |
| bogdanm | 0:9b334a45a8ff | 327 | #define SMBUS_FIRST_FRAME ((uint32_t)(SMBUS_SOFTEND_MODE)) |
| bogdanm | 0:9b334a45a8ff | 328 | #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) |
| bogdanm | 0:9b334a45a8ff | 329 | #define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE |
| bogdanm | 0:9b334a45a8ff | 330 | #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE |
| bogdanm | 0:9b334a45a8ff | 331 | #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) |
| bogdanm | 0:9b334a45a8ff | 332 | #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) |
| bogdanm | 0:9b334a45a8ff | 333 | |
| bogdanm | 0:9b334a45a8ff | 334 | #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \ |
| bogdanm | 0:9b334a45a8ff | 335 | ((REQUEST) == SMBUS_NEXT_FRAME) || \ |
| bogdanm | 0:9b334a45a8ff | 336 | ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ |
| bogdanm | 0:9b334a45a8ff | 337 | ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ |
| bogdanm | 0:9b334a45a8ff | 338 | ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ |
| bogdanm | 0:9b334a45a8ff | 339 | ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) |
| bogdanm | 0:9b334a45a8ff | 340 | |
| bogdanm | 0:9b334a45a8ff | 341 | /** |
| bogdanm | 0:9b334a45a8ff | 342 | * @} |
| bogdanm | 0:9b334a45a8ff | 343 | */ |
| bogdanm | 0:9b334a45a8ff | 344 | |
| bogdanm | 0:9b334a45a8ff | 345 | /** @defgroup SMBUS_Interrupt_configuration_definition |
| bogdanm | 0:9b334a45a8ff | 346 | * @brief SMBUS Interrupt definition |
| bogdanm | 0:9b334a45a8ff | 347 | * Elements values convention: 0xXXXXXXXX |
| bogdanm | 0:9b334a45a8ff | 348 | * - XXXXXXXX : Interrupt control mask |
| bogdanm | 0:9b334a45a8ff | 349 | * @{ |
| bogdanm | 0:9b334a45a8ff | 350 | */ |
| bogdanm | 0:9b334a45a8ff | 351 | #define SMBUS_IT_ERRI I2C_CR1_ERRIE |
| bogdanm | 0:9b334a45a8ff | 352 | #define SMBUS_IT_TCI I2C_CR1_TCIE |
| bogdanm | 0:9b334a45a8ff | 353 | #define SMBUS_IT_STOPI I2C_CR1_STOPIE |
| bogdanm | 0:9b334a45a8ff | 354 | #define SMBUS_IT_NACKI I2C_CR1_NACKIE |
| bogdanm | 0:9b334a45a8ff | 355 | #define SMBUS_IT_ADDRI I2C_CR1_ADDRIE |
| bogdanm | 0:9b334a45a8ff | 356 | #define SMBUS_IT_RXI I2C_CR1_RXIE |
| bogdanm | 0:9b334a45a8ff | 357 | #define SMBUS_IT_TXI I2C_CR1_TXIE |
| bogdanm | 0:9b334a45a8ff | 358 | #define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI) |
| bogdanm | 0:9b334a45a8ff | 359 | #define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI) |
| bogdanm | 0:9b334a45a8ff | 360 | #define SMBUS_IT_ALERT (SMBUS_IT_ERRI) |
| bogdanm | 0:9b334a45a8ff | 361 | #define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) |
| bogdanm | 0:9b334a45a8ff | 362 | /** |
| bogdanm | 0:9b334a45a8ff | 363 | * @} |
| bogdanm | 0:9b334a45a8ff | 364 | */ |
| bogdanm | 0:9b334a45a8ff | 365 | |
| bogdanm | 0:9b334a45a8ff | 366 | /** @defgroup SMBUS_Flag_definition |
| bogdanm | 0:9b334a45a8ff | 367 | * @brief Flag definition |
| bogdanm | 0:9b334a45a8ff | 368 | * Elements values convention: 0xXXXXYYYY |
| bogdanm | 0:9b334a45a8ff | 369 | * - XXXXXXXX : Flag mask |
| bogdanm | 0:9b334a45a8ff | 370 | * @{ |
| bogdanm | 0:9b334a45a8ff | 371 | */ |
| bogdanm | 0:9b334a45a8ff | 372 | |
| bogdanm | 0:9b334a45a8ff | 373 | #define SMBUS_FLAG_TXE I2C_ISR_TXE |
| bogdanm | 0:9b334a45a8ff | 374 | #define SMBUS_FLAG_TXIS I2C_ISR_TXIS |
| bogdanm | 0:9b334a45a8ff | 375 | #define SMBUS_FLAG_RXNE I2C_ISR_RXNE |
| bogdanm | 0:9b334a45a8ff | 376 | #define SMBUS_FLAG_ADDR I2C_ISR_ADDR |
| bogdanm | 0:9b334a45a8ff | 377 | #define SMBUS_FLAG_AF I2C_ISR_NACKF |
| bogdanm | 0:9b334a45a8ff | 378 | #define SMBUS_FLAG_STOPF I2C_ISR_STOPF |
| bogdanm | 0:9b334a45a8ff | 379 | #define SMBUS_FLAG_TC I2C_ISR_TC |
| bogdanm | 0:9b334a45a8ff | 380 | #define SMBUS_FLAG_TCR I2C_ISR_TCR |
| bogdanm | 0:9b334a45a8ff | 381 | #define SMBUS_FLAG_BERR I2C_ISR_BERR |
| bogdanm | 0:9b334a45a8ff | 382 | #define SMBUS_FLAG_ARLO I2C_ISR_ARLO |
| bogdanm | 0:9b334a45a8ff | 383 | #define SMBUS_FLAG_OVR I2C_ISR_OVR |
| bogdanm | 0:9b334a45a8ff | 384 | #define SMBUS_FLAG_PECERR I2C_ISR_PECERR |
| bogdanm | 0:9b334a45a8ff | 385 | #define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT |
| bogdanm | 0:9b334a45a8ff | 386 | #define SMBUS_FLAG_ALERT I2C_ISR_ALERT |
| bogdanm | 0:9b334a45a8ff | 387 | #define SMBUS_FLAG_BUSY I2C_ISR_BUSY |
| bogdanm | 0:9b334a45a8ff | 388 | #define SMBUS_FLAG_DIR I2C_ISR_DIR |
| bogdanm | 0:9b334a45a8ff | 389 | /** |
| bogdanm | 0:9b334a45a8ff | 390 | * @} |
| bogdanm | 0:9b334a45a8ff | 391 | */ |
| bogdanm | 0:9b334a45a8ff | 392 | |
| bogdanm | 0:9b334a45a8ff | 393 | /** |
| bogdanm | 0:9b334a45a8ff | 394 | * @} |
| bogdanm | 0:9b334a45a8ff | 395 | */ |
| bogdanm | 0:9b334a45a8ff | 396 | |
| bogdanm | 0:9b334a45a8ff | 397 | /* Exported macro ------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 398 | |
| bogdanm | 0:9b334a45a8ff | 399 | /** @brief Reset SMBUS handle state |
| bogdanm | 0:9b334a45a8ff | 400 | * @param __HANDLE__: specifies the SMBUS Handle. |
| bogdanm | 0:9b334a45a8ff | 401 | * This parameter can be SMBUSx where x: 1 or 2 to select the SMBUS peripheral. |
| bogdanm | 0:9b334a45a8ff | 402 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 403 | */ |
| bogdanm | 0:9b334a45a8ff | 404 | #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) |
| bogdanm | 0:9b334a45a8ff | 405 | |
| bogdanm | 0:9b334a45a8ff | 406 | /** @brief Enable or disable the specified SMBUS interrupts. |
| bogdanm | 0:9b334a45a8ff | 407 | * @param __HANDLE__: specifies the SMBUS Handle. |
| bogdanm | 0:9b334a45a8ff | 408 | * This parameter can be SMBUSx where x: 1 or 2 to select the SMBUS peripheral. |
| bogdanm | 0:9b334a45a8ff | 409 | * @param __INTERRUPT__: specifies the interrupt source to enable or disable. |
| bogdanm | 0:9b334a45a8ff | 410 | * This parameter can be one of the following values: |
| bogdanm | 0:9b334a45a8ff | 411 | * @arg SMBUS_IT_ERRI: Errors interrupt enable |
| bogdanm | 0:9b334a45a8ff | 412 | * @arg SMBUS_IT_TCI: Transfer complete interrupt enable |
| bogdanm | 0:9b334a45a8ff | 413 | * @arg SMBUS_IT_STOPI: STOP detection interrupt enable |
| bogdanm | 0:9b334a45a8ff | 414 | * @arg SMBUS_IT_NACKI: NACK received interrupt enable |
| bogdanm | 0:9b334a45a8ff | 415 | * @arg SMBUS_IT_ADDRI: Address match interrupt enable |
| bogdanm | 0:9b334a45a8ff | 416 | * @arg SMBUS_IT_RXI: RX interrupt enable |
| bogdanm | 0:9b334a45a8ff | 417 | * @arg SMBUS_IT_TXI: TX interrupt enable |
| bogdanm | 0:9b334a45a8ff | 418 | * |
| bogdanm | 0:9b334a45a8ff | 419 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 420 | */ |
| bogdanm | 0:9b334a45a8ff | 421 | |
| bogdanm | 0:9b334a45a8ff | 422 | #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) |
| bogdanm | 0:9b334a45a8ff | 423 | #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) |
| bogdanm | 0:9b334a45a8ff | 424 | |
| bogdanm | 0:9b334a45a8ff | 425 | /** @brief Checks if the specified SMBUS interrupt source is enabled or disabled. |
| bogdanm | 0:9b334a45a8ff | 426 | * @param __HANDLE__: specifies the SMBUS Handle. |
| bogdanm | 0:9b334a45a8ff | 427 | * This parameter can be SMBUSx where x: 1 or 2 to select the SMBUS peripheral. |
| bogdanm | 0:9b334a45a8ff | 428 | * @param __INTERRUPT__: specifies the SMBUS interrupt source to check. |
| bogdanm | 0:9b334a45a8ff | 429 | * This parameter can be one of the following values: |
| bogdanm | 0:9b334a45a8ff | 430 | * @arg SMBUS_IT_ERRI: Errors interrupt enable |
| bogdanm | 0:9b334a45a8ff | 431 | * @arg SMBUS_IT_TCI: Transfer complete interrupt enable |
| bogdanm | 0:9b334a45a8ff | 432 | * @arg SMBUS_IT_STOPI: STOP detection interrupt enable |
| bogdanm | 0:9b334a45a8ff | 433 | * @arg SMBUS_IT_NACKI: NACK received interrupt enable |
| bogdanm | 0:9b334a45a8ff | 434 | * @arg SMBUS_IT_ADDRI: Address match interrupt enable |
| bogdanm | 0:9b334a45a8ff | 435 | * @arg SMBUS_IT_RXI: RX interrupt enable |
| bogdanm | 0:9b334a45a8ff | 436 | * @arg SMBUS_IT_TXI: TX interrupt enable |
| bogdanm | 0:9b334a45a8ff | 437 | * |
| bogdanm | 0:9b334a45a8ff | 438 | * @retval The new state of __IT__ (TRUE or FALSE). |
| bogdanm | 0:9b334a45a8ff | 439 | */ |
| bogdanm | 0:9b334a45a8ff | 440 | #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
| bogdanm | 0:9b334a45a8ff | 441 | |
| bogdanm | 0:9b334a45a8ff | 442 | /** @brief Checks whether the specified SMBUS flag is set or not. |
| bogdanm | 0:9b334a45a8ff | 443 | * @param __HANDLE__: specifies the SMBUS Handle. |
| bogdanm | 0:9b334a45a8ff | 444 | * This parameter can be SMBUSx where x: 1 or 2 to select the SMBUS peripheral. |
| bogdanm | 0:9b334a45a8ff | 445 | * @param __FLAG__: specifies the flag to check. |
| bogdanm | 0:9b334a45a8ff | 446 | * This parameter can be one of the following values: |
| bogdanm | 0:9b334a45a8ff | 447 | * @arg SMBUS_FLAG_TXE: Transmit data register empty |
| bogdanm | 0:9b334a45a8ff | 448 | * @arg SMBUS_FLAG_TXIS: Transmit interrupt status |
| bogdanm | 0:9b334a45a8ff | 449 | * @arg SMBUS_FLAG_RXNE: Receive data register not empty |
| bogdanm | 0:9b334a45a8ff | 450 | * @arg SMBUS_FLAG_ADDR: Address matched (slave mode) |
| bogdanm | 0:9b334a45a8ff | 451 | * @arg SMBUS_FLAG_AF NACK received flag |
| bogdanm | 0:9b334a45a8ff | 452 | * @arg SMBUS_FLAG_STOPF: STOP detection flag |
| bogdanm | 0:9b334a45a8ff | 453 | * @arg SMBUS_FLAG_TC: Transfer complete (master mode) |
| bogdanm | 0:9b334a45a8ff | 454 | * @arg SMBUS_FLAG_TCR: Transfer complete reload |
| bogdanm | 0:9b334a45a8ff | 455 | * @arg SMBUS_FLAG_BERR: Bus error |
| bogdanm | 0:9b334a45a8ff | 456 | * @arg SMBUS_FLAG_ARLO: Arbitration lost |
| bogdanm | 0:9b334a45a8ff | 457 | * @arg SMBUS_FLAG_OVR: Overrun/Underrun |
| bogdanm | 0:9b334a45a8ff | 458 | * @arg SMBUS_FLAG_PECERR: PEC error in reception |
| bogdanm | 0:9b334a45a8ff | 459 | * @arg SMBUS_FLAG_TIMEOUT: Timeout or Tlow detection flag |
| bogdanm | 0:9b334a45a8ff | 460 | * @arg SMBUS_FLAG_ALERT: SMBus alert |
| bogdanm | 0:9b334a45a8ff | 461 | * @arg SMBUS_FLAG_BUSY: Bus busy |
| bogdanm | 0:9b334a45a8ff | 462 | * @arg SMBUS_FLAG_DIR: Transfer direction (slave mode) |
| bogdanm | 0:9b334a45a8ff | 463 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| bogdanm | 0:9b334a45a8ff | 464 | */ |
| bogdanm | 0:9b334a45a8ff | 465 | #define SMBUS_FLAG_MASK ((uint32_t)0x0001FFFF) |
| bogdanm | 0:9b334a45a8ff | 466 | #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) |
| bogdanm | 0:9b334a45a8ff | 467 | |
| bogdanm | 0:9b334a45a8ff | 468 | /** @brief Clears the SMBUS pending flags which are cleared by writing 1 in a specific bit. |
| bogdanm | 0:9b334a45a8ff | 469 | * @param __HANDLE__: specifies the SMBUS Handle. |
| bogdanm | 0:9b334a45a8ff | 470 | * This parameter can be SMBUSx where x: 1 or 2 to select the SMBUS peripheral. |
| bogdanm | 0:9b334a45a8ff | 471 | * @param __FLAG__: specifies the flag to clear. |
| bogdanm | 0:9b334a45a8ff | 472 | * This parameter can be any combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 473 | * @arg SMBUS_FLAG_ADDR: Address matched (slave mode) |
| bogdanm | 0:9b334a45a8ff | 474 | * @arg SMBUS_FLAG_AF: NACK received flag |
| bogdanm | 0:9b334a45a8ff | 475 | * @arg SMBUS_FLAG_STOPF: STOP detection flag |
| bogdanm | 0:9b334a45a8ff | 476 | * @arg SMBUS_FLAG_BERR: Bus error |
| bogdanm | 0:9b334a45a8ff | 477 | * @arg SMBUS_FLAG_ARLO: Arbitration lost |
| bogdanm | 0:9b334a45a8ff | 478 | * @arg SMBUS_FLAG_OVR: Overrun/Underrun |
| bogdanm | 0:9b334a45a8ff | 479 | * @arg SMBUS_FLAG_PECERR: PEC error in reception |
| bogdanm | 0:9b334a45a8ff | 480 | * @arg SMBUS_FLAG_TIMEOUT: Timeout or Tlow detection flag |
| bogdanm | 0:9b334a45a8ff | 481 | * @arg SMBUS_FLAG_ALERT: SMBus alert |
| bogdanm | 0:9b334a45a8ff | 482 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 483 | */ |
| bogdanm | 0:9b334a45a8ff | 484 | #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = ((__FLAG__) & SMBUS_FLAG_MASK)) |
| bogdanm | 0:9b334a45a8ff | 485 | |
| bogdanm | 0:9b334a45a8ff | 486 | |
| bogdanm | 0:9b334a45a8ff | 487 | #define __HAL_SMBUS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE) |
| bogdanm | 0:9b334a45a8ff | 488 | #define __HAL_SMBUS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE) |
| bogdanm | 0:9b334a45a8ff | 489 | |
| bogdanm | 0:9b334a45a8ff | 490 | #define __SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN))) |
| bogdanm | 0:9b334a45a8ff | 491 | #define __SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) |
| bogdanm | 0:9b334a45a8ff | 492 | |
| bogdanm | 0:9b334a45a8ff | 493 | #define __SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ |
| bogdanm | 0:9b334a45a8ff | 494 | (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) |
| bogdanm | 0:9b334a45a8ff | 495 | |
| bogdanm | 0:9b334a45a8ff | 496 | #define __SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17) |
| bogdanm | 0:9b334a45a8ff | 497 | #define __SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16) |
| bogdanm | 0:9b334a45a8ff | 498 | #define __SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) |
| bogdanm | 0:9b334a45a8ff | 499 | #define __SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) |
| bogdanm | 0:9b334a45a8ff | 500 | #define __SMBUS_GET_ALERT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) |
| bogdanm | 0:9b334a45a8ff | 501 | #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= I2C_CR2_NACK) |
| bogdanm | 0:9b334a45a8ff | 502 | |
| bogdanm | 0:9b334a45a8ff | 503 | #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF) |
| bogdanm | 0:9b334a45a8ff | 504 | #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF) |
| bogdanm | 0:9b334a45a8ff | 505 | |
| bogdanm | 0:9b334a45a8ff | 506 | /* Exported functions --------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 507 | /* Initialization and de-initialization functions ****************************/ |
| bogdanm | 0:9b334a45a8ff | 508 | HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 0:9b334a45a8ff | 509 | HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 0:9b334a45a8ff | 510 | void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 0:9b334a45a8ff | 511 | void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 0:9b334a45a8ff | 512 | |
| bogdanm | 0:9b334a45a8ff | 513 | /* IO operation functions ****************************************************/ |
| bogdanm | 0:9b334a45a8ff | 514 | HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 0:9b334a45a8ff | 515 | HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 0:9b334a45a8ff | 516 | HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 0:9b334a45a8ff | 517 | HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 0:9b334a45a8ff | 518 | /* Aliases for inter STM32 series compatibility */ |
| bogdanm | 0:9b334a45a8ff | 519 | #define HAL_SMBUS_EnableListen_IT HAL_SMBUS_EnableListen_IT |
| bogdanm | 0:9b334a45a8ff | 520 | |
| bogdanm | 0:9b334a45a8ff | 521 | /******* Blocking mode: Polling */ |
| bogdanm | 0:9b334a45a8ff | 522 | HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); |
| bogdanm | 0:9b334a45a8ff | 523 | |
| bogdanm | 0:9b334a45a8ff | 524 | /******* Non-Blocking mode: Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 525 | HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
| bogdanm | 0:9b334a45a8ff | 526 | HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
| bogdanm | 0:9b334a45a8ff | 527 | HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress); |
| bogdanm | 0:9b334a45a8ff | 528 | HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
| bogdanm | 0:9b334a45a8ff | 529 | HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
| bogdanm | 0:9b334a45a8ff | 530 | |
| bogdanm | 0:9b334a45a8ff | 531 | /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ |
| bogdanm | 0:9b334a45a8ff | 532 | void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 0:9b334a45a8ff | 533 | void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 0:9b334a45a8ff | 534 | void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 0:9b334a45a8ff | 535 | void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 0:9b334a45a8ff | 536 | void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 0:9b334a45a8ff | 537 | void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 0:9b334a45a8ff | 538 | void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); |
| bogdanm | 0:9b334a45a8ff | 539 | void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 0:9b334a45a8ff | 540 | /* Aliases for inter STM32 series compatibility */ |
| bogdanm | 0:9b334a45a8ff | 541 | #define HAL_SMBUS_AddrCallback HAL_SMBUS_AddrCallback |
| bogdanm | 0:9b334a45a8ff | 542 | #define HAL_SMBUS_ListenCpltCallback HAL_SMBUS_ListenCpltCallback |
| bogdanm | 0:9b334a45a8ff | 543 | |
| bogdanm | 0:9b334a45a8ff | 544 | void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 0:9b334a45a8ff | 545 | |
| bogdanm | 0:9b334a45a8ff | 546 | /* Peripheral State and Errors functions *************************************/ |
| bogdanm | 0:9b334a45a8ff | 547 | uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 0:9b334a45a8ff | 548 | uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); |
| bogdanm | 0:9b334a45a8ff | 549 | |
| bogdanm | 0:9b334a45a8ff | 550 | /** |
| bogdanm | 0:9b334a45a8ff | 551 | * @} |
| bogdanm | 0:9b334a45a8ff | 552 | */ |
| bogdanm | 0:9b334a45a8ff | 553 | |
| bogdanm | 0:9b334a45a8ff | 554 | /** |
| bogdanm | 0:9b334a45a8ff | 555 | * @} |
| bogdanm | 0:9b334a45a8ff | 556 | */ |
| bogdanm | 0:9b334a45a8ff | 557 | |
| bogdanm | 0:9b334a45a8ff | 558 | #ifdef __cplusplus |
| bogdanm | 0:9b334a45a8ff | 559 | } |
| bogdanm | 0:9b334a45a8ff | 560 | #endif |
| bogdanm | 0:9b334a45a8ff | 561 | |
| bogdanm | 0:9b334a45a8ff | 562 | |
| bogdanm | 0:9b334a45a8ff | 563 | #endif /* __STM32L0xx_HAL_SMBUS_H */ |
| bogdanm | 0:9b334a45a8ff | 564 | |
| bogdanm | 0:9b334a45a8ff | 565 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| bogdanm | 0:9b334a45a8ff | 566 | |
| bogdanm | 0:9b334a45a8ff | 567 |