Frederick Huang / mbed-STM32L452

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Dependents:   STM32L452_Nucleo_ticker

Fork of mbed-dev by mbed official

targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_flash.h@182:59ec31722650, 2017-12-15 (annotated)

Committer:
Frederick_H
Date:
Fri Dec 15 08:17:23 2017 +0000
Revision:
182:59ec31722650
Parent:
167:e84263d55307 
Modify hal_tick.h of TARGET_STM32L476xG

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_hal_flash.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.7.1
AnnaBridge 167:e84263d55307 6 * @date 21-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief Header file of FLASH HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
AnnaBridge 167:e84263d55307 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32L4xx_HAL_FLASH_H
<> 144:ef7eb2e8f9f7 40 #define __STM32L4xx_HAL_FLASH_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32l4xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32L4xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup FLASH
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @defgroup FLASH_Exported_Types FLASH Exported Types
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /**
<> 144:ef7eb2e8f9f7 63 * @brief FLASH Erase structure definition
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65 typedef struct
<> 144:ef7eb2e8f9f7 66 {
<> 144:ef7eb2e8f9f7 67 uint32_t TypeErase; /*!< Mass erase or page erase.
<> 144:ef7eb2e8f9f7 68 This parameter can be a value of @ref FLASH_Type_Erase */
<> 144:ef7eb2e8f9f7 69 uint32_t Banks; /*!< Select bank to erase.
<> 144:ef7eb2e8f9f7 70 This parameter must be a value of @ref FLASH_Banks
<> 144:ef7eb2e8f9f7 71 (FLASH_BANK_BOTH should be used only for mass erase) */
<> 144:ef7eb2e8f9f7 72 uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled
<> 144:ef7eb2e8f9f7 73 This parameter must be a value between 0 and (max number of pages in the bank - 1)
<> 144:ef7eb2e8f9f7 74 (eg : 255 for 1MB dual bank) */
<> 144:ef7eb2e8f9f7 75 uint32_t NbPages; /*!< Number of pages to be erased.
<> 144:ef7eb2e8f9f7 76 This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/
<> 144:ef7eb2e8f9f7 77 } FLASH_EraseInitTypeDef;
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 /**
<> 144:ef7eb2e8f9f7 80 * @brief FLASH Option Bytes Program structure definition
<> 144:ef7eb2e8f9f7 81 */
<> 144:ef7eb2e8f9f7 82 typedef struct
<> 144:ef7eb2e8f9f7 83 {
<> 144:ef7eb2e8f9f7 84 uint32_t OptionType; /*!< Option byte to be configured.
<> 144:ef7eb2e8f9f7 85 This parameter can be a combination of the values of @ref FLASH_OB_Type */
<> 144:ef7eb2e8f9f7 86 uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP).
<> 144:ef7eb2e8f9f7 87 Only one WRP area could be programmed at the same time.
<> 144:ef7eb2e8f9f7 88 This parameter can be value of @ref FLASH_OB_WRP_Area */
<> 144:ef7eb2e8f9f7 89 uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP).
<> 144:ef7eb2e8f9f7 90 This parameter must be a value between 0 and (max number of pages in the bank - 1)
<> 144:ef7eb2e8f9f7 91 (eg : 25 for 1MB dual bank) */
<> 144:ef7eb2e8f9f7 92 uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP).
<> 144:ef7eb2e8f9f7 93 This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */
<> 144:ef7eb2e8f9f7 94 uint32_t RDPLevel; /*!< Set the read protection level.. (used for OPTIONBYTE_RDP).
<> 144:ef7eb2e8f9f7 95 This parameter can be a value of @ref FLASH_OB_Read_Protection */
<> 144:ef7eb2e8f9f7 96 uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
<> 144:ef7eb2e8f9f7 97 This parameter can be a combination of @ref FLASH_OB_USER_Type */
<> 144:ef7eb2e8f9f7 98 uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER).
<> 144:ef7eb2e8f9f7 99 This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
<> 144:ef7eb2e8f9f7 100 @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
<> 144:ef7eb2e8f9f7 101 @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
<> 144:ef7eb2e8f9f7 102 @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
<> 144:ef7eb2e8f9f7 103 @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2,
<> 144:ef7eb2e8f9f7 104 @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_nBOOT1,
<> 144:ef7eb2e8f9f7 105 @ref FLASH_OB_USER_SRAM2_PE and @ref FLASH_OB_USER_SRAM2_RST */
<> 144:ef7eb2e8f9f7 106 uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP).
<> 144:ef7eb2e8f9f7 107 This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH)
<> 144:ef7eb2e8f9f7 108 and @ref FLASH_OB_PCROP_RDP */
<> 144:ef7eb2e8f9f7 109 uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).
<> 144:ef7eb2e8f9f7 110 This parameter must be a value between begin and end of bank
<> 144:ef7eb2e8f9f7 111 => Be careful of the bank swapping for the address */
<> 144:ef7eb2e8f9f7 112 uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP).
<> 144:ef7eb2e8f9f7 113 This parameter must be a value between PCROP Start address and end of bank */
<> 144:ef7eb2e8f9f7 114 } FLASH_OBProgramInitTypeDef;
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /**
<> 144:ef7eb2e8f9f7 117 * @brief FLASH Procedure structure definition
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119 typedef enum
<> 144:ef7eb2e8f9f7 120 {
<> 144:ef7eb2e8f9f7 121 FLASH_PROC_NONE = 0,
<> 144:ef7eb2e8f9f7 122 FLASH_PROC_PAGE_ERASE,
<> 144:ef7eb2e8f9f7 123 FLASH_PROC_MASS_ERASE,
<> 144:ef7eb2e8f9f7 124 FLASH_PROC_PROGRAM,
<> 144:ef7eb2e8f9f7 125 FLASH_PROC_PROGRAM_LAST
<> 144:ef7eb2e8f9f7 126 } FLASH_ProcedureTypeDef;
<> 144:ef7eb2e8f9f7 127
AnnaBridge 167:e84263d55307 128 /**
AnnaBridge 167:e84263d55307 129 * @brief FLASH Cache structure definition
AnnaBridge 167:e84263d55307 130 */
AnnaBridge 167:e84263d55307 131 typedef enum
AnnaBridge 167:e84263d55307 132 {
AnnaBridge 167:e84263d55307 133 FLASH_CACHE_DISABLED = 0,
AnnaBridge 167:e84263d55307 134 FLASH_CACHE_ICACHE_ENABLED,
AnnaBridge 167:e84263d55307 135 FLASH_CACHE_DCACHE_ENABLED,
AnnaBridge 167:e84263d55307 136 FLASH_CACHE_ICACHE_DCACHE_ENABLED
AnnaBridge 167:e84263d55307 137 } FLASH_CacheTypeDef;
AnnaBridge 167:e84263d55307 138
<> 144:ef7eb2e8f9f7 139 /**
<> 144:ef7eb2e8f9f7 140 * @brief FLASH handle Structure definition
<> 144:ef7eb2e8f9f7 141 */
<> 144:ef7eb2e8f9f7 142 typedef struct
<> 144:ef7eb2e8f9f7 143 {
<> 144:ef7eb2e8f9f7 144 HAL_LockTypeDef Lock; /* FLASH locking object */
<> 144:ef7eb2e8f9f7 145 __IO uint32_t ErrorCode; /* FLASH error code */
<> 144:ef7eb2e8f9f7 146 __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */
<> 144:ef7eb2e8f9f7 147 __IO uint32_t Address; /* Internal variable to save address selected for program in IT context */
<> 144:ef7eb2e8f9f7 148 __IO uint32_t Bank; /* Internal variable to save current bank selected during erase in IT context */
<> 144:ef7eb2e8f9f7 149 __IO uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */
<> 144:ef7eb2e8f9f7 150 __IO uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */
AnnaBridge 167:e84263d55307 151 __IO FLASH_CacheTypeDef CacheToReactivate; /* Internal variable to indicate which caches should be reactivated */
<> 144:ef7eb2e8f9f7 152 }FLASH_ProcessTypeDef;
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 /**
<> 144:ef7eb2e8f9f7 155 * @}
<> 144:ef7eb2e8f9f7 156 */
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 159 /** @defgroup FLASH_Exported_Constants FLASH Exported Constants
<> 144:ef7eb2e8f9f7 160 * @{
<> 144:ef7eb2e8f9f7 161 */
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /** @defgroup FLASH_Error FLASH Error
<> 144:ef7eb2e8f9f7 164 * @{
<> 144:ef7eb2e8f9f7 165 */
<> 144:ef7eb2e8f9f7 166 #define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 167 #define HAL_FLASH_ERROR_OP ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 168 #define HAL_FLASH_ERROR_PROG ((uint32_t)0x00000002)
<> 144:ef7eb2e8f9f7 169 #define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000004)
<> 144:ef7eb2e8f9f7 170 #define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008)
<> 144:ef7eb2e8f9f7 171 #define HAL_FLASH_ERROR_SIZ ((uint32_t)0x00000010)
<> 144:ef7eb2e8f9f7 172 #define HAL_FLASH_ERROR_PGS ((uint32_t)0x00000020)
<> 144:ef7eb2e8f9f7 173 #define HAL_FLASH_ERROR_MIS ((uint32_t)0x00000040)
<> 144:ef7eb2e8f9f7 174 #define HAL_FLASH_ERROR_FAST ((uint32_t)0x00000080)
<> 144:ef7eb2e8f9f7 175 #define HAL_FLASH_ERROR_RD ((uint32_t)0x00000100)
<> 144:ef7eb2e8f9f7 176 #define HAL_FLASH_ERROR_OPTV ((uint32_t)0x00000200)
<> 144:ef7eb2e8f9f7 177 #define HAL_FLASH_ERROR_ECCD ((uint32_t)0x00000400)
AnnaBridge 167:e84263d55307 178 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
AnnaBridge 167:e84263d55307 179 defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 180 #define HAL_FLASH_ERROR_PEMPTY ((uint32_t)0x00000800)
<> 144:ef7eb2e8f9f7 181 #endif
<> 144:ef7eb2e8f9f7 182 /**
<> 144:ef7eb2e8f9f7 183 * @}
<> 144:ef7eb2e8f9f7 184 */
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 /** @defgroup FLASH_Type_Erase FLASH Erase Type
<> 144:ef7eb2e8f9f7 187 * @{
<> 144:ef7eb2e8f9f7 188 */
<> 144:ef7eb2e8f9f7 189 #define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!<Pages erase only*/
<> 144:ef7eb2e8f9f7 190 #define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01) /*!<Flash mass erase activation*/
<> 144:ef7eb2e8f9f7 191 /**
<> 144:ef7eb2e8f9f7 192 * @}
<> 144:ef7eb2e8f9f7 193 */
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 /** @defgroup FLASH_Banks FLASH Banks
<> 144:ef7eb2e8f9f7 196 * @{
<> 144:ef7eb2e8f9f7 197 */
<> 144:ef7eb2e8f9f7 198 #define FLASH_BANK_1 ((uint32_t)0x01) /*!< Bank 1 */
AnnaBridge 167:e84263d55307 199 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
AnnaBridge 167:e84263d55307 200 defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 201 #define FLASH_BANK_2 ((uint32_t)0x02) /*!< Bank 2 */
<> 144:ef7eb2e8f9f7 202 #define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2 */
<> 144:ef7eb2e8f9f7 203 #else
<> 144:ef7eb2e8f9f7 204 #define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1)) /*!< Bank 1 */
<> 144:ef7eb2e8f9f7 205 #endif
<> 144:ef7eb2e8f9f7 206 /**
<> 144:ef7eb2e8f9f7 207 * @}
<> 144:ef7eb2e8f9f7 208 */
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /** @defgroup FLASH_Type_Program FLASH Program Type
<> 144:ef7eb2e8f9f7 212 * @{
<> 144:ef7eb2e8f9f7 213 */
<> 144:ef7eb2e8f9f7 214 #define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x00) /*!<Program a double-word (64-bit) at a specified address.*/
<> 144:ef7eb2e8f9f7 215 #define FLASH_TYPEPROGRAM_FAST ((uint32_t)0x01) /*!<Fast program a 32 row double-word (64-bit) at a specified address.
<> 144:ef7eb2e8f9f7 216 And another 32 row double-word (64-bit) will be programmed */
<> 144:ef7eb2e8f9f7 217 #define FLASH_TYPEPROGRAM_FAST_AND_LAST ((uint32_t)0x02) /*!<Fast program a 32 row double-word (64-bit) at a specified address.
<> 144:ef7eb2e8f9f7 218 And this is the last 32 row double-word (64-bit) programmed */
<> 144:ef7eb2e8f9f7 219 /**
<> 144:ef7eb2e8f9f7 220 * @}
<> 144:ef7eb2e8f9f7 221 */
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /** @defgroup FLASH_OB_Type FLASH Option Bytes Type
<> 144:ef7eb2e8f9f7 224 * @{
<> 144:ef7eb2e8f9f7 225 */
<> 144:ef7eb2e8f9f7 226 #define OPTIONBYTE_WRP ((uint32_t)0x01) /*!< WRP option byte configuration */
<> 144:ef7eb2e8f9f7 227 #define OPTIONBYTE_RDP ((uint32_t)0x02) /*!< RDP option byte configuration */
<> 144:ef7eb2e8f9f7 228 #define OPTIONBYTE_USER ((uint32_t)0x04) /*!< USER option byte configuration */
<> 144:ef7eb2e8f9f7 229 #define OPTIONBYTE_PCROP ((uint32_t)0x08) /*!< PCROP option byte configuration */
<> 144:ef7eb2e8f9f7 230 /**
<> 144:ef7eb2e8f9f7 231 * @}
<> 144:ef7eb2e8f9f7 232 */
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 /** @defgroup FLASH_OB_WRP_Area FLASH WRP Area
<> 144:ef7eb2e8f9f7 235 * @{
<> 144:ef7eb2e8f9f7 236 */
<> 144:ef7eb2e8f9f7 237 #define OB_WRPAREA_BANK1_AREAA ((uint32_t)0x00) /*!< Flash Bank 1 Area A */
<> 144:ef7eb2e8f9f7 238 #define OB_WRPAREA_BANK1_AREAB ((uint32_t)0x01) /*!< Flash Bank 1 Area B */
AnnaBridge 167:e84263d55307 239 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
AnnaBridge 167:e84263d55307 240 defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 241 #define OB_WRPAREA_BANK2_AREAA ((uint32_t)0x02) /*!< Flash Bank 2 Area A */
<> 144:ef7eb2e8f9f7 242 #define OB_WRPAREA_BANK2_AREAB ((uint32_t)0x04) /*!< Flash Bank 2 Area B */
<> 144:ef7eb2e8f9f7 243 #endif
<> 144:ef7eb2e8f9f7 244 /**
<> 144:ef7eb2e8f9f7 245 * @}
<> 144:ef7eb2e8f9f7 246 */
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection
<> 144:ef7eb2e8f9f7 249 * @{
<> 144:ef7eb2e8f9f7 250 */
<> 144:ef7eb2e8f9f7 251 #define OB_RDP_LEVEL_0 ((uint32_t)0xAA)
<> 144:ef7eb2e8f9f7 252 #define OB_RDP_LEVEL_1 ((uint32_t)0xBB)
<> 144:ef7eb2e8f9f7 253 #define OB_RDP_LEVEL_2 ((uint32_t)0xCC) /*!< Warning: When enabling read protection level 2
<> 144:ef7eb2e8f9f7 254 it's no more possible to go back to level 1 or 0 */
<> 144:ef7eb2e8f9f7 255 /**
<> 144:ef7eb2e8f9f7 256 * @}
<> 144:ef7eb2e8f9f7 257 */
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type
<> 144:ef7eb2e8f9f7 260 * @{
<> 144:ef7eb2e8f9f7 261 */
<> 144:ef7eb2e8f9f7 262 #define OB_USER_BOR_LEV ((uint32_t)0x0001) /*!< BOR reset Level */
<> 144:ef7eb2e8f9f7 263 #define OB_USER_nRST_STOP ((uint32_t)0x0002) /*!< Reset generated when entering the stop mode */
<> 144:ef7eb2e8f9f7 264 #define OB_USER_nRST_STDBY ((uint32_t)0x0004) /*!< Reset generated when entering the standby mode */
<> 144:ef7eb2e8f9f7 265 #define OB_USER_IWDG_SW ((uint32_t)0x0008) /*!< Independent watchdog selection */
<> 144:ef7eb2e8f9f7 266 #define OB_USER_IWDG_STOP ((uint32_t)0x0010) /*!< Independent watchdog counter freeze in stop mode */
<> 144:ef7eb2e8f9f7 267 #define OB_USER_IWDG_STDBY ((uint32_t)0x0020) /*!< Independent watchdog counter freeze in standby mode */
<> 144:ef7eb2e8f9f7 268 #define OB_USER_WWDG_SW ((uint32_t)0x0040) /*!< Window watchdog selection */
AnnaBridge 167:e84263d55307 269 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
AnnaBridge 167:e84263d55307 270 defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 271 #define OB_USER_BFB2 ((uint32_t)0x0080) /*!< Dual-bank boot */
<> 144:ef7eb2e8f9f7 272 #define OB_USER_DUALBANK ((uint32_t)0x0100) /*!< Dual-Bank on 512KB or 256KB Flash memory devices */
<> 144:ef7eb2e8f9f7 273 #endif
<> 144:ef7eb2e8f9f7 274 #define OB_USER_nBOOT1 ((uint32_t)0x0200) /*!< Boot configuration */
<> 144:ef7eb2e8f9f7 275 #define OB_USER_SRAM2_PE ((uint32_t)0x0400) /*!< SRAM2 parity check enable */
<> 144:ef7eb2e8f9f7 276 #define OB_USER_SRAM2_RST ((uint32_t)0x0800) /*!< SRAM2 Erase when system reset */
<> 144:ef7eb2e8f9f7 277 #define OB_USER_nRST_SHDW ((uint32_t)0x1000) /*!< Reset generated when entering the shutdown mode */
AnnaBridge 167:e84263d55307 278 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \
AnnaBridge 167:e84263d55307 279 defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \
AnnaBridge 167:e84263d55307 280 defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 281 #define OB_USER_nSWBOOT0 ((uint32_t)0x2000) /*!< Software BOOT0 */
<> 144:ef7eb2e8f9f7 282 #define OB_USER_nBOOT0 ((uint32_t)0x4000) /*!< nBOOT0 option bit */
<> 144:ef7eb2e8f9f7 283 #endif
<> 144:ef7eb2e8f9f7 284 /**
<> 144:ef7eb2e8f9f7 285 * @}
<> 144:ef7eb2e8f9f7 286 */
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level
<> 144:ef7eb2e8f9f7 289 * @{
<> 144:ef7eb2e8f9f7 290 */
<> 144:ef7eb2e8f9f7 291 #define OB_BOR_LEVEL_0 ((uint32_t)FLASH_OPTR_BOR_LEV_0) /*!< Reset level threshold is around 1.7V */
<> 144:ef7eb2e8f9f7 292 #define OB_BOR_LEVEL_1 ((uint32_t)FLASH_OPTR_BOR_LEV_1) /*!< Reset level threshold is around 2.0V */
<> 144:ef7eb2e8f9f7 293 #define OB_BOR_LEVEL_2 ((uint32_t)FLASH_OPTR_BOR_LEV_2) /*!< Reset level threshold is around 2.2V */
<> 144:ef7eb2e8f9f7 294 #define OB_BOR_LEVEL_3 ((uint32_t)FLASH_OPTR_BOR_LEV_3) /*!< Reset level threshold is around 2.5V */
<> 144:ef7eb2e8f9f7 295 #define OB_BOR_LEVEL_4 ((uint32_t)FLASH_OPTR_BOR_LEV_4) /*!< Reset level threshold is around 2.8V */
<> 144:ef7eb2e8f9f7 296 /**
<> 144:ef7eb2e8f9f7 297 * @}
<> 144:ef7eb2e8f9f7 298 */
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop
<> 144:ef7eb2e8f9f7 301 * @{
<> 144:ef7eb2e8f9f7 302 */
<> 144:ef7eb2e8f9f7 303 #define OB_STOP_RST ((uint32_t)0x0000) /*!< Reset generated when entering the stop mode */
<> 144:ef7eb2e8f9f7 304 #define OB_STOP_NORST ((uint32_t)FLASH_OPTR_nRST_STOP) /*!< No reset generated when entering the stop mode */
<> 144:ef7eb2e8f9f7 305 /**
<> 144:ef7eb2e8f9f7 306 * @}
<> 144:ef7eb2e8f9f7 307 */
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby
<> 144:ef7eb2e8f9f7 310 * @{
<> 144:ef7eb2e8f9f7 311 */
<> 144:ef7eb2e8f9f7 312 #define OB_STANDBY_RST ((uint32_t)0x0000) /*!< Reset generated when entering the standby mode */
<> 144:ef7eb2e8f9f7 313 #define OB_STANDBY_NORST ((uint32_t)FLASH_OPTR_nRST_STDBY) /*!< No reset generated when entering the standby mode */
<> 144:ef7eb2e8f9f7 314 /**
<> 144:ef7eb2e8f9f7 315 * @}
<> 144:ef7eb2e8f9f7 316 */
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 /** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown
<> 144:ef7eb2e8f9f7 319 * @{
<> 144:ef7eb2e8f9f7 320 */
<> 144:ef7eb2e8f9f7 321 #define OB_SHUTDOWN_RST ((uint32_t)0x0000) /*!< Reset generated when entering the shutdown mode */
<> 144:ef7eb2e8f9f7 322 #define OB_SHUTDOWN_NORST ((uint32_t)FLASH_OPTR_nRST_SHDW) /*!< No reset generated when entering the shutdown mode */
<> 144:ef7eb2e8f9f7 323 /**
<> 144:ef7eb2e8f9f7 324 * @}
<> 144:ef7eb2e8f9f7 325 */
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type
<> 144:ef7eb2e8f9f7 328 * @{
<> 144:ef7eb2e8f9f7 329 */
<> 144:ef7eb2e8f9f7 330 #define OB_IWDG_HW ((uint32_t)0x00000) /*!< Hardware independent watchdog */
<> 144:ef7eb2e8f9f7 331 #define OB_IWDG_SW ((uint32_t)FLASH_OPTR_IWDG_SW) /*!< Software independent watchdog */
<> 144:ef7eb2e8f9f7 332 /**
<> 144:ef7eb2e8f9f7 333 * @}
<> 144:ef7eb2e8f9f7 334 */
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop
<> 144:ef7eb2e8f9f7 337 * @{
<> 144:ef7eb2e8f9f7 338 */
<> 144:ef7eb2e8f9f7 339 #define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000) /*!< Independent watchdog counter is frozen in Stop mode */
<> 144:ef7eb2e8f9f7 340 #define OB_IWDG_STOP_RUN ((uint32_t)FLASH_OPTR_IWDG_STOP) /*!< Independent watchdog counter is running in Stop mode */
<> 144:ef7eb2e8f9f7 341 /**
<> 144:ef7eb2e8f9f7 342 * @}
<> 144:ef7eb2e8f9f7 343 */
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby
<> 144:ef7eb2e8f9f7 346 * @{
<> 144:ef7eb2e8f9f7 347 */
<> 144:ef7eb2e8f9f7 348 #define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000) /*!< Independent watchdog counter is frozen in Standby mode */
<> 144:ef7eb2e8f9f7 349 #define OB_IWDG_STDBY_RUN ((uint32_t)FLASH_OPTR_IWDG_STDBY) /*!< Independent watchdog counter is running in Standby mode */
<> 144:ef7eb2e8f9f7 350 /**
<> 144:ef7eb2e8f9f7 351 * @}
<> 144:ef7eb2e8f9f7 352 */
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 /** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type
<> 144:ef7eb2e8f9f7 355 * @{
<> 144:ef7eb2e8f9f7 356 */
<> 144:ef7eb2e8f9f7 357 #define OB_WWDG_HW ((uint32_t)0x00000) /*!< Hardware window watchdog */
<> 144:ef7eb2e8f9f7 358 #define OB_WWDG_SW ((uint32_t)FLASH_OPTR_WWDG_SW) /*!< Software window watchdog */
<> 144:ef7eb2e8f9f7 359 /**
<> 144:ef7eb2e8f9f7 360 * @}
<> 144:ef7eb2e8f9f7 361 */
<> 144:ef7eb2e8f9f7 362
AnnaBridge 167:e84263d55307 363 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
AnnaBridge 167:e84263d55307 364 defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 365 /** @defgroup FLASH_OB_USER_BFB2 FLASH Option Bytes User BFB2 Mode
<> 144:ef7eb2e8f9f7 366 * @{
<> 144:ef7eb2e8f9f7 367 */
<> 144:ef7eb2e8f9f7 368 #define OB_BFB2_DISABLE ((uint32_t)0x000000) /*!< Dual-bank boot disable */
<> 144:ef7eb2e8f9f7 369 #define OB_BFB2_ENABLE ((uint32_t)FLASH_OPTR_BFB2) /*!< Dual-bank boot enable */
<> 144:ef7eb2e8f9f7 370 /**
<> 144:ef7eb2e8f9f7 371 * @}
<> 144:ef7eb2e8f9f7 372 */
<> 144:ef7eb2e8f9f7 373 /** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type
<> 144:ef7eb2e8f9f7 374 * @{
<> 144:ef7eb2e8f9f7 375 */
<> 144:ef7eb2e8f9f7 376 #define OB_DUALBANK_SINGLE ((uint32_t)0x000000) /*!< 256 KB/512 KB Single-bank Flash */
<> 144:ef7eb2e8f9f7 377 #define OB_DUALBANK_DUAL ((uint32_t)FLASH_OPTR_DUALBANK) /*!< 256 KB/512 KB Dual-bank Flash */
<> 144:ef7eb2e8f9f7 378 /**
<> 144:ef7eb2e8f9f7 379 * @}
<> 144:ef7eb2e8f9f7 380 */
<> 144:ef7eb2e8f9f7 381 #endif
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 /** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type
<> 144:ef7eb2e8f9f7 384 * @{
<> 144:ef7eb2e8f9f7 385 */
<> 144:ef7eb2e8f9f7 386 #define OB_BOOT1_SRAM ((uint32_t)0x000000) /*!< Embedded SRAM1 is selected as boot space (if BOOT0=1) */
<> 144:ef7eb2e8f9f7 387 #define OB_BOOT1_SYSTEM ((uint32_t)FLASH_OPTR_nBOOT1) /*!< System memory is selected as boot space (if BOOT0=1) */
<> 144:ef7eb2e8f9f7 388 /**
<> 144:ef7eb2e8f9f7 389 * @}
<> 144:ef7eb2e8f9f7 390 */
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 /** @defgroup FLASH_OB_USER_SRAM2_PE FLASH Option Bytes User SRAM2 Parity Check Type
<> 144:ef7eb2e8f9f7 393 * @{
<> 144:ef7eb2e8f9f7 394 */
<> 144:ef7eb2e8f9f7 395 #define OB_SRAM2_PARITY_ENABLE ((uint32_t)0x0000000) /*!< SRAM2 parity check enable */
<> 144:ef7eb2e8f9f7 396 #define OB_SRAM2_PARITY_DISABLE ((uint32_t)FLASH_OPTR_SRAM2_PE) /*!< SRAM2 parity check disable */
<> 144:ef7eb2e8f9f7 397 /**
<> 144:ef7eb2e8f9f7 398 * @}
<> 144:ef7eb2e8f9f7 399 */
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 /** @defgroup FLASH_OB_USER_SRAM2_RST FLASH Option Bytes User SRAM2 Erase On Reset Type
<> 144:ef7eb2e8f9f7 402 * @{
<> 144:ef7eb2e8f9f7 403 */
<> 144:ef7eb2e8f9f7 404 #define OB_SRAM2_RST_ERASE ((uint32_t)0x0000000) /*!< SRAM2 erased when a system reset occurs */
<> 144:ef7eb2e8f9f7 405 #define OB_SRAM2_RST_NOT_ERASE ((uint32_t)FLASH_OPTR_SRAM2_RST) /*!< SRAM2 is not erased when a system reset occurs */
<> 144:ef7eb2e8f9f7 406 /**
<> 144:ef7eb2e8f9f7 407 * @}
<> 144:ef7eb2e8f9f7 408 */
<> 144:ef7eb2e8f9f7 409
AnnaBridge 167:e84263d55307 410 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \
AnnaBridge 167:e84263d55307 411 defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \
AnnaBridge 167:e84263d55307 412 defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 413 /** @defgroup OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0
<> 144:ef7eb2e8f9f7 414 * @{
<> 144:ef7eb2e8f9f7 415 */
<> 144:ef7eb2e8f9f7 416 #define OB_BOOT0_FROM_OB ((uint32_t)0x0000000) /*!< BOOT0 taken from the option bit nBOOT0 */
<> 144:ef7eb2e8f9f7 417 #define OB_BOOT0_FROM_PIN ((uint32_t)FLASH_OPTR_nSWBOOT0) /*!< BOOT0 taken from PH3/BOOT0 pin */
<> 144:ef7eb2e8f9f7 418 /**
<> 144:ef7eb2e8f9f7 419 * @}
<> 144:ef7eb2e8f9f7 420 */
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /** @defgroup OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit
<> 144:ef7eb2e8f9f7 423 * @{
<> 144:ef7eb2e8f9f7 424 */
<> 144:ef7eb2e8f9f7 425 #define OB_BOOT0_RESET ((uint32_t)0x0000000) /*!< nBOOT0 = 0 */
<> 144:ef7eb2e8f9f7 426 #define OB_BOOT0_SET ((uint32_t)FLASH_OPTR_nBOOT0) /*!< nBOOT0 = 1 */
<> 144:ef7eb2e8f9f7 427 /**
<> 144:ef7eb2e8f9f7 428 * @}
<> 144:ef7eb2e8f9f7 429 */
<> 144:ef7eb2e8f9f7 430 #endif
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 /** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type
<> 144:ef7eb2e8f9f7 433 * @{
<> 144:ef7eb2e8f9f7 434 */
<> 144:ef7eb2e8f9f7 435 #define OB_PCROP_RDP_NOT_ERASE ((uint32_t)0x00000000) /*!< PCROP area is not erased when the RDP level
<> 144:ef7eb2e8f9f7 436 is decreased from Level 1 to Level 0 */
<> 144:ef7eb2e8f9f7 437 #define OB_PCROP_RDP_ERASE ((uint32_t)FLASH_PCROP1ER_PCROP_RDP) /*!< PCROP area is erased when the RDP level is
<> 144:ef7eb2e8f9f7 438 decreased from Level 1 to Level 0 (full mass erase) */
<> 144:ef7eb2e8f9f7 439 /**
<> 144:ef7eb2e8f9f7 440 * @}
<> 144:ef7eb2e8f9f7 441 */
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 /** @defgroup FLASH_Latency FLASH Latency
<> 144:ef7eb2e8f9f7 444 * @{
<> 144:ef7eb2e8f9f7 445 */
<> 144:ef7eb2e8f9f7 446 #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
<> 144:ef7eb2e8f9f7 447 #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
<> 144:ef7eb2e8f9f7 448 #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
<> 144:ef7eb2e8f9f7 449 #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
<> 144:ef7eb2e8f9f7 450 #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */
<> 144:ef7eb2e8f9f7 451 /**
<> 144:ef7eb2e8f9f7 452 * @}
<> 144:ef7eb2e8f9f7 453 */
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /** @defgroup FLASH_Keys FLASH Keys
<> 144:ef7eb2e8f9f7 456 * @{
<> 144:ef7eb2e8f9f7 457 */
<> 144:ef7eb2e8f9f7 458 #define FLASH_KEY1 ((uint32_t)0x45670123U) /*!< Flash key1 */
<> 144:ef7eb2e8f9f7 459 #define FLASH_KEY2 ((uint32_t)0xCDEF89ABU) /*!< Flash key2: used with FLASH_KEY1
<> 144:ef7eb2e8f9f7 460 to unlock the FLASH registers access */
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 #define FLASH_PDKEY1 ((uint32_t)0x04152637U) /*!< Flash power down key1 */
<> 144:ef7eb2e8f9f7 463 #define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1
<> 144:ef7eb2e8f9f7 464 to unlock the RUN_PD bit in FLASH_ACR */
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 #define FLASH_OPTKEY1 ((uint32_t)0x08192A3BU) /*!< Flash option byte key1 */
<> 144:ef7eb2e8f9f7 467 #define FLASH_OPTKEY2 ((uint32_t)0x4C5D6E7FU) /*!< Flash option byte key2: used with FLASH_OPTKEY1
<> 144:ef7eb2e8f9f7 468 to allow option bytes operations */
<> 144:ef7eb2e8f9f7 469 /**
<> 144:ef7eb2e8f9f7 470 * @}
<> 144:ef7eb2e8f9f7 471 */
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 /** @defgroup FLASH_Flags FLASH Flags Definition
<> 144:ef7eb2e8f9f7 474 * @{
<> 144:ef7eb2e8f9f7 475 */
<> 144:ef7eb2e8f9f7 476 #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of operation flag */
<> 144:ef7eb2e8f9f7 477 #define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH Operation error flag */
<> 144:ef7eb2e8f9f7 478 #define FLASH_FLAG_PROGERR FLASH_SR_PROGERR /*!< FLASH Programming error flag */
<> 144:ef7eb2e8f9f7 479 #define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protection error flag */
<> 144:ef7eb2e8f9f7 480 #define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming alignment error flag */
<> 144:ef7eb2e8f9f7 481 #define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */
<> 144:ef7eb2e8f9f7 482 #define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming sequence error flag */
<> 144:ef7eb2e8f9f7 483 #define FLASH_FLAG_MISERR FLASH_SR_MISERR /*!< FLASH Fast programming data miss error flag */
<> 144:ef7eb2e8f9f7 484 #define FLASH_FLAG_FASTERR FLASH_SR_FASTERR /*!< FLASH Fast programming error flag */
<> 144:ef7eb2e8f9f7 485 #define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH PCROP read error flag */
<> 144:ef7eb2e8f9f7 486 #define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option validity error flag */
<> 144:ef7eb2e8f9f7 487 #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
AnnaBridge 167:e84263d55307 488 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
AnnaBridge 167:e84263d55307 489 defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 490 #define FLASH_FLAG_PEMPTY FLASH_SR_PEMPTY /*!< FLASH Program empty */
<> 144:ef7eb2e8f9f7 491 #endif
<> 144:ef7eb2e8f9f7 492 #define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */
<> 144:ef7eb2e8f9f7 493 #define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 #define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
<> 144:ef7eb2e8f9f7 496 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \
<> 144:ef7eb2e8f9f7 497 FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \
<> 144:ef7eb2e8f9f7 498 FLASH_FLAG_OPTVERR | FLASH_FLAG_ECCD)
<> 144:ef7eb2e8f9f7 499 /**
<> 144:ef7eb2e8f9f7 500 * @}
<> 144:ef7eb2e8f9f7 501 */
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition
<> 144:ef7eb2e8f9f7 504 * @brief FLASH Interrupt definition
<> 144:ef7eb2e8f9f7 505 * @{
<> 144:ef7eb2e8f9f7 506 */
<> 144:ef7eb2e8f9f7 507 #define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
<> 144:ef7eb2e8f9f7 508 #define FLASH_IT_OPERR FLASH_CR_ERRIE /*!< Error Interrupt source */
<> 144:ef7eb2e8f9f7 509 #define FLASH_IT_RDERR FLASH_CR_RDERRIE /*!< PCROP Read Error Interrupt source*/
<> 144:ef7eb2e8f9f7 510 #define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24) /*!< ECC Correction Interrupt source */
<> 144:ef7eb2e8f9f7 511 /**
<> 144:ef7eb2e8f9f7 512 * @}
<> 144:ef7eb2e8f9f7 513 */
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 /**
<> 144:ef7eb2e8f9f7 516 * @}
<> 144:ef7eb2e8f9f7 517 */
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 520 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros
<> 144:ef7eb2e8f9f7 521 * @brief macros to control FLASH features
<> 144:ef7eb2e8f9f7 522 * @{
<> 144:ef7eb2e8f9f7 523 */
<> 144:ef7eb2e8f9f7 524
<> 144:ef7eb2e8f9f7 525 /**
<> 144:ef7eb2e8f9f7 526 * @brief Set the FLASH Latency.
<> 144:ef7eb2e8f9f7 527 * @param __LATENCY__: FLASH Latency
<> 144:ef7eb2e8f9f7 528 * This parameter can be one of the following values :
<> 144:ef7eb2e8f9f7 529 * @arg FLASH_LATENCY_0: FLASH Zero wait state
<> 144:ef7eb2e8f9f7 530 * @arg FLASH_LATENCY_1: FLASH One wait state
<> 144:ef7eb2e8f9f7 531 * @arg FLASH_LATENCY_2: FLASH Two wait states
<> 144:ef7eb2e8f9f7 532 * @arg FLASH_LATENCY_3: FLASH Three wait states
<> 144:ef7eb2e8f9f7 533 * @arg FLASH_LATENCY_4: FLASH Four wait states
<> 144:ef7eb2e8f9f7 534 * @retval None
<> 144:ef7eb2e8f9f7 535 */
<> 144:ef7eb2e8f9f7 536 #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)))
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 /**
<> 144:ef7eb2e8f9f7 539 * @brief Get the FLASH Latency.
<> 144:ef7eb2e8f9f7 540 * @retval FLASH Latency
<> 144:ef7eb2e8f9f7 541 * This parameter can be one of the following values :
<> 144:ef7eb2e8f9f7 542 * @arg FLASH_LATENCY_0: FLASH Zero wait state
<> 144:ef7eb2e8f9f7 543 * @arg FLASH_LATENCY_1: FLASH One wait state
<> 144:ef7eb2e8f9f7 544 * @arg FLASH_LATENCY_2: FLASH Two wait states
<> 144:ef7eb2e8f9f7 545 * @arg FLASH_LATENCY_3: FLASH Three wait states
<> 144:ef7eb2e8f9f7 546 * @arg FLASH_LATENCY_4: FLASH Four wait states
<> 144:ef7eb2e8f9f7 547 */
<> 144:ef7eb2e8f9f7 548 #define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 /**
<> 144:ef7eb2e8f9f7 551 * @brief Enable the FLASH prefetch buffer.
<> 144:ef7eb2e8f9f7 552 * @retval None
<> 144:ef7eb2e8f9f7 553 */
<> 144:ef7eb2e8f9f7 554 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 /**
<> 144:ef7eb2e8f9f7 557 * @brief Disable the FLASH prefetch buffer.
<> 144:ef7eb2e8f9f7 558 * @retval None
<> 144:ef7eb2e8f9f7 559 */
<> 144:ef7eb2e8f9f7 560 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 /**
<> 144:ef7eb2e8f9f7 563 * @brief Enable the FLASH instruction cache.
<> 144:ef7eb2e8f9f7 564 * @retval none
<> 144:ef7eb2e8f9f7 565 */
<> 144:ef7eb2e8f9f7 566 #define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 /**
<> 144:ef7eb2e8f9f7 569 * @brief Disable the FLASH instruction cache.
<> 144:ef7eb2e8f9f7 570 * @retval none
<> 144:ef7eb2e8f9f7 571 */
<> 144:ef7eb2e8f9f7 572 #define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 /**
<> 144:ef7eb2e8f9f7 575 * @brief Enable the FLASH data cache.
<> 144:ef7eb2e8f9f7 576 * @retval none
<> 144:ef7eb2e8f9f7 577 */
<> 144:ef7eb2e8f9f7 578 #define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 /**
<> 144:ef7eb2e8f9f7 581 * @brief Disable the FLASH data cache.
<> 144:ef7eb2e8f9f7 582 * @retval none
<> 144:ef7eb2e8f9f7 583 */
<> 144:ef7eb2e8f9f7 584 #define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 /**
<> 144:ef7eb2e8f9f7 587 * @brief Reset the FLASH instruction Cache.
<> 144:ef7eb2e8f9f7 588 * @note This function must be used only when the Instruction Cache is disabled.
<> 144:ef7eb2e8f9f7 589 * @retval None
<> 144:ef7eb2e8f9f7 590 */
<> 144:ef7eb2e8f9f7 591 #define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
<> 144:ef7eb2e8f9f7 592 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
<> 144:ef7eb2e8f9f7 593 } while (0)
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 /**
<> 144:ef7eb2e8f9f7 596 * @brief Reset the FLASH data Cache.
<> 144:ef7eb2e8f9f7 597 * @note This function must be used only when the data Cache is disabled.
<> 144:ef7eb2e8f9f7 598 * @retval None
<> 144:ef7eb2e8f9f7 599 */
<> 144:ef7eb2e8f9f7 600 #define __HAL_FLASH_DATA_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
<> 144:ef7eb2e8f9f7 601 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
<> 144:ef7eb2e8f9f7 602 } while (0)
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 /**
<> 144:ef7eb2e8f9f7 605 * @brief Enable the FLASH power down during Low-power run mode.
<> 144:ef7eb2e8f9f7 606 * @note Writing this bit to 0 this bit, automatically the keys are
<> 144:ef7eb2e8f9f7 607 * loss and a new unlock sequence is necessary to re-write it to 1.
<> 144:ef7eb2e8f9f7 608 */
<> 144:ef7eb2e8f9f7 609 #define __HAL_FLASH_POWER_DOWN_ENABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
<> 144:ef7eb2e8f9f7 610 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
<> 144:ef7eb2e8f9f7 611 SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
<> 144:ef7eb2e8f9f7 612 } while (0)
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 /**
<> 144:ef7eb2e8f9f7 615 * @brief Disable the FLASH power down during Low-power run mode.
<> 144:ef7eb2e8f9f7 616 * @note Writing this bit to 0 this bit, automatically the keys are
<> 144:ef7eb2e8f9f7 617 * loss and a new unlock sequence is necessary to re-write it to 1.
<> 144:ef7eb2e8f9f7 618 */
<> 144:ef7eb2e8f9f7 619 #define __HAL_FLASH_POWER_DOWN_DISABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
<> 144:ef7eb2e8f9f7 620 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
<> 144:ef7eb2e8f9f7 621 CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
<> 144:ef7eb2e8f9f7 622 } while (0)
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /**
<> 144:ef7eb2e8f9f7 625 * @brief Enable the FLASH power down during Low-Power sleep mode
<> 144:ef7eb2e8f9f7 626 * @retval none
<> 144:ef7eb2e8f9f7 627 */
<> 144:ef7eb2e8f9f7 628 #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630 /**
<> 144:ef7eb2e8f9f7 631 * @brief Disable the FLASH power down during Low-Power sleep mode
<> 144:ef7eb2e8f9f7 632 * @retval none
<> 144:ef7eb2e8f9f7 633 */
<> 144:ef7eb2e8f9f7 634 #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636 /**
<> 144:ef7eb2e8f9f7 637 * @}
<> 144:ef7eb2e8f9f7 638 */
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 /** @defgroup FLASH_Interrupt FLASH Interrupts Macros
<> 144:ef7eb2e8f9f7 641 * @brief macros to handle FLASH interrupts
<> 144:ef7eb2e8f9f7 642 * @{
<> 144:ef7eb2e8f9f7 643 */
<> 144:ef7eb2e8f9f7 644
<> 144:ef7eb2e8f9f7 645 /**
<> 144:ef7eb2e8f9f7 646 * @brief Enable the specified FLASH interrupt.
<> 144:ef7eb2e8f9f7 647 * @param __INTERRUPT__: FLASH interrupt
<> 144:ef7eb2e8f9f7 648 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 649 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
<> 144:ef7eb2e8f9f7 650 * @arg FLASH_IT_OPERR: Error Interrupt
<> 144:ef7eb2e8f9f7 651 * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
<> 144:ef7eb2e8f9f7 652 * @arg FLASH_IT_ECCC: ECC Correction Interrupt
<> 144:ef7eb2e8f9f7 653 * @retval none
<> 144:ef7eb2e8f9f7 654 */
<> 144:ef7eb2e8f9f7 655 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if((__INTERRUPT__) & FLASH_IT_ECCC) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
<> 144:ef7eb2e8f9f7 656 if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
<> 144:ef7eb2e8f9f7 657 } while(0)
<> 144:ef7eb2e8f9f7 658
<> 144:ef7eb2e8f9f7 659 /**
<> 144:ef7eb2e8f9f7 660 * @brief Disable the specified FLASH interrupt.
<> 144:ef7eb2e8f9f7 661 * @param __INTERRUPT__: FLASH interrupt
<> 144:ef7eb2e8f9f7 662 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 663 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
<> 144:ef7eb2e8f9f7 664 * @arg FLASH_IT_OPERR: Error Interrupt
<> 144:ef7eb2e8f9f7 665 * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
<> 144:ef7eb2e8f9f7 666 * @arg FLASH_IT_ECCC: ECC Correction Interrupt
<> 144:ef7eb2e8f9f7 667 * @retval none
<> 144:ef7eb2e8f9f7 668 */
<> 144:ef7eb2e8f9f7 669 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if((__INTERRUPT__) & FLASH_IT_ECCC) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
<> 144:ef7eb2e8f9f7 670 if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
<> 144:ef7eb2e8f9f7 671 } while(0)
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673 /**
<> 144:ef7eb2e8f9f7 674 * @brief Check whether the specified FLASH flag is set or not.
<> 144:ef7eb2e8f9f7 675 * @param __FLAG__: specifies the FLASH flag to check.
<> 144:ef7eb2e8f9f7 676 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 677 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
<> 144:ef7eb2e8f9f7 678 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag
<> 144:ef7eb2e8f9f7 679 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
<> 144:ef7eb2e8f9f7 680 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
<> 144:ef7eb2e8f9f7 681 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
<> 144:ef7eb2e8f9f7 682 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag
<> 144:ef7eb2e8f9f7 683 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
<> 144:ef7eb2e8f9f7 684 * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
<> 144:ef7eb2e8f9f7 685 * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
<> 144:ef7eb2e8f9f7 686 * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag
<> 144:ef7eb2e8f9f7 687 * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
<> 144:ef7eb2e8f9f7 688 * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag
<> 144:ef7eb2e8f9f7 689 * @arg FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices)
<> 144:ef7eb2e8f9f7 690 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
<> 144:ef7eb2e8f9f7 691 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
<> 144:ef7eb2e8f9f7 692 * @retval The new state of FLASH_FLAG (SET or RESET).
<> 144:ef7eb2e8f9f7 693 */
<> 144:ef7eb2e8f9f7 694 #define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) ? \
<> 144:ef7eb2e8f9f7 695 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \
<> 144:ef7eb2e8f9f7 696 (READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__)))
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 /**
<> 144:ef7eb2e8f9f7 699 * @brief Clear the FLASH's pending flags.
<> 144:ef7eb2e8f9f7 700 * @param __FLAG__: specifies the FLASH flags to clear.
<> 144:ef7eb2e8f9f7 701 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 702 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
<> 144:ef7eb2e8f9f7 703 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag
<> 144:ef7eb2e8f9f7 704 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
<> 144:ef7eb2e8f9f7 705 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
<> 144:ef7eb2e8f9f7 706 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
<> 144:ef7eb2e8f9f7 707 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag
<> 144:ef7eb2e8f9f7 708 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
<> 144:ef7eb2e8f9f7 709 * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
<> 144:ef7eb2e8f9f7 710 * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
<> 144:ef7eb2e8f9f7 711 * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag
<> 144:ef7eb2e8f9f7 712 * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
<> 144:ef7eb2e8f9f7 713 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
<> 144:ef7eb2e8f9f7 714 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
<> 144:ef7eb2e8f9f7 715 * @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags
<> 144:ef7eb2e8f9f7 716 * @retval None
<> 144:ef7eb2e8f9f7 717 */
<> 144:ef7eb2e8f9f7 718 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\
<> 144:ef7eb2e8f9f7 719 if((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\
<> 144:ef7eb2e8f9f7 720 } while(0)
<> 144:ef7eb2e8f9f7 721 /**
<> 144:ef7eb2e8f9f7 722 * @}
<> 144:ef7eb2e8f9f7 723 */
<> 144:ef7eb2e8f9f7 724
<> 144:ef7eb2e8f9f7 725 /* Include FLASH HAL Extended module */
<> 144:ef7eb2e8f9f7 726 #include "stm32l4xx_hal_flash_ex.h"
<> 144:ef7eb2e8f9f7 727 #include "stm32l4xx_hal_flash_ramfunc.h"
<> 144:ef7eb2e8f9f7 728
<> 144:ef7eb2e8f9f7 729 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 730 /** @addtogroup FLASH_Exported_Functions
<> 144:ef7eb2e8f9f7 731 * @{
<> 144:ef7eb2e8f9f7 732 */
<> 144:ef7eb2e8f9f7 733
<> 144:ef7eb2e8f9f7 734 /* Program operation functions ***********************************************/
<> 144:ef7eb2e8f9f7 735 /** @addtogroup FLASH_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 736 * @{
<> 144:ef7eb2e8f9f7 737 */
<> 144:ef7eb2e8f9f7 738 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
<> 144:ef7eb2e8f9f7 739 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
<> 144:ef7eb2e8f9f7 740 /* FLASH IRQ handler method */
<> 144:ef7eb2e8f9f7 741 void HAL_FLASH_IRQHandler(void);
<> 144:ef7eb2e8f9f7 742 /* Callbacks in non blocking modes */
<> 144:ef7eb2e8f9f7 743 void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
<> 144:ef7eb2e8f9f7 744 void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
<> 144:ef7eb2e8f9f7 745 /**
<> 144:ef7eb2e8f9f7 746 * @}
<> 144:ef7eb2e8f9f7 747 */
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 /* Peripheral Control functions **********************************************/
<> 144:ef7eb2e8f9f7 750 /** @addtogroup FLASH_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 751 * @{
<> 144:ef7eb2e8f9f7 752 */
<> 144:ef7eb2e8f9f7 753 HAL_StatusTypeDef HAL_FLASH_Unlock(void);
<> 144:ef7eb2e8f9f7 754 HAL_StatusTypeDef HAL_FLASH_Lock(void);
<> 144:ef7eb2e8f9f7 755 /* Option bytes control */
<> 144:ef7eb2e8f9f7 756 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
<> 144:ef7eb2e8f9f7 757 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
<> 144:ef7eb2e8f9f7 758 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
<> 144:ef7eb2e8f9f7 759 /**
<> 144:ef7eb2e8f9f7 760 * @}
<> 144:ef7eb2e8f9f7 761 */
<> 144:ef7eb2e8f9f7 762
<> 144:ef7eb2e8f9f7 763 /* Peripheral State functions ************************************************/
<> 144:ef7eb2e8f9f7 764 /** @addtogroup FLASH_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 765 * @{
<> 144:ef7eb2e8f9f7 766 */
<> 144:ef7eb2e8f9f7 767 uint32_t HAL_FLASH_GetError(void);
<> 144:ef7eb2e8f9f7 768 /**
<> 144:ef7eb2e8f9f7 769 * @}
<> 144:ef7eb2e8f9f7 770 */
<> 144:ef7eb2e8f9f7 771
<> 144:ef7eb2e8f9f7 772 /**
<> 144:ef7eb2e8f9f7 773 * @}
<> 144:ef7eb2e8f9f7 774 */
<> 144:ef7eb2e8f9f7 775
<> 144:ef7eb2e8f9f7 776 /* Private constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 777 /** @defgroup FLASH_Private_Constants FLASH Private Constants
<> 144:ef7eb2e8f9f7 778 * @{
<> 144:ef7eb2e8f9f7 779 */
<> 144:ef7eb2e8f9f7 780 #define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
<> 144:ef7eb2e8f9f7 781
AnnaBridge 167:e84263d55307 782 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
AnnaBridge 167:e84263d55307 783 #define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x200 << 10) : \
AnnaBridge 167:e84263d55307 784 (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10))
AnnaBridge 167:e84263d55307 785 #else
<> 144:ef7eb2e8f9f7 786 #define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x400 << 10) : \
<> 144:ef7eb2e8f9f7 787 (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10))
AnnaBridge 167:e84263d55307 788 #endif
<> 144:ef7eb2e8f9f7 789
AnnaBridge 167:e84263d55307 790 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
AnnaBridge 167:e84263d55307 791 defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 792 #define FLASH_BANK_SIZE (FLASH_SIZE >> 1)
<> 144:ef7eb2e8f9f7 793 #else
<> 144:ef7eb2e8f9f7 794 #define FLASH_BANK_SIZE (FLASH_SIZE)
<> 144:ef7eb2e8f9f7 795 #endif
<> 144:ef7eb2e8f9f7 796
<> 144:ef7eb2e8f9f7 797 #define FLASH_PAGE_SIZE ((uint32_t)0x800)
<> 144:ef7eb2e8f9f7 798
<> 144:ef7eb2e8f9f7 799 #define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
<> 144:ef7eb2e8f9f7 800 /**
<> 144:ef7eb2e8f9f7 801 * @}
<> 144:ef7eb2e8f9f7 802 */
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 805 /** @defgroup FLASH_Private_Macros FLASH Private Macros
<> 144:ef7eb2e8f9f7 806 * @{
<> 144:ef7eb2e8f9f7 807 */
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \
<> 144:ef7eb2e8f9f7 810 ((VALUE) == FLASH_TYPEERASE_MASSERASE))
<> 144:ef7eb2e8f9f7 811
AnnaBridge 167:e84263d55307 812 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
AnnaBridge 167:e84263d55307 813 defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 814 #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
<> 144:ef7eb2e8f9f7 815 ((BANK) == FLASH_BANK_2) || \
<> 144:ef7eb2e8f9f7 816 ((BANK) == FLASH_BANK_BOTH))
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 #define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \
<> 144:ef7eb2e8f9f7 819 ((BANK) == FLASH_BANK_2))
<> 144:ef7eb2e8f9f7 820 #else
<> 144:ef7eb2e8f9f7 821 #define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1)
<> 144:ef7eb2e8f9f7 822
<> 144:ef7eb2e8f9f7 823 #define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1)
<> 144:ef7eb2e8f9f7 824 #endif
<> 144:ef7eb2e8f9f7 825
<> 144:ef7eb2e8f9f7 826 #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \
<> 144:ef7eb2e8f9f7 827 ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \
<> 144:ef7eb2e8f9f7 828 ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST))
<> 144:ef7eb2e8f9f7 829
<> 144:ef7eb2e8f9f7 830 #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? \
<> 144:ef7eb2e8f9f7 831 ((ADDRESS) <= FLASH_BASE+0xFFFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? \
<> 144:ef7eb2e8f9f7 832 ((ADDRESS) <= FLASH_BASE+0x7FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? \
<> 144:ef7eb2e8f9f7 833 ((ADDRESS) <= FLASH_BASE+0x3FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x80) ? \
<> 144:ef7eb2e8f9f7 834 ((ADDRESS) <= FLASH_BASE+0x1FFFF) : ((ADDRESS) <= FLASH_BASE+0xFFFFF))))))
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 #define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000) && ((ADDRESS) <= 0x1FFF73FF))
<> 144:ef7eb2e8f9f7 837
<> 144:ef7eb2e8f9f7 838 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS))
<> 144:ef7eb2e8f9f7 839
AnnaBridge 167:e84263d55307 840 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
<> 144:ef7eb2e8f9f7 841 #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? ((PAGE) < 256) : \
<> 144:ef7eb2e8f9f7 842 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 128) : \
<> 144:ef7eb2e8f9f7 843 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 64) : \
<> 144:ef7eb2e8f9f7 844 ((PAGE) < 256)))))
AnnaBridge 167:e84263d55307 845 #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
AnnaBridge 167:e84263d55307 846 #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 256) : \
AnnaBridge 167:e84263d55307 847 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 128) : \
AnnaBridge 167:e84263d55307 848 ((PAGE) < 256))))
<> 144:ef7eb2e8f9f7 849 #else
<> 144:ef7eb2e8f9f7 850 #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 128) : \
<> 144:ef7eb2e8f9f7 851 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x80) ? ((PAGE) < 64) : \
<> 144:ef7eb2e8f9f7 852 ((PAGE) < 128))))
<> 144:ef7eb2e8f9f7 853 #endif
<> 144:ef7eb2e8f9f7 854
<> 144:ef7eb2e8f9f7 855 #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP)))
<> 144:ef7eb2e8f9f7 856
AnnaBridge 167:e84263d55307 857 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
AnnaBridge 167:e84263d55307 858 defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 859 #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \
<> 144:ef7eb2e8f9f7 860 ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB))
<> 144:ef7eb2e8f9f7 861 #else
<> 144:ef7eb2e8f9f7 862 #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB))
<> 144:ef7eb2e8f9f7 863 #endif
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865 #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
<> 144:ef7eb2e8f9f7 866 ((LEVEL) == OB_RDP_LEVEL_1)/* ||\
<> 144:ef7eb2e8f9f7 867 ((LEVEL) == OB_RDP_LEVEL_2)*/)
<> 144:ef7eb2e8f9f7 868
AnnaBridge 167:e84263d55307 869 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
<> 144:ef7eb2e8f9f7 870 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x1FFF) && ((TYPE) != 0))
<> 144:ef7eb2e8f9f7 871 #else
<> 144:ef7eb2e8f9f7 872 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x7E7F) && ((TYPE) != 0) && (((TYPE)&0x0180) == 0))
<> 144:ef7eb2e8f9f7 873 #endif
<> 144:ef7eb2e8f9f7 874
<> 144:ef7eb2e8f9f7 875 #define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \
<> 144:ef7eb2e8f9f7 876 ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \
<> 144:ef7eb2e8f9f7 877 ((LEVEL) == OB_BOR_LEVEL_4))
<> 144:ef7eb2e8f9f7 878
<> 144:ef7eb2e8f9f7 879 #define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST))
<> 144:ef7eb2e8f9f7 880
<> 144:ef7eb2e8f9f7 881 #define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST))
<> 144:ef7eb2e8f9f7 882
<> 144:ef7eb2e8f9f7 883 #define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST))
<> 144:ef7eb2e8f9f7 884
<> 144:ef7eb2e8f9f7 885 #define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW))
<> 144:ef7eb2e8f9f7 886
<> 144:ef7eb2e8f9f7 887 #define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN))
<> 144:ef7eb2e8f9f7 888
<> 144:ef7eb2e8f9f7 889 #define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN))
<> 144:ef7eb2e8f9f7 890
<> 144:ef7eb2e8f9f7 891 #define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW))
<> 144:ef7eb2e8f9f7 892
AnnaBridge 167:e84263d55307 893 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
AnnaBridge 167:e84263d55307 894 defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 895 #define IS_OB_USER_BFB2(VALUE) (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE))
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 #define IS_OB_USER_DUALBANK(VALUE) (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL))
<> 144:ef7eb2e8f9f7 898 #endif
<> 144:ef7eb2e8f9f7 899
<> 144:ef7eb2e8f9f7 900 #define IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM))
<> 144:ef7eb2e8f9f7 901
<> 144:ef7eb2e8f9f7 902 #define IS_OB_USER_SRAM2_PARITY(VALUE) (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE))
<> 144:ef7eb2e8f9f7 903
<> 144:ef7eb2e8f9f7 904 #define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE))
<> 144:ef7eb2e8f9f7 905
AnnaBridge 167:e84263d55307 906 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \
AnnaBridge 167:e84263d55307 907 defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \
AnnaBridge 167:e84263d55307 908 defined (STM32L496xx) || defined (STM32L4A6xx)
<> 144:ef7eb2e8f9f7 909 #define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN))
<> 144:ef7eb2e8f9f7 910
<> 144:ef7eb2e8f9f7 911 #define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_BOOT0_RESET) || ((VALUE) == OB_BOOT0_SET))
<> 144:ef7eb2e8f9f7 912 #endif
<> 144:ef7eb2e8f9f7 913
<> 144:ef7eb2e8f9f7 914 #define IS_OB_PCROP_RDP(VALUE) (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE))
<> 144:ef7eb2e8f9f7 915
<> 144:ef7eb2e8f9f7 916 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
<> 144:ef7eb2e8f9f7 917 ((LATENCY) == FLASH_LATENCY_1) || \
<> 144:ef7eb2e8f9f7 918 ((LATENCY) == FLASH_LATENCY_2) || \
<> 144:ef7eb2e8f9f7 919 ((LATENCY) == FLASH_LATENCY_3) || \
<> 144:ef7eb2e8f9f7 920 ((LATENCY) == FLASH_LATENCY_4))
<> 144:ef7eb2e8f9f7 921 /**
<> 144:ef7eb2e8f9f7 922 * @}
<> 144:ef7eb2e8f9f7 923 */
<> 144:ef7eb2e8f9f7 924
<> 144:ef7eb2e8f9f7 925 /**
<> 144:ef7eb2e8f9f7 926 * @}
<> 144:ef7eb2e8f9f7 927 */
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 /**
<> 144:ef7eb2e8f9f7 930 * @}
<> 144:ef7eb2e8f9f7 931 */
<> 144:ef7eb2e8f9f7 932
<> 144:ef7eb2e8f9f7 933 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 934 }
<> 144:ef7eb2e8f9f7 935 #endif
<> 144:ef7eb2e8f9f7 936
<> 144:ef7eb2e8f9f7 937 #endif /* __STM32L4xx_HAL_FLASH_H */
<> 144:ef7eb2e8f9f7 938
<> 144:ef7eb2e8f9f7 939 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/