Frederick Huang / mbed-STM32L452

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Dependents:   STM32L452_Nucleo_ticker

Fork of mbed-dev by mbed official

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_spi.h@161:2cc1468da177, 2017-03-30 (annotated)

Committer:
<>
Date:
Thu Mar 30 13:45:57 2017 +0100
Revision:
161:2cc1468da177
This updates the lib to the mbed lib v139

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 161:2cc1468da177 1 /**
<> 161:2cc1468da177 2 ******************************************************************************
<> 161:2cc1468da177 3 * @file stm32f7xx_ll_spi.h
<> 161:2cc1468da177 4 * @author MCD Application Team
<> 161:2cc1468da177 5 * @version V1.2.0
<> 161:2cc1468da177 6 * @date 30-December-2016
<> 161:2cc1468da177 7 * @brief Header file of SPI LL module.
<> 161:2cc1468da177 8 ******************************************************************************
<> 161:2cc1468da177 9 * @attention
<> 161:2cc1468da177 10 *
<> 161:2cc1468da177 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 161:2cc1468da177 12 *
<> 161:2cc1468da177 13 * Redistribution and use in source and binary forms, with or without modification,
<> 161:2cc1468da177 14 * are permitted provided that the following conditions are met:
<> 161:2cc1468da177 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 161:2cc1468da177 16 * this list of conditions and the following disclaimer.
<> 161:2cc1468da177 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 161:2cc1468da177 18 * this list of conditions and the following disclaimer in the documentation
<> 161:2cc1468da177 19 * and/or other materials provided with the distribution.
<> 161:2cc1468da177 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 161:2cc1468da177 21 * may be used to endorse or promote products derived from this software
<> 161:2cc1468da177 22 * without specific prior written permission.
<> 161:2cc1468da177 23 *
<> 161:2cc1468da177 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 161:2cc1468da177 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 161:2cc1468da177 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 161:2cc1468da177 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 161:2cc1468da177 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 161:2cc1468da177 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 161:2cc1468da177 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 161:2cc1468da177 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 161:2cc1468da177 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 161:2cc1468da177 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 161:2cc1468da177 34 *
<> 161:2cc1468da177 35 ******************************************************************************
<> 161:2cc1468da177 36 */
<> 161:2cc1468da177 37
<> 161:2cc1468da177 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 161:2cc1468da177 39 #ifndef __STM32F7xx_LL_SPI_H
<> 161:2cc1468da177 40 #define __STM32F7xx_LL_SPI_H
<> 161:2cc1468da177 41
<> 161:2cc1468da177 42 #ifdef __cplusplus
<> 161:2cc1468da177 43 extern "C" {
<> 161:2cc1468da177 44 #endif
<> 161:2cc1468da177 45
<> 161:2cc1468da177 46 /* Includes ------------------------------------------------------------------*/
<> 161:2cc1468da177 47 #include "stm32f7xx.h"
<> 161:2cc1468da177 48
<> 161:2cc1468da177 49 /** @addtogroup STM32F7xx_LL_Driver
<> 161:2cc1468da177 50 * @{
<> 161:2cc1468da177 51 */
<> 161:2cc1468da177 52
<> 161:2cc1468da177 53 #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6)
<> 161:2cc1468da177 54
<> 161:2cc1468da177 55 /** @defgroup SPI_LL SPI
<> 161:2cc1468da177 56 * @{
<> 161:2cc1468da177 57 */
<> 161:2cc1468da177 58
<> 161:2cc1468da177 59 /* Private types -------------------------------------------------------------*/
<> 161:2cc1468da177 60 /* Private variables ---------------------------------------------------------*/
<> 161:2cc1468da177 61 /* Private macros ------------------------------------------------------------*/
<> 161:2cc1468da177 62
<> 161:2cc1468da177 63 /* Exported types ------------------------------------------------------------*/
<> 161:2cc1468da177 64 #if defined(USE_FULL_LL_DRIVER)
<> 161:2cc1468da177 65 /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
<> 161:2cc1468da177 66 * @{
<> 161:2cc1468da177 67 */
<> 161:2cc1468da177 68
<> 161:2cc1468da177 69 /**
<> 161:2cc1468da177 70 * @brief SPI Init structures definition
<> 161:2cc1468da177 71 */
<> 161:2cc1468da177 72 typedef struct
<> 161:2cc1468da177 73 {
<> 161:2cc1468da177 74 uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
<> 161:2cc1468da177 75 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
<> 161:2cc1468da177 76
<> 161:2cc1468da177 77 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
<> 161:2cc1468da177 78
<> 161:2cc1468da177 79 uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
<> 161:2cc1468da177 80 This parameter can be a value of @ref SPI_LL_EC_MODE.
<> 161:2cc1468da177 81
<> 161:2cc1468da177 82 This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
<> 161:2cc1468da177 83
<> 161:2cc1468da177 84 uint32_t DataWidth; /*!< Specifies the SPI data width.
<> 161:2cc1468da177 85 This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
<> 161:2cc1468da177 86
<> 161:2cc1468da177 87 This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
<> 161:2cc1468da177 88
<> 161:2cc1468da177 89 uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
<> 161:2cc1468da177 90 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
<> 161:2cc1468da177 91
<> 161:2cc1468da177 92 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
<> 161:2cc1468da177 93
<> 161:2cc1468da177 94 uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
<> 161:2cc1468da177 95 This parameter can be a value of @ref SPI_LL_EC_PHASE.
<> 161:2cc1468da177 96
<> 161:2cc1468da177 97 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
<> 161:2cc1468da177 98
<> 161:2cc1468da177 99 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
<> 161:2cc1468da177 100 This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
<> 161:2cc1468da177 101
<> 161:2cc1468da177 102 This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
<> 161:2cc1468da177 103
<> 161:2cc1468da177 104 uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
<> 161:2cc1468da177 105 This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
<> 161:2cc1468da177 106 @note The communication clock is derived from the master clock. The slave clock does not need to be set.
<> 161:2cc1468da177 107
<> 161:2cc1468da177 108 This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
<> 161:2cc1468da177 109
<> 161:2cc1468da177 110 uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
<> 161:2cc1468da177 111 This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
<> 161:2cc1468da177 112
<> 161:2cc1468da177 113 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
<> 161:2cc1468da177 114
<> 161:2cc1468da177 115 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
<> 161:2cc1468da177 116 This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
<> 161:2cc1468da177 117
<> 161:2cc1468da177 118 This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
<> 161:2cc1468da177 119
<> 161:2cc1468da177 120 uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
<> 161:2cc1468da177 121 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
<> 161:2cc1468da177 122
<> 161:2cc1468da177 123 This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
<> 161:2cc1468da177 124
<> 161:2cc1468da177 125 } LL_SPI_InitTypeDef;
<> 161:2cc1468da177 126
<> 161:2cc1468da177 127 /**
<> 161:2cc1468da177 128 * @}
<> 161:2cc1468da177 129 */
<> 161:2cc1468da177 130 #endif /* USE_FULL_LL_DRIVER */
<> 161:2cc1468da177 131
<> 161:2cc1468da177 132 /* Exported constants --------------------------------------------------------*/
<> 161:2cc1468da177 133 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
<> 161:2cc1468da177 134 * @{
<> 161:2cc1468da177 135 */
<> 161:2cc1468da177 136
<> 161:2cc1468da177 137 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
<> 161:2cc1468da177 138 * @brief Flags defines which can be used with LL_SPI_ReadReg function
<> 161:2cc1468da177 139 * @{
<> 161:2cc1468da177 140 */
<> 161:2cc1468da177 141 #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
<> 161:2cc1468da177 142 #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
<> 161:2cc1468da177 143 #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
<> 161:2cc1468da177 144 #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
<> 161:2cc1468da177 145 #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
<> 161:2cc1468da177 146 #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
<> 161:2cc1468da177 147 #define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
<> 161:2cc1468da177 148 /**
<> 161:2cc1468da177 149 * @}
<> 161:2cc1468da177 150 */
<> 161:2cc1468da177 151
<> 161:2cc1468da177 152 /** @defgroup SPI_LL_EC_IT IT Defines
<> 161:2cc1468da177 153 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
<> 161:2cc1468da177 154 * @{
<> 161:2cc1468da177 155 */
<> 161:2cc1468da177 156 #define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
<> 161:2cc1468da177 157 #define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
<> 161:2cc1468da177 158 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
<> 161:2cc1468da177 159 /**
<> 161:2cc1468da177 160 * @}
<> 161:2cc1468da177 161 */
<> 161:2cc1468da177 162
<> 161:2cc1468da177 163 /** @defgroup SPI_LL_EC_MODE Operation Mode
<> 161:2cc1468da177 164 * @{
<> 161:2cc1468da177 165 */
<> 161:2cc1468da177 166 #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
<> 161:2cc1468da177 167 #define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
<> 161:2cc1468da177 168 /**
<> 161:2cc1468da177 169 * @}
<> 161:2cc1468da177 170 */
<> 161:2cc1468da177 171
<> 161:2cc1468da177 172 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
<> 161:2cc1468da177 173 * @{
<> 161:2cc1468da177 174 */
<> 161:2cc1468da177 175 #define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */
<> 161:2cc1468da177 176 #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */
<> 161:2cc1468da177 177 /**
<> 161:2cc1468da177 178 * @}
<> 161:2cc1468da177 179 */
<> 161:2cc1468da177 180
<> 161:2cc1468da177 181 /** @defgroup SPI_LL_EC_PHASE Clock Phase
<> 161:2cc1468da177 182 * @{
<> 161:2cc1468da177 183 */
<> 161:2cc1468da177 184 #define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */
<> 161:2cc1468da177 185 #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
<> 161:2cc1468da177 186 /**
<> 161:2cc1468da177 187 * @}
<> 161:2cc1468da177 188 */
<> 161:2cc1468da177 189
<> 161:2cc1468da177 190 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
<> 161:2cc1468da177 191 * @{
<> 161:2cc1468da177 192 */
<> 161:2cc1468da177 193 #define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
<> 161:2cc1468da177 194 #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
<> 161:2cc1468da177 195 /**
<> 161:2cc1468da177 196 * @}
<> 161:2cc1468da177 197 */
<> 161:2cc1468da177 198
<> 161:2cc1468da177 199 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
<> 161:2cc1468da177 200 * @{
<> 161:2cc1468da177 201 */
<> 161:2cc1468da177 202 #define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
<> 161:2cc1468da177 203 #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
<> 161:2cc1468da177 204 #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
<> 161:2cc1468da177 205 #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
<> 161:2cc1468da177 206 #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
<> 161:2cc1468da177 207 #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
<> 161:2cc1468da177 208 #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
<> 161:2cc1468da177 209 #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
<> 161:2cc1468da177 210 /**
<> 161:2cc1468da177 211 * @}
<> 161:2cc1468da177 212 */
<> 161:2cc1468da177 213
<> 161:2cc1468da177 214 /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
<> 161:2cc1468da177 215 * @{
<> 161:2cc1468da177 216 */
<> 161:2cc1468da177 217 #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
<> 161:2cc1468da177 218 #define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */
<> 161:2cc1468da177 219 /**
<> 161:2cc1468da177 220 * @}
<> 161:2cc1468da177 221 */
<> 161:2cc1468da177 222
<> 161:2cc1468da177 223 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
<> 161:2cc1468da177 224 * @{
<> 161:2cc1468da177 225 */
<> 161:2cc1468da177 226 #define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
<> 161:2cc1468da177 227 #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
<> 161:2cc1468da177 228 #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
<> 161:2cc1468da177 229 #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
<> 161:2cc1468da177 230 /**
<> 161:2cc1468da177 231 * @}
<> 161:2cc1468da177 232 */
<> 161:2cc1468da177 233
<> 161:2cc1468da177 234 /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
<> 161:2cc1468da177 235 * @{
<> 161:2cc1468da177 236 */
<> 161:2cc1468da177 237 #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
<> 161:2cc1468da177 238 #define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
<> 161:2cc1468da177 239 #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
<> 161:2cc1468da177 240 /**
<> 161:2cc1468da177 241 * @}
<> 161:2cc1468da177 242 */
<> 161:2cc1468da177 243
<> 161:2cc1468da177 244 /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
<> 161:2cc1468da177 245 * @{
<> 161:2cc1468da177 246 */
<> 161:2cc1468da177 247 #define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 4 bits */
<> 161:2cc1468da177 248 #define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) /*!< Data length for SPI transfer: 5 bits */
<> 161:2cc1468da177 249 #define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 6 bits */
<> 161:2cc1468da177 250 #define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 7 bits */
<> 161:2cc1468da177 251 #define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 8 bits */
<> 161:2cc1468da177 252 #define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) /*!< Data length for SPI transfer: 9 bits */
<> 161:2cc1468da177 253 #define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 10 bits */
<> 161:2cc1468da177 254 #define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 11 bits */
<> 161:2cc1468da177 255 #define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 12 bits */
<> 161:2cc1468da177 256 #define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2) /*!< Data length for SPI transfer: 13 bits */
<> 161:2cc1468da177 257 #define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 14 bits */
<> 161:2cc1468da177 258 #define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 15 bits */
<> 161:2cc1468da177 259 #define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */
<> 161:2cc1468da177 260 /**
<> 161:2cc1468da177 261 * @}
<> 161:2cc1468da177 262 */
<> 161:2cc1468da177 263 #if defined(USE_FULL_LL_DRIVER)
<> 161:2cc1468da177 264
<> 161:2cc1468da177 265 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
<> 161:2cc1468da177 266 * @{
<> 161:2cc1468da177 267 */
<> 161:2cc1468da177 268 #define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
<> 161:2cc1468da177 269 #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
<> 161:2cc1468da177 270 /**
<> 161:2cc1468da177 271 * @}
<> 161:2cc1468da177 272 */
<> 161:2cc1468da177 273 #endif /* USE_FULL_LL_DRIVER */
<> 161:2cc1468da177 274
<> 161:2cc1468da177 275 /** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
<> 161:2cc1468da177 276 * @{
<> 161:2cc1468da177 277 */
<> 161:2cc1468da177 278 #define LL_SPI_CRC_8BIT 0x00000000U /*!< 8-bit CRC length */
<> 161:2cc1468da177 279 #define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */
<> 161:2cc1468da177 280 /**
<> 161:2cc1468da177 281 * @}
<> 161:2cc1468da177 282 */
<> 161:2cc1468da177 283
<> 161:2cc1468da177 284 /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
<> 161:2cc1468da177 285 * @{
<> 161:2cc1468da177 286 */
<> 161:2cc1468da177 287 #define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */
<> 161:2cc1468da177 288 #define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) */
<> 161:2cc1468da177 289 /**
<> 161:2cc1468da177 290 * @}
<> 161:2cc1468da177 291 */
<> 161:2cc1468da177 292
<> 161:2cc1468da177 293 /** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
<> 161:2cc1468da177 294 * @{
<> 161:2cc1468da177 295 */
<> 161:2cc1468da177 296 #define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception empty */
<> 161:2cc1468da177 297 #define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/4 */
<> 161:2cc1468da177 298 #define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/2 */
<> 161:2cc1468da177 299 #define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full */
<> 161:2cc1468da177 300 /**
<> 161:2cc1468da177 301 * @}
<> 161:2cc1468da177 302 */
<> 161:2cc1468da177 303
<> 161:2cc1468da177 304 /** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
<> 161:2cc1468da177 305 * @{
<> 161:2cc1468da177 306 */
<> 161:2cc1468da177 307 #define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission empty */
<> 161:2cc1468da177 308 #define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission 1/4 */
<> 161:2cc1468da177 309 #define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission 1/2 */
<> 161:2cc1468da177 310 #define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full */
<> 161:2cc1468da177 311 /**
<> 161:2cc1468da177 312 * @}
<> 161:2cc1468da177 313 */
<> 161:2cc1468da177 314
<> 161:2cc1468da177 315 /** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
<> 161:2cc1468da177 316 * @{
<> 161:2cc1468da177 317 */
<> 161:2cc1468da177 318 #define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */
<> 161:2cc1468da177 319 #define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */
<> 161:2cc1468da177 320
<> 161:2cc1468da177 321 /**
<> 161:2cc1468da177 322 * @}
<> 161:2cc1468da177 323 */
<> 161:2cc1468da177 324
<> 161:2cc1468da177 325 /**
<> 161:2cc1468da177 326 * @}
<> 161:2cc1468da177 327 */
<> 161:2cc1468da177 328
<> 161:2cc1468da177 329 /* Exported macro ------------------------------------------------------------*/
<> 161:2cc1468da177 330 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
<> 161:2cc1468da177 331 * @{
<> 161:2cc1468da177 332 */
<> 161:2cc1468da177 333
<> 161:2cc1468da177 334 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
<> 161:2cc1468da177 335 * @{
<> 161:2cc1468da177 336 */
<> 161:2cc1468da177 337
<> 161:2cc1468da177 338 /**
<> 161:2cc1468da177 339 * @brief Write a value in SPI register
<> 161:2cc1468da177 340 * @param __INSTANCE__ SPI Instance
<> 161:2cc1468da177 341 * @param __REG__ Register to be written
<> 161:2cc1468da177 342 * @param __VALUE__ Value to be written in the register
<> 161:2cc1468da177 343 * @retval None
<> 161:2cc1468da177 344 */
<> 161:2cc1468da177 345 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<> 161:2cc1468da177 346
<> 161:2cc1468da177 347 /**
<> 161:2cc1468da177 348 * @brief Read a value in SPI register
<> 161:2cc1468da177 349 * @param __INSTANCE__ SPI Instance
<> 161:2cc1468da177 350 * @param __REG__ Register to be read
<> 161:2cc1468da177 351 * @retval Register value
<> 161:2cc1468da177 352 */
<> 161:2cc1468da177 353 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<> 161:2cc1468da177 354 /**
<> 161:2cc1468da177 355 * @}
<> 161:2cc1468da177 356 */
<> 161:2cc1468da177 357
<> 161:2cc1468da177 358 /**
<> 161:2cc1468da177 359 * @}
<> 161:2cc1468da177 360 */
<> 161:2cc1468da177 361
<> 161:2cc1468da177 362 /* Exported functions --------------------------------------------------------*/
<> 161:2cc1468da177 363 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
<> 161:2cc1468da177 364 * @{
<> 161:2cc1468da177 365 */
<> 161:2cc1468da177 366
<> 161:2cc1468da177 367 /** @defgroup SPI_LL_EF_Configuration Configuration
<> 161:2cc1468da177 368 * @{
<> 161:2cc1468da177 369 */
<> 161:2cc1468da177 370
<> 161:2cc1468da177 371 /**
<> 161:2cc1468da177 372 * @brief Enable SPI peripheral
<> 161:2cc1468da177 373 * @rmtoll CR1 SPE LL_SPI_Enable
<> 161:2cc1468da177 374 * @param SPIx SPI Instance
<> 161:2cc1468da177 375 * @retval None
<> 161:2cc1468da177 376 */
<> 161:2cc1468da177 377 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 378 {
<> 161:2cc1468da177 379 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
<> 161:2cc1468da177 380 }
<> 161:2cc1468da177 381
<> 161:2cc1468da177 382 /**
<> 161:2cc1468da177 383 * @brief Disable SPI peripheral
<> 161:2cc1468da177 384 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
<> 161:2cc1468da177 385 * @rmtoll CR1 SPE LL_SPI_Disable
<> 161:2cc1468da177 386 * @param SPIx SPI Instance
<> 161:2cc1468da177 387 * @retval None
<> 161:2cc1468da177 388 */
<> 161:2cc1468da177 389 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 390 {
<> 161:2cc1468da177 391 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
<> 161:2cc1468da177 392 }
<> 161:2cc1468da177 393
<> 161:2cc1468da177 394 /**
<> 161:2cc1468da177 395 * @brief Check if SPI peripheral is enabled
<> 161:2cc1468da177 396 * @rmtoll CR1 SPE LL_SPI_IsEnabled
<> 161:2cc1468da177 397 * @param SPIx SPI Instance
<> 161:2cc1468da177 398 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 399 */
<> 161:2cc1468da177 400 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 401 {
<> 161:2cc1468da177 402 return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
<> 161:2cc1468da177 403 }
<> 161:2cc1468da177 404
<> 161:2cc1468da177 405 /**
<> 161:2cc1468da177 406 * @brief Set SPI operation mode to Master or Slave
<> 161:2cc1468da177 407 * @note This bit should not be changed when communication is ongoing.
<> 161:2cc1468da177 408 * @rmtoll CR1 MSTR LL_SPI_SetMode\n
<> 161:2cc1468da177 409 * CR1 SSI LL_SPI_SetMode
<> 161:2cc1468da177 410 * @param SPIx SPI Instance
<> 161:2cc1468da177 411 * @param Mode This parameter can be one of the following values:
<> 161:2cc1468da177 412 * @arg @ref LL_SPI_MODE_MASTER
<> 161:2cc1468da177 413 * @arg @ref LL_SPI_MODE_SLAVE
<> 161:2cc1468da177 414 * @retval None
<> 161:2cc1468da177 415 */
<> 161:2cc1468da177 416 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
<> 161:2cc1468da177 417 {
<> 161:2cc1468da177 418 MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
<> 161:2cc1468da177 419 }
<> 161:2cc1468da177 420
<> 161:2cc1468da177 421 /**
<> 161:2cc1468da177 422 * @brief Get SPI operation mode (Master or Slave)
<> 161:2cc1468da177 423 * @rmtoll CR1 MSTR LL_SPI_GetMode\n
<> 161:2cc1468da177 424 * CR1 SSI LL_SPI_GetMode
<> 161:2cc1468da177 425 * @param SPIx SPI Instance
<> 161:2cc1468da177 426 * @retval Returned value can be one of the following values:
<> 161:2cc1468da177 427 * @arg @ref LL_SPI_MODE_MASTER
<> 161:2cc1468da177 428 * @arg @ref LL_SPI_MODE_SLAVE
<> 161:2cc1468da177 429 */
<> 161:2cc1468da177 430 __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 431 {
<> 161:2cc1468da177 432 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
<> 161:2cc1468da177 433 }
<> 161:2cc1468da177 434
<> 161:2cc1468da177 435 /**
<> 161:2cc1468da177 436 * @brief Set serial protocol used
<> 161:2cc1468da177 437 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
<> 161:2cc1468da177 438 * @rmtoll CR2 FRF LL_SPI_SetStandard
<> 161:2cc1468da177 439 * @param SPIx SPI Instance
<> 161:2cc1468da177 440 * @param Standard This parameter can be one of the following values:
<> 161:2cc1468da177 441 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
<> 161:2cc1468da177 442 * @arg @ref LL_SPI_PROTOCOL_TI
<> 161:2cc1468da177 443 * @retval None
<> 161:2cc1468da177 444 */
<> 161:2cc1468da177 445 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
<> 161:2cc1468da177 446 {
<> 161:2cc1468da177 447 MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
<> 161:2cc1468da177 448 }
<> 161:2cc1468da177 449
<> 161:2cc1468da177 450 /**
<> 161:2cc1468da177 451 * @brief Get serial protocol used
<> 161:2cc1468da177 452 * @rmtoll CR2 FRF LL_SPI_GetStandard
<> 161:2cc1468da177 453 * @param SPIx SPI Instance
<> 161:2cc1468da177 454 * @retval Returned value can be one of the following values:
<> 161:2cc1468da177 455 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
<> 161:2cc1468da177 456 * @arg @ref LL_SPI_PROTOCOL_TI
<> 161:2cc1468da177 457 */
<> 161:2cc1468da177 458 __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 459 {
<> 161:2cc1468da177 460 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
<> 161:2cc1468da177 461 }
<> 161:2cc1468da177 462
<> 161:2cc1468da177 463 /**
<> 161:2cc1468da177 464 * @brief Set clock phase
<> 161:2cc1468da177 465 * @note This bit should not be changed when communication is ongoing.
<> 161:2cc1468da177 466 * This bit is not used in SPI TI mode.
<> 161:2cc1468da177 467 * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
<> 161:2cc1468da177 468 * @param SPIx SPI Instance
<> 161:2cc1468da177 469 * @param ClockPhase This parameter can be one of the following values:
<> 161:2cc1468da177 470 * @arg @ref LL_SPI_PHASE_1EDGE
<> 161:2cc1468da177 471 * @arg @ref LL_SPI_PHASE_2EDGE
<> 161:2cc1468da177 472 * @retval None
<> 161:2cc1468da177 473 */
<> 161:2cc1468da177 474 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
<> 161:2cc1468da177 475 {
<> 161:2cc1468da177 476 MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
<> 161:2cc1468da177 477 }
<> 161:2cc1468da177 478
<> 161:2cc1468da177 479 /**
<> 161:2cc1468da177 480 * @brief Get clock phase
<> 161:2cc1468da177 481 * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
<> 161:2cc1468da177 482 * @param SPIx SPI Instance
<> 161:2cc1468da177 483 * @retval Returned value can be one of the following values:
<> 161:2cc1468da177 484 * @arg @ref LL_SPI_PHASE_1EDGE
<> 161:2cc1468da177 485 * @arg @ref LL_SPI_PHASE_2EDGE
<> 161:2cc1468da177 486 */
<> 161:2cc1468da177 487 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 488 {
<> 161:2cc1468da177 489 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
<> 161:2cc1468da177 490 }
<> 161:2cc1468da177 491
<> 161:2cc1468da177 492 /**
<> 161:2cc1468da177 493 * @brief Set clock polarity
<> 161:2cc1468da177 494 * @note This bit should not be changed when communication is ongoing.
<> 161:2cc1468da177 495 * This bit is not used in SPI TI mode.
<> 161:2cc1468da177 496 * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
<> 161:2cc1468da177 497 * @param SPIx SPI Instance
<> 161:2cc1468da177 498 * @param ClockPolarity This parameter can be one of the following values:
<> 161:2cc1468da177 499 * @arg @ref LL_SPI_POLARITY_LOW
<> 161:2cc1468da177 500 * @arg @ref LL_SPI_POLARITY_HIGH
<> 161:2cc1468da177 501 * @retval None
<> 161:2cc1468da177 502 */
<> 161:2cc1468da177 503 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
<> 161:2cc1468da177 504 {
<> 161:2cc1468da177 505 MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
<> 161:2cc1468da177 506 }
<> 161:2cc1468da177 507
<> 161:2cc1468da177 508 /**
<> 161:2cc1468da177 509 * @brief Get clock polarity
<> 161:2cc1468da177 510 * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
<> 161:2cc1468da177 511 * @param SPIx SPI Instance
<> 161:2cc1468da177 512 * @retval Returned value can be one of the following values:
<> 161:2cc1468da177 513 * @arg @ref LL_SPI_POLARITY_LOW
<> 161:2cc1468da177 514 * @arg @ref LL_SPI_POLARITY_HIGH
<> 161:2cc1468da177 515 */
<> 161:2cc1468da177 516 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 517 {
<> 161:2cc1468da177 518 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
<> 161:2cc1468da177 519 }
<> 161:2cc1468da177 520
<> 161:2cc1468da177 521 /**
<> 161:2cc1468da177 522 * @brief Set baud rate prescaler
<> 161:2cc1468da177 523 * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
<> 161:2cc1468da177 524 * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
<> 161:2cc1468da177 525 * @param SPIx SPI Instance
<> 161:2cc1468da177 526 * @param BaudRate This parameter can be one of the following values:
<> 161:2cc1468da177 527 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
<> 161:2cc1468da177 528 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
<> 161:2cc1468da177 529 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
<> 161:2cc1468da177 530 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
<> 161:2cc1468da177 531 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
<> 161:2cc1468da177 532 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
<> 161:2cc1468da177 533 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
<> 161:2cc1468da177 534 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
<> 161:2cc1468da177 535 * @retval None
<> 161:2cc1468da177 536 */
<> 161:2cc1468da177 537 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
<> 161:2cc1468da177 538 {
<> 161:2cc1468da177 539 MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
<> 161:2cc1468da177 540 }
<> 161:2cc1468da177 541
<> 161:2cc1468da177 542 /**
<> 161:2cc1468da177 543 * @brief Get baud rate prescaler
<> 161:2cc1468da177 544 * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
<> 161:2cc1468da177 545 * @param SPIx SPI Instance
<> 161:2cc1468da177 546 * @retval Returned value can be one of the following values:
<> 161:2cc1468da177 547 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
<> 161:2cc1468da177 548 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
<> 161:2cc1468da177 549 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
<> 161:2cc1468da177 550 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
<> 161:2cc1468da177 551 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
<> 161:2cc1468da177 552 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
<> 161:2cc1468da177 553 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
<> 161:2cc1468da177 554 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
<> 161:2cc1468da177 555 */
<> 161:2cc1468da177 556 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 557 {
<> 161:2cc1468da177 558 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
<> 161:2cc1468da177 559 }
<> 161:2cc1468da177 560
<> 161:2cc1468da177 561 /**
<> 161:2cc1468da177 562 * @brief Set transfer bit order
<> 161:2cc1468da177 563 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
<> 161:2cc1468da177 564 * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
<> 161:2cc1468da177 565 * @param SPIx SPI Instance
<> 161:2cc1468da177 566 * @param BitOrder This parameter can be one of the following values:
<> 161:2cc1468da177 567 * @arg @ref LL_SPI_LSB_FIRST
<> 161:2cc1468da177 568 * @arg @ref LL_SPI_MSB_FIRST
<> 161:2cc1468da177 569 * @retval None
<> 161:2cc1468da177 570 */
<> 161:2cc1468da177 571 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
<> 161:2cc1468da177 572 {
<> 161:2cc1468da177 573 MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
<> 161:2cc1468da177 574 }
<> 161:2cc1468da177 575
<> 161:2cc1468da177 576 /**
<> 161:2cc1468da177 577 * @brief Get transfer bit order
<> 161:2cc1468da177 578 * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
<> 161:2cc1468da177 579 * @param SPIx SPI Instance
<> 161:2cc1468da177 580 * @retval Returned value can be one of the following values:
<> 161:2cc1468da177 581 * @arg @ref LL_SPI_LSB_FIRST
<> 161:2cc1468da177 582 * @arg @ref LL_SPI_MSB_FIRST
<> 161:2cc1468da177 583 */
<> 161:2cc1468da177 584 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 585 {
<> 161:2cc1468da177 586 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
<> 161:2cc1468da177 587 }
<> 161:2cc1468da177 588
<> 161:2cc1468da177 589 /**
<> 161:2cc1468da177 590 * @brief Set transfer direction mode
<> 161:2cc1468da177 591 * @note For Half-Duplex mode, Rx Direction is set by default.
<> 161:2cc1468da177 592 * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
<> 161:2cc1468da177 593 * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
<> 161:2cc1468da177 594 * CR1 BIDIMODE LL_SPI_SetTransferDirection\n
<> 161:2cc1468da177 595 * CR1 BIDIOE LL_SPI_SetTransferDirection
<> 161:2cc1468da177 596 * @param SPIx SPI Instance
<> 161:2cc1468da177 597 * @param TransferDirection This parameter can be one of the following values:
<> 161:2cc1468da177 598 * @arg @ref LL_SPI_FULL_DUPLEX
<> 161:2cc1468da177 599 * @arg @ref LL_SPI_SIMPLEX_RX
<> 161:2cc1468da177 600 * @arg @ref LL_SPI_HALF_DUPLEX_RX
<> 161:2cc1468da177 601 * @arg @ref LL_SPI_HALF_DUPLEX_TX
<> 161:2cc1468da177 602 * @retval None
<> 161:2cc1468da177 603 */
<> 161:2cc1468da177 604 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
<> 161:2cc1468da177 605 {
<> 161:2cc1468da177 606 MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
<> 161:2cc1468da177 607 }
<> 161:2cc1468da177 608
<> 161:2cc1468da177 609 /**
<> 161:2cc1468da177 610 * @brief Get transfer direction mode
<> 161:2cc1468da177 611 * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
<> 161:2cc1468da177 612 * CR1 BIDIMODE LL_SPI_GetTransferDirection\n
<> 161:2cc1468da177 613 * CR1 BIDIOE LL_SPI_GetTransferDirection
<> 161:2cc1468da177 614 * @param SPIx SPI Instance
<> 161:2cc1468da177 615 * @retval Returned value can be one of the following values:
<> 161:2cc1468da177 616 * @arg @ref LL_SPI_FULL_DUPLEX
<> 161:2cc1468da177 617 * @arg @ref LL_SPI_SIMPLEX_RX
<> 161:2cc1468da177 618 * @arg @ref LL_SPI_HALF_DUPLEX_RX
<> 161:2cc1468da177 619 * @arg @ref LL_SPI_HALF_DUPLEX_TX
<> 161:2cc1468da177 620 */
<> 161:2cc1468da177 621 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 622 {
<> 161:2cc1468da177 623 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
<> 161:2cc1468da177 624 }
<> 161:2cc1468da177 625
<> 161:2cc1468da177 626 /**
<> 161:2cc1468da177 627 * @brief Set frame data width
<> 161:2cc1468da177 628 * @rmtoll CR2 DS LL_SPI_SetDataWidth
<> 161:2cc1468da177 629 * @param SPIx SPI Instance
<> 161:2cc1468da177 630 * @param DataWidth This parameter can be one of the following values:
<> 161:2cc1468da177 631 * @arg @ref LL_SPI_DATAWIDTH_4BIT
<> 161:2cc1468da177 632 * @arg @ref LL_SPI_DATAWIDTH_5BIT
<> 161:2cc1468da177 633 * @arg @ref LL_SPI_DATAWIDTH_6BIT
<> 161:2cc1468da177 634 * @arg @ref LL_SPI_DATAWIDTH_7BIT
<> 161:2cc1468da177 635 * @arg @ref LL_SPI_DATAWIDTH_8BIT
<> 161:2cc1468da177 636 * @arg @ref LL_SPI_DATAWIDTH_9BIT
<> 161:2cc1468da177 637 * @arg @ref LL_SPI_DATAWIDTH_10BIT
<> 161:2cc1468da177 638 * @arg @ref LL_SPI_DATAWIDTH_11BIT
<> 161:2cc1468da177 639 * @arg @ref LL_SPI_DATAWIDTH_12BIT
<> 161:2cc1468da177 640 * @arg @ref LL_SPI_DATAWIDTH_13BIT
<> 161:2cc1468da177 641 * @arg @ref LL_SPI_DATAWIDTH_14BIT
<> 161:2cc1468da177 642 * @arg @ref LL_SPI_DATAWIDTH_15BIT
<> 161:2cc1468da177 643 * @arg @ref LL_SPI_DATAWIDTH_16BIT
<> 161:2cc1468da177 644 * @retval None
<> 161:2cc1468da177 645 */
<> 161:2cc1468da177 646 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
<> 161:2cc1468da177 647 {
<> 161:2cc1468da177 648 MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
<> 161:2cc1468da177 649 }
<> 161:2cc1468da177 650
<> 161:2cc1468da177 651 /**
<> 161:2cc1468da177 652 * @brief Get frame data width
<> 161:2cc1468da177 653 * @rmtoll CR2 DS LL_SPI_GetDataWidth
<> 161:2cc1468da177 654 * @param SPIx SPI Instance
<> 161:2cc1468da177 655 * @retval Returned value can be one of the following values:
<> 161:2cc1468da177 656 * @arg @ref LL_SPI_DATAWIDTH_4BIT
<> 161:2cc1468da177 657 * @arg @ref LL_SPI_DATAWIDTH_5BIT
<> 161:2cc1468da177 658 * @arg @ref LL_SPI_DATAWIDTH_6BIT
<> 161:2cc1468da177 659 * @arg @ref LL_SPI_DATAWIDTH_7BIT
<> 161:2cc1468da177 660 * @arg @ref LL_SPI_DATAWIDTH_8BIT
<> 161:2cc1468da177 661 * @arg @ref LL_SPI_DATAWIDTH_9BIT
<> 161:2cc1468da177 662 * @arg @ref LL_SPI_DATAWIDTH_10BIT
<> 161:2cc1468da177 663 * @arg @ref LL_SPI_DATAWIDTH_11BIT
<> 161:2cc1468da177 664 * @arg @ref LL_SPI_DATAWIDTH_12BIT
<> 161:2cc1468da177 665 * @arg @ref LL_SPI_DATAWIDTH_13BIT
<> 161:2cc1468da177 666 * @arg @ref LL_SPI_DATAWIDTH_14BIT
<> 161:2cc1468da177 667 * @arg @ref LL_SPI_DATAWIDTH_15BIT
<> 161:2cc1468da177 668 * @arg @ref LL_SPI_DATAWIDTH_16BIT
<> 161:2cc1468da177 669 */
<> 161:2cc1468da177 670 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 671 {
<> 161:2cc1468da177 672 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
<> 161:2cc1468da177 673 }
<> 161:2cc1468da177 674
<> 161:2cc1468da177 675 /**
<> 161:2cc1468da177 676 * @brief Set threshold of RXFIFO that triggers an RXNE event
<> 161:2cc1468da177 677 * @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold
<> 161:2cc1468da177 678 * @param SPIx SPI Instance
<> 161:2cc1468da177 679 * @param Threshold This parameter can be one of the following values:
<> 161:2cc1468da177 680 * @arg @ref LL_SPI_RX_FIFO_TH_HALF
<> 161:2cc1468da177 681 * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
<> 161:2cc1468da177 682 * @retval None
<> 161:2cc1468da177 683 */
<> 161:2cc1468da177 684 __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
<> 161:2cc1468da177 685 {
<> 161:2cc1468da177 686 MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
<> 161:2cc1468da177 687 }
<> 161:2cc1468da177 688
<> 161:2cc1468da177 689 /**
<> 161:2cc1468da177 690 * @brief Get threshold of RXFIFO that triggers an RXNE event
<> 161:2cc1468da177 691 * @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold
<> 161:2cc1468da177 692 * @param SPIx SPI Instance
<> 161:2cc1468da177 693 * @retval Returned value can be one of the following values:
<> 161:2cc1468da177 694 * @arg @ref LL_SPI_RX_FIFO_TH_HALF
<> 161:2cc1468da177 695 * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
<> 161:2cc1468da177 696 */
<> 161:2cc1468da177 697 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 698 {
<> 161:2cc1468da177 699 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
<> 161:2cc1468da177 700 }
<> 161:2cc1468da177 701
<> 161:2cc1468da177 702 /**
<> 161:2cc1468da177 703 * @}
<> 161:2cc1468da177 704 */
<> 161:2cc1468da177 705
<> 161:2cc1468da177 706 /** @defgroup SPI_LL_EF_CRC_Management CRC Management
<> 161:2cc1468da177 707 * @{
<> 161:2cc1468da177 708 */
<> 161:2cc1468da177 709
<> 161:2cc1468da177 710 /**
<> 161:2cc1468da177 711 * @brief Enable CRC
<> 161:2cc1468da177 712 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
<> 161:2cc1468da177 713 * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
<> 161:2cc1468da177 714 * @param SPIx SPI Instance
<> 161:2cc1468da177 715 * @retval None
<> 161:2cc1468da177 716 */
<> 161:2cc1468da177 717 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 718 {
<> 161:2cc1468da177 719 SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
<> 161:2cc1468da177 720 }
<> 161:2cc1468da177 721
<> 161:2cc1468da177 722 /**
<> 161:2cc1468da177 723 * @brief Disable CRC
<> 161:2cc1468da177 724 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
<> 161:2cc1468da177 725 * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
<> 161:2cc1468da177 726 * @param SPIx SPI Instance
<> 161:2cc1468da177 727 * @retval None
<> 161:2cc1468da177 728 */
<> 161:2cc1468da177 729 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 730 {
<> 161:2cc1468da177 731 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
<> 161:2cc1468da177 732 }
<> 161:2cc1468da177 733
<> 161:2cc1468da177 734 /**
<> 161:2cc1468da177 735 * @brief Check if CRC is enabled
<> 161:2cc1468da177 736 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
<> 161:2cc1468da177 737 * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
<> 161:2cc1468da177 738 * @param SPIx SPI Instance
<> 161:2cc1468da177 739 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 740 */
<> 161:2cc1468da177 741 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 742 {
<> 161:2cc1468da177 743 return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
<> 161:2cc1468da177 744 }
<> 161:2cc1468da177 745
<> 161:2cc1468da177 746 /**
<> 161:2cc1468da177 747 * @brief Set CRC Length
<> 161:2cc1468da177 748 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
<> 161:2cc1468da177 749 * @rmtoll CR1 CRCL LL_SPI_SetCRCWidth
<> 161:2cc1468da177 750 * @param SPIx SPI Instance
<> 161:2cc1468da177 751 * @param CRCLength This parameter can be one of the following values:
<> 161:2cc1468da177 752 * @arg @ref LL_SPI_CRC_8BIT
<> 161:2cc1468da177 753 * @arg @ref LL_SPI_CRC_16BIT
<> 161:2cc1468da177 754 * @retval None
<> 161:2cc1468da177 755 */
<> 161:2cc1468da177 756 __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
<> 161:2cc1468da177 757 {
<> 161:2cc1468da177 758 MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
<> 161:2cc1468da177 759 }
<> 161:2cc1468da177 760
<> 161:2cc1468da177 761 /**
<> 161:2cc1468da177 762 * @brief Get CRC Length
<> 161:2cc1468da177 763 * @rmtoll CR1 CRCL LL_SPI_GetCRCWidth
<> 161:2cc1468da177 764 * @param SPIx SPI Instance
<> 161:2cc1468da177 765 * @retval Returned value can be one of the following values:
<> 161:2cc1468da177 766 * @arg @ref LL_SPI_CRC_8BIT
<> 161:2cc1468da177 767 * @arg @ref LL_SPI_CRC_16BIT
<> 161:2cc1468da177 768 */
<> 161:2cc1468da177 769 __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 770 {
<> 161:2cc1468da177 771 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
<> 161:2cc1468da177 772 }
<> 161:2cc1468da177 773
<> 161:2cc1468da177 774 /**
<> 161:2cc1468da177 775 * @brief Set CRCNext to transfer CRC on the line
<> 161:2cc1468da177 776 * @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
<> 161:2cc1468da177 777 * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
<> 161:2cc1468da177 778 * @param SPIx SPI Instance
<> 161:2cc1468da177 779 * @retval None
<> 161:2cc1468da177 780 */
<> 161:2cc1468da177 781 __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 782 {
<> 161:2cc1468da177 783 SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
<> 161:2cc1468da177 784 }
<> 161:2cc1468da177 785
<> 161:2cc1468da177 786 /**
<> 161:2cc1468da177 787 * @brief Set polynomial for CRC calculation
<> 161:2cc1468da177 788 * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
<> 161:2cc1468da177 789 * @param SPIx SPI Instance
<> 161:2cc1468da177 790 * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
<> 161:2cc1468da177 791 * @retval None
<> 161:2cc1468da177 792 */
<> 161:2cc1468da177 793 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
<> 161:2cc1468da177 794 {
<> 161:2cc1468da177 795 WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
<> 161:2cc1468da177 796 }
<> 161:2cc1468da177 797
<> 161:2cc1468da177 798 /**
<> 161:2cc1468da177 799 * @brief Get polynomial for CRC calculation
<> 161:2cc1468da177 800 * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
<> 161:2cc1468da177 801 * @param SPIx SPI Instance
<> 161:2cc1468da177 802 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
<> 161:2cc1468da177 803 */
<> 161:2cc1468da177 804 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 805 {
<> 161:2cc1468da177 806 return (uint32_t)(READ_REG(SPIx->CRCPR));
<> 161:2cc1468da177 807 }
<> 161:2cc1468da177 808
<> 161:2cc1468da177 809 /**
<> 161:2cc1468da177 810 * @brief Get Rx CRC
<> 161:2cc1468da177 811 * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
<> 161:2cc1468da177 812 * @param SPIx SPI Instance
<> 161:2cc1468da177 813 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
<> 161:2cc1468da177 814 */
<> 161:2cc1468da177 815 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 816 {
<> 161:2cc1468da177 817 return (uint32_t)(READ_REG(SPIx->RXCRCR));
<> 161:2cc1468da177 818 }
<> 161:2cc1468da177 819
<> 161:2cc1468da177 820 /**
<> 161:2cc1468da177 821 * @brief Get Tx CRC
<> 161:2cc1468da177 822 * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
<> 161:2cc1468da177 823 * @param SPIx SPI Instance
<> 161:2cc1468da177 824 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
<> 161:2cc1468da177 825 */
<> 161:2cc1468da177 826 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 827 {
<> 161:2cc1468da177 828 return (uint32_t)(READ_REG(SPIx->TXCRCR));
<> 161:2cc1468da177 829 }
<> 161:2cc1468da177 830
<> 161:2cc1468da177 831 /**
<> 161:2cc1468da177 832 * @}
<> 161:2cc1468da177 833 */
<> 161:2cc1468da177 834
<> 161:2cc1468da177 835 /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
<> 161:2cc1468da177 836 * @{
<> 161:2cc1468da177 837 */
<> 161:2cc1468da177 838
<> 161:2cc1468da177 839 /**
<> 161:2cc1468da177 840 * @brief Set NSS mode
<> 161:2cc1468da177 841 * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
<> 161:2cc1468da177 842 * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
<> 161:2cc1468da177 843 * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
<> 161:2cc1468da177 844 * @param SPIx SPI Instance
<> 161:2cc1468da177 845 * @param NSS This parameter can be one of the following values:
<> 161:2cc1468da177 846 * @arg @ref LL_SPI_NSS_SOFT
<> 161:2cc1468da177 847 * @arg @ref LL_SPI_NSS_HARD_INPUT
<> 161:2cc1468da177 848 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
<> 161:2cc1468da177 849 * @retval None
<> 161:2cc1468da177 850 */
<> 161:2cc1468da177 851 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
<> 161:2cc1468da177 852 {
<> 161:2cc1468da177 853 MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
<> 161:2cc1468da177 854 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
<> 161:2cc1468da177 855 }
<> 161:2cc1468da177 856
<> 161:2cc1468da177 857 /**
<> 161:2cc1468da177 858 * @brief Get NSS mode
<> 161:2cc1468da177 859 * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
<> 161:2cc1468da177 860 * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
<> 161:2cc1468da177 861 * @param SPIx SPI Instance
<> 161:2cc1468da177 862 * @retval Returned value can be one of the following values:
<> 161:2cc1468da177 863 * @arg @ref LL_SPI_NSS_SOFT
<> 161:2cc1468da177 864 * @arg @ref LL_SPI_NSS_HARD_INPUT
<> 161:2cc1468da177 865 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
<> 161:2cc1468da177 866 */
<> 161:2cc1468da177 867 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 868 {
<> 161:2cc1468da177 869 register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
<> 161:2cc1468da177 870 register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
<> 161:2cc1468da177 871 return (Ssm | Ssoe);
<> 161:2cc1468da177 872 }
<> 161:2cc1468da177 873
<> 161:2cc1468da177 874 /**
<> 161:2cc1468da177 875 * @brief Enable NSS pulse management
<> 161:2cc1468da177 876 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
<> 161:2cc1468da177 877 * @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt
<> 161:2cc1468da177 878 * @param SPIx SPI Instance
<> 161:2cc1468da177 879 * @retval None
<> 161:2cc1468da177 880 */
<> 161:2cc1468da177 881 __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 882 {
<> 161:2cc1468da177 883 SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
<> 161:2cc1468da177 884 }
<> 161:2cc1468da177 885
<> 161:2cc1468da177 886 /**
<> 161:2cc1468da177 887 * @brief Disable NSS pulse management
<> 161:2cc1468da177 888 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
<> 161:2cc1468da177 889 * @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt
<> 161:2cc1468da177 890 * @param SPIx SPI Instance
<> 161:2cc1468da177 891 * @retval None
<> 161:2cc1468da177 892 */
<> 161:2cc1468da177 893 __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 894 {
<> 161:2cc1468da177 895 CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
<> 161:2cc1468da177 896 }
<> 161:2cc1468da177 897
<> 161:2cc1468da177 898 /**
<> 161:2cc1468da177 899 * @brief Check if NSS pulse is enabled
<> 161:2cc1468da177 900 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
<> 161:2cc1468da177 901 * @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse
<> 161:2cc1468da177 902 * @param SPIx SPI Instance
<> 161:2cc1468da177 903 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 904 */
<> 161:2cc1468da177 905 __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 906 {
<> 161:2cc1468da177 907 return (READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP));
<> 161:2cc1468da177 908 }
<> 161:2cc1468da177 909
<> 161:2cc1468da177 910 /**
<> 161:2cc1468da177 911 * @}
<> 161:2cc1468da177 912 */
<> 161:2cc1468da177 913
<> 161:2cc1468da177 914 /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
<> 161:2cc1468da177 915 * @{
<> 161:2cc1468da177 916 */
<> 161:2cc1468da177 917
<> 161:2cc1468da177 918 /**
<> 161:2cc1468da177 919 * @brief Check if Rx buffer is not empty
<> 161:2cc1468da177 920 * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
<> 161:2cc1468da177 921 * @param SPIx SPI Instance
<> 161:2cc1468da177 922 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 923 */
<> 161:2cc1468da177 924 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 925 {
<> 161:2cc1468da177 926 return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
<> 161:2cc1468da177 927 }
<> 161:2cc1468da177 928
<> 161:2cc1468da177 929 /**
<> 161:2cc1468da177 930 * @brief Check if Tx buffer is empty
<> 161:2cc1468da177 931 * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
<> 161:2cc1468da177 932 * @param SPIx SPI Instance
<> 161:2cc1468da177 933 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 934 */
<> 161:2cc1468da177 935 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 936 {
<> 161:2cc1468da177 937 return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
<> 161:2cc1468da177 938 }
<> 161:2cc1468da177 939
<> 161:2cc1468da177 940 /**
<> 161:2cc1468da177 941 * @brief Get CRC error flag
<> 161:2cc1468da177 942 * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
<> 161:2cc1468da177 943 * @param SPIx SPI Instance
<> 161:2cc1468da177 944 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 945 */
<> 161:2cc1468da177 946 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 947 {
<> 161:2cc1468da177 948 return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
<> 161:2cc1468da177 949 }
<> 161:2cc1468da177 950
<> 161:2cc1468da177 951 /**
<> 161:2cc1468da177 952 * @brief Get mode fault error flag
<> 161:2cc1468da177 953 * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
<> 161:2cc1468da177 954 * @param SPIx SPI Instance
<> 161:2cc1468da177 955 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 956 */
<> 161:2cc1468da177 957 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 958 {
<> 161:2cc1468da177 959 return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
<> 161:2cc1468da177 960 }
<> 161:2cc1468da177 961
<> 161:2cc1468da177 962 /**
<> 161:2cc1468da177 963 * @brief Get overrun error flag
<> 161:2cc1468da177 964 * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
<> 161:2cc1468da177 965 * @param SPIx SPI Instance
<> 161:2cc1468da177 966 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 967 */
<> 161:2cc1468da177 968 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 969 {
<> 161:2cc1468da177 970 return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
<> 161:2cc1468da177 971 }
<> 161:2cc1468da177 972
<> 161:2cc1468da177 973 /**
<> 161:2cc1468da177 974 * @brief Get busy flag
<> 161:2cc1468da177 975 * @note The BSY flag is cleared under any one of the following conditions:
<> 161:2cc1468da177 976 * -When the SPI is correctly disabled
<> 161:2cc1468da177 977 * -When a fault is detected in Master mode (MODF bit set to 1)
<> 161:2cc1468da177 978 * -In Master mode, when it finishes a data transmission and no new data is ready to be
<> 161:2cc1468da177 979 * sent
<> 161:2cc1468da177 980 * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
<> 161:2cc1468da177 981 * each data transfer.
<> 161:2cc1468da177 982 * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
<> 161:2cc1468da177 983 * @param SPIx SPI Instance
<> 161:2cc1468da177 984 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 985 */
<> 161:2cc1468da177 986 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 987 {
<> 161:2cc1468da177 988 return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
<> 161:2cc1468da177 989 }
<> 161:2cc1468da177 990
<> 161:2cc1468da177 991 /**
<> 161:2cc1468da177 992 * @brief Get frame format error flag
<> 161:2cc1468da177 993 * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
<> 161:2cc1468da177 994 * @param SPIx SPI Instance
<> 161:2cc1468da177 995 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 996 */
<> 161:2cc1468da177 997 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 998 {
<> 161:2cc1468da177 999 return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
<> 161:2cc1468da177 1000 }
<> 161:2cc1468da177 1001
<> 161:2cc1468da177 1002 /**
<> 161:2cc1468da177 1003 * @brief Get FIFO reception Level
<> 161:2cc1468da177 1004 * @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel
<> 161:2cc1468da177 1005 * @param SPIx SPI Instance
<> 161:2cc1468da177 1006 * @retval Returned value can be one of the following values:
<> 161:2cc1468da177 1007 * @arg @ref LL_SPI_RX_FIFO_EMPTY
<> 161:2cc1468da177 1008 * @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
<> 161:2cc1468da177 1009 * @arg @ref LL_SPI_RX_FIFO_HALF_FULL
<> 161:2cc1468da177 1010 * @arg @ref LL_SPI_RX_FIFO_FULL
<> 161:2cc1468da177 1011 */
<> 161:2cc1468da177 1012 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1013 {
<> 161:2cc1468da177 1014 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
<> 161:2cc1468da177 1015 }
<> 161:2cc1468da177 1016
<> 161:2cc1468da177 1017 /**
<> 161:2cc1468da177 1018 * @brief Get FIFO Transmission Level
<> 161:2cc1468da177 1019 * @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel
<> 161:2cc1468da177 1020 * @param SPIx SPI Instance
<> 161:2cc1468da177 1021 * @retval Returned value can be one of the following values:
<> 161:2cc1468da177 1022 * @arg @ref LL_SPI_TX_FIFO_EMPTY
<> 161:2cc1468da177 1023 * @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
<> 161:2cc1468da177 1024 * @arg @ref LL_SPI_TX_FIFO_HALF_FULL
<> 161:2cc1468da177 1025 * @arg @ref LL_SPI_TX_FIFO_FULL
<> 161:2cc1468da177 1026 */
<> 161:2cc1468da177 1027 __STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1028 {
<> 161:2cc1468da177 1029 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
<> 161:2cc1468da177 1030 }
<> 161:2cc1468da177 1031
<> 161:2cc1468da177 1032 /**
<> 161:2cc1468da177 1033 * @brief Clear CRC error flag
<> 161:2cc1468da177 1034 * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
<> 161:2cc1468da177 1035 * @param SPIx SPI Instance
<> 161:2cc1468da177 1036 * @retval None
<> 161:2cc1468da177 1037 */
<> 161:2cc1468da177 1038 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1039 {
<> 161:2cc1468da177 1040 CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
<> 161:2cc1468da177 1041 }
<> 161:2cc1468da177 1042
<> 161:2cc1468da177 1043 /**
<> 161:2cc1468da177 1044 * @brief Clear mode fault error flag
<> 161:2cc1468da177 1045 * @note Clearing this flag is done by a read access to the SPIx_SR
<> 161:2cc1468da177 1046 * register followed by a write access to the SPIx_CR1 register
<> 161:2cc1468da177 1047 * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
<> 161:2cc1468da177 1048 * @param SPIx SPI Instance
<> 161:2cc1468da177 1049 * @retval None
<> 161:2cc1468da177 1050 */
<> 161:2cc1468da177 1051 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1052 {
<> 161:2cc1468da177 1053 __IO uint32_t tmpreg;
<> 161:2cc1468da177 1054 tmpreg = SPIx->SR;
<> 161:2cc1468da177 1055 (void) tmpreg;
<> 161:2cc1468da177 1056 tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
<> 161:2cc1468da177 1057 (void) tmpreg;
<> 161:2cc1468da177 1058 }
<> 161:2cc1468da177 1059
<> 161:2cc1468da177 1060 /**
<> 161:2cc1468da177 1061 * @brief Clear overrun error flag
<> 161:2cc1468da177 1062 * @note Clearing this flag is done by a read access to the SPIx_DR
<> 161:2cc1468da177 1063 * register followed by a read access to the SPIx_SR register
<> 161:2cc1468da177 1064 * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
<> 161:2cc1468da177 1065 * @param SPIx SPI Instance
<> 161:2cc1468da177 1066 * @retval None
<> 161:2cc1468da177 1067 */
<> 161:2cc1468da177 1068 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1069 {
<> 161:2cc1468da177 1070 __IO uint32_t tmpreg;
<> 161:2cc1468da177 1071 tmpreg = SPIx->DR;
<> 161:2cc1468da177 1072 (void) tmpreg;
<> 161:2cc1468da177 1073 tmpreg = SPIx->SR;
<> 161:2cc1468da177 1074 (void) tmpreg;
<> 161:2cc1468da177 1075 }
<> 161:2cc1468da177 1076
<> 161:2cc1468da177 1077 /**
<> 161:2cc1468da177 1078 * @brief Clear frame format error flag
<> 161:2cc1468da177 1079 * @note Clearing this flag is done by reading SPIx_SR register
<> 161:2cc1468da177 1080 * @rmtoll SR FRE LL_SPI_ClearFlag_FRE
<> 161:2cc1468da177 1081 * @param SPIx SPI Instance
<> 161:2cc1468da177 1082 * @retval None
<> 161:2cc1468da177 1083 */
<> 161:2cc1468da177 1084 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1085 {
<> 161:2cc1468da177 1086 __IO uint32_t tmpreg;
<> 161:2cc1468da177 1087 tmpreg = SPIx->SR;
<> 161:2cc1468da177 1088 (void) tmpreg;
<> 161:2cc1468da177 1089 }
<> 161:2cc1468da177 1090
<> 161:2cc1468da177 1091 /**
<> 161:2cc1468da177 1092 * @}
<> 161:2cc1468da177 1093 */
<> 161:2cc1468da177 1094
<> 161:2cc1468da177 1095 /** @defgroup SPI_LL_EF_IT_Management Interrupt Management
<> 161:2cc1468da177 1096 * @{
<> 161:2cc1468da177 1097 */
<> 161:2cc1468da177 1098
<> 161:2cc1468da177 1099 /**
<> 161:2cc1468da177 1100 * @brief Enable error interrupt
<> 161:2cc1468da177 1101 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
<> 161:2cc1468da177 1102 * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
<> 161:2cc1468da177 1103 * @param SPIx SPI Instance
<> 161:2cc1468da177 1104 * @retval None
<> 161:2cc1468da177 1105 */
<> 161:2cc1468da177 1106 __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1107 {
<> 161:2cc1468da177 1108 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
<> 161:2cc1468da177 1109 }
<> 161:2cc1468da177 1110
<> 161:2cc1468da177 1111 /**
<> 161:2cc1468da177 1112 * @brief Enable Rx buffer not empty interrupt
<> 161:2cc1468da177 1113 * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
<> 161:2cc1468da177 1114 * @param SPIx SPI Instance
<> 161:2cc1468da177 1115 * @retval None
<> 161:2cc1468da177 1116 */
<> 161:2cc1468da177 1117 __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1118 {
<> 161:2cc1468da177 1119 SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
<> 161:2cc1468da177 1120 }
<> 161:2cc1468da177 1121
<> 161:2cc1468da177 1122 /**
<> 161:2cc1468da177 1123 * @brief Enable Tx buffer empty interrupt
<> 161:2cc1468da177 1124 * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
<> 161:2cc1468da177 1125 * @param SPIx SPI Instance
<> 161:2cc1468da177 1126 * @retval None
<> 161:2cc1468da177 1127 */
<> 161:2cc1468da177 1128 __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1129 {
<> 161:2cc1468da177 1130 SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
<> 161:2cc1468da177 1131 }
<> 161:2cc1468da177 1132
<> 161:2cc1468da177 1133 /**
<> 161:2cc1468da177 1134 * @brief Disable error interrupt
<> 161:2cc1468da177 1135 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
<> 161:2cc1468da177 1136 * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
<> 161:2cc1468da177 1137 * @param SPIx SPI Instance
<> 161:2cc1468da177 1138 * @retval None
<> 161:2cc1468da177 1139 */
<> 161:2cc1468da177 1140 __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1141 {
<> 161:2cc1468da177 1142 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
<> 161:2cc1468da177 1143 }
<> 161:2cc1468da177 1144
<> 161:2cc1468da177 1145 /**
<> 161:2cc1468da177 1146 * @brief Disable Rx buffer not empty interrupt
<> 161:2cc1468da177 1147 * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
<> 161:2cc1468da177 1148 * @param SPIx SPI Instance
<> 161:2cc1468da177 1149 * @retval None
<> 161:2cc1468da177 1150 */
<> 161:2cc1468da177 1151 __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1152 {
<> 161:2cc1468da177 1153 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
<> 161:2cc1468da177 1154 }
<> 161:2cc1468da177 1155
<> 161:2cc1468da177 1156 /**
<> 161:2cc1468da177 1157 * @brief Disable Tx buffer empty interrupt
<> 161:2cc1468da177 1158 * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
<> 161:2cc1468da177 1159 * @param SPIx SPI Instance
<> 161:2cc1468da177 1160 * @retval None
<> 161:2cc1468da177 1161 */
<> 161:2cc1468da177 1162 __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1163 {
<> 161:2cc1468da177 1164 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
<> 161:2cc1468da177 1165 }
<> 161:2cc1468da177 1166
<> 161:2cc1468da177 1167 /**
<> 161:2cc1468da177 1168 * @brief Check if error interrupt is enabled
<> 161:2cc1468da177 1169 * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
<> 161:2cc1468da177 1170 * @param SPIx SPI Instance
<> 161:2cc1468da177 1171 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 1172 */
<> 161:2cc1468da177 1173 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1174 {
<> 161:2cc1468da177 1175 return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
<> 161:2cc1468da177 1176 }
<> 161:2cc1468da177 1177
<> 161:2cc1468da177 1178 /**
<> 161:2cc1468da177 1179 * @brief Check if Rx buffer not empty interrupt is enabled
<> 161:2cc1468da177 1180 * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
<> 161:2cc1468da177 1181 * @param SPIx SPI Instance
<> 161:2cc1468da177 1182 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 1183 */
<> 161:2cc1468da177 1184 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1185 {
<> 161:2cc1468da177 1186 return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
<> 161:2cc1468da177 1187 }
<> 161:2cc1468da177 1188
<> 161:2cc1468da177 1189 /**
<> 161:2cc1468da177 1190 * @brief Check if Tx buffer empty interrupt
<> 161:2cc1468da177 1191 * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
<> 161:2cc1468da177 1192 * @param SPIx SPI Instance
<> 161:2cc1468da177 1193 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 1194 */
<> 161:2cc1468da177 1195 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1196 {
<> 161:2cc1468da177 1197 return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
<> 161:2cc1468da177 1198 }
<> 161:2cc1468da177 1199
<> 161:2cc1468da177 1200 /**
<> 161:2cc1468da177 1201 * @}
<> 161:2cc1468da177 1202 */
<> 161:2cc1468da177 1203
<> 161:2cc1468da177 1204 /** @defgroup SPI_LL_EF_DMA_Management DMA Management
<> 161:2cc1468da177 1205 * @{
<> 161:2cc1468da177 1206 */
<> 161:2cc1468da177 1207
<> 161:2cc1468da177 1208 /**
<> 161:2cc1468da177 1209 * @brief Enable DMA Rx
<> 161:2cc1468da177 1210 * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
<> 161:2cc1468da177 1211 * @param SPIx SPI Instance
<> 161:2cc1468da177 1212 * @retval None
<> 161:2cc1468da177 1213 */
<> 161:2cc1468da177 1214 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1215 {
<> 161:2cc1468da177 1216 SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
<> 161:2cc1468da177 1217 }
<> 161:2cc1468da177 1218
<> 161:2cc1468da177 1219 /**
<> 161:2cc1468da177 1220 * @brief Disable DMA Rx
<> 161:2cc1468da177 1221 * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
<> 161:2cc1468da177 1222 * @param SPIx SPI Instance
<> 161:2cc1468da177 1223 * @retval None
<> 161:2cc1468da177 1224 */
<> 161:2cc1468da177 1225 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1226 {
<> 161:2cc1468da177 1227 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
<> 161:2cc1468da177 1228 }
<> 161:2cc1468da177 1229
<> 161:2cc1468da177 1230 /**
<> 161:2cc1468da177 1231 * @brief Check if DMA Rx is enabled
<> 161:2cc1468da177 1232 * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
<> 161:2cc1468da177 1233 * @param SPIx SPI Instance
<> 161:2cc1468da177 1234 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 1235 */
<> 161:2cc1468da177 1236 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1237 {
<> 161:2cc1468da177 1238 return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
<> 161:2cc1468da177 1239 }
<> 161:2cc1468da177 1240
<> 161:2cc1468da177 1241 /**
<> 161:2cc1468da177 1242 * @brief Enable DMA Tx
<> 161:2cc1468da177 1243 * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
<> 161:2cc1468da177 1244 * @param SPIx SPI Instance
<> 161:2cc1468da177 1245 * @retval None
<> 161:2cc1468da177 1246 */
<> 161:2cc1468da177 1247 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1248 {
<> 161:2cc1468da177 1249 SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
<> 161:2cc1468da177 1250 }
<> 161:2cc1468da177 1251
<> 161:2cc1468da177 1252 /**
<> 161:2cc1468da177 1253 * @brief Disable DMA Tx
<> 161:2cc1468da177 1254 * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
<> 161:2cc1468da177 1255 * @param SPIx SPI Instance
<> 161:2cc1468da177 1256 * @retval None
<> 161:2cc1468da177 1257 */
<> 161:2cc1468da177 1258 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1259 {
<> 161:2cc1468da177 1260 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
<> 161:2cc1468da177 1261 }
<> 161:2cc1468da177 1262
<> 161:2cc1468da177 1263 /**
<> 161:2cc1468da177 1264 * @brief Check if DMA Tx is enabled
<> 161:2cc1468da177 1265 * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
<> 161:2cc1468da177 1266 * @param SPIx SPI Instance
<> 161:2cc1468da177 1267 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 1268 */
<> 161:2cc1468da177 1269 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1270 {
<> 161:2cc1468da177 1271 return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
<> 161:2cc1468da177 1272 }
<> 161:2cc1468da177 1273
<> 161:2cc1468da177 1274 /**
<> 161:2cc1468da177 1275 * @brief Set parity of Last DMA reception
<> 161:2cc1468da177 1276 * @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX
<> 161:2cc1468da177 1277 * @param SPIx SPI Instance
<> 161:2cc1468da177 1278 * @param Parity This parameter can be one of the following values:
<> 161:2cc1468da177 1279 * @arg @ref LL_SPI_DMA_PARITY_ODD
<> 161:2cc1468da177 1280 * @arg @ref LL_SPI_DMA_PARITY_EVEN
<> 161:2cc1468da177 1281 * @retval None
<> 161:2cc1468da177 1282 */
<> 161:2cc1468da177 1283 __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
<> 161:2cc1468da177 1284 {
<> 161:2cc1468da177 1285 MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
<> 161:2cc1468da177 1286 }
<> 161:2cc1468da177 1287
<> 161:2cc1468da177 1288 /**
<> 161:2cc1468da177 1289 * @brief Get parity configuration for Last DMA reception
<> 161:2cc1468da177 1290 * @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX
<> 161:2cc1468da177 1291 * @param SPIx SPI Instance
<> 161:2cc1468da177 1292 * @retval Returned value can be one of the following values:
<> 161:2cc1468da177 1293 * @arg @ref LL_SPI_DMA_PARITY_ODD
<> 161:2cc1468da177 1294 * @arg @ref LL_SPI_DMA_PARITY_EVEN
<> 161:2cc1468da177 1295 */
<> 161:2cc1468da177 1296 __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1297 {
<> 161:2cc1468da177 1298 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
<> 161:2cc1468da177 1299 }
<> 161:2cc1468da177 1300
<> 161:2cc1468da177 1301 /**
<> 161:2cc1468da177 1302 * @brief Set parity of Last DMA transmission
<> 161:2cc1468da177 1303 * @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX
<> 161:2cc1468da177 1304 * @param SPIx SPI Instance
<> 161:2cc1468da177 1305 * @param Parity This parameter can be one of the following values:
<> 161:2cc1468da177 1306 * @arg @ref LL_SPI_DMA_PARITY_ODD
<> 161:2cc1468da177 1307 * @arg @ref LL_SPI_DMA_PARITY_EVEN
<> 161:2cc1468da177 1308 * @retval None
<> 161:2cc1468da177 1309 */
<> 161:2cc1468da177 1310 __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
<> 161:2cc1468da177 1311 {
<> 161:2cc1468da177 1312 MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
<> 161:2cc1468da177 1313 }
<> 161:2cc1468da177 1314
<> 161:2cc1468da177 1315 /**
<> 161:2cc1468da177 1316 * @brief Get parity configuration for Last DMA transmission
<> 161:2cc1468da177 1317 * @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX
<> 161:2cc1468da177 1318 * @param SPIx SPI Instance
<> 161:2cc1468da177 1319 * @retval Returned value can be one of the following values:
<> 161:2cc1468da177 1320 * @arg @ref LL_SPI_DMA_PARITY_ODD
<> 161:2cc1468da177 1321 * @arg @ref LL_SPI_DMA_PARITY_EVEN
<> 161:2cc1468da177 1322 */
<> 161:2cc1468da177 1323 __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1324 {
<> 161:2cc1468da177 1325 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
<> 161:2cc1468da177 1326 }
<> 161:2cc1468da177 1327
<> 161:2cc1468da177 1328 /**
<> 161:2cc1468da177 1329 * @brief Get the data register address used for DMA transfer
<> 161:2cc1468da177 1330 * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
<> 161:2cc1468da177 1331 * @param SPIx SPI Instance
<> 161:2cc1468da177 1332 * @retval Address of data register
<> 161:2cc1468da177 1333 */
<> 161:2cc1468da177 1334 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1335 {
<> 161:2cc1468da177 1336 return (uint32_t) & (SPIx->DR);
<> 161:2cc1468da177 1337 }
<> 161:2cc1468da177 1338
<> 161:2cc1468da177 1339 /**
<> 161:2cc1468da177 1340 * @}
<> 161:2cc1468da177 1341 */
<> 161:2cc1468da177 1342
<> 161:2cc1468da177 1343 /** @defgroup SPI_LL_EF_DATA_Management DATA Management
<> 161:2cc1468da177 1344 * @{
<> 161:2cc1468da177 1345 */
<> 161:2cc1468da177 1346
<> 161:2cc1468da177 1347 /**
<> 161:2cc1468da177 1348 * @brief Read 8-Bits in the data register
<> 161:2cc1468da177 1349 * @rmtoll DR DR LL_SPI_ReceiveData8
<> 161:2cc1468da177 1350 * @param SPIx SPI Instance
<> 161:2cc1468da177 1351 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
<> 161:2cc1468da177 1352 */
<> 161:2cc1468da177 1353 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1354 {
<> 161:2cc1468da177 1355 return (uint8_t)(READ_REG(SPIx->DR));
<> 161:2cc1468da177 1356 }
<> 161:2cc1468da177 1357
<> 161:2cc1468da177 1358 /**
<> 161:2cc1468da177 1359 * @brief Read 16-Bits in the data register
<> 161:2cc1468da177 1360 * @rmtoll DR DR LL_SPI_ReceiveData16
<> 161:2cc1468da177 1361 * @param SPIx SPI Instance
<> 161:2cc1468da177 1362 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
<> 161:2cc1468da177 1363 */
<> 161:2cc1468da177 1364 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1365 {
<> 161:2cc1468da177 1366 return (uint16_t)(READ_REG(SPIx->DR));
<> 161:2cc1468da177 1367 }
<> 161:2cc1468da177 1368
<> 161:2cc1468da177 1369 /**
<> 161:2cc1468da177 1370 * @brief Write 8-Bits in the data register
<> 161:2cc1468da177 1371 * @rmtoll DR DR LL_SPI_TransmitData8
<> 161:2cc1468da177 1372 * @param SPIx SPI Instance
<> 161:2cc1468da177 1373 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
<> 161:2cc1468da177 1374 * @retval None
<> 161:2cc1468da177 1375 */
<> 161:2cc1468da177 1376 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
<> 161:2cc1468da177 1377 {
<> 161:2cc1468da177 1378 *((__IO uint8_t *)&SPIx->DR) = TxData;
<> 161:2cc1468da177 1379 }
<> 161:2cc1468da177 1380
<> 161:2cc1468da177 1381 /**
<> 161:2cc1468da177 1382 * @brief Write 16-Bits in the data register
<> 161:2cc1468da177 1383 * @rmtoll DR DR LL_SPI_TransmitData16
<> 161:2cc1468da177 1384 * @param SPIx SPI Instance
<> 161:2cc1468da177 1385 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
<> 161:2cc1468da177 1386 * @retval None
<> 161:2cc1468da177 1387 */
<> 161:2cc1468da177 1388 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
<> 161:2cc1468da177 1389 {
<> 161:2cc1468da177 1390 *((__IO uint16_t *)&SPIx->DR) = TxData;
<> 161:2cc1468da177 1391 }
<> 161:2cc1468da177 1392
<> 161:2cc1468da177 1393 /**
<> 161:2cc1468da177 1394 * @}
<> 161:2cc1468da177 1395 */
<> 161:2cc1468da177 1396 #if defined(USE_FULL_LL_DRIVER)
<> 161:2cc1468da177 1397 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
<> 161:2cc1468da177 1398 * @{
<> 161:2cc1468da177 1399 */
<> 161:2cc1468da177 1400
<> 161:2cc1468da177 1401 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
<> 161:2cc1468da177 1402 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
<> 161:2cc1468da177 1403 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
<> 161:2cc1468da177 1404
<> 161:2cc1468da177 1405 /**
<> 161:2cc1468da177 1406 * @}
<> 161:2cc1468da177 1407 */
<> 161:2cc1468da177 1408 #endif /* USE_FULL_LL_DRIVER */
<> 161:2cc1468da177 1409 /**
<> 161:2cc1468da177 1410 * @}
<> 161:2cc1468da177 1411 */
<> 161:2cc1468da177 1412
<> 161:2cc1468da177 1413 /**
<> 161:2cc1468da177 1414 * @}
<> 161:2cc1468da177 1415 */
<> 161:2cc1468da177 1416
<> 161:2cc1468da177 1417 /** @defgroup I2S_LL I2S
<> 161:2cc1468da177 1418 * @{
<> 161:2cc1468da177 1419 */
<> 161:2cc1468da177 1420
<> 161:2cc1468da177 1421 /* Private variables ---------------------------------------------------------*/
<> 161:2cc1468da177 1422 /* Private constants ---------------------------------------------------------*/
<> 161:2cc1468da177 1423 /* Private macros ------------------------------------------------------------*/
<> 161:2cc1468da177 1424
<> 161:2cc1468da177 1425 /* Exported types ------------------------------------------------------------*/
<> 161:2cc1468da177 1426 #if defined(USE_FULL_LL_DRIVER)
<> 161:2cc1468da177 1427 /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
<> 161:2cc1468da177 1428 * @{
<> 161:2cc1468da177 1429 */
<> 161:2cc1468da177 1430
<> 161:2cc1468da177 1431 /**
<> 161:2cc1468da177 1432 * @brief I2S Init structure definition
<> 161:2cc1468da177 1433 */
<> 161:2cc1468da177 1434
<> 161:2cc1468da177 1435 typedef struct
<> 161:2cc1468da177 1436 {
<> 161:2cc1468da177 1437 uint32_t Mode; /*!< Specifies the I2S operating mode.
<> 161:2cc1468da177 1438 This parameter can be a value of @ref I2S_LL_EC_MODE
<> 161:2cc1468da177 1439
<> 161:2cc1468da177 1440 This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
<> 161:2cc1468da177 1441
<> 161:2cc1468da177 1442 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
<> 161:2cc1468da177 1443 This parameter can be a value of @ref I2S_LL_EC_STANDARD
<> 161:2cc1468da177 1444
<> 161:2cc1468da177 1445 This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
<> 161:2cc1468da177 1446
<> 161:2cc1468da177 1447
<> 161:2cc1468da177 1448 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
<> 161:2cc1468da177 1449 This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
<> 161:2cc1468da177 1450
<> 161:2cc1468da177 1451 This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
<> 161:2cc1468da177 1452
<> 161:2cc1468da177 1453
<> 161:2cc1468da177 1454 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
<> 161:2cc1468da177 1455 This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
<> 161:2cc1468da177 1456
<> 161:2cc1468da177 1457 This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
<> 161:2cc1468da177 1458
<> 161:2cc1468da177 1459
<> 161:2cc1468da177 1460 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
<> 161:2cc1468da177 1461 This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
<> 161:2cc1468da177 1462
<> 161:2cc1468da177 1463 Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
<> 161:2cc1468da177 1464 and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
<> 161:2cc1468da177 1465
<> 161:2cc1468da177 1466
<> 161:2cc1468da177 1467 uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
<> 161:2cc1468da177 1468 This parameter can be a value of @ref I2S_LL_EC_POLARITY
<> 161:2cc1468da177 1469
<> 161:2cc1468da177 1470 This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
<> 161:2cc1468da177 1471
<> 161:2cc1468da177 1472 } LL_I2S_InitTypeDef;
<> 161:2cc1468da177 1473
<> 161:2cc1468da177 1474 /**
<> 161:2cc1468da177 1475 * @}
<> 161:2cc1468da177 1476 */
<> 161:2cc1468da177 1477 #endif /*USE_FULL_LL_DRIVER*/
<> 161:2cc1468da177 1478
<> 161:2cc1468da177 1479 /* Exported constants --------------------------------------------------------*/
<> 161:2cc1468da177 1480 /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
<> 161:2cc1468da177 1481 * @{
<> 161:2cc1468da177 1482 */
<> 161:2cc1468da177 1483
<> 161:2cc1468da177 1484 /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
<> 161:2cc1468da177 1485 * @brief Flags defines which can be used with LL_I2S_ReadReg function
<> 161:2cc1468da177 1486 * @{
<> 161:2cc1468da177 1487 */
<> 161:2cc1468da177 1488 #define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
<> 161:2cc1468da177 1489 #define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
<> 161:2cc1468da177 1490 #define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
<> 161:2cc1468da177 1491 #define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */
<> 161:2cc1468da177 1492 #define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
<> 161:2cc1468da177 1493 #define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
<> 161:2cc1468da177 1494 /**
<> 161:2cc1468da177 1495 * @}
<> 161:2cc1468da177 1496 */
<> 161:2cc1468da177 1497
<> 161:2cc1468da177 1498 /** @defgroup SPI_LL_EC_IT IT Defines
<> 161:2cc1468da177 1499 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
<> 161:2cc1468da177 1500 * @{
<> 161:2cc1468da177 1501 */
<> 161:2cc1468da177 1502 #define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
<> 161:2cc1468da177 1503 #define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
<> 161:2cc1468da177 1504 #define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */
<> 161:2cc1468da177 1505 /**
<> 161:2cc1468da177 1506 * @}
<> 161:2cc1468da177 1507 */
<> 161:2cc1468da177 1508
<> 161:2cc1468da177 1509 /** @defgroup I2S_LL_EC_DATA_FORMAT Data format
<> 161:2cc1468da177 1510 * @{
<> 161:2cc1468da177 1511 */
<> 161:2cc1468da177 1512 #define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */
<> 161:2cc1468da177 1513 #define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */
<> 161:2cc1468da177 1514 #define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */
<> 161:2cc1468da177 1515 #define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */
<> 161:2cc1468da177 1516 /**
<> 161:2cc1468da177 1517 * @}
<> 161:2cc1468da177 1518 */
<> 161:2cc1468da177 1519
<> 161:2cc1468da177 1520 /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
<> 161:2cc1468da177 1521 * @{
<> 161:2cc1468da177 1522 */
<> 161:2cc1468da177 1523 #define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */
<> 161:2cc1468da177 1524 #define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
<> 161:2cc1468da177 1525 /**
<> 161:2cc1468da177 1526 * @}
<> 161:2cc1468da177 1527 */
<> 161:2cc1468da177 1528
<> 161:2cc1468da177 1529 /** @defgroup I2S_LL_EC_STANDARD I2s Standard
<> 161:2cc1468da177 1530 * @{
<> 161:2cc1468da177 1531 */
<> 161:2cc1468da177 1532 #define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */
<> 161:2cc1468da177 1533 #define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
<> 161:2cc1468da177 1534 #define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
<> 161:2cc1468da177 1535 #define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
<> 161:2cc1468da177 1536 #define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */
<> 161:2cc1468da177 1537 /**
<> 161:2cc1468da177 1538 * @}
<> 161:2cc1468da177 1539 */
<> 161:2cc1468da177 1540
<> 161:2cc1468da177 1541 /** @defgroup I2S_LL_EC_MODE Operation Mode
<> 161:2cc1468da177 1542 * @{
<> 161:2cc1468da177 1543 */
<> 161:2cc1468da177 1544 #define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */
<> 161:2cc1468da177 1545 #define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
<> 161:2cc1468da177 1546 #define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
<> 161:2cc1468da177 1547 #define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
<> 161:2cc1468da177 1548 /**
<> 161:2cc1468da177 1549 * @}
<> 161:2cc1468da177 1550 */
<> 161:2cc1468da177 1551
<> 161:2cc1468da177 1552 /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
<> 161:2cc1468da177 1553 * @{
<> 161:2cc1468da177 1554 */
<> 161:2cc1468da177 1555 #define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */
<> 161:2cc1468da177 1556 #define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
<> 161:2cc1468da177 1557 /**
<> 161:2cc1468da177 1558 * @}
<> 161:2cc1468da177 1559 */
<> 161:2cc1468da177 1560
<> 161:2cc1468da177 1561 #if defined(USE_FULL_LL_DRIVER)
<> 161:2cc1468da177 1562
<> 161:2cc1468da177 1563 /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
<> 161:2cc1468da177 1564 * @{
<> 161:2cc1468da177 1565 */
<> 161:2cc1468da177 1566 #define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */
<> 161:2cc1468da177 1567 #define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
<> 161:2cc1468da177 1568 /**
<> 161:2cc1468da177 1569 * @}
<> 161:2cc1468da177 1570 */
<> 161:2cc1468da177 1571
<> 161:2cc1468da177 1572 /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
<> 161:2cc1468da177 1573 * @{
<> 161:2cc1468da177 1574 */
<> 161:2cc1468da177 1575
<> 161:2cc1468da177 1576 #define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
<> 161:2cc1468da177 1577 #define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
<> 161:2cc1468da177 1578 #define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
<> 161:2cc1468da177 1579 #define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
<> 161:2cc1468da177 1580 #define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
<> 161:2cc1468da177 1581 #define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
<> 161:2cc1468da177 1582 #define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
<> 161:2cc1468da177 1583 #define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
<> 161:2cc1468da177 1584 #define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
<> 161:2cc1468da177 1585 #define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
<> 161:2cc1468da177 1586 /**
<> 161:2cc1468da177 1587 * @}
<> 161:2cc1468da177 1588 */
<> 161:2cc1468da177 1589 #endif /* USE_FULL_LL_DRIVER */
<> 161:2cc1468da177 1590
<> 161:2cc1468da177 1591 /**
<> 161:2cc1468da177 1592 * @}
<> 161:2cc1468da177 1593 */
<> 161:2cc1468da177 1594
<> 161:2cc1468da177 1595 /* Exported macro ------------------------------------------------------------*/
<> 161:2cc1468da177 1596 /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
<> 161:2cc1468da177 1597 * @{
<> 161:2cc1468da177 1598 */
<> 161:2cc1468da177 1599
<> 161:2cc1468da177 1600 /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
<> 161:2cc1468da177 1601 * @{
<> 161:2cc1468da177 1602 */
<> 161:2cc1468da177 1603
<> 161:2cc1468da177 1604 /**
<> 161:2cc1468da177 1605 * @brief Write a value in I2S register
<> 161:2cc1468da177 1606 * @param __INSTANCE__ I2S Instance
<> 161:2cc1468da177 1607 * @param __REG__ Register to be written
<> 161:2cc1468da177 1608 * @param __VALUE__ Value to be written in the register
<> 161:2cc1468da177 1609 * @retval None
<> 161:2cc1468da177 1610 */
<> 161:2cc1468da177 1611 #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<> 161:2cc1468da177 1612
<> 161:2cc1468da177 1613 /**
<> 161:2cc1468da177 1614 * @brief Read a value in I2S register
<> 161:2cc1468da177 1615 * @param __INSTANCE__ I2S Instance
<> 161:2cc1468da177 1616 * @param __REG__ Register to be read
<> 161:2cc1468da177 1617 * @retval Register value
<> 161:2cc1468da177 1618 */
<> 161:2cc1468da177 1619 #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<> 161:2cc1468da177 1620 /**
<> 161:2cc1468da177 1621 * @}
<> 161:2cc1468da177 1622 */
<> 161:2cc1468da177 1623
<> 161:2cc1468da177 1624 /**
<> 161:2cc1468da177 1625 * @}
<> 161:2cc1468da177 1626 */
<> 161:2cc1468da177 1627
<> 161:2cc1468da177 1628
<> 161:2cc1468da177 1629 /* Exported functions --------------------------------------------------------*/
<> 161:2cc1468da177 1630
<> 161:2cc1468da177 1631 /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
<> 161:2cc1468da177 1632 * @{
<> 161:2cc1468da177 1633 */
<> 161:2cc1468da177 1634
<> 161:2cc1468da177 1635 /** @defgroup I2S_LL_EF_Configuration Configuration
<> 161:2cc1468da177 1636 * @{
<> 161:2cc1468da177 1637 */
<> 161:2cc1468da177 1638
<> 161:2cc1468da177 1639 /**
<> 161:2cc1468da177 1640 * @brief Select I2S mode and Enable I2S peripheral
<> 161:2cc1468da177 1641 * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
<> 161:2cc1468da177 1642 * I2SCFGR I2SE LL_I2S_Enable
<> 161:2cc1468da177 1643 * @param SPIx SPI Instance
<> 161:2cc1468da177 1644 * @retval None
<> 161:2cc1468da177 1645 */
<> 161:2cc1468da177 1646 __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1647 {
<> 161:2cc1468da177 1648 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
<> 161:2cc1468da177 1649 }
<> 161:2cc1468da177 1650
<> 161:2cc1468da177 1651 /**
<> 161:2cc1468da177 1652 * @brief Disable I2S peripheral
<> 161:2cc1468da177 1653 * @rmtoll I2SCFGR I2SE LL_I2S_Disable
<> 161:2cc1468da177 1654 * @param SPIx SPI Instance
<> 161:2cc1468da177 1655 * @retval None
<> 161:2cc1468da177 1656 */
<> 161:2cc1468da177 1657 __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1658 {
<> 161:2cc1468da177 1659 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
<> 161:2cc1468da177 1660 }
<> 161:2cc1468da177 1661
<> 161:2cc1468da177 1662 /**
<> 161:2cc1468da177 1663 * @brief Check if I2S peripheral is enabled
<> 161:2cc1468da177 1664 * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
<> 161:2cc1468da177 1665 * @param SPIx SPI Instance
<> 161:2cc1468da177 1666 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 1667 */
<> 161:2cc1468da177 1668 __STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1669 {
<> 161:2cc1468da177 1670 return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
<> 161:2cc1468da177 1671 }
<> 161:2cc1468da177 1672
<> 161:2cc1468da177 1673 /**
<> 161:2cc1468da177 1674 * @brief Set I2S data frame length
<> 161:2cc1468da177 1675 * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
<> 161:2cc1468da177 1676 * I2SCFGR CHLEN LL_I2S_SetDataFormat
<> 161:2cc1468da177 1677 * @param SPIx SPI Instance
<> 161:2cc1468da177 1678 * @param DataFormat This parameter can be one of the following values:
<> 161:2cc1468da177 1679 * @arg @ref LL_I2S_DATAFORMAT_16B
<> 161:2cc1468da177 1680 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
<> 161:2cc1468da177 1681 * @arg @ref LL_I2S_DATAFORMAT_24B
<> 161:2cc1468da177 1682 * @arg @ref LL_I2S_DATAFORMAT_32B
<> 161:2cc1468da177 1683 * @retval None
<> 161:2cc1468da177 1684 */
<> 161:2cc1468da177 1685 __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
<> 161:2cc1468da177 1686 {
<> 161:2cc1468da177 1687 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
<> 161:2cc1468da177 1688 }
<> 161:2cc1468da177 1689
<> 161:2cc1468da177 1690 /**
<> 161:2cc1468da177 1691 * @brief Get I2S data frame length
<> 161:2cc1468da177 1692 * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
<> 161:2cc1468da177 1693 * I2SCFGR CHLEN LL_I2S_GetDataFormat
<> 161:2cc1468da177 1694 * @param SPIx SPI Instance
<> 161:2cc1468da177 1695 * @retval Returned value can be one of the following values:
<> 161:2cc1468da177 1696 * @arg @ref LL_I2S_DATAFORMAT_16B
<> 161:2cc1468da177 1697 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
<> 161:2cc1468da177 1698 * @arg @ref LL_I2S_DATAFORMAT_24B
<> 161:2cc1468da177 1699 * @arg @ref LL_I2S_DATAFORMAT_32B
<> 161:2cc1468da177 1700 */
<> 161:2cc1468da177 1701 __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1702 {
<> 161:2cc1468da177 1703 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
<> 161:2cc1468da177 1704 }
<> 161:2cc1468da177 1705
<> 161:2cc1468da177 1706 /**
<> 161:2cc1468da177 1707 * @brief Set I2S clock polarity
<> 161:2cc1468da177 1708 * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
<> 161:2cc1468da177 1709 * @param SPIx SPI Instance
<> 161:2cc1468da177 1710 * @param ClockPolarity This parameter can be one of the following values:
<> 161:2cc1468da177 1711 * @arg @ref LL_I2S_POLARITY_LOW
<> 161:2cc1468da177 1712 * @arg @ref LL_I2S_POLARITY_HIGH
<> 161:2cc1468da177 1713 * @retval None
<> 161:2cc1468da177 1714 */
<> 161:2cc1468da177 1715 __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
<> 161:2cc1468da177 1716 {
<> 161:2cc1468da177 1717 SET_BIT(SPIx->I2SCFGR, ClockPolarity);
<> 161:2cc1468da177 1718 }
<> 161:2cc1468da177 1719
<> 161:2cc1468da177 1720 /**
<> 161:2cc1468da177 1721 * @brief Get I2S clock polarity
<> 161:2cc1468da177 1722 * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
<> 161:2cc1468da177 1723 * @param SPIx SPI Instance
<> 161:2cc1468da177 1724 * @retval Returned value can be one of the following values:
<> 161:2cc1468da177 1725 * @arg @ref LL_I2S_POLARITY_LOW
<> 161:2cc1468da177 1726 * @arg @ref LL_I2S_POLARITY_HIGH
<> 161:2cc1468da177 1727 */
<> 161:2cc1468da177 1728 __STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1729 {
<> 161:2cc1468da177 1730 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
<> 161:2cc1468da177 1731 }
<> 161:2cc1468da177 1732
<> 161:2cc1468da177 1733 /**
<> 161:2cc1468da177 1734 * @brief Set I2S standard protocol
<> 161:2cc1468da177 1735 * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
<> 161:2cc1468da177 1736 * I2SCFGR PCMSYNC LL_I2S_SetStandard
<> 161:2cc1468da177 1737 * @param SPIx SPI Instance
<> 161:2cc1468da177 1738 * @param Standard This parameter can be one of the following values:
<> 161:2cc1468da177 1739 * @arg @ref LL_I2S_STANDARD_PHILIPS
<> 161:2cc1468da177 1740 * @arg @ref LL_I2S_STANDARD_MSB
<> 161:2cc1468da177 1741 * @arg @ref LL_I2S_STANDARD_LSB
<> 161:2cc1468da177 1742 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
<> 161:2cc1468da177 1743 * @arg @ref LL_I2S_STANDARD_PCM_LONG
<> 161:2cc1468da177 1744 * @retval None
<> 161:2cc1468da177 1745 */
<> 161:2cc1468da177 1746 __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
<> 161:2cc1468da177 1747 {
<> 161:2cc1468da177 1748 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
<> 161:2cc1468da177 1749 }
<> 161:2cc1468da177 1750
<> 161:2cc1468da177 1751 /**
<> 161:2cc1468da177 1752 * @brief Get I2S standard protocol
<> 161:2cc1468da177 1753 * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
<> 161:2cc1468da177 1754 * I2SCFGR PCMSYNC LL_I2S_GetStandard
<> 161:2cc1468da177 1755 * @param SPIx SPI Instance
<> 161:2cc1468da177 1756 * @retval Returned value can be one of the following values:
<> 161:2cc1468da177 1757 * @arg @ref LL_I2S_STANDARD_PHILIPS
<> 161:2cc1468da177 1758 * @arg @ref LL_I2S_STANDARD_MSB
<> 161:2cc1468da177 1759 * @arg @ref LL_I2S_STANDARD_LSB
<> 161:2cc1468da177 1760 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
<> 161:2cc1468da177 1761 * @arg @ref LL_I2S_STANDARD_PCM_LONG
<> 161:2cc1468da177 1762 */
<> 161:2cc1468da177 1763 __STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1764 {
<> 161:2cc1468da177 1765 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
<> 161:2cc1468da177 1766 }
<> 161:2cc1468da177 1767
<> 161:2cc1468da177 1768 /**
<> 161:2cc1468da177 1769 * @brief Set I2S transfer mode
<> 161:2cc1468da177 1770 * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
<> 161:2cc1468da177 1771 * @param SPIx SPI Instance
<> 161:2cc1468da177 1772 * @param Mode This parameter can be one of the following values:
<> 161:2cc1468da177 1773 * @arg @ref LL_I2S_MODE_SLAVE_TX
<> 161:2cc1468da177 1774 * @arg @ref LL_I2S_MODE_SLAVE_RX
<> 161:2cc1468da177 1775 * @arg @ref LL_I2S_MODE_MASTER_TX
<> 161:2cc1468da177 1776 * @arg @ref LL_I2S_MODE_MASTER_RX
<> 161:2cc1468da177 1777 * @retval None
<> 161:2cc1468da177 1778 */
<> 161:2cc1468da177 1779 __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
<> 161:2cc1468da177 1780 {
<> 161:2cc1468da177 1781 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
<> 161:2cc1468da177 1782 }
<> 161:2cc1468da177 1783
<> 161:2cc1468da177 1784 /**
<> 161:2cc1468da177 1785 * @brief Get I2S transfer mode
<> 161:2cc1468da177 1786 * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
<> 161:2cc1468da177 1787 * @param SPIx SPI Instance
<> 161:2cc1468da177 1788 * @retval Returned value can be one of the following values:
<> 161:2cc1468da177 1789 * @arg @ref LL_I2S_MODE_SLAVE_TX
<> 161:2cc1468da177 1790 * @arg @ref LL_I2S_MODE_SLAVE_RX
<> 161:2cc1468da177 1791 * @arg @ref LL_I2S_MODE_MASTER_TX
<> 161:2cc1468da177 1792 * @arg @ref LL_I2S_MODE_MASTER_RX
<> 161:2cc1468da177 1793 */
<> 161:2cc1468da177 1794 __STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1795 {
<> 161:2cc1468da177 1796 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
<> 161:2cc1468da177 1797 }
<> 161:2cc1468da177 1798
<> 161:2cc1468da177 1799 /**
<> 161:2cc1468da177 1800 * @brief Set I2S linear prescaler
<> 161:2cc1468da177 1801 * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
<> 161:2cc1468da177 1802 * @param SPIx SPI Instance
<> 161:2cc1468da177 1803 * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
<> 161:2cc1468da177 1804 * @retval None
<> 161:2cc1468da177 1805 */
<> 161:2cc1468da177 1806 __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
<> 161:2cc1468da177 1807 {
<> 161:2cc1468da177 1808 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
<> 161:2cc1468da177 1809 }
<> 161:2cc1468da177 1810
<> 161:2cc1468da177 1811 /**
<> 161:2cc1468da177 1812 * @brief Get I2S linear prescaler
<> 161:2cc1468da177 1813 * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
<> 161:2cc1468da177 1814 * @param SPIx SPI Instance
<> 161:2cc1468da177 1815 * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
<> 161:2cc1468da177 1816 */
<> 161:2cc1468da177 1817 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1818 {
<> 161:2cc1468da177 1819 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
<> 161:2cc1468da177 1820 }
<> 161:2cc1468da177 1821
<> 161:2cc1468da177 1822 /**
<> 161:2cc1468da177 1823 * @brief Set I2S parity prescaler
<> 161:2cc1468da177 1824 * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
<> 161:2cc1468da177 1825 * @param SPIx SPI Instance
<> 161:2cc1468da177 1826 * @param PrescalerParity This parameter can be one of the following values:
<> 161:2cc1468da177 1827 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
<> 161:2cc1468da177 1828 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
<> 161:2cc1468da177 1829 * @retval None
<> 161:2cc1468da177 1830 */
<> 161:2cc1468da177 1831 __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
<> 161:2cc1468da177 1832 {
<> 161:2cc1468da177 1833 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
<> 161:2cc1468da177 1834 }
<> 161:2cc1468da177 1835
<> 161:2cc1468da177 1836 /**
<> 161:2cc1468da177 1837 * @brief Get I2S parity prescaler
<> 161:2cc1468da177 1838 * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
<> 161:2cc1468da177 1839 * @param SPIx SPI Instance
<> 161:2cc1468da177 1840 * @retval Returned value can be one of the following values:
<> 161:2cc1468da177 1841 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
<> 161:2cc1468da177 1842 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
<> 161:2cc1468da177 1843 */
<> 161:2cc1468da177 1844 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1845 {
<> 161:2cc1468da177 1846 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
<> 161:2cc1468da177 1847 }
<> 161:2cc1468da177 1848
<> 161:2cc1468da177 1849 /**
<> 161:2cc1468da177 1850 * @brief Enable the master clock ouput (Pin MCK)
<> 161:2cc1468da177 1851 * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
<> 161:2cc1468da177 1852 * @param SPIx SPI Instance
<> 161:2cc1468da177 1853 * @retval None
<> 161:2cc1468da177 1854 */
<> 161:2cc1468da177 1855 __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1856 {
<> 161:2cc1468da177 1857 SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
<> 161:2cc1468da177 1858 }
<> 161:2cc1468da177 1859
<> 161:2cc1468da177 1860 /**
<> 161:2cc1468da177 1861 * @brief Disable the master clock ouput (Pin MCK)
<> 161:2cc1468da177 1862 * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
<> 161:2cc1468da177 1863 * @param SPIx SPI Instance
<> 161:2cc1468da177 1864 * @retval None
<> 161:2cc1468da177 1865 */
<> 161:2cc1468da177 1866 __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1867 {
<> 161:2cc1468da177 1868 CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
<> 161:2cc1468da177 1869 }
<> 161:2cc1468da177 1870
<> 161:2cc1468da177 1871 /**
<> 161:2cc1468da177 1872 * @brief Check if the master clock ouput (Pin MCK) is enabled
<> 161:2cc1468da177 1873 * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
<> 161:2cc1468da177 1874 * @param SPIx SPI Instance
<> 161:2cc1468da177 1875 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 1876 */
<> 161:2cc1468da177 1877 __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1878 {
<> 161:2cc1468da177 1879 return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
<> 161:2cc1468da177 1880 }
<> 161:2cc1468da177 1881
<> 161:2cc1468da177 1882 #if defined(SPI_I2SCFGR_ASTRTEN)
<> 161:2cc1468da177 1883 /**
<> 161:2cc1468da177 1884 * @brief Enable asynchronous start
<> 161:2cc1468da177 1885 * @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart
<> 161:2cc1468da177 1886 * @param SPIx SPI Instance
<> 161:2cc1468da177 1887 * @retval None
<> 161:2cc1468da177 1888 */
<> 161:2cc1468da177 1889 __STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1890 {
<> 161:2cc1468da177 1891 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
<> 161:2cc1468da177 1892 }
<> 161:2cc1468da177 1893
<> 161:2cc1468da177 1894 /**
<> 161:2cc1468da177 1895 * @brief Disable asynchronous start
<> 161:2cc1468da177 1896 * @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart
<> 161:2cc1468da177 1897 * @param SPIx SPI Instance
<> 161:2cc1468da177 1898 * @retval None
<> 161:2cc1468da177 1899 */
<> 161:2cc1468da177 1900 __STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1901 {
<> 161:2cc1468da177 1902 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
<> 161:2cc1468da177 1903 }
<> 161:2cc1468da177 1904
<> 161:2cc1468da177 1905 /**
<> 161:2cc1468da177 1906 * @brief Check if asynchronous start is enabled
<> 161:2cc1468da177 1907 * @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart
<> 161:2cc1468da177 1908 * @param SPIx SPI Instance
<> 161:2cc1468da177 1909 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 1910 */
<> 161:2cc1468da177 1911 __STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1912 {
<> 161:2cc1468da177 1913 return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN));
<> 161:2cc1468da177 1914 }
<> 161:2cc1468da177 1915 #endif /* SPI_I2SCFGR_ASTRTEN */
<> 161:2cc1468da177 1916
<> 161:2cc1468da177 1917 /**
<> 161:2cc1468da177 1918 * @}
<> 161:2cc1468da177 1919 */
<> 161:2cc1468da177 1920
<> 161:2cc1468da177 1921 /** @defgroup I2S_LL_EF_FLAG FLAG Management
<> 161:2cc1468da177 1922 * @{
<> 161:2cc1468da177 1923 */
<> 161:2cc1468da177 1924
<> 161:2cc1468da177 1925 /**
<> 161:2cc1468da177 1926 * @brief Check if Rx buffer is not empty
<> 161:2cc1468da177 1927 * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
<> 161:2cc1468da177 1928 * @param SPIx SPI Instance
<> 161:2cc1468da177 1929 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 1930 */
<> 161:2cc1468da177 1931 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1932 {
<> 161:2cc1468da177 1933 return LL_SPI_IsActiveFlag_RXNE(SPIx);
<> 161:2cc1468da177 1934 }
<> 161:2cc1468da177 1935
<> 161:2cc1468da177 1936 /**
<> 161:2cc1468da177 1937 * @brief Check if Tx buffer is empty
<> 161:2cc1468da177 1938 * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
<> 161:2cc1468da177 1939 * @param SPIx SPI Instance
<> 161:2cc1468da177 1940 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 1941 */
<> 161:2cc1468da177 1942 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1943 {
<> 161:2cc1468da177 1944 return LL_SPI_IsActiveFlag_TXE(SPIx);
<> 161:2cc1468da177 1945 }
<> 161:2cc1468da177 1946
<> 161:2cc1468da177 1947 /**
<> 161:2cc1468da177 1948 * @brief Get busy flag
<> 161:2cc1468da177 1949 * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
<> 161:2cc1468da177 1950 * @param SPIx SPI Instance
<> 161:2cc1468da177 1951 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 1952 */
<> 161:2cc1468da177 1953 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1954 {
<> 161:2cc1468da177 1955 return LL_SPI_IsActiveFlag_BSY(SPIx);
<> 161:2cc1468da177 1956 }
<> 161:2cc1468da177 1957
<> 161:2cc1468da177 1958 /**
<> 161:2cc1468da177 1959 * @brief Get overrun error flag
<> 161:2cc1468da177 1960 * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
<> 161:2cc1468da177 1961 * @param SPIx SPI Instance
<> 161:2cc1468da177 1962 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 1963 */
<> 161:2cc1468da177 1964 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1965 {
<> 161:2cc1468da177 1966 return LL_SPI_IsActiveFlag_OVR(SPIx);
<> 161:2cc1468da177 1967 }
<> 161:2cc1468da177 1968
<> 161:2cc1468da177 1969 /**
<> 161:2cc1468da177 1970 * @brief Get underrun error flag
<> 161:2cc1468da177 1971 * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
<> 161:2cc1468da177 1972 * @param SPIx SPI Instance
<> 161:2cc1468da177 1973 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 1974 */
<> 161:2cc1468da177 1975 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1976 {
<> 161:2cc1468da177 1977 return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
<> 161:2cc1468da177 1978 }
<> 161:2cc1468da177 1979
<> 161:2cc1468da177 1980 /**
<> 161:2cc1468da177 1981 * @brief Get frame format error flag
<> 161:2cc1468da177 1982 * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
<> 161:2cc1468da177 1983 * @param SPIx SPI Instance
<> 161:2cc1468da177 1984 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 1985 */
<> 161:2cc1468da177 1986 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 1987 {
<> 161:2cc1468da177 1988 return LL_SPI_IsActiveFlag_FRE(SPIx);
<> 161:2cc1468da177 1989 }
<> 161:2cc1468da177 1990
<> 161:2cc1468da177 1991 /**
<> 161:2cc1468da177 1992 * @brief Get channel side flag.
<> 161:2cc1468da177 1993 * @note 0: Channel Left has to be transmitted or has been received\n
<> 161:2cc1468da177 1994 * 1: Channel Right has to be transmitted or has been received\n
<> 161:2cc1468da177 1995 * It has no significance in PCM mode.
<> 161:2cc1468da177 1996 * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
<> 161:2cc1468da177 1997 * @param SPIx SPI Instance
<> 161:2cc1468da177 1998 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 1999 */
<> 161:2cc1468da177 2000 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 2001 {
<> 161:2cc1468da177 2002 return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
<> 161:2cc1468da177 2003 }
<> 161:2cc1468da177 2004
<> 161:2cc1468da177 2005 /**
<> 161:2cc1468da177 2006 * @brief Clear overrun error flag
<> 161:2cc1468da177 2007 * @rmtoll SR OVR LL_I2S_ClearFlag_OVR
<> 161:2cc1468da177 2008 * @param SPIx SPI Instance
<> 161:2cc1468da177 2009 * @retval None
<> 161:2cc1468da177 2010 */
<> 161:2cc1468da177 2011 __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 2012 {
<> 161:2cc1468da177 2013 LL_SPI_ClearFlag_OVR(SPIx);
<> 161:2cc1468da177 2014 }
<> 161:2cc1468da177 2015
<> 161:2cc1468da177 2016 /**
<> 161:2cc1468da177 2017 * @brief Clear underrun error flag
<> 161:2cc1468da177 2018 * @rmtoll SR UDR LL_I2S_ClearFlag_UDR
<> 161:2cc1468da177 2019 * @param SPIx SPI Instance
<> 161:2cc1468da177 2020 * @retval None
<> 161:2cc1468da177 2021 */
<> 161:2cc1468da177 2022 __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 2023 {
<> 161:2cc1468da177 2024 __IO uint32_t tmpreg;
<> 161:2cc1468da177 2025 tmpreg = SPIx->SR;
<> 161:2cc1468da177 2026 (void)tmpreg;
<> 161:2cc1468da177 2027 }
<> 161:2cc1468da177 2028
<> 161:2cc1468da177 2029 /**
<> 161:2cc1468da177 2030 * @brief Clear frame format error flag
<> 161:2cc1468da177 2031 * @rmtoll SR FRE LL_I2S_ClearFlag_FRE
<> 161:2cc1468da177 2032 * @param SPIx SPI Instance
<> 161:2cc1468da177 2033 * @retval None
<> 161:2cc1468da177 2034 */
<> 161:2cc1468da177 2035 __STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 2036 {
<> 161:2cc1468da177 2037 LL_SPI_ClearFlag_FRE(SPIx);
<> 161:2cc1468da177 2038 }
<> 161:2cc1468da177 2039
<> 161:2cc1468da177 2040 /**
<> 161:2cc1468da177 2041 * @}
<> 161:2cc1468da177 2042 */
<> 161:2cc1468da177 2043
<> 161:2cc1468da177 2044 /** @defgroup I2S_LL_EF_IT Interrupt Management
<> 161:2cc1468da177 2045 * @{
<> 161:2cc1468da177 2046 */
<> 161:2cc1468da177 2047
<> 161:2cc1468da177 2048 /**
<> 161:2cc1468da177 2049 * @brief Enable error IT
<> 161:2cc1468da177 2050 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
<> 161:2cc1468da177 2051 * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
<> 161:2cc1468da177 2052 * @param SPIx SPI Instance
<> 161:2cc1468da177 2053 * @retval None
<> 161:2cc1468da177 2054 */
<> 161:2cc1468da177 2055 __STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 2056 {
<> 161:2cc1468da177 2057 LL_SPI_EnableIT_ERR(SPIx);
<> 161:2cc1468da177 2058 }
<> 161:2cc1468da177 2059
<> 161:2cc1468da177 2060 /**
<> 161:2cc1468da177 2061 * @brief Enable Rx buffer not empty IT
<> 161:2cc1468da177 2062 * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
<> 161:2cc1468da177 2063 * @param SPIx SPI Instance
<> 161:2cc1468da177 2064 * @retval None
<> 161:2cc1468da177 2065 */
<> 161:2cc1468da177 2066 __STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 2067 {
<> 161:2cc1468da177 2068 LL_SPI_EnableIT_RXNE(SPIx);
<> 161:2cc1468da177 2069 }
<> 161:2cc1468da177 2070
<> 161:2cc1468da177 2071 /**
<> 161:2cc1468da177 2072 * @brief Enable Tx buffer empty IT
<> 161:2cc1468da177 2073 * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
<> 161:2cc1468da177 2074 * @param SPIx SPI Instance
<> 161:2cc1468da177 2075 * @retval None
<> 161:2cc1468da177 2076 */
<> 161:2cc1468da177 2077 __STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 2078 {
<> 161:2cc1468da177 2079 LL_SPI_EnableIT_TXE(SPIx);
<> 161:2cc1468da177 2080 }
<> 161:2cc1468da177 2081
<> 161:2cc1468da177 2082 /**
<> 161:2cc1468da177 2083 * @brief Disable error IT
<> 161:2cc1468da177 2084 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
<> 161:2cc1468da177 2085 * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
<> 161:2cc1468da177 2086 * @param SPIx SPI Instance
<> 161:2cc1468da177 2087 * @retval None
<> 161:2cc1468da177 2088 */
<> 161:2cc1468da177 2089 __STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 2090 {
<> 161:2cc1468da177 2091 LL_SPI_DisableIT_ERR(SPIx);
<> 161:2cc1468da177 2092 }
<> 161:2cc1468da177 2093
<> 161:2cc1468da177 2094 /**
<> 161:2cc1468da177 2095 * @brief Disable Rx buffer not empty IT
<> 161:2cc1468da177 2096 * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
<> 161:2cc1468da177 2097 * @param SPIx SPI Instance
<> 161:2cc1468da177 2098 * @retval None
<> 161:2cc1468da177 2099 */
<> 161:2cc1468da177 2100 __STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 2101 {
<> 161:2cc1468da177 2102 LL_SPI_DisableIT_RXNE(SPIx);
<> 161:2cc1468da177 2103 }
<> 161:2cc1468da177 2104
<> 161:2cc1468da177 2105 /**
<> 161:2cc1468da177 2106 * @brief Disable Tx buffer empty IT
<> 161:2cc1468da177 2107 * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
<> 161:2cc1468da177 2108 * @param SPIx SPI Instance
<> 161:2cc1468da177 2109 * @retval None
<> 161:2cc1468da177 2110 */
<> 161:2cc1468da177 2111 __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 2112 {
<> 161:2cc1468da177 2113 LL_SPI_DisableIT_TXE(SPIx);
<> 161:2cc1468da177 2114 }
<> 161:2cc1468da177 2115
<> 161:2cc1468da177 2116 /**
<> 161:2cc1468da177 2117 * @brief Check if ERR IT is enabled
<> 161:2cc1468da177 2118 * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
<> 161:2cc1468da177 2119 * @param SPIx SPI Instance
<> 161:2cc1468da177 2120 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 2121 */
<> 161:2cc1468da177 2122 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 2123 {
<> 161:2cc1468da177 2124 return LL_SPI_IsEnabledIT_ERR(SPIx);
<> 161:2cc1468da177 2125 }
<> 161:2cc1468da177 2126
<> 161:2cc1468da177 2127 /**
<> 161:2cc1468da177 2128 * @brief Check if RXNE IT is enabled
<> 161:2cc1468da177 2129 * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
<> 161:2cc1468da177 2130 * @param SPIx SPI Instance
<> 161:2cc1468da177 2131 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 2132 */
<> 161:2cc1468da177 2133 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 2134 {
<> 161:2cc1468da177 2135 return LL_SPI_IsEnabledIT_RXNE(SPIx);
<> 161:2cc1468da177 2136 }
<> 161:2cc1468da177 2137
<> 161:2cc1468da177 2138 /**
<> 161:2cc1468da177 2139 * @brief Check if TXE IT is enabled
<> 161:2cc1468da177 2140 * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
<> 161:2cc1468da177 2141 * @param SPIx SPI Instance
<> 161:2cc1468da177 2142 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 2143 */
<> 161:2cc1468da177 2144 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 2145 {
<> 161:2cc1468da177 2146 return LL_SPI_IsEnabledIT_TXE(SPIx);
<> 161:2cc1468da177 2147 }
<> 161:2cc1468da177 2148
<> 161:2cc1468da177 2149 /**
<> 161:2cc1468da177 2150 * @}
<> 161:2cc1468da177 2151 */
<> 161:2cc1468da177 2152
<> 161:2cc1468da177 2153 /** @defgroup I2S_LL_EF_DMA DMA Management
<> 161:2cc1468da177 2154 * @{
<> 161:2cc1468da177 2155 */
<> 161:2cc1468da177 2156
<> 161:2cc1468da177 2157 /**
<> 161:2cc1468da177 2158 * @brief Enable DMA Rx
<> 161:2cc1468da177 2159 * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
<> 161:2cc1468da177 2160 * @param SPIx SPI Instance
<> 161:2cc1468da177 2161 * @retval None
<> 161:2cc1468da177 2162 */
<> 161:2cc1468da177 2163 __STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 2164 {
<> 161:2cc1468da177 2165 LL_SPI_EnableDMAReq_RX(SPIx);
<> 161:2cc1468da177 2166 }
<> 161:2cc1468da177 2167
<> 161:2cc1468da177 2168 /**
<> 161:2cc1468da177 2169 * @brief Disable DMA Rx
<> 161:2cc1468da177 2170 * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
<> 161:2cc1468da177 2171 * @param SPIx SPI Instance
<> 161:2cc1468da177 2172 * @retval None
<> 161:2cc1468da177 2173 */
<> 161:2cc1468da177 2174 __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 2175 {
<> 161:2cc1468da177 2176 LL_SPI_DisableDMAReq_RX(SPIx);
<> 161:2cc1468da177 2177 }
<> 161:2cc1468da177 2178
<> 161:2cc1468da177 2179 /**
<> 161:2cc1468da177 2180 * @brief Check if DMA Rx is enabled
<> 161:2cc1468da177 2181 * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
<> 161:2cc1468da177 2182 * @param SPIx SPI Instance
<> 161:2cc1468da177 2183 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 2184 */
<> 161:2cc1468da177 2185 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 2186 {
<> 161:2cc1468da177 2187 return LL_SPI_IsEnabledDMAReq_RX(SPIx);
<> 161:2cc1468da177 2188 }
<> 161:2cc1468da177 2189
<> 161:2cc1468da177 2190 /**
<> 161:2cc1468da177 2191 * @brief Enable DMA Tx
<> 161:2cc1468da177 2192 * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
<> 161:2cc1468da177 2193 * @param SPIx SPI Instance
<> 161:2cc1468da177 2194 * @retval None
<> 161:2cc1468da177 2195 */
<> 161:2cc1468da177 2196 __STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 2197 {
<> 161:2cc1468da177 2198 LL_SPI_EnableDMAReq_TX(SPIx);
<> 161:2cc1468da177 2199 }
<> 161:2cc1468da177 2200
<> 161:2cc1468da177 2201 /**
<> 161:2cc1468da177 2202 * @brief Disable DMA Tx
<> 161:2cc1468da177 2203 * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
<> 161:2cc1468da177 2204 * @param SPIx SPI Instance
<> 161:2cc1468da177 2205 * @retval None
<> 161:2cc1468da177 2206 */
<> 161:2cc1468da177 2207 __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 2208 {
<> 161:2cc1468da177 2209 LL_SPI_DisableDMAReq_TX(SPIx);
<> 161:2cc1468da177 2210 }
<> 161:2cc1468da177 2211
<> 161:2cc1468da177 2212 /**
<> 161:2cc1468da177 2213 * @brief Check if DMA Tx is enabled
<> 161:2cc1468da177 2214 * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
<> 161:2cc1468da177 2215 * @param SPIx SPI Instance
<> 161:2cc1468da177 2216 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 2217 */
<> 161:2cc1468da177 2218 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 2219 {
<> 161:2cc1468da177 2220 return LL_SPI_IsEnabledDMAReq_TX(SPIx);
<> 161:2cc1468da177 2221 }
<> 161:2cc1468da177 2222
<> 161:2cc1468da177 2223 /**
<> 161:2cc1468da177 2224 * @}
<> 161:2cc1468da177 2225 */
<> 161:2cc1468da177 2226
<> 161:2cc1468da177 2227 /** @defgroup I2S_LL_EF_DATA DATA Management
<> 161:2cc1468da177 2228 * @{
<> 161:2cc1468da177 2229 */
<> 161:2cc1468da177 2230
<> 161:2cc1468da177 2231 /**
<> 161:2cc1468da177 2232 * @brief Read 16-Bits in data register
<> 161:2cc1468da177 2233 * @rmtoll DR DR LL_I2S_ReceiveData16
<> 161:2cc1468da177 2234 * @param SPIx SPI Instance
<> 161:2cc1468da177 2235 * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
<> 161:2cc1468da177 2236 */
<> 161:2cc1468da177 2237 __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 2238 {
<> 161:2cc1468da177 2239 return LL_SPI_ReceiveData16(SPIx);
<> 161:2cc1468da177 2240 }
<> 161:2cc1468da177 2241
<> 161:2cc1468da177 2242 /**
<> 161:2cc1468da177 2243 * @brief Write 16-Bits in data register
<> 161:2cc1468da177 2244 * @rmtoll DR DR LL_I2S_TransmitData16
<> 161:2cc1468da177 2245 * @param SPIx SPI Instance
<> 161:2cc1468da177 2246 * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
<> 161:2cc1468da177 2247 * @retval None
<> 161:2cc1468da177 2248 */
<> 161:2cc1468da177 2249 __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
<> 161:2cc1468da177 2250 {
<> 161:2cc1468da177 2251 LL_SPI_TransmitData16(SPIx, TxData);
<> 161:2cc1468da177 2252 }
<> 161:2cc1468da177 2253
<> 161:2cc1468da177 2254 /**
<> 161:2cc1468da177 2255 * @}
<> 161:2cc1468da177 2256 */
<> 161:2cc1468da177 2257
<> 161:2cc1468da177 2258 #if defined(USE_FULL_LL_DRIVER)
<> 161:2cc1468da177 2259 /** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
<> 161:2cc1468da177 2260 * @{
<> 161:2cc1468da177 2261 */
<> 161:2cc1468da177 2262
<> 161:2cc1468da177 2263 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
<> 161:2cc1468da177 2264 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
<> 161:2cc1468da177 2265 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
<> 161:2cc1468da177 2266 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
<> 161:2cc1468da177 2267
<> 161:2cc1468da177 2268 /**
<> 161:2cc1468da177 2269 * @}
<> 161:2cc1468da177 2270 */
<> 161:2cc1468da177 2271 #endif /* USE_FULL_LL_DRIVER */
<> 161:2cc1468da177 2272
<> 161:2cc1468da177 2273 /**
<> 161:2cc1468da177 2274 * @}
<> 161:2cc1468da177 2275 */
<> 161:2cc1468da177 2276
<> 161:2cc1468da177 2277 /**
<> 161:2cc1468da177 2278 * @}
<> 161:2cc1468da177 2279 */
<> 161:2cc1468da177 2280
<> 161:2cc1468da177 2281 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */
<> 161:2cc1468da177 2282
<> 161:2cc1468da177 2283 /**
<> 161:2cc1468da177 2284 * @}
<> 161:2cc1468da177 2285 */
<> 161:2cc1468da177 2286
<> 161:2cc1468da177 2287 #ifdef __cplusplus
<> 161:2cc1468da177 2288 }
<> 161:2cc1468da177 2289 #endif
<> 161:2cc1468da177 2290
<> 161:2cc1468da177 2291 #endif /* __STM32F7xx_LL_SPI_H */
<> 161:2cc1468da177 2292
<> 161:2cc1468da177 2293 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/