Frederick Huang
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mbed-STM32L452
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targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dma.c@161:2cc1468da177, 2017-03-30 (annotated)
- Committer:
- <>
- Date:
- Thu Mar 30 13:45:57 2017 +0100
- Revision:
- 161:2cc1468da177
This updates the lib to the mbed lib v139
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| <> | 161:2cc1468da177 | 1 | /** |
| <> | 161:2cc1468da177 | 2 | ****************************************************************************** |
| <> | 161:2cc1468da177 | 3 | * @file stm32f7xx_ll_dma.c |
| <> | 161:2cc1468da177 | 4 | * @author MCD Application Team |
| <> | 161:2cc1468da177 | 5 | * @version V1.2.0 |
| <> | 161:2cc1468da177 | 6 | * @date 30-December-2016 |
| <> | 161:2cc1468da177 | 7 | * @brief DMA LL module driver. |
| <> | 161:2cc1468da177 | 8 | ****************************************************************************** |
| <> | 161:2cc1468da177 | 9 | * @attention |
| <> | 161:2cc1468da177 | 10 | * |
| <> | 161:2cc1468da177 | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| <> | 161:2cc1468da177 | 12 | * |
| <> | 161:2cc1468da177 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| <> | 161:2cc1468da177 | 14 | * are permitted provided that the following conditions are met: |
| <> | 161:2cc1468da177 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| <> | 161:2cc1468da177 | 16 | * this list of conditions and the following disclaimer. |
| <> | 161:2cc1468da177 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| <> | 161:2cc1468da177 | 18 | * this list of conditions and the following disclaimer in the documentation |
| <> | 161:2cc1468da177 | 19 | * and/or other materials provided with the distribution. |
| <> | 161:2cc1468da177 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| <> | 161:2cc1468da177 | 21 | * may be used to endorse or promote products derived from this software |
| <> | 161:2cc1468da177 | 22 | * without specific prior written permission. |
| <> | 161:2cc1468da177 | 23 | * |
| <> | 161:2cc1468da177 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| <> | 161:2cc1468da177 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| <> | 161:2cc1468da177 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| <> | 161:2cc1468da177 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| <> | 161:2cc1468da177 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| <> | 161:2cc1468da177 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| <> | 161:2cc1468da177 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| <> | 161:2cc1468da177 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| <> | 161:2cc1468da177 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| <> | 161:2cc1468da177 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| <> | 161:2cc1468da177 | 34 | * |
| <> | 161:2cc1468da177 | 35 | ****************************************************************************** |
| <> | 161:2cc1468da177 | 36 | */ |
| <> | 161:2cc1468da177 | 37 | #if defined(USE_FULL_LL_DRIVER) |
| <> | 161:2cc1468da177 | 38 | |
| <> | 161:2cc1468da177 | 39 | /* Includes ------------------------------------------------------------------*/ |
| <> | 161:2cc1468da177 | 40 | #include "stm32f7xx_ll_dma.h" |
| <> | 161:2cc1468da177 | 41 | #include "stm32f7xx_ll_bus.h" |
| <> | 161:2cc1468da177 | 42 | #ifdef USE_FULL_ASSERT |
| <> | 161:2cc1468da177 | 43 | #include "stm32_assert.h" |
| <> | 161:2cc1468da177 | 44 | #else |
| <> | 161:2cc1468da177 | 45 | #define assert_param(expr) ((void)0U) |
| <> | 161:2cc1468da177 | 46 | #endif |
| <> | 161:2cc1468da177 | 47 | |
| <> | 161:2cc1468da177 | 48 | /** @addtogroup STM32F7xx_LL_Driver |
| <> | 161:2cc1468da177 | 49 | * @{ |
| <> | 161:2cc1468da177 | 50 | */ |
| <> | 161:2cc1468da177 | 51 | |
| <> | 161:2cc1468da177 | 52 | #if defined (DMA1) || defined (DMA2) |
| <> | 161:2cc1468da177 | 53 | |
| <> | 161:2cc1468da177 | 54 | /** @defgroup DMA_LL DMA |
| <> | 161:2cc1468da177 | 55 | * @{ |
| <> | 161:2cc1468da177 | 56 | */ |
| <> | 161:2cc1468da177 | 57 | |
| <> | 161:2cc1468da177 | 58 | /* Private types -------------------------------------------------------------*/ |
| <> | 161:2cc1468da177 | 59 | /* Private variables ---------------------------------------------------------*/ |
| <> | 161:2cc1468da177 | 60 | /* Private constants ---------------------------------------------------------*/ |
| <> | 161:2cc1468da177 | 61 | /* Private macros ------------------------------------------------------------*/ |
| <> | 161:2cc1468da177 | 62 | /** @addtogroup DMA_LL_Private_Macros |
| <> | 161:2cc1468da177 | 63 | * @{ |
| <> | 161:2cc1468da177 | 64 | */ |
| <> | 161:2cc1468da177 | 65 | #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \ |
| <> | 161:2cc1468da177 | 66 | ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \ |
| <> | 161:2cc1468da177 | 67 | ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY)) |
| <> | 161:2cc1468da177 | 68 | |
| <> | 161:2cc1468da177 | 69 | #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \ |
| <> | 161:2cc1468da177 | 70 | ((__VALUE__) == LL_DMA_MODE_CIRCULAR) || \ |
| <> | 161:2cc1468da177 | 71 | ((__VALUE__) == LL_DMA_MODE_PFCTRL)) |
| <> | 161:2cc1468da177 | 72 | |
| <> | 161:2cc1468da177 | 73 | #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \ |
| <> | 161:2cc1468da177 | 74 | ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT)) |
| <> | 161:2cc1468da177 | 75 | |
| <> | 161:2cc1468da177 | 76 | #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \ |
| <> | 161:2cc1468da177 | 77 | ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT)) |
| <> | 161:2cc1468da177 | 78 | |
| <> | 161:2cc1468da177 | 79 | #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \ |
| <> | 161:2cc1468da177 | 80 | ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \ |
| <> | 161:2cc1468da177 | 81 | ((__VALUE__) == LL_DMA_PDATAALIGN_WORD)) |
| <> | 161:2cc1468da177 | 82 | |
| <> | 161:2cc1468da177 | 83 | #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \ |
| <> | 161:2cc1468da177 | 84 | ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \ |
| <> | 161:2cc1468da177 | 85 | ((__VALUE__) == LL_DMA_MDATAALIGN_WORD)) |
| <> | 161:2cc1468da177 | 86 | |
| <> | 161:2cc1468da177 | 87 | #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) |
| <> | 161:2cc1468da177 | 88 | |
| <> | 161:2cc1468da177 | 89 | #if defined(DMA_CHANNEL_SELECTION_8_15) |
| <> | 161:2cc1468da177 | 90 | #define IS_LL_DMA_CHANNEL(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_0) || \ |
| <> | 161:2cc1468da177 | 91 | ((__VALUE__) == LL_DMA_CHANNEL_1) || \ |
| <> | 161:2cc1468da177 | 92 | ((__VALUE__) == LL_DMA_CHANNEL_2) || \ |
| <> | 161:2cc1468da177 | 93 | ((__VALUE__) == LL_DMA_CHANNEL_3) || \ |
| <> | 161:2cc1468da177 | 94 | ((__VALUE__) == LL_DMA_CHANNEL_4) || \ |
| <> | 161:2cc1468da177 | 95 | ((__VALUE__) == LL_DMA_CHANNEL_5) || \ |
| <> | 161:2cc1468da177 | 96 | ((__VALUE__) == LL_DMA_CHANNEL_6) || \ |
| <> | 161:2cc1468da177 | 97 | ((__VALUE__) == LL_DMA_CHANNEL_7) || \ |
| <> | 161:2cc1468da177 | 98 | ((__VALUE__) == LL_DMA_CHANNEL_8) || \ |
| <> | 161:2cc1468da177 | 99 | ((__VALUE__) == LL_DMA_CHANNEL_9) || \ |
| <> | 161:2cc1468da177 | 100 | ((__VALUE__) == LL_DMA_CHANNEL_10) || \ |
| <> | 161:2cc1468da177 | 101 | ((__VALUE__) == LL_DMA_CHANNEL_11) || \ |
| <> | 161:2cc1468da177 | 102 | ((__VALUE__) == LL_DMA_CHANNEL_12) || \ |
| <> | 161:2cc1468da177 | 103 | ((__VALUE__) == LL_DMA_CHANNEL_13) || \ |
| <> | 161:2cc1468da177 | 104 | ((__VALUE__) == LL_DMA_CHANNEL_14) || \ |
| <> | 161:2cc1468da177 | 105 | ((__VALUE__) == LL_DMA_CHANNEL_15)) |
| <> | 161:2cc1468da177 | 106 | |
| <> | 161:2cc1468da177 | 107 | #else |
| <> | 161:2cc1468da177 | 108 | #define IS_LL_DMA_CHANNEL(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_0) || \ |
| <> | 161:2cc1468da177 | 109 | ((__VALUE__) == LL_DMA_CHANNEL_1) || \ |
| <> | 161:2cc1468da177 | 110 | ((__VALUE__) == LL_DMA_CHANNEL_2) || \ |
| <> | 161:2cc1468da177 | 111 | ((__VALUE__) == LL_DMA_CHANNEL_3) || \ |
| <> | 161:2cc1468da177 | 112 | ((__VALUE__) == LL_DMA_CHANNEL_4) || \ |
| <> | 161:2cc1468da177 | 113 | ((__VALUE__) == LL_DMA_CHANNEL_5) || \ |
| <> | 161:2cc1468da177 | 114 | ((__VALUE__) == LL_DMA_CHANNEL_6) || \ |
| <> | 161:2cc1468da177 | 115 | ((__VALUE__) == LL_DMA_CHANNEL_7)) |
| <> | 161:2cc1468da177 | 116 | |
| <> | 161:2cc1468da177 | 117 | #endif /* DMA_CHANNEL_SELECTION_8_15 */ |
| <> | 161:2cc1468da177 | 118 | |
| <> | 161:2cc1468da177 | 119 | #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \ |
| <> | 161:2cc1468da177 | 120 | ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \ |
| <> | 161:2cc1468da177 | 121 | ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \ |
| <> | 161:2cc1468da177 | 122 | ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH)) |
| <> | 161:2cc1468da177 | 123 | |
| <> | 161:2cc1468da177 | 124 | #define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM) ((((INSTANCE) == DMA1) && \ |
| <> | 161:2cc1468da177 | 125 | (((STREAM) == LL_DMA_STREAM_0) || \ |
| <> | 161:2cc1468da177 | 126 | ((STREAM) == LL_DMA_STREAM_1) || \ |
| <> | 161:2cc1468da177 | 127 | ((STREAM) == LL_DMA_STREAM_2) || \ |
| <> | 161:2cc1468da177 | 128 | ((STREAM) == LL_DMA_STREAM_3) || \ |
| <> | 161:2cc1468da177 | 129 | ((STREAM) == LL_DMA_STREAM_4) || \ |
| <> | 161:2cc1468da177 | 130 | ((STREAM) == LL_DMA_STREAM_5) || \ |
| <> | 161:2cc1468da177 | 131 | ((STREAM) == LL_DMA_STREAM_6) || \ |
| <> | 161:2cc1468da177 | 132 | ((STREAM) == LL_DMA_STREAM_7) || \ |
| <> | 161:2cc1468da177 | 133 | ((STREAM) == LL_DMA_STREAM_ALL))) ||\ |
| <> | 161:2cc1468da177 | 134 | (((INSTANCE) == DMA2) && \ |
| <> | 161:2cc1468da177 | 135 | (((STREAM) == LL_DMA_STREAM_0) || \ |
| <> | 161:2cc1468da177 | 136 | ((STREAM) == LL_DMA_STREAM_1) || \ |
| <> | 161:2cc1468da177 | 137 | ((STREAM) == LL_DMA_STREAM_2) || \ |
| <> | 161:2cc1468da177 | 138 | ((STREAM) == LL_DMA_STREAM_3) || \ |
| <> | 161:2cc1468da177 | 139 | ((STREAM) == LL_DMA_STREAM_4) || \ |
| <> | 161:2cc1468da177 | 140 | ((STREAM) == LL_DMA_STREAM_5) || \ |
| <> | 161:2cc1468da177 | 141 | ((STREAM) == LL_DMA_STREAM_6) || \ |
| <> | 161:2cc1468da177 | 142 | ((STREAM) == LL_DMA_STREAM_7) || \ |
| <> | 161:2cc1468da177 | 143 | ((STREAM) == LL_DMA_STREAM_ALL)))) |
| <> | 161:2cc1468da177 | 144 | |
| <> | 161:2cc1468da177 | 145 | #define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \ |
| <> | 161:2cc1468da177 | 146 | ((STATE) == LL_DMA_FIFOMODE_ENABLE)) |
| <> | 161:2cc1468da177 | 147 | |
| <> | 161:2cc1468da177 | 148 | #define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \ |
| <> | 161:2cc1468da177 | 149 | ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2) || \ |
| <> | 161:2cc1468da177 | 150 | ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4) || \ |
| <> | 161:2cc1468da177 | 151 | ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL)) |
| <> | 161:2cc1468da177 | 152 | |
| <> | 161:2cc1468da177 | 153 | #define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \ |
| <> | 161:2cc1468da177 | 154 | ((BURST) == LL_DMA_MBURST_INC4) || \ |
| <> | 161:2cc1468da177 | 155 | ((BURST) == LL_DMA_MBURST_INC8) || \ |
| <> | 161:2cc1468da177 | 156 | ((BURST) == LL_DMA_MBURST_INC16)) |
| <> | 161:2cc1468da177 | 157 | |
| <> | 161:2cc1468da177 | 158 | #define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \ |
| <> | 161:2cc1468da177 | 159 | ((BURST) == LL_DMA_PBURST_INC4) || \ |
| <> | 161:2cc1468da177 | 160 | ((BURST) == LL_DMA_PBURST_INC8) || \ |
| <> | 161:2cc1468da177 | 161 | ((BURST) == LL_DMA_PBURST_INC16)) |
| <> | 161:2cc1468da177 | 162 | |
| <> | 161:2cc1468da177 | 163 | /** |
| <> | 161:2cc1468da177 | 164 | * @} |
| <> | 161:2cc1468da177 | 165 | */ |
| <> | 161:2cc1468da177 | 166 | |
| <> | 161:2cc1468da177 | 167 | /* Private function prototypes -----------------------------------------------*/ |
| <> | 161:2cc1468da177 | 168 | |
| <> | 161:2cc1468da177 | 169 | /* Exported functions --------------------------------------------------------*/ |
| <> | 161:2cc1468da177 | 170 | /** @addtogroup DMA_LL_Exported_Functions |
| <> | 161:2cc1468da177 | 171 | * @{ |
| <> | 161:2cc1468da177 | 172 | */ |
| <> | 161:2cc1468da177 | 173 | |
| <> | 161:2cc1468da177 | 174 | /** @addtogroup DMA_LL_EF_Init |
| <> | 161:2cc1468da177 | 175 | * @{ |
| <> | 161:2cc1468da177 | 176 | */ |
| <> | 161:2cc1468da177 | 177 | |
| <> | 161:2cc1468da177 | 178 | /** |
| <> | 161:2cc1468da177 | 179 | * @brief De-initialize the DMA registers to their default reset values. |
| <> | 161:2cc1468da177 | 180 | * @param DMAx DMAx Instance |
| <> | 161:2cc1468da177 | 181 | * @param Stream This parameter can be one of the following values: |
| <> | 161:2cc1468da177 | 182 | * @arg @ref LL_DMA_STREAM_0 |
| <> | 161:2cc1468da177 | 183 | * @arg @ref LL_DMA_STREAM_1 |
| <> | 161:2cc1468da177 | 184 | * @arg @ref LL_DMA_STREAM_2 |
| <> | 161:2cc1468da177 | 185 | * @arg @ref LL_DMA_STREAM_3 |
| <> | 161:2cc1468da177 | 186 | * @arg @ref LL_DMA_STREAM_4 |
| <> | 161:2cc1468da177 | 187 | * @arg @ref LL_DMA_STREAM_5 |
| <> | 161:2cc1468da177 | 188 | * @arg @ref LL_DMA_STREAM_6 |
| <> | 161:2cc1468da177 | 189 | * @arg @ref LL_DMA_STREAM_7 |
| <> | 161:2cc1468da177 | 190 | * @arg @ref LL_DMA_STREAM_ALL |
| <> | 161:2cc1468da177 | 191 | * @retval An ErrorStatus enumeration value: |
| <> | 161:2cc1468da177 | 192 | * - SUCCESS: DMA registers are de-initialized |
| <> | 161:2cc1468da177 | 193 | * - ERROR: DMA registers are not de-initialized |
| <> | 161:2cc1468da177 | 194 | */ |
| <> | 161:2cc1468da177 | 195 | uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream) |
| <> | 161:2cc1468da177 | 196 | { |
| <> | 161:2cc1468da177 | 197 | DMA_Stream_TypeDef *tmp = (DMA_Stream_TypeDef *)DMA1_Stream0; |
| <> | 161:2cc1468da177 | 198 | ErrorStatus status = SUCCESS; |
| <> | 161:2cc1468da177 | 199 | |
| <> | 161:2cc1468da177 | 200 | /* Check the DMA Instance DMAx and Stream parameters*/ |
| <> | 161:2cc1468da177 | 201 | assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream)); |
| <> | 161:2cc1468da177 | 202 | |
| <> | 161:2cc1468da177 | 203 | if (Stream == LL_DMA_STREAM_ALL) |
| <> | 161:2cc1468da177 | 204 | { |
| <> | 161:2cc1468da177 | 205 | if (DMAx == DMA1) |
| <> | 161:2cc1468da177 | 206 | { |
| <> | 161:2cc1468da177 | 207 | /* Force reset of DMA clock */ |
| <> | 161:2cc1468da177 | 208 | LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1); |
| <> | 161:2cc1468da177 | 209 | |
| <> | 161:2cc1468da177 | 210 | /* Release reset of DMA clock */ |
| <> | 161:2cc1468da177 | 211 | LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1); |
| <> | 161:2cc1468da177 | 212 | } |
| <> | 161:2cc1468da177 | 213 | else if (DMAx == DMA2) |
| <> | 161:2cc1468da177 | 214 | { |
| <> | 161:2cc1468da177 | 215 | /* Force reset of DMA clock */ |
| <> | 161:2cc1468da177 | 216 | LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2); |
| <> | 161:2cc1468da177 | 217 | |
| <> | 161:2cc1468da177 | 218 | /* Release reset of DMA clock */ |
| <> | 161:2cc1468da177 | 219 | LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2); |
| <> | 161:2cc1468da177 | 220 | } |
| <> | 161:2cc1468da177 | 221 | else |
| <> | 161:2cc1468da177 | 222 | { |
| <> | 161:2cc1468da177 | 223 | status = ERROR; |
| <> | 161:2cc1468da177 | 224 | } |
| <> | 161:2cc1468da177 | 225 | } |
| <> | 161:2cc1468da177 | 226 | else |
| <> | 161:2cc1468da177 | 227 | { |
| <> | 161:2cc1468da177 | 228 | /* Disable the selected Stream */ |
| <> | 161:2cc1468da177 | 229 | LL_DMA_DisableStream(DMAx,Stream); |
| <> | 161:2cc1468da177 | 230 | |
| <> | 161:2cc1468da177 | 231 | /* Get the DMA Stream Instance */ |
| <> | 161:2cc1468da177 | 232 | tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream)); |
| <> | 161:2cc1468da177 | 233 | |
| <> | 161:2cc1468da177 | 234 | /* Reset DMAx_Streamy configuration register */ |
| <> | 161:2cc1468da177 | 235 | LL_DMA_WriteReg(tmp, CR, 0U); |
| <> | 161:2cc1468da177 | 236 | |
| <> | 161:2cc1468da177 | 237 | /* Reset DMAx_Streamy remaining bytes register */ |
| <> | 161:2cc1468da177 | 238 | LL_DMA_WriteReg(tmp, NDTR, 0U); |
| <> | 161:2cc1468da177 | 239 | |
| <> | 161:2cc1468da177 | 240 | /* Reset DMAx_Streamy peripheral address register */ |
| <> | 161:2cc1468da177 | 241 | LL_DMA_WriteReg(tmp, PAR, 0U); |
| <> | 161:2cc1468da177 | 242 | |
| <> | 161:2cc1468da177 | 243 | /* Reset DMAx_Streamy memory address register */ |
| <> | 161:2cc1468da177 | 244 | LL_DMA_WriteReg(tmp, M0AR, 0U); |
| <> | 161:2cc1468da177 | 245 | |
| <> | 161:2cc1468da177 | 246 | /* Reset DMAx_Streamy memory address register */ |
| <> | 161:2cc1468da177 | 247 | LL_DMA_WriteReg(tmp, M1AR, 0U); |
| <> | 161:2cc1468da177 | 248 | |
| <> | 161:2cc1468da177 | 249 | /* Reset DMAx_Streamy FIFO control register */ |
| <> | 161:2cc1468da177 | 250 | LL_DMA_WriteReg(tmp, FCR, 0x00000021U); |
| <> | 161:2cc1468da177 | 251 | |
| <> | 161:2cc1468da177 | 252 | /* Reset Channel register field for DMAx Stream*/ |
| <> | 161:2cc1468da177 | 253 | LL_DMA_SetChannelSelection(DMAx, Stream, LL_DMA_CHANNEL_0); |
| <> | 161:2cc1468da177 | 254 | |
| <> | 161:2cc1468da177 | 255 | if(Stream == LL_DMA_STREAM_0) |
| <> | 161:2cc1468da177 | 256 | { |
| <> | 161:2cc1468da177 | 257 | /* Reset the Stream0 pending flags */ |
| <> | 161:2cc1468da177 | 258 | DMAx->LIFCR = 0x0000003FU; |
| <> | 161:2cc1468da177 | 259 | } |
| <> | 161:2cc1468da177 | 260 | else if(Stream == LL_DMA_STREAM_1) |
| <> | 161:2cc1468da177 | 261 | { |
| <> | 161:2cc1468da177 | 262 | /* Reset the Stream1 pending flags */ |
| <> | 161:2cc1468da177 | 263 | DMAx->LIFCR = 0x00000F40U; |
| <> | 161:2cc1468da177 | 264 | } |
| <> | 161:2cc1468da177 | 265 | else if(Stream == LL_DMA_STREAM_2) |
| <> | 161:2cc1468da177 | 266 | { |
| <> | 161:2cc1468da177 | 267 | /* Reset the Stream2 pending flags */ |
| <> | 161:2cc1468da177 | 268 | DMAx->LIFCR = 0x003F0000U; |
| <> | 161:2cc1468da177 | 269 | } |
| <> | 161:2cc1468da177 | 270 | else if(Stream == LL_DMA_STREAM_3) |
| <> | 161:2cc1468da177 | 271 | { |
| <> | 161:2cc1468da177 | 272 | /* Reset the Stream3 pending flags */ |
| <> | 161:2cc1468da177 | 273 | DMAx->LIFCR = 0x0F400000U; |
| <> | 161:2cc1468da177 | 274 | } |
| <> | 161:2cc1468da177 | 275 | else if(Stream == LL_DMA_STREAM_4) |
| <> | 161:2cc1468da177 | 276 | { |
| <> | 161:2cc1468da177 | 277 | /* Reset the Stream4 pending flags */ |
| <> | 161:2cc1468da177 | 278 | DMAx->HIFCR = 0x0000003FU; |
| <> | 161:2cc1468da177 | 279 | } |
| <> | 161:2cc1468da177 | 280 | else if(Stream == LL_DMA_STREAM_5) |
| <> | 161:2cc1468da177 | 281 | { |
| <> | 161:2cc1468da177 | 282 | /* Reset the Stream5 pending flags */ |
| <> | 161:2cc1468da177 | 283 | DMAx->HIFCR = 0x00000F40U; |
| <> | 161:2cc1468da177 | 284 | } |
| <> | 161:2cc1468da177 | 285 | else if(Stream == LL_DMA_STREAM_6) |
| <> | 161:2cc1468da177 | 286 | { |
| <> | 161:2cc1468da177 | 287 | /* Reset the Stream6 pending flags */ |
| <> | 161:2cc1468da177 | 288 | DMAx->HIFCR = 0x003F0000U; |
| <> | 161:2cc1468da177 | 289 | } |
| <> | 161:2cc1468da177 | 290 | else if(Stream == LL_DMA_STREAM_7) |
| <> | 161:2cc1468da177 | 291 | { |
| <> | 161:2cc1468da177 | 292 | /* Reset the Stream7 pending flags */ |
| <> | 161:2cc1468da177 | 293 | DMAx->HIFCR = 0x0F400000U; |
| <> | 161:2cc1468da177 | 294 | } |
| <> | 161:2cc1468da177 | 295 | else |
| <> | 161:2cc1468da177 | 296 | { |
| <> | 161:2cc1468da177 | 297 | status = ERROR; |
| <> | 161:2cc1468da177 | 298 | } |
| <> | 161:2cc1468da177 | 299 | } |
| <> | 161:2cc1468da177 | 300 | |
| <> | 161:2cc1468da177 | 301 | return status; |
| <> | 161:2cc1468da177 | 302 | } |
| <> | 161:2cc1468da177 | 303 | |
| <> | 161:2cc1468da177 | 304 | /** |
| <> | 161:2cc1468da177 | 305 | * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct. |
| <> | 161:2cc1468da177 | 306 | * @note To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros : |
| <> | 161:2cc1468da177 | 307 | * @arg @ref __LL_DMA_GET_INSTANCE |
| <> | 161:2cc1468da177 | 308 | * @arg @ref __LL_DMA_GET_STREAM |
| <> | 161:2cc1468da177 | 309 | * @param DMAx DMAx Instance |
| <> | 161:2cc1468da177 | 310 | * @param Stream This parameter can be one of the following values: |
| <> | 161:2cc1468da177 | 311 | * @arg @ref LL_DMA_STREAM_0 |
| <> | 161:2cc1468da177 | 312 | * @arg @ref LL_DMA_STREAM_1 |
| <> | 161:2cc1468da177 | 313 | * @arg @ref LL_DMA_STREAM_2 |
| <> | 161:2cc1468da177 | 314 | * @arg @ref LL_DMA_STREAM_3 |
| <> | 161:2cc1468da177 | 315 | * @arg @ref LL_DMA_STREAM_4 |
| <> | 161:2cc1468da177 | 316 | * @arg @ref LL_DMA_STREAM_5 |
| <> | 161:2cc1468da177 | 317 | * @arg @ref LL_DMA_STREAM_6 |
| <> | 161:2cc1468da177 | 318 | * @arg @ref LL_DMA_STREAM_7 |
| <> | 161:2cc1468da177 | 319 | * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure. |
| <> | 161:2cc1468da177 | 320 | * @retval An ErrorStatus enumeration value: |
| <> | 161:2cc1468da177 | 321 | * - SUCCESS: DMA registers are initialized |
| <> | 161:2cc1468da177 | 322 | * - ERROR: Not applicable |
| <> | 161:2cc1468da177 | 323 | */ |
| <> | 161:2cc1468da177 | 324 | uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct) |
| <> | 161:2cc1468da177 | 325 | { |
| <> | 161:2cc1468da177 | 326 | /* Check the DMA Instance DMAx and Stream parameters*/ |
| <> | 161:2cc1468da177 | 327 | assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream)); |
| <> | 161:2cc1468da177 | 328 | |
| <> | 161:2cc1468da177 | 329 | /* Check the DMA parameters from DMA_InitStruct */ |
| <> | 161:2cc1468da177 | 330 | assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction)); |
| <> | 161:2cc1468da177 | 331 | assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode)); |
| <> | 161:2cc1468da177 | 332 | assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode)); |
| <> | 161:2cc1468da177 | 333 | assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode)); |
| <> | 161:2cc1468da177 | 334 | assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize)); |
| <> | 161:2cc1468da177 | 335 | assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize)); |
| <> | 161:2cc1468da177 | 336 | assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData)); |
| <> | 161:2cc1468da177 | 337 | assert_param(IS_LL_DMA_CHANNEL(DMA_InitStruct->Channel)); |
| <> | 161:2cc1468da177 | 338 | assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority)); |
| <> | 161:2cc1468da177 | 339 | assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode)); |
| <> | 161:2cc1468da177 | 340 | /* Check the memory burst, peripheral burst and FIFO threshold parameters only |
| <> | 161:2cc1468da177 | 341 | when FIFO mode is enabled */ |
| <> | 161:2cc1468da177 | 342 | if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE) |
| <> | 161:2cc1468da177 | 343 | { |
| <> | 161:2cc1468da177 | 344 | assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold)); |
| <> | 161:2cc1468da177 | 345 | assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst)); |
| <> | 161:2cc1468da177 | 346 | assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst)); |
| <> | 161:2cc1468da177 | 347 | } |
| <> | 161:2cc1468da177 | 348 | |
| <> | 161:2cc1468da177 | 349 | /*---------------------------- DMAx SxCR Configuration ------------------------ |
| <> | 161:2cc1468da177 | 350 | * Configure DMAx_Streamy: data transfer direction, data transfer mode, |
| <> | 161:2cc1468da177 | 351 | * peripheral and memory increment mode, |
| <> | 161:2cc1468da177 | 352 | * data size alignment and priority level with parameters : |
| <> | 161:2cc1468da177 | 353 | * - Direction: DMA_SxCR_DIR[1:0] bits |
| <> | 161:2cc1468da177 | 354 | * - Mode: DMA_SxCR_CIRC bit |
| <> | 161:2cc1468da177 | 355 | * - PeriphOrM2MSrcIncMode: DMA_SxCR_PINC bit |
| <> | 161:2cc1468da177 | 356 | * - MemoryOrM2MDstIncMode: DMA_SxCR_MINC bit |
| <> | 161:2cc1468da177 | 357 | * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits |
| <> | 161:2cc1468da177 | 358 | * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits |
| <> | 161:2cc1468da177 | 359 | * - Priority: DMA_SxCR_PL[1:0] bits |
| <> | 161:2cc1468da177 | 360 | */ |
| <> | 161:2cc1468da177 | 361 | LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \ |
| <> | 161:2cc1468da177 | 362 | DMA_InitStruct->Mode | \ |
| <> | 161:2cc1468da177 | 363 | DMA_InitStruct->PeriphOrM2MSrcIncMode | \ |
| <> | 161:2cc1468da177 | 364 | DMA_InitStruct->MemoryOrM2MDstIncMode | \ |
| <> | 161:2cc1468da177 | 365 | DMA_InitStruct->PeriphOrM2MSrcDataSize | \ |
| <> | 161:2cc1468da177 | 366 | DMA_InitStruct->MemoryOrM2MDstDataSize | \ |
| <> | 161:2cc1468da177 | 367 | DMA_InitStruct->Priority |
| <> | 161:2cc1468da177 | 368 | ); |
| <> | 161:2cc1468da177 | 369 | |
| <> | 161:2cc1468da177 | 370 | if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE) |
| <> | 161:2cc1468da177 | 371 | { |
| <> | 161:2cc1468da177 | 372 | /*---------------------------- DMAx SxFCR Configuration ------------------------ |
| <> | 161:2cc1468da177 | 373 | * Configure DMAx_Streamy: fifo mode and fifo threshold with parameters : |
| <> | 161:2cc1468da177 | 374 | * - FIFOMode: DMA_SxFCR_DMDIS bit |
| <> | 161:2cc1468da177 | 375 | * - FIFOThreshold: DMA_SxFCR_FTH[1:0] bits |
| <> | 161:2cc1468da177 | 376 | */ |
| <> | 161:2cc1468da177 | 377 | LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold); |
| <> | 161:2cc1468da177 | 378 | |
| <> | 161:2cc1468da177 | 379 | /*---------------------------- DMAx SxCR Configuration -------------------------- |
| <> | 161:2cc1468da177 | 380 | * Configure DMAx_Streamy: memory burst transfer with parameters : |
| <> | 161:2cc1468da177 | 381 | * - MemBurst: DMA_SxCR_MBURST[1:0] bits |
| <> | 161:2cc1468da177 | 382 | */ |
| <> | 161:2cc1468da177 | 383 | LL_DMA_SetMemoryBurstxfer(DMAx,Stream,DMA_InitStruct->MemBurst); |
| <> | 161:2cc1468da177 | 384 | |
| <> | 161:2cc1468da177 | 385 | /*---------------------------- DMAx SxCR Configuration -------------------------- |
| <> | 161:2cc1468da177 | 386 | * Configure DMAx_Streamy: peripheral burst transfer with parameters : |
| <> | 161:2cc1468da177 | 387 | * - PeriphBurst: DMA_SxCR_PBURST[1:0] bits |
| <> | 161:2cc1468da177 | 388 | */ |
| <> | 161:2cc1468da177 | 389 | LL_DMA_SetPeriphBurstxfer(DMAx,Stream,DMA_InitStruct->PeriphBurst); |
| <> | 161:2cc1468da177 | 390 | } |
| <> | 161:2cc1468da177 | 391 | |
| <> | 161:2cc1468da177 | 392 | /*-------------------------- DMAx SxM0AR Configuration -------------------------- |
| <> | 161:2cc1468da177 | 393 | * Configure the memory or destination base address with parameter : |
| <> | 161:2cc1468da177 | 394 | * - MemoryOrM2MDstAddress: DMA_SxM0AR_M0A[31:0] bits |
| <> | 161:2cc1468da177 | 395 | */ |
| <> | 161:2cc1468da177 | 396 | LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress); |
| <> | 161:2cc1468da177 | 397 | |
| <> | 161:2cc1468da177 | 398 | /*-------------------------- DMAx SxPAR Configuration --------------------------- |
| <> | 161:2cc1468da177 | 399 | * Configure the peripheral or source base address with parameter : |
| <> | 161:2cc1468da177 | 400 | * - PeriphOrM2MSrcAddress: DMA_SxPAR_PA[31:0] bits |
| <> | 161:2cc1468da177 | 401 | */ |
| <> | 161:2cc1468da177 | 402 | LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress); |
| <> | 161:2cc1468da177 | 403 | |
| <> | 161:2cc1468da177 | 404 | /*--------------------------- DMAx SxNDTR Configuration ------------------------- |
| <> | 161:2cc1468da177 | 405 | * Configure the peripheral base address with parameter : |
| <> | 161:2cc1468da177 | 406 | * - NbData: DMA_SxNDT[15:0] bits |
| <> | 161:2cc1468da177 | 407 | */ |
| <> | 161:2cc1468da177 | 408 | LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData); |
| <> | 161:2cc1468da177 | 409 | |
| <> | 161:2cc1468da177 | 410 | /*--------------------------- DMA SxCR_CHSEL Configuration ---------------------- |
| <> | 161:2cc1468da177 | 411 | * Configure the peripheral base address with parameter : |
| <> | 161:2cc1468da177 | 412 | * - PeriphRequest: DMA_SxCR_CHSEL[3:0] bits |
| <> | 161:2cc1468da177 | 413 | */ |
| <> | 161:2cc1468da177 | 414 | LL_DMA_SetChannelSelection(DMAx, Stream, DMA_InitStruct->Channel); |
| <> | 161:2cc1468da177 | 415 | |
| <> | 161:2cc1468da177 | 416 | return SUCCESS; |
| <> | 161:2cc1468da177 | 417 | } |
| <> | 161:2cc1468da177 | 418 | |
| <> | 161:2cc1468da177 | 419 | /** |
| <> | 161:2cc1468da177 | 420 | * @brief Set each @ref LL_DMA_InitTypeDef field to default value. |
| <> | 161:2cc1468da177 | 421 | * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure. |
| <> | 161:2cc1468da177 | 422 | * @retval None |
| <> | 161:2cc1468da177 | 423 | */ |
| <> | 161:2cc1468da177 | 424 | void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) |
| <> | 161:2cc1468da177 | 425 | { |
| <> | 161:2cc1468da177 | 426 | /* Set DMA_InitStruct fields to default values */ |
| <> | 161:2cc1468da177 | 427 | DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U; |
| <> | 161:2cc1468da177 | 428 | DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U; |
| <> | 161:2cc1468da177 | 429 | DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; |
| <> | 161:2cc1468da177 | 430 | DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL; |
| <> | 161:2cc1468da177 | 431 | DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; |
| <> | 161:2cc1468da177 | 432 | DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; |
| <> | 161:2cc1468da177 | 433 | DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; |
| <> | 161:2cc1468da177 | 434 | DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; |
| <> | 161:2cc1468da177 | 435 | DMA_InitStruct->NbData = 0x00000000U; |
| <> | 161:2cc1468da177 | 436 | DMA_InitStruct->Channel = LL_DMA_CHANNEL_0; |
| <> | 161:2cc1468da177 | 437 | DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW; |
| <> | 161:2cc1468da177 | 438 | DMA_InitStruct->FIFOMode = LL_DMA_FIFOMODE_DISABLE; |
| <> | 161:2cc1468da177 | 439 | DMA_InitStruct->FIFOThreshold = LL_DMA_FIFOTHRESHOLD_1_4; |
| <> | 161:2cc1468da177 | 440 | DMA_InitStruct->MemBurst = LL_DMA_MBURST_SINGLE; |
| <> | 161:2cc1468da177 | 441 | DMA_InitStruct->PeriphBurst = LL_DMA_PBURST_SINGLE; |
| <> | 161:2cc1468da177 | 442 | } |
| <> | 161:2cc1468da177 | 443 | |
| <> | 161:2cc1468da177 | 444 | /** |
| <> | 161:2cc1468da177 | 445 | * @} |
| <> | 161:2cc1468da177 | 446 | */ |
| <> | 161:2cc1468da177 | 447 | |
| <> | 161:2cc1468da177 | 448 | /** |
| <> | 161:2cc1468da177 | 449 | * @} |
| <> | 161:2cc1468da177 | 450 | */ |
| <> | 161:2cc1468da177 | 451 | |
| <> | 161:2cc1468da177 | 452 | /** |
| <> | 161:2cc1468da177 | 453 | * @} |
| <> | 161:2cc1468da177 | 454 | */ |
| <> | 161:2cc1468da177 | 455 | |
| <> | 161:2cc1468da177 | 456 | #endif /* DMA1 || DMA2 */ |
| <> | 161:2cc1468da177 | 457 | |
| <> | 161:2cc1468da177 | 458 | /** |
| <> | 161:2cc1468da177 | 459 | * @} |
| <> | 161:2cc1468da177 | 460 | */ |
| <> | 161:2cc1468da177 | 461 | |
| <> | 161:2cc1468da177 | 462 | #endif /* USE_FULL_LL_DRIVER */ |
| <> | 161:2cc1468da177 | 463 | |
| <> | 161:2cc1468da177 | 464 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |