Frederick Huang / mbed-STM32L452

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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc_ex.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc_ex.c@144:ef7eb2e8f9f7
Child:
154:37f96f9d4de2
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_rcc_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.0.4
<> 144:ef7eb2e8f9f7 6 * @date 29-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief Extended RCC HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities RCC extension peripheral:
<> 144:ef7eb2e8f9f7 10 * + Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 ******************************************************************************
<> 144:ef7eb2e8f9f7 13 * @attention
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 16 *
<> 144:ef7eb2e8f9f7 17 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 18 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 19 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 20 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 21 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 22 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 23 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 25 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 26 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 27 *
<> 144:ef7eb2e8f9f7 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 38 *
<> 144:ef7eb2e8f9f7 39 ******************************************************************************
<> 144:ef7eb2e8f9f7 40 */
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 43 #include "stm32f1xx_hal.h"
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 46 * @{
<> 144:ef7eb2e8f9f7 47 */
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 #ifdef HAL_RCC_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /** @defgroup RCCEx RCCEx
<> 144:ef7eb2e8f9f7 52 * @brief RCC Extension HAL module driver.
<> 144:ef7eb2e8f9f7 53 * @{
<> 144:ef7eb2e8f9f7 54 */
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 57 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61 /**
<> 144:ef7eb2e8f9f7 62 * @}
<> 144:ef7eb2e8f9f7 63 */
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 66 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
<> 144:ef7eb2e8f9f7 67 * @{
<> 144:ef7eb2e8f9f7 68 */
<> 144:ef7eb2e8f9f7 69 /**
<> 144:ef7eb2e8f9f7 70 * @}
<> 144:ef7eb2e8f9f7 71 */
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 74 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 75 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
<> 144:ef7eb2e8f9f7 78 * @{
<> 144:ef7eb2e8f9f7 79 */
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 /** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions
<> 144:ef7eb2e8f9f7 82 * @brief Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 83 *
<> 144:ef7eb2e8f9f7 84 @verbatim
<> 144:ef7eb2e8f9f7 85 ===============================================================================
<> 144:ef7eb2e8f9f7 86 ##### Extended Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 87 ===============================================================================
<> 144:ef7eb2e8f9f7 88 [..]
<> 144:ef7eb2e8f9f7 89 This subsection provides a set of functions allowing to control the RCC Clocks
<> 144:ef7eb2e8f9f7 90 frequencies.
<> 144:ef7eb2e8f9f7 91 [..]
<> 144:ef7eb2e8f9f7 92 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
<> 144:ef7eb2e8f9f7 93 select the RTC clock source; in this case the Backup domain will be reset in
<> 144:ef7eb2e8f9f7 94 order to modify the RTC Clock source, as consequence RTC registers (including
<> 144:ef7eb2e8f9f7 95 the backup registers) are set to their reset values.
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 @endverbatim
<> 144:ef7eb2e8f9f7 98 * @{
<> 144:ef7eb2e8f9f7 99 */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /**
<> 144:ef7eb2e8f9f7 102 * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
<> 144:ef7eb2e8f9f7 103 * RCC_PeriphCLKInitTypeDef.
<> 144:ef7eb2e8f9f7 104 * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
<> 144:ef7eb2e8f9f7 105 * contains the configuration information for the Extended Peripherals clocks(RTC clock).
<> 144:ef7eb2e8f9f7 106 *
<> 144:ef7eb2e8f9f7 107 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
<> 144:ef7eb2e8f9f7 108 * the RTC clock source; in this case the Backup domain will be reset in
<> 144:ef7eb2e8f9f7 109 * order to modify the RTC Clock source, as consequence RTC registers (including
<> 144:ef7eb2e8f9f7 110 * the backup registers) are set to their reset values.
<> 144:ef7eb2e8f9f7 111 *
<> 144:ef7eb2e8f9f7 112 * @note In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on
<> 144:ef7eb2e8f9f7 113 * one of 2 I2S interfaces. When PLLI2S is enabled, you need to call HAL_RCCEx_DisablePLLI2S to
<> 144:ef7eb2e8f9f7 114 * manually disable it.
<> 144:ef7eb2e8f9f7 115 *
<> 144:ef7eb2e8f9f7 116 * @retval HAL status
<> 144:ef7eb2e8f9f7 117 */
<> 144:ef7eb2e8f9f7 118 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
<> 144:ef7eb2e8f9f7 119 {
<> 144:ef7eb2e8f9f7 120 uint32_t tickstart = 0, temp_reg = 0;
<> 144:ef7eb2e8f9f7 121 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 122 uint32_t pllactive = 0;
<> 144:ef7eb2e8f9f7 123 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /* Check the parameters */
<> 144:ef7eb2e8f9f7 126 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /*------------------------------- RTC/LCD Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 129 if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
<> 144:ef7eb2e8f9f7 130 {
<> 144:ef7eb2e8f9f7 131 /* check for RTC Parameters used to output RTCCLK */
<> 144:ef7eb2e8f9f7 132 assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /* Enable Power Clock*/
<> 144:ef7eb2e8f9f7 135 __HAL_RCC_PWR_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /* Enable write access to Backup domain */
<> 144:ef7eb2e8f9f7 138 SET_BIT(PWR->CR, PWR_CR_DBP);
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 /* Wait for Backup domain Write protection disable */
<> 144:ef7eb2e8f9f7 141 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 while((PWR->CR & PWR_CR_DBP) == RESET)
<> 144:ef7eb2e8f9f7 144 {
<> 144:ef7eb2e8f9f7 145 if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 146 {
<> 144:ef7eb2e8f9f7 147 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 148 }
<> 144:ef7eb2e8f9f7 149 }
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
<> 144:ef7eb2e8f9f7 152 temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
<> 144:ef7eb2e8f9f7 153 if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
<> 144:ef7eb2e8f9f7 154 {
<> 144:ef7eb2e8f9f7 155 /* Store the content of BDCR register before the reset of Backup Domain */
<> 144:ef7eb2e8f9f7 156 temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
<> 144:ef7eb2e8f9f7 157 /* RTC Clock selection can be changed only if the Backup Domain is reset */
<> 144:ef7eb2e8f9f7 158 __HAL_RCC_BACKUPRESET_FORCE();
<> 144:ef7eb2e8f9f7 159 __HAL_RCC_BACKUPRESET_RELEASE();
<> 144:ef7eb2e8f9f7 160 /* Restore the Content of BDCR register */
<> 144:ef7eb2e8f9f7 161 RCC->BDCR = temp_reg;
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /* Wait for LSERDY if LSE was enabled */
<> 144:ef7eb2e8f9f7 164 if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
<> 144:ef7eb2e8f9f7 165 {
<> 144:ef7eb2e8f9f7 166 /* Get timeout */
<> 144:ef7eb2e8f9f7 167 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 /* Wait till LSE is ready */
<> 144:ef7eb2e8f9f7 170 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
<> 144:ef7eb2e8f9f7 171 {
<> 144:ef7eb2e8f9f7 172 if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 173 {
<> 144:ef7eb2e8f9f7 174 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 175 }
<> 144:ef7eb2e8f9f7 176 }
<> 144:ef7eb2e8f9f7 177 }
<> 144:ef7eb2e8f9f7 178 }
<> 144:ef7eb2e8f9f7 179 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
<> 144:ef7eb2e8f9f7 180 }
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /*------------------------------ ADC clock Configuration ------------------*/
<> 144:ef7eb2e8f9f7 183 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
<> 144:ef7eb2e8f9f7 184 {
<> 144:ef7eb2e8f9f7 185 /* Check the parameters */
<> 144:ef7eb2e8f9f7 186 assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /* Configure the ADC clock source */
<> 144:ef7eb2e8f9f7 189 __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
<> 144:ef7eb2e8f9f7 190 }
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 193 /*------------------------------ I2S2 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 194 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2)
<> 144:ef7eb2e8f9f7 195 {
<> 144:ef7eb2e8f9f7 196 /* Check the parameters */
<> 144:ef7eb2e8f9f7 197 assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection));
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /* Configure the I2S2 clock source */
<> 144:ef7eb2e8f9f7 200 __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection);
<> 144:ef7eb2e8f9f7 201 }
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /*------------------------------ I2S3 Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 204 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3)
<> 144:ef7eb2e8f9f7 205 {
<> 144:ef7eb2e8f9f7 206 /* Check the parameters */
<> 144:ef7eb2e8f9f7 207 assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection));
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 /* Configure the I2S3 clock source */
<> 144:ef7eb2e8f9f7 210 __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection);
<> 144:ef7eb2e8f9f7 211 }
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /*------------------------------ PLL I2S Configuration ----------------------*/
<> 144:ef7eb2e8f9f7 214 /* Check that PLLI2S need to be enabled */
<> 144:ef7eb2e8f9f7 215 if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
<> 144:ef7eb2e8f9f7 216 {
<> 144:ef7eb2e8f9f7 217 /* Update flag to indicate that PLL I2S should be active */
<> 144:ef7eb2e8f9f7 218 pllactive = 1;
<> 144:ef7eb2e8f9f7 219 }
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /* Check if PLL I2S need to be enabled */
<> 144:ef7eb2e8f9f7 222 if (pllactive == 1)
<> 144:ef7eb2e8f9f7 223 {
<> 144:ef7eb2e8f9f7 224 /* Enable PLL I2S only if not active */
<> 144:ef7eb2e8f9f7 225 if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON))
<> 144:ef7eb2e8f9f7 226 {
<> 144:ef7eb2e8f9f7 227 /* Check the parameters */
<> 144:ef7eb2e8f9f7 228 assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL));
<> 144:ef7eb2e8f9f7 229 assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value));
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 /* Prediv2 can be written only when the PLL2 is disabled. */
<> 144:ef7eb2e8f9f7 232 /* Return an error only if new value is different from the programmed value */
<> 144:ef7eb2e8f9f7 233 if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL2ON) && \
<> 144:ef7eb2e8f9f7 234 (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value))
<> 144:ef7eb2e8f9f7 235 {
<> 144:ef7eb2e8f9f7 236 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 237 }
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /* Configure the HSE prediv2 factor --------------------------------*/
<> 144:ef7eb2e8f9f7 240 __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value);
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /* Configure the main PLLI2S multiplication factors. */
<> 144:ef7eb2e8f9f7 243 __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL);
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /* Enable the main PLLI2S. */
<> 144:ef7eb2e8f9f7 246 __HAL_RCC_PLLI2S_ENABLE();
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 249 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /* Wait till PLLI2S is ready */
<> 144:ef7eb2e8f9f7 252 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
<> 144:ef7eb2e8f9f7 253 {
<> 144:ef7eb2e8f9f7 254 if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 255 {
<> 144:ef7eb2e8f9f7 256 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 257 }
<> 144:ef7eb2e8f9f7 258 }
<> 144:ef7eb2e8f9f7 259 }
<> 144:ef7eb2e8f9f7 260 else
<> 144:ef7eb2e8f9f7 261 {
<> 144:ef7eb2e8f9f7 262 /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */
<> 144:ef7eb2e8f9f7 263 if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL)
<> 144:ef7eb2e8f9f7 264 {
<> 144:ef7eb2e8f9f7 265 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 266 }
<> 144:ef7eb2e8f9f7 267 }
<> 144:ef7eb2e8f9f7 268 }
<> 144:ef7eb2e8f9f7 269 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
<> 144:ef7eb2e8f9f7 272 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
<> 144:ef7eb2e8f9f7 273 || defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 274 /*------------------------------ USB clock Configuration ------------------*/
<> 144:ef7eb2e8f9f7 275 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
<> 144:ef7eb2e8f9f7 276 {
<> 144:ef7eb2e8f9f7 277 /* Check the parameters */
<> 144:ef7eb2e8f9f7 278 assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 /* Configure the USB clock source */
<> 144:ef7eb2e8f9f7 281 __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
<> 144:ef7eb2e8f9f7 282 }
<> 144:ef7eb2e8f9f7 283 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 return HAL_OK;
<> 144:ef7eb2e8f9f7 286 }
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /**
<> 144:ef7eb2e8f9f7 289 * @brief Get the PeriphClkInit according to the internal
<> 144:ef7eb2e8f9f7 290 * RCC configuration registers.
<> 144:ef7eb2e8f9f7 291 * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
<> 144:ef7eb2e8f9f7 292 * returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks).
<> 144:ef7eb2e8f9f7 293 * @retval None
<> 144:ef7eb2e8f9f7 294 */
<> 144:ef7eb2e8f9f7 295 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
<> 144:ef7eb2e8f9f7 296 {
<> 144:ef7eb2e8f9f7 297 uint32_t srcclk = 0;
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 /* Set all possible values for the extended clock type parameter------------*/
<> 144:ef7eb2e8f9f7 300 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC;
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 /* Get the RTC configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 303 srcclk = __HAL_RCC_GET_RTC_SOURCE();
<> 144:ef7eb2e8f9f7 304 /* Source clock is LSE or LSI*/
<> 144:ef7eb2e8f9f7 305 PeriphClkInit->RTCClockSelection = srcclk;
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /* Get the ADC clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 308 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC;
<> 144:ef7eb2e8f9f7 309 PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 312 /* Get the I2S2 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 313 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
<> 144:ef7eb2e8f9f7 314 PeriphClkInit->I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE();
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 /* Get the I2S3 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 317 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
<> 144:ef7eb2e8f9f7 318 PeriphClkInit->I2s3ClockSelection = __HAL_RCC_GET_I2S3_SOURCE();
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 #if defined(STM32F103xE) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 323 /* Get the I2S2 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 324 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
<> 144:ef7eb2e8f9f7 325 PeriphClkInit->I2s2ClockSelection = RCC_I2S2CLKSOURCE_SYSCLK;
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /* Get the I2S3 clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 328 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
<> 144:ef7eb2e8f9f7 329 PeriphClkInit->I2s3ClockSelection = RCC_I2S3CLKSOURCE_SYSCLK;
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 #endif /* STM32F103xE || STM32F103xG */
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
<> 144:ef7eb2e8f9f7 334 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
<> 144:ef7eb2e8f9f7 335 || defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 336 /* Get the USB clock configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 337 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
<> 144:ef7eb2e8f9f7 338 PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
<> 144:ef7eb2e8f9f7 339 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 340 }
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /**
<> 144:ef7eb2e8f9f7 343 * @brief Returns the peripheral clock frequency
<> 144:ef7eb2e8f9f7 344 * @note Returns 0 if peripheral clock is unknown
<> 144:ef7eb2e8f9f7 345 * @param PeriphClk Peripheral clock identifier
<> 144:ef7eb2e8f9f7 346 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 347 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
<> 144:ef7eb2e8f9f7 348 * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock
<> 144:ef7eb2e8f9f7 349 @if STM32F103xE
<> 144:ef7eb2e8f9f7 350 * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
<> 144:ef7eb2e8f9f7 351 * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
<> 144:ef7eb2e8f9f7 352 * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
<> 144:ef7eb2e8f9f7 353 @endif
<> 144:ef7eb2e8f9f7 354 @if STM32F103xG
<> 144:ef7eb2e8f9f7 355 * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
<> 144:ef7eb2e8f9f7 356 * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
<> 144:ef7eb2e8f9f7 357 * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
<> 144:ef7eb2e8f9f7 358 * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
<> 144:ef7eb2e8f9f7 359 @endif
<> 144:ef7eb2e8f9f7 360 @if STM32F105xC
<> 144:ef7eb2e8f9f7 361 * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
<> 144:ef7eb2e8f9f7 362 * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
<> 144:ef7eb2e8f9f7 363 * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
<> 144:ef7eb2e8f9f7 364 * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
<> 144:ef7eb2e8f9f7 365 * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
<> 144:ef7eb2e8f9f7 366 * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
<> 144:ef7eb2e8f9f7 367 * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
<> 144:ef7eb2e8f9f7 368 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
<> 144:ef7eb2e8f9f7 369 @endif
<> 144:ef7eb2e8f9f7 370 @if STM32F107xC
<> 144:ef7eb2e8f9f7 371 * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
<> 144:ef7eb2e8f9f7 372 * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
<> 144:ef7eb2e8f9f7 373 * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
<> 144:ef7eb2e8f9f7 374 * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
<> 144:ef7eb2e8f9f7 375 * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
<> 144:ef7eb2e8f9f7 376 * @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
<> 144:ef7eb2e8f9f7 377 * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
<> 144:ef7eb2e8f9f7 378 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
<> 144:ef7eb2e8f9f7 379 @endif
<> 144:ef7eb2e8f9f7 380 @if STM32F102xx
<> 144:ef7eb2e8f9f7 381 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
<> 144:ef7eb2e8f9f7 382 @endif
<> 144:ef7eb2e8f9f7 383 @if STM32F103xx
<> 144:ef7eb2e8f9f7 384 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
<> 144:ef7eb2e8f9f7 385 @endif
<> 144:ef7eb2e8f9f7 386 * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
<> 144:ef7eb2e8f9f7 387 */
<> 144:ef7eb2e8f9f7 388 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
<> 144:ef7eb2e8f9f7 389 {
<> 144:ef7eb2e8f9f7 390 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
<> 144:ef7eb2e8f9f7 391 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
<> 144:ef7eb2e8f9f7 392 || defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 393 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 394 const uint8_t aPLLMULFactorTable[12] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 13};
<> 144:ef7eb2e8f9f7 395 const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16};
<> 144:ef7eb2e8f9f7 396 #else
<> 144:ef7eb2e8f9f7 397 const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
<> 144:ef7eb2e8f9f7 398 const uint8_t aPredivFactorTable[2] = { 1, 2};
<> 144:ef7eb2e8f9f7 399 #endif
<> 144:ef7eb2e8f9f7 400 #endif
<> 144:ef7eb2e8f9f7 401 uint32_t temp_reg = 0, frequency = 0;
<> 144:ef7eb2e8f9f7 402 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
<> 144:ef7eb2e8f9f7 403 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
<> 144:ef7eb2e8f9f7 404 || defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 405 uint32_t prediv1 = 0, pllclk = 0, pllmul = 0;
<> 144:ef7eb2e8f9f7 406 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 407 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 408 uint32_t pll2mul = 0, pll3mul = 0, prediv2 = 0;
<> 144:ef7eb2e8f9f7 409 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 /* Check the parameters */
<> 144:ef7eb2e8f9f7 412 assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 switch (PeriphClk)
<> 144:ef7eb2e8f9f7 415 {
<> 144:ef7eb2e8f9f7 416 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
<> 144:ef7eb2e8f9f7 417 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
<> 144:ef7eb2e8f9f7 418 || defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 419 case RCC_PERIPHCLK_USB:
<> 144:ef7eb2e8f9f7 420 {
<> 144:ef7eb2e8f9f7 421 /* Get RCC configuration ------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 422 temp_reg = RCC->CFGR;
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /* Check if PLL is enabled */
<> 144:ef7eb2e8f9f7 425 if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLLON))
<> 144:ef7eb2e8f9f7 426 {
<> 144:ef7eb2e8f9f7 427 pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> POSITION_VAL(RCC_CFGR_PLLMULL)];
<> 144:ef7eb2e8f9f7 428 if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
<> 144:ef7eb2e8f9f7 429 {
<> 144:ef7eb2e8f9f7 430 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
<> 144:ef7eb2e8f9f7 431 || defined(STM32F100xE)
<> 144:ef7eb2e8f9f7 432 prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> POSITION_VAL(RCC_CFGR2_PREDIV1)];
<> 144:ef7eb2e8f9f7 433 #else
<> 144:ef7eb2e8f9f7 434 prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> POSITION_VAL(RCC_CFGR_PLLXTPRE)];
<> 144:ef7eb2e8f9f7 435 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 438 if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
<> 144:ef7eb2e8f9f7 439 {
<> 144:ef7eb2e8f9f7 440 /* PLL2 selected as Prediv1 source */
<> 144:ef7eb2e8f9f7 441 /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
<> 144:ef7eb2e8f9f7 442 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
<> 144:ef7eb2e8f9f7 443 pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> POSITION_VAL(RCC_CFGR2_PLL2MUL)) + 2;
<> 144:ef7eb2e8f9f7 444 pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul);
<> 144:ef7eb2e8f9f7 445 }
<> 144:ef7eb2e8f9f7 446 else
<> 144:ef7eb2e8f9f7 447 {
<> 144:ef7eb2e8f9f7 448 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
<> 144:ef7eb2e8f9f7 449 pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
<> 144:ef7eb2e8f9f7 450 }
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
<> 144:ef7eb2e8f9f7 453 /* In this case need to divide pllclk by 2 */
<> 144:ef7eb2e8f9f7 454 if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> POSITION_VAL(RCC_CFGR_PLLMULL)])
<> 144:ef7eb2e8f9f7 455 {
<> 144:ef7eb2e8f9f7 456 pllclk = pllclk / 2;
<> 144:ef7eb2e8f9f7 457 }
<> 144:ef7eb2e8f9f7 458 #else
<> 144:ef7eb2e8f9f7 459 if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
<> 144:ef7eb2e8f9f7 460 {
<> 144:ef7eb2e8f9f7 461 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
<> 144:ef7eb2e8f9f7 462 pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
<> 144:ef7eb2e8f9f7 463 }
<> 144:ef7eb2e8f9f7 464 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 465 }
<> 144:ef7eb2e8f9f7 466 else
<> 144:ef7eb2e8f9f7 467 {
<> 144:ef7eb2e8f9f7 468 /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
<> 144:ef7eb2e8f9f7 469 pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
<> 144:ef7eb2e8f9f7 470 }
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 /* Calcul of the USB frequency*/
<> 144:ef7eb2e8f9f7 473 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 474 /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */
<> 144:ef7eb2e8f9f7 475 if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2)
<> 144:ef7eb2e8f9f7 476 {
<> 144:ef7eb2e8f9f7 477 /* Prescaler of 2 selected for USB */
<> 144:ef7eb2e8f9f7 478 frequency = pllclk;
<> 144:ef7eb2e8f9f7 479 }
<> 144:ef7eb2e8f9f7 480 else
<> 144:ef7eb2e8f9f7 481 {
<> 144:ef7eb2e8f9f7 482 /* Prescaler of 3 selected for USB */
<> 144:ef7eb2e8f9f7 483 frequency = (2 * pllclk) / 3;
<> 144:ef7eb2e8f9f7 484 }
<> 144:ef7eb2e8f9f7 485 #else
<> 144:ef7eb2e8f9f7 486 /* USBCLK = PLLCLK / USB prescaler */
<> 144:ef7eb2e8f9f7 487 if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL)
<> 144:ef7eb2e8f9f7 488 {
<> 144:ef7eb2e8f9f7 489 /* No prescaler selected for USB */
<> 144:ef7eb2e8f9f7 490 frequency = pllclk;
<> 144:ef7eb2e8f9f7 491 }
<> 144:ef7eb2e8f9f7 492 else
<> 144:ef7eb2e8f9f7 493 {
<> 144:ef7eb2e8f9f7 494 /* Prescaler of 1.5 selected for USB */
<> 144:ef7eb2e8f9f7 495 frequency = (pllclk * 2) / 3;
<> 144:ef7eb2e8f9f7 496 }
<> 144:ef7eb2e8f9f7 497 #endif
<> 144:ef7eb2e8f9f7 498 }
<> 144:ef7eb2e8f9f7 499 break;
<> 144:ef7eb2e8f9f7 500 }
<> 144:ef7eb2e8f9f7 501 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 502 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
<> 144:ef7eb2e8f9f7 503 || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 504 case RCC_PERIPHCLK_I2S2:
<> 144:ef7eb2e8f9f7 505 {
<> 144:ef7eb2e8f9f7 506 #if defined(STM32F103xE) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 507 /* SYSCLK used as source clock for I2S2 */
<> 144:ef7eb2e8f9f7 508 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 509 #else
<> 144:ef7eb2e8f9f7 510 if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 511 {
<> 144:ef7eb2e8f9f7 512 /* SYSCLK used as source clock for I2S2 */
<> 144:ef7eb2e8f9f7 513 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 514 }
<> 144:ef7eb2e8f9f7 515 else
<> 144:ef7eb2e8f9f7 516 {
<> 144:ef7eb2e8f9f7 517 /* Check if PLLI2S is enabled */
<> 144:ef7eb2e8f9f7 518 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))
<> 144:ef7eb2e8f9f7 519 {
<> 144:ef7eb2e8f9f7 520 /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
<> 144:ef7eb2e8f9f7 521 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
<> 144:ef7eb2e8f9f7 522 pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> POSITION_VAL(RCC_CFGR2_PLL3MUL)) + 2;
<> 144:ef7eb2e8f9f7 523 frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
<> 144:ef7eb2e8f9f7 524 }
<> 144:ef7eb2e8f9f7 525 }
<> 144:ef7eb2e8f9f7 526 #endif /* STM32F103xE || STM32F103xG */
<> 144:ef7eb2e8f9f7 527 break;
<> 144:ef7eb2e8f9f7 528 }
<> 144:ef7eb2e8f9f7 529 case RCC_PERIPHCLK_I2S3:
<> 144:ef7eb2e8f9f7 530 {
<> 144:ef7eb2e8f9f7 531 #if defined(STM32F103xE) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 532 /* SYSCLK used as source clock for I2S3 */
<> 144:ef7eb2e8f9f7 533 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 534 #else
<> 144:ef7eb2e8f9f7 535 if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 536 {
<> 144:ef7eb2e8f9f7 537 /* SYSCLK used as source clock for I2S3 */
<> 144:ef7eb2e8f9f7 538 frequency = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 539 }
<> 144:ef7eb2e8f9f7 540 else
<> 144:ef7eb2e8f9f7 541 {
<> 144:ef7eb2e8f9f7 542 /* Check if PLLI2S is enabled */
<> 144:ef7eb2e8f9f7 543 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))
<> 144:ef7eb2e8f9f7 544 {
<> 144:ef7eb2e8f9f7 545 /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
<> 144:ef7eb2e8f9f7 546 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
<> 144:ef7eb2e8f9f7 547 pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> POSITION_VAL(RCC_CFGR2_PLL3MUL)) + 2;
<> 144:ef7eb2e8f9f7 548 frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
<> 144:ef7eb2e8f9f7 549 }
<> 144:ef7eb2e8f9f7 550 }
<> 144:ef7eb2e8f9f7 551 #endif /* STM32F103xE || STM32F103xG */
<> 144:ef7eb2e8f9f7 552 break;
<> 144:ef7eb2e8f9f7 553 }
<> 144:ef7eb2e8f9f7 554 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 555 case RCC_PERIPHCLK_RTC:
<> 144:ef7eb2e8f9f7 556 {
<> 144:ef7eb2e8f9f7 557 /* Get RCC BDCR configuration ------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 558 temp_reg = RCC->BDCR;
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 /* Check if LSE is ready if RTC clock selection is LSE */
<> 144:ef7eb2e8f9f7 561 if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY)))
<> 144:ef7eb2e8f9f7 562 {
<> 144:ef7eb2e8f9f7 563 frequency = LSE_VALUE;
<> 144:ef7eb2e8f9f7 564 }
<> 144:ef7eb2e8f9f7 565 /* Check if LSI is ready if RTC clock selection is LSI */
<> 144:ef7eb2e8f9f7 566 else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
<> 144:ef7eb2e8f9f7 567 {
<> 144:ef7eb2e8f9f7 568 frequency = LSI_VALUE;
<> 144:ef7eb2e8f9f7 569 }
<> 144:ef7eb2e8f9f7 570 else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
<> 144:ef7eb2e8f9f7 571 {
<> 144:ef7eb2e8f9f7 572 frequency = HSE_VALUE / 128;
<> 144:ef7eb2e8f9f7 573 }
<> 144:ef7eb2e8f9f7 574 /* Clock not enabled for RTC*/
<> 144:ef7eb2e8f9f7 575 else
<> 144:ef7eb2e8f9f7 576 {
<> 144:ef7eb2e8f9f7 577 frequency = 0;
<> 144:ef7eb2e8f9f7 578 }
<> 144:ef7eb2e8f9f7 579 break;
<> 144:ef7eb2e8f9f7 580 }
<> 144:ef7eb2e8f9f7 581 case RCC_PERIPHCLK_ADC:
<> 144:ef7eb2e8f9f7 582 {
<> 144:ef7eb2e8f9f7 583 frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> POSITION_VAL(RCC_CFGR_ADCPRE_DIV4)) + 1) * 2);
<> 144:ef7eb2e8f9f7 584 break;
<> 144:ef7eb2e8f9f7 585 }
<> 144:ef7eb2e8f9f7 586 default:
<> 144:ef7eb2e8f9f7 587 {
<> 144:ef7eb2e8f9f7 588 break;
<> 144:ef7eb2e8f9f7 589 }
<> 144:ef7eb2e8f9f7 590 }
<> 144:ef7eb2e8f9f7 591 return(frequency);
<> 144:ef7eb2e8f9f7 592 }
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 /**
<> 144:ef7eb2e8f9f7 595 * @}
<> 144:ef7eb2e8f9f7 596 */
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 599 /** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function
<> 144:ef7eb2e8f9f7 600 * @brief PLLI2S Management functions
<> 144:ef7eb2e8f9f7 601 *
<> 144:ef7eb2e8f9f7 602 @verbatim
<> 144:ef7eb2e8f9f7 603 ===============================================================================
<> 144:ef7eb2e8f9f7 604 ##### Extended PLLI2S Management functions #####
<> 144:ef7eb2e8f9f7 605 ===============================================================================
<> 144:ef7eb2e8f9f7 606 [..]
<> 144:ef7eb2e8f9f7 607 This subsection provides a set of functions allowing to control the PLLI2S
<> 144:ef7eb2e8f9f7 608 activation or deactivation
<> 144:ef7eb2e8f9f7 609 @endverbatim
<> 144:ef7eb2e8f9f7 610 * @{
<> 144:ef7eb2e8f9f7 611 */
<> 144:ef7eb2e8f9f7 612
<> 144:ef7eb2e8f9f7 613 /**
<> 144:ef7eb2e8f9f7 614 * @brief Enable PLLI2S
<> 144:ef7eb2e8f9f7 615 * @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that
<> 144:ef7eb2e8f9f7 616 * contains the configuration information for the PLLI2S
<> 144:ef7eb2e8f9f7 617 * @note The PLLI2S configuration not modified if used by I2S2 or I2S3 Interface.
<> 144:ef7eb2e8f9f7 618 * @retval HAL status
<> 144:ef7eb2e8f9f7 619 */
<> 144:ef7eb2e8f9f7 620 HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit)
<> 144:ef7eb2e8f9f7 621 {
<> 144:ef7eb2e8f9f7 622 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /* Check that PLL I2S has not been already enabled by I2S2 or I2S3*/
<> 144:ef7eb2e8f9f7 625 if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
<> 144:ef7eb2e8f9f7 626 {
<> 144:ef7eb2e8f9f7 627 /* Check the parameters */
<> 144:ef7eb2e8f9f7 628 assert_param(IS_RCC_PLLI2S_MUL(PLLI2SInit->PLLI2SMUL));
<> 144:ef7eb2e8f9f7 629 assert_param(IS_RCC_HSE_PREDIV2(PLLI2SInit->HSEPrediv2Value));
<> 144:ef7eb2e8f9f7 630
<> 144:ef7eb2e8f9f7 631 /* Prediv2 can be written only when the PLL2 is disabled. */
<> 144:ef7eb2e8f9f7 632 /* Return an error only if new value is different from the programmed value */
<> 144:ef7eb2e8f9f7 633 if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL2ON) && \
<> 144:ef7eb2e8f9f7 634 (__HAL_RCC_HSE_GET_PREDIV2() != PLLI2SInit->HSEPrediv2Value))
<> 144:ef7eb2e8f9f7 635 {
<> 144:ef7eb2e8f9f7 636 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 637 }
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 /* Disable the main PLLI2S. */
<> 144:ef7eb2e8f9f7 640 __HAL_RCC_PLLI2S_DISABLE();
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 643 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 644
<> 144:ef7eb2e8f9f7 645 /* Wait till PLLI2S is ready */
<> 144:ef7eb2e8f9f7 646 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
<> 144:ef7eb2e8f9f7 647 {
<> 144:ef7eb2e8f9f7 648 if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 649 {
<> 144:ef7eb2e8f9f7 650 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 651 }
<> 144:ef7eb2e8f9f7 652 }
<> 144:ef7eb2e8f9f7 653
<> 144:ef7eb2e8f9f7 654 /* Configure the HSE prediv2 factor --------------------------------*/
<> 144:ef7eb2e8f9f7 655 __HAL_RCC_HSE_PREDIV2_CONFIG(PLLI2SInit->HSEPrediv2Value);
<> 144:ef7eb2e8f9f7 656
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 /* Configure the main PLLI2S multiplication factors. */
<> 144:ef7eb2e8f9f7 659 __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SMUL);
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 /* Enable the main PLLI2S. */
<> 144:ef7eb2e8f9f7 662 __HAL_RCC_PLLI2S_ENABLE();
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 665 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 666
<> 144:ef7eb2e8f9f7 667 /* Wait till PLLI2S is ready */
<> 144:ef7eb2e8f9f7 668 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
<> 144:ef7eb2e8f9f7 669 {
<> 144:ef7eb2e8f9f7 670 if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 671 {
<> 144:ef7eb2e8f9f7 672 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 673 }
<> 144:ef7eb2e8f9f7 674 }
<> 144:ef7eb2e8f9f7 675 }
<> 144:ef7eb2e8f9f7 676 else
<> 144:ef7eb2e8f9f7 677 {
<> 144:ef7eb2e8f9f7 678 /* PLLI2S cannot be modified as already used by I2S2 or I2S3 */
<> 144:ef7eb2e8f9f7 679 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 680 }
<> 144:ef7eb2e8f9f7 681
<> 144:ef7eb2e8f9f7 682 return HAL_OK;
<> 144:ef7eb2e8f9f7 683 }
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 /**
<> 144:ef7eb2e8f9f7 686 * @brief Disable PLLI2S
<> 144:ef7eb2e8f9f7 687 * @note PLLI2S is not disabled if used by I2S2 or I2S3 Interface.
<> 144:ef7eb2e8f9f7 688 * @retval HAL status
<> 144:ef7eb2e8f9f7 689 */
<> 144:ef7eb2e8f9f7 690 HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
<> 144:ef7eb2e8f9f7 691 {
<> 144:ef7eb2e8f9f7 692 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 /* Disable PLL I2S as not requested by I2S2 or I2S3*/
<> 144:ef7eb2e8f9f7 695 if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
<> 144:ef7eb2e8f9f7 696 {
<> 144:ef7eb2e8f9f7 697 /* Disable the main PLLI2S. */
<> 144:ef7eb2e8f9f7 698 __HAL_RCC_PLLI2S_DISABLE();
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 701 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 /* Wait till PLLI2S is ready */
<> 144:ef7eb2e8f9f7 704 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
<> 144:ef7eb2e8f9f7 705 {
<> 144:ef7eb2e8f9f7 706 if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 707 {
<> 144:ef7eb2e8f9f7 708 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 709 }
<> 144:ef7eb2e8f9f7 710 }
<> 144:ef7eb2e8f9f7 711 }
<> 144:ef7eb2e8f9f7 712 else
<> 144:ef7eb2e8f9f7 713 {
<> 144:ef7eb2e8f9f7 714 /* PLLI2S is currently used by I2S2 or I2S3. Cannot be disabled.*/
<> 144:ef7eb2e8f9f7 715 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 716 }
<> 144:ef7eb2e8f9f7 717
<> 144:ef7eb2e8f9f7 718 return HAL_OK;
<> 144:ef7eb2e8f9f7 719 }
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 /**
<> 144:ef7eb2e8f9f7 722 * @}
<> 144:ef7eb2e8f9f7 723 */
<> 144:ef7eb2e8f9f7 724
<> 144:ef7eb2e8f9f7 725 /** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function
<> 144:ef7eb2e8f9f7 726 * @brief PLL2 Management functions
<> 144:ef7eb2e8f9f7 727 *
<> 144:ef7eb2e8f9f7 728 @verbatim
<> 144:ef7eb2e8f9f7 729 ===============================================================================
<> 144:ef7eb2e8f9f7 730 ##### Extended PLL2 Management functions #####
<> 144:ef7eb2e8f9f7 731 ===============================================================================
<> 144:ef7eb2e8f9f7 732 [..]
<> 144:ef7eb2e8f9f7 733 This subsection provides a set of functions allowing to control the PLL2
<> 144:ef7eb2e8f9f7 734 activation or deactivation
<> 144:ef7eb2e8f9f7 735 @endverbatim
<> 144:ef7eb2e8f9f7 736 * @{
<> 144:ef7eb2e8f9f7 737 */
<> 144:ef7eb2e8f9f7 738
<> 144:ef7eb2e8f9f7 739 /**
<> 144:ef7eb2e8f9f7 740 * @brief Enable PLL2
<> 144:ef7eb2e8f9f7 741 * @param PLL2Init pointer to an RCC_PLL2InitTypeDef structure that
<> 144:ef7eb2e8f9f7 742 * contains the configuration information for the PLL2
<> 144:ef7eb2e8f9f7 743 * @note The PLL2 configuration not modified if used indirectly as system clock.
<> 144:ef7eb2e8f9f7 744 * @retval HAL status
<> 144:ef7eb2e8f9f7 745 */
<> 144:ef7eb2e8f9f7 746 HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init)
<> 144:ef7eb2e8f9f7 747 {
<> 144:ef7eb2e8f9f7 748 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 749
<> 144:ef7eb2e8f9f7 750 /* This bit can not be cleared if the PLL2 clock is used indirectly as system
<> 144:ef7eb2e8f9f7 751 clock (i.e. it is used as PLL clock entry that is used as system clock). */
<> 144:ef7eb2e8f9f7 752 if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
<> 144:ef7eb2e8f9f7 753 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
<> 144:ef7eb2e8f9f7 754 ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
<> 144:ef7eb2e8f9f7 755 {
<> 144:ef7eb2e8f9f7 756 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 757 }
<> 144:ef7eb2e8f9f7 758 else
<> 144:ef7eb2e8f9f7 759 {
<> 144:ef7eb2e8f9f7 760 /* Check the parameters */
<> 144:ef7eb2e8f9f7 761 assert_param(IS_RCC_PLL2_MUL(PLL2Init->PLL2MUL));
<> 144:ef7eb2e8f9f7 762 assert_param(IS_RCC_HSE_PREDIV2(PLL2Init->HSEPrediv2Value));
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 /* Prediv2 can be written only when the PLLI2S is disabled. */
<> 144:ef7eb2e8f9f7 765 /* Return an error only if new value is different from the programmed value */
<> 144:ef7eb2e8f9f7 766 if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \
<> 144:ef7eb2e8f9f7 767 (__HAL_RCC_HSE_GET_PREDIV2() != PLL2Init->HSEPrediv2Value))
<> 144:ef7eb2e8f9f7 768 {
<> 144:ef7eb2e8f9f7 769 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 770 }
<> 144:ef7eb2e8f9f7 771
<> 144:ef7eb2e8f9f7 772 /* Disable the main PLL2. */
<> 144:ef7eb2e8f9f7 773 __HAL_RCC_PLL2_DISABLE();
<> 144:ef7eb2e8f9f7 774
<> 144:ef7eb2e8f9f7 775 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 776 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 777
<> 144:ef7eb2e8f9f7 778 /* Wait till PLL2 is disabled */
<> 144:ef7eb2e8f9f7 779 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
<> 144:ef7eb2e8f9f7 780 {
<> 144:ef7eb2e8f9f7 781 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 782 {
<> 144:ef7eb2e8f9f7 783 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 784 }
<> 144:ef7eb2e8f9f7 785 }
<> 144:ef7eb2e8f9f7 786
<> 144:ef7eb2e8f9f7 787 /* Configure the HSE prediv2 factor --------------------------------*/
<> 144:ef7eb2e8f9f7 788 __HAL_RCC_HSE_PREDIV2_CONFIG(PLL2Init->HSEPrediv2Value);
<> 144:ef7eb2e8f9f7 789
<> 144:ef7eb2e8f9f7 790 /* Configure the main PLL2 multiplication factors. */
<> 144:ef7eb2e8f9f7 791 __HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2MUL);
<> 144:ef7eb2e8f9f7 792
<> 144:ef7eb2e8f9f7 793 /* Enable the main PLL2. */
<> 144:ef7eb2e8f9f7 794 __HAL_RCC_PLL2_ENABLE();
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 797 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 798
<> 144:ef7eb2e8f9f7 799 /* Wait till PLL2 is ready */
<> 144:ef7eb2e8f9f7 800 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
<> 144:ef7eb2e8f9f7 801 {
<> 144:ef7eb2e8f9f7 802 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 803 {
<> 144:ef7eb2e8f9f7 804 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 805 }
<> 144:ef7eb2e8f9f7 806 }
<> 144:ef7eb2e8f9f7 807 }
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 return HAL_OK;
<> 144:ef7eb2e8f9f7 810 }
<> 144:ef7eb2e8f9f7 811
<> 144:ef7eb2e8f9f7 812 /**
<> 144:ef7eb2e8f9f7 813 * @brief Disable PLL2
<> 144:ef7eb2e8f9f7 814 * @note PLL2 is not disabled if used indirectly as system clock.
<> 144:ef7eb2e8f9f7 815 * @retval HAL status
<> 144:ef7eb2e8f9f7 816 */
<> 144:ef7eb2e8f9f7 817 HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void)
<> 144:ef7eb2e8f9f7 818 {
<> 144:ef7eb2e8f9f7 819 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821 /* This bit can not be cleared if the PLL2 clock is used indirectly as system
<> 144:ef7eb2e8f9f7 822 clock (i.e. it is used as PLL clock entry that is used as system clock). */
<> 144:ef7eb2e8f9f7 823 if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
<> 144:ef7eb2e8f9f7 824 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
<> 144:ef7eb2e8f9f7 825 ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
<> 144:ef7eb2e8f9f7 826 {
<> 144:ef7eb2e8f9f7 827 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 828 }
<> 144:ef7eb2e8f9f7 829 else
<> 144:ef7eb2e8f9f7 830 {
<> 144:ef7eb2e8f9f7 831 /* Disable the main PLL2. */
<> 144:ef7eb2e8f9f7 832 __HAL_RCC_PLL2_DISABLE();
<> 144:ef7eb2e8f9f7 833
<> 144:ef7eb2e8f9f7 834 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 835 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 836
<> 144:ef7eb2e8f9f7 837 /* Wait till PLL2 is disabled */
<> 144:ef7eb2e8f9f7 838 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
<> 144:ef7eb2e8f9f7 839 {
<> 144:ef7eb2e8f9f7 840 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 841 {
<> 144:ef7eb2e8f9f7 842 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 843 }
<> 144:ef7eb2e8f9f7 844 }
<> 144:ef7eb2e8f9f7 845 }
<> 144:ef7eb2e8f9f7 846
<> 144:ef7eb2e8f9f7 847 return HAL_OK;
<> 144:ef7eb2e8f9f7 848 }
<> 144:ef7eb2e8f9f7 849
<> 144:ef7eb2e8f9f7 850 /**
<> 144:ef7eb2e8f9f7 851 * @}
<> 144:ef7eb2e8f9f7 852 */
<> 144:ef7eb2e8f9f7 853 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 854
<> 144:ef7eb2e8f9f7 855 /**
<> 144:ef7eb2e8f9f7 856 * @}
<> 144:ef7eb2e8f9f7 857 */
<> 144:ef7eb2e8f9f7 858
<> 144:ef7eb2e8f9f7 859 /**
<> 144:ef7eb2e8f9f7 860 * @}
<> 144:ef7eb2e8f9f7 861 */
<> 144:ef7eb2e8f9f7 862
<> 144:ef7eb2e8f9f7 863 #endif /* HAL_RCC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865 /**
<> 144:ef7eb2e8f9f7 866 * @}
<> 144:ef7eb2e8f9f7 867 */
<> 144:ef7eb2e8f9f7 868
<> 144:ef7eb2e8f9f7 869 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 870