This library creates the interface to operate the TLC5940. This device manages 16 PWM outputs.
tlc5940.cpp@0:64ea4d75027c, 2010-11-27 (annotated)
- Committer:
- Fiuba
- Date:
- Sat Nov 27 00:28:33 2010 +0000
- Revision:
- 0:64ea4d75027c
- Child:
- 1:e8c8347fa919
Initial commit
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Fiuba | 0:64ea4d75027c | 1 | #include "tlc5940.h" |
Fiuba | 0:64ea4d75027c | 2 | #include "mbed.h" |
Fiuba | 0:64ea4d75027c | 3 | |
Fiuba | 0:64ea4d75027c | 4 | /** Create a tlc5940 interface object connected to some specifics pins |
Fiuba | 0:64ea4d75027c | 5 | * |
Fiuba | 0:64ea4d75027c | 6 | * @param DC_data[] Dot Correction values for initialization |
Fiuba | 0:64ea4d75027c | 7 | */ |
Fiuba | 0:64ea4d75027c | 8 | tlc5940::tlc5940 (int DC_data[]) : VPROG(p21), SIN(p22), SCLK(p23), XLAT(p24), BLANK(p25), DCPROG(p27), GSCLK(p26), SOUT(p28), XERR(p29) { |
Fiuba | 0:64ea4d75027c | 9 | first_cycle_flag = false; |
Fiuba | 0:64ea4d75027c | 10 | |
Fiuba | 0:64ea4d75027c | 11 | // Pins in startup state |
Fiuba | 0:64ea4d75027c | 12 | GSCLK = 0; |
Fiuba | 0:64ea4d75027c | 13 | SCLK = 0; |
Fiuba | 0:64ea4d75027c | 14 | VPROG = 1; |
Fiuba | 0:64ea4d75027c | 15 | XLAT = 0; |
Fiuba | 0:64ea4d75027c | 16 | BLANK = 1; |
Fiuba | 0:64ea4d75027c | 17 | DCPROG = 0; |
Fiuba | 0:64ea4d75027c | 18 | wait(0.01); |
Fiuba | 0:64ea4d75027c | 19 | |
Fiuba | 0:64ea4d75027c | 20 | // DC input cycle starts |
Fiuba | 0:64ea4d75027c | 21 | DCPROG = 1; |
Fiuba | 0:64ea4d75027c | 22 | VPROG = 1; |
Fiuba | 0:64ea4d75027c | 23 | |
Fiuba | 0:64ea4d75027c | 24 | for (int counter=0; counter < (2*96); counter++) { |
Fiuba | 0:64ea4d75027c | 25 | SIN = DC_data[counter]; |
Fiuba | 0:64ea4d75027c | 26 | SCLK = 1; |
Fiuba | 0:64ea4d75027c | 27 | wait_us(5); |
Fiuba | 0:64ea4d75027c | 28 | SCLK = 0; |
Fiuba | 0:64ea4d75027c | 29 | wait_us(5); |
Fiuba | 0:64ea4d75027c | 30 | } |
Fiuba | 0:64ea4d75027c | 31 | XLAT = 1; |
Fiuba | 0:64ea4d75027c | 32 | wait_us(5); |
Fiuba | 0:64ea4d75027c | 33 | XLAT = 0; |
Fiuba | 0:64ea4d75027c | 34 | wait_us(5); |
Fiuba | 0:64ea4d75027c | 35 | DCPROG = 0; |
Fiuba | 0:64ea4d75027c | 36 | // DC input cycle ends |
Fiuba | 0:64ea4d75027c | 37 | } |
Fiuba | 0:64ea4d75027c | 38 | |
Fiuba | 0:64ea4d75027c | 39 | /** Send the specified set of grayscale values |
Fiuba | 0:64ea4d75027c | 40 | * |
Fiuba | 0:64ea4d75027c | 41 | * @param data[] Array of 12-bit Grayscale values for transmission |
Fiuba | 0:64ea4d75027c | 42 | */ |
Fiuba | 0:64ea4d75027c | 43 | void tlc5940::send_data (int data[]) { |
Fiuba | 0:64ea4d75027c | 44 | // Grayscale data input + Grayscale PWM |
Fiuba | 0:64ea4d75027c | 45 | data_counter = 0; |
Fiuba | 0:64ea4d75027c | 46 | GSCLK_counter = 0; |
Fiuba | 0:64ea4d75027c | 47 | |
Fiuba | 0:64ea4d75027c | 48 | if (VPROG == 1) { |
Fiuba | 0:64ea4d75027c | 49 | VPROG = 0; |
Fiuba | 0:64ea4d75027c | 50 | first_cycle_flag = true; |
Fiuba | 0:64ea4d75027c | 51 | } |
Fiuba | 0:64ea4d75027c | 52 | |
Fiuba | 0:64ea4d75027c | 53 | // Send the new data |
Fiuba | 0:64ea4d75027c | 54 | BLANK = 0; |
Fiuba | 0:64ea4d75027c | 55 | for (GSCLK_counter = 0; GSCLK_counter <= 4095; GSCLK_counter++) { |
Fiuba | 0:64ea4d75027c | 56 | if (data_counter < 2*192) { |
Fiuba | 0:64ea4d75027c | 57 | // Every new led consists of 12 bits |
Fiuba | 0:64ea4d75027c | 58 | aux_ind = data_counter % 12; |
Fiuba | 0:64ea4d75027c | 59 | if ( aux_ind == 0 ) aux_value = data[data_counter/12]; |
Fiuba | 0:64ea4d75027c | 60 | // Send the last bit |
Fiuba | 0:64ea4d75027c | 61 | SIN = (aux_value >> aux_ind) & 0x01; |
Fiuba | 0:64ea4d75027c | 62 | |
Fiuba | 0:64ea4d75027c | 63 | SCLK = 1; |
Fiuba | 0:64ea4d75027c | 64 | GSCLK = 1; |
Fiuba | 0:64ea4d75027c | 65 | SCLK = 0; |
Fiuba | 0:64ea4d75027c | 66 | GSCLK = 0; |
Fiuba | 0:64ea4d75027c | 67 | |
Fiuba | 0:64ea4d75027c | 68 | data_counter++; |
Fiuba | 0:64ea4d75027c | 69 | } else { |
Fiuba | 0:64ea4d75027c | 70 | GSCLK = 1; |
Fiuba | 0:64ea4d75027c | 71 | GSCLK = 0; |
Fiuba | 0:64ea4d75027c | 72 | } |
Fiuba | 0:64ea4d75027c | 73 | } |
Fiuba | 0:64ea4d75027c | 74 | BLANK = 1; |
Fiuba | 0:64ea4d75027c | 75 | |
Fiuba | 0:64ea4d75027c | 76 | XLAT = 1; |
Fiuba | 0:64ea4d75027c | 77 | XLAT = 0; |
Fiuba | 0:64ea4d75027c | 78 | |
Fiuba | 0:64ea4d75027c | 79 | if (first_cycle_flag) { |
Fiuba | 0:64ea4d75027c | 80 | SCLK = 1; |
Fiuba | 0:64ea4d75027c | 81 | SCLK = 0; |
Fiuba | 0:64ea4d75027c | 82 | first_cycle_flag = false; |
Fiuba | 0:64ea4d75027c | 83 | } |
Fiuba | 0:64ea4d75027c | 84 | } |