Felipe Velazquez / SMARTES_lib

SMARTEST lib for MPS2

Dependents:   MSP2_LCD_HOLA

core_cmInstr.h@0:f1a413971403, 2018-08-23 (annotated)

Committer:
FelipeVR
Date:
Thu Aug 23 13:39:38 2018 +0000
Revision:
0:f1a413971403
SMARTEST LCD

Who changed what in which revision?

UserRevisionLine numberNew contents of line
FelipeVR 0:f1a413971403 1 /**************************************************************************//**
FelipeVR 0:f1a413971403 2 * @file core_cmInstr.h
FelipeVR 0:f1a413971403 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
FelipeVR 0:f1a413971403 4 * @version V3.20
FelipeVR 0:f1a413971403 5 * @date 05. March 2013
FelipeVR 0:f1a413971403 6 *
FelipeVR 0:f1a413971403 7 * @note
FelipeVR 0:f1a413971403 8 *
FelipeVR 0:f1a413971403 9 ******************************************************************************/
FelipeVR 0:f1a413971403 10 /* Copyright (c) 2009-2013 ARM LIMITED
FelipeVR 0:f1a413971403 11
FelipeVR 0:f1a413971403 12 All rights reserved.
FelipeVR 0:f1a413971403 13 Redistribution and use in source and binary forms, with or without
FelipeVR 0:f1a413971403 14 modification, are permitted provided that the following conditions are met:
FelipeVR 0:f1a413971403 15 - Redistributions of source code must retain the above copyright
FelipeVR 0:f1a413971403 16 notice, this list of conditions and the following disclaimer.
FelipeVR 0:f1a413971403 17 - Redistributions in binary form must reproduce the above copyright
FelipeVR 0:f1a413971403 18 notice, this list of conditions and the following disclaimer in the
FelipeVR 0:f1a413971403 19 documentation and/or other materials provided with the distribution.
FelipeVR 0:f1a413971403 20 - Neither the name of ARM nor the names of its contributors may be used
FelipeVR 0:f1a413971403 21 to endorse or promote products derived from this software without
FelipeVR 0:f1a413971403 22 specific prior written permission.
FelipeVR 0:f1a413971403 23 *
FelipeVR 0:f1a413971403 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
FelipeVR 0:f1a413971403 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
FelipeVR 0:f1a413971403 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
FelipeVR 0:f1a413971403 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
FelipeVR 0:f1a413971403 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
FelipeVR 0:f1a413971403 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
FelipeVR 0:f1a413971403 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
FelipeVR 0:f1a413971403 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
FelipeVR 0:f1a413971403 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
FelipeVR 0:f1a413971403 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
FelipeVR 0:f1a413971403 34 POSSIBILITY OF SUCH DAMAGE.
FelipeVR 0:f1a413971403 35 ---------------------------------------------------------------------------*/
FelipeVR 0:f1a413971403 36
FelipeVR 0:f1a413971403 37
FelipeVR 0:f1a413971403 38 #ifndef __CORE_CMINSTR_H
FelipeVR 0:f1a413971403 39 #define __CORE_CMINSTR_H
FelipeVR 0:f1a413971403 40
FelipeVR 0:f1a413971403 41
FelipeVR 0:f1a413971403 42 /* ########################## Core Instruction Access ######################### */
FelipeVR 0:f1a413971403 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
FelipeVR 0:f1a413971403 44 Access to dedicated instructions
FelipeVR 0:f1a413971403 45 @{
FelipeVR 0:f1a413971403 46 */
FelipeVR 0:f1a413971403 47
FelipeVR 0:f1a413971403 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
FelipeVR 0:f1a413971403 49 /* ARM armcc specific functions */
FelipeVR 0:f1a413971403 50
FelipeVR 0:f1a413971403 51 #if (__ARMCC_VERSION < 400677)
FelipeVR 0:f1a413971403 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
FelipeVR 0:f1a413971403 53 #endif
FelipeVR 0:f1a413971403 54
FelipeVR 0:f1a413971403 55
FelipeVR 0:f1a413971403 56 /** \brief No Operation
FelipeVR 0:f1a413971403 57
FelipeVR 0:f1a413971403 58 No Operation does nothing. This instruction can be used for code alignment purposes.
FelipeVR 0:f1a413971403 59 */
FelipeVR 0:f1a413971403 60 #define __NOP __nop
FelipeVR 0:f1a413971403 61
FelipeVR 0:f1a413971403 62
FelipeVR 0:f1a413971403 63 /** \brief Wait For Interrupt
FelipeVR 0:f1a413971403 64
FelipeVR 0:f1a413971403 65 Wait For Interrupt is a hint instruction that suspends execution
FelipeVR 0:f1a413971403 66 until one of a number of events occurs.
FelipeVR 0:f1a413971403 67 */
FelipeVR 0:f1a413971403 68 #define __WFI __wfi
FelipeVR 0:f1a413971403 69
FelipeVR 0:f1a413971403 70
FelipeVR 0:f1a413971403 71 /** \brief Wait For Event
FelipeVR 0:f1a413971403 72
FelipeVR 0:f1a413971403 73 Wait For Event is a hint instruction that permits the processor to enter
FelipeVR 0:f1a413971403 74 a low-power state until one of a number of events occurs.
FelipeVR 0:f1a413971403 75 */
FelipeVR 0:f1a413971403 76 #define __WFE __wfe
FelipeVR 0:f1a413971403 77
FelipeVR 0:f1a413971403 78
FelipeVR 0:f1a413971403 79 /** \brief Send Event
FelipeVR 0:f1a413971403 80
FelipeVR 0:f1a413971403 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
FelipeVR 0:f1a413971403 82 */
FelipeVR 0:f1a413971403 83 #define __SEV __sev
FelipeVR 0:f1a413971403 84
FelipeVR 0:f1a413971403 85
FelipeVR 0:f1a413971403 86 /** \brief Instruction Synchronization Barrier
FelipeVR 0:f1a413971403 87
FelipeVR 0:f1a413971403 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
FelipeVR 0:f1a413971403 89 so that all instructions following the ISB are fetched from cache or
FelipeVR 0:f1a413971403 90 memory, after the instruction has been completed.
FelipeVR 0:f1a413971403 91 */
FelipeVR 0:f1a413971403 92 #define __ISB() __isb(0xF)
FelipeVR 0:f1a413971403 93
FelipeVR 0:f1a413971403 94
FelipeVR 0:f1a413971403 95 /** \brief Data Synchronization Barrier
FelipeVR 0:f1a413971403 96
FelipeVR 0:f1a413971403 97 This function acts as a special kind of Data Memory Barrier.
FelipeVR 0:f1a413971403 98 It completes when all explicit memory accesses before this instruction complete.
FelipeVR 0:f1a413971403 99 */
FelipeVR 0:f1a413971403 100 #define __DSB() __dsb(0xF)
FelipeVR 0:f1a413971403 101
FelipeVR 0:f1a413971403 102
FelipeVR 0:f1a413971403 103 /** \brief Data Memory Barrier
FelipeVR 0:f1a413971403 104
FelipeVR 0:f1a413971403 105 This function ensures the apparent order of the explicit memory operations before
FelipeVR 0:f1a413971403 106 and after the instruction, without ensuring their completion.
FelipeVR 0:f1a413971403 107 */
FelipeVR 0:f1a413971403 108 #define __DMB() __dmb(0xF)
FelipeVR 0:f1a413971403 109
FelipeVR 0:f1a413971403 110
FelipeVR 0:f1a413971403 111 /** \brief Reverse byte order (32 bit)
FelipeVR 0:f1a413971403 112
FelipeVR 0:f1a413971403 113 This function reverses the byte order in integer value.
FelipeVR 0:f1a413971403 114
FelipeVR 0:f1a413971403 115 \param [in] value Value to reverse
FelipeVR 0:f1a413971403 116 \return Reversed value
FelipeVR 0:f1a413971403 117 */
FelipeVR 0:f1a413971403 118 #define __REV __rev
FelipeVR 0:f1a413971403 119
FelipeVR 0:f1a413971403 120
FelipeVR 0:f1a413971403 121 /** \brief Reverse byte order (16 bit)
FelipeVR 0:f1a413971403 122
FelipeVR 0:f1a413971403 123 This function reverses the byte order in two unsigned short values.
FelipeVR 0:f1a413971403 124
FelipeVR 0:f1a413971403 125 \param [in] value Value to reverse
FelipeVR 0:f1a413971403 126 \return Reversed value
FelipeVR 0:f1a413971403 127 */
FelipeVR 0:f1a413971403 128 #ifndef __NO_EMBEDDED_ASM
FelipeVR 0:f1a413971403 129 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
FelipeVR 0:f1a413971403 130 {
FelipeVR 0:f1a413971403 131 rev16 r0, r0
FelipeVR 0:f1a413971403 132 bx lr
FelipeVR 0:f1a413971403 133 }
FelipeVR 0:f1a413971403 134 #endif
FelipeVR 0:f1a413971403 135
FelipeVR 0:f1a413971403 136 /** \brief Reverse byte order in signed short value
FelipeVR 0:f1a413971403 137
FelipeVR 0:f1a413971403 138 This function reverses the byte order in a signed short value with sign extension to integer.
FelipeVR 0:f1a413971403 139
FelipeVR 0:f1a413971403 140 \param [in] value Value to reverse
FelipeVR 0:f1a413971403 141 \return Reversed value
FelipeVR 0:f1a413971403 142 */
FelipeVR 0:f1a413971403 143 #ifndef __NO_EMBEDDED_ASM
FelipeVR 0:f1a413971403 144 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
FelipeVR 0:f1a413971403 145 {
FelipeVR 0:f1a413971403 146 revsh r0, r0
FelipeVR 0:f1a413971403 147 bx lr
FelipeVR 0:f1a413971403 148 }
FelipeVR 0:f1a413971403 149 #endif
FelipeVR 0:f1a413971403 150
FelipeVR 0:f1a413971403 151
FelipeVR 0:f1a413971403 152 /** \brief Rotate Right in unsigned value (32 bit)
FelipeVR 0:f1a413971403 153
FelipeVR 0:f1a413971403 154 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
FelipeVR 0:f1a413971403 155
FelipeVR 0:f1a413971403 156 \param [in] value Value to rotate
FelipeVR 0:f1a413971403 157 \param [in] value Number of Bits to rotate
FelipeVR 0:f1a413971403 158 \return Rotated value
FelipeVR 0:f1a413971403 159 */
FelipeVR 0:f1a413971403 160 #define __ROR __ror
FelipeVR 0:f1a413971403 161
FelipeVR 0:f1a413971403 162
FelipeVR 0:f1a413971403 163 /** \brief Breakpoint
FelipeVR 0:f1a413971403 164
FelipeVR 0:f1a413971403 165 This function causes the processor to enter Debug state.
FelipeVR 0:f1a413971403 166 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
FelipeVR 0:f1a413971403 167
FelipeVR 0:f1a413971403 168 \param [in] value is ignored by the processor.
FelipeVR 0:f1a413971403 169 If required, a debugger can use it to store additional information about the breakpoint.
FelipeVR 0:f1a413971403 170 */
FelipeVR 0:f1a413971403 171 #define __BKPT(value) __breakpoint(value)
FelipeVR 0:f1a413971403 172
FelipeVR 0:f1a413971403 173
FelipeVR 0:f1a413971403 174 #if (__CORTEX_M >= 0x03)
FelipeVR 0:f1a413971403 175
FelipeVR 0:f1a413971403 176 /** \brief Reverse bit order of value
FelipeVR 0:f1a413971403 177
FelipeVR 0:f1a413971403 178 This function reverses the bit order of the given value.
FelipeVR 0:f1a413971403 179
FelipeVR 0:f1a413971403 180 \param [in] value Value to reverse
FelipeVR 0:f1a413971403 181 \return Reversed value
FelipeVR 0:f1a413971403 182 */
FelipeVR 0:f1a413971403 183 #define __RBIT __rbit
FelipeVR 0:f1a413971403 184
FelipeVR 0:f1a413971403 185
FelipeVR 0:f1a413971403 186 /** \brief LDR Exclusive (8 bit)
FelipeVR 0:f1a413971403 187
FelipeVR 0:f1a413971403 188 This function performs a exclusive LDR command for 8 bit value.
FelipeVR 0:f1a413971403 189
FelipeVR 0:f1a413971403 190 \param [in] ptr Pointer to data
FelipeVR 0:f1a413971403 191 \return value of type uint8_t at (*ptr)
FelipeVR 0:f1a413971403 192 */
FelipeVR 0:f1a413971403 193 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
FelipeVR 0:f1a413971403 194
FelipeVR 0:f1a413971403 195
FelipeVR 0:f1a413971403 196 /** \brief LDR Exclusive (16 bit)
FelipeVR 0:f1a413971403 197
FelipeVR 0:f1a413971403 198 This function performs a exclusive LDR command for 16 bit values.
FelipeVR 0:f1a413971403 199
FelipeVR 0:f1a413971403 200 \param [in] ptr Pointer to data
FelipeVR 0:f1a413971403 201 \return value of type uint16_t at (*ptr)
FelipeVR 0:f1a413971403 202 */
FelipeVR 0:f1a413971403 203 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
FelipeVR 0:f1a413971403 204
FelipeVR 0:f1a413971403 205
FelipeVR 0:f1a413971403 206 /** \brief LDR Exclusive (32 bit)
FelipeVR 0:f1a413971403 207
FelipeVR 0:f1a413971403 208 This function performs a exclusive LDR command for 32 bit values.
FelipeVR 0:f1a413971403 209
FelipeVR 0:f1a413971403 210 \param [in] ptr Pointer to data
FelipeVR 0:f1a413971403 211 \return value of type uint32_t at (*ptr)
FelipeVR 0:f1a413971403 212 */
FelipeVR 0:f1a413971403 213 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
FelipeVR 0:f1a413971403 214
FelipeVR 0:f1a413971403 215
FelipeVR 0:f1a413971403 216 /** \brief STR Exclusive (8 bit)
FelipeVR 0:f1a413971403 217
FelipeVR 0:f1a413971403 218 This function performs a exclusive STR command for 8 bit values.
FelipeVR 0:f1a413971403 219
FelipeVR 0:f1a413971403 220 \param [in] value Value to store
FelipeVR 0:f1a413971403 221 \param [in] ptr Pointer to location
FelipeVR 0:f1a413971403 222 \return 0 Function succeeded
FelipeVR 0:f1a413971403 223 \return 1 Function failed
FelipeVR 0:f1a413971403 224 */
FelipeVR 0:f1a413971403 225 #define __STREXB(value, ptr) __strex(value, ptr)
FelipeVR 0:f1a413971403 226
FelipeVR 0:f1a413971403 227
FelipeVR 0:f1a413971403 228 /** \brief STR Exclusive (16 bit)
FelipeVR 0:f1a413971403 229
FelipeVR 0:f1a413971403 230 This function performs a exclusive STR command for 16 bit values.
FelipeVR 0:f1a413971403 231
FelipeVR 0:f1a413971403 232 \param [in] value Value to store
FelipeVR 0:f1a413971403 233 \param [in] ptr Pointer to location
FelipeVR 0:f1a413971403 234 \return 0 Function succeeded
FelipeVR 0:f1a413971403 235 \return 1 Function failed
FelipeVR 0:f1a413971403 236 */
FelipeVR 0:f1a413971403 237 #define __STREXH(value, ptr) __strex(value, ptr)
FelipeVR 0:f1a413971403 238
FelipeVR 0:f1a413971403 239
FelipeVR 0:f1a413971403 240 /** \brief STR Exclusive (32 bit)
FelipeVR 0:f1a413971403 241
FelipeVR 0:f1a413971403 242 This function performs a exclusive STR command for 32 bit values.
FelipeVR 0:f1a413971403 243
FelipeVR 0:f1a413971403 244 \param [in] value Value to store
FelipeVR 0:f1a413971403 245 \param [in] ptr Pointer to location
FelipeVR 0:f1a413971403 246 \return 0 Function succeeded
FelipeVR 0:f1a413971403 247 \return 1 Function failed
FelipeVR 0:f1a413971403 248 */
FelipeVR 0:f1a413971403 249 #define __STREXW(value, ptr) __strex(value, ptr)
FelipeVR 0:f1a413971403 250
FelipeVR 0:f1a413971403 251
FelipeVR 0:f1a413971403 252 /** \brief Remove the exclusive lock
FelipeVR 0:f1a413971403 253
FelipeVR 0:f1a413971403 254 This function removes the exclusive lock which is created by LDREX.
FelipeVR 0:f1a413971403 255
FelipeVR 0:f1a413971403 256 */
FelipeVR 0:f1a413971403 257 #define __CLREX __clrex
FelipeVR 0:f1a413971403 258
FelipeVR 0:f1a413971403 259
FelipeVR 0:f1a413971403 260 /** \brief Signed Saturate
FelipeVR 0:f1a413971403 261
FelipeVR 0:f1a413971403 262 This function saturates a signed value.
FelipeVR 0:f1a413971403 263
FelipeVR 0:f1a413971403 264 \param [in] value Value to be saturated
FelipeVR 0:f1a413971403 265 \param [in] sat Bit position to saturate to (1..32)
FelipeVR 0:f1a413971403 266 \return Saturated value
FelipeVR 0:f1a413971403 267 */
FelipeVR 0:f1a413971403 268 #define __SSAT __ssat
FelipeVR 0:f1a413971403 269
FelipeVR 0:f1a413971403 270
FelipeVR 0:f1a413971403 271 /** \brief Unsigned Saturate
FelipeVR 0:f1a413971403 272
FelipeVR 0:f1a413971403 273 This function saturates an unsigned value.
FelipeVR 0:f1a413971403 274
FelipeVR 0:f1a413971403 275 \param [in] value Value to be saturated
FelipeVR 0:f1a413971403 276 \param [in] sat Bit position to saturate to (0..31)
FelipeVR 0:f1a413971403 277 \return Saturated value
FelipeVR 0:f1a413971403 278 */
FelipeVR 0:f1a413971403 279 #define __USAT __usat
FelipeVR 0:f1a413971403 280
FelipeVR 0:f1a413971403 281
FelipeVR 0:f1a413971403 282 /** \brief Count leading zeros
FelipeVR 0:f1a413971403 283
FelipeVR 0:f1a413971403 284 This function counts the number of leading zeros of a data value.
FelipeVR 0:f1a413971403 285
FelipeVR 0:f1a413971403 286 \param [in] value Value to count the leading zeros
FelipeVR 0:f1a413971403 287 \return number of leading zeros in value
FelipeVR 0:f1a413971403 288 */
FelipeVR 0:f1a413971403 289 #define __CLZ __clz
FelipeVR 0:f1a413971403 290
FelipeVR 0:f1a413971403 291 #endif /* (__CORTEX_M >= 0x03) */
FelipeVR 0:f1a413971403 292
FelipeVR 0:f1a413971403 293
FelipeVR 0:f1a413971403 294
FelipeVR 0:f1a413971403 295 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
FelipeVR 0:f1a413971403 296 /* IAR iccarm specific functions */
FelipeVR 0:f1a413971403 297
FelipeVR 0:f1a413971403 298 #include <cmsis_iar.h>
FelipeVR 0:f1a413971403 299
FelipeVR 0:f1a413971403 300
FelipeVR 0:f1a413971403 301 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
FelipeVR 0:f1a413971403 302 /* TI CCS specific functions */
FelipeVR 0:f1a413971403 303
FelipeVR 0:f1a413971403 304 #include <cmsis_ccs.h>
FelipeVR 0:f1a413971403 305
FelipeVR 0:f1a413971403 306
FelipeVR 0:f1a413971403 307 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
FelipeVR 0:f1a413971403 308 /* GNU gcc specific functions */
FelipeVR 0:f1a413971403 309
FelipeVR 0:f1a413971403 310 /* Define macros for porting to both thumb1 and thumb2.
FelipeVR 0:f1a413971403 311 * For thumb1, use low register (r0-r7), specified by constrant "l"
FelipeVR 0:f1a413971403 312 * Otherwise, use general registers, specified by constrant "r" */
FelipeVR 0:f1a413971403 313 #if defined (__thumb__) && !defined (__thumb2__)
FelipeVR 0:f1a413971403 314 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
FelipeVR 0:f1a413971403 315 #define __CMSIS_GCC_USE_REG(r) "l" (r)
FelipeVR 0:f1a413971403 316 #else
FelipeVR 0:f1a413971403 317 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
FelipeVR 0:f1a413971403 318 #define __CMSIS_GCC_USE_REG(r) "r" (r)
FelipeVR 0:f1a413971403 319 #endif
FelipeVR 0:f1a413971403 320
FelipeVR 0:f1a413971403 321 /** \brief No Operation
FelipeVR 0:f1a413971403 322
FelipeVR 0:f1a413971403 323 No Operation does nothing. This instruction can be used for code alignment purposes.
FelipeVR 0:f1a413971403 324 */
FelipeVR 0:f1a413971403 325 __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
FelipeVR 0:f1a413971403 326 {
FelipeVR 0:f1a413971403 327 __ASM volatile ("nop");
FelipeVR 0:f1a413971403 328 }
FelipeVR 0:f1a413971403 329
FelipeVR 0:f1a413971403 330
FelipeVR 0:f1a413971403 331 /** \brief Wait For Interrupt
FelipeVR 0:f1a413971403 332
FelipeVR 0:f1a413971403 333 Wait For Interrupt is a hint instruction that suspends execution
FelipeVR 0:f1a413971403 334 until one of a number of events occurs.
FelipeVR 0:f1a413971403 335 */
FelipeVR 0:f1a413971403 336 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
FelipeVR 0:f1a413971403 337 {
FelipeVR 0:f1a413971403 338 __ASM volatile ("wfi");
FelipeVR 0:f1a413971403 339 }
FelipeVR 0:f1a413971403 340
FelipeVR 0:f1a413971403 341
FelipeVR 0:f1a413971403 342 /** \brief Wait For Event
FelipeVR 0:f1a413971403 343
FelipeVR 0:f1a413971403 344 Wait For Event is a hint instruction that permits the processor to enter
FelipeVR 0:f1a413971403 345 a low-power state until one of a number of events occurs.
FelipeVR 0:f1a413971403 346 */
FelipeVR 0:f1a413971403 347 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
FelipeVR 0:f1a413971403 348 {
FelipeVR 0:f1a413971403 349 __ASM volatile ("wfe");
FelipeVR 0:f1a413971403 350 }
FelipeVR 0:f1a413971403 351
FelipeVR 0:f1a413971403 352
FelipeVR 0:f1a413971403 353 /** \brief Send Event
FelipeVR 0:f1a413971403 354
FelipeVR 0:f1a413971403 355 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
FelipeVR 0:f1a413971403 356 */
FelipeVR 0:f1a413971403 357 __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
FelipeVR 0:f1a413971403 358 {
FelipeVR 0:f1a413971403 359 __ASM volatile ("sev");
FelipeVR 0:f1a413971403 360 }
FelipeVR 0:f1a413971403 361
FelipeVR 0:f1a413971403 362
FelipeVR 0:f1a413971403 363 /** \brief Instruction Synchronization Barrier
FelipeVR 0:f1a413971403 364
FelipeVR 0:f1a413971403 365 Instruction Synchronization Barrier flushes the pipeline in the processor,
FelipeVR 0:f1a413971403 366 so that all instructions following the ISB are fetched from cache or
FelipeVR 0:f1a413971403 367 memory, after the instruction has been completed.
FelipeVR 0:f1a413971403 368 */
FelipeVR 0:f1a413971403 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
FelipeVR 0:f1a413971403 370 {
FelipeVR 0:f1a413971403 371 __ASM volatile ("isb");
FelipeVR 0:f1a413971403 372 }
FelipeVR 0:f1a413971403 373
FelipeVR 0:f1a413971403 374
FelipeVR 0:f1a413971403 375 /** \brief Data Synchronization Barrier
FelipeVR 0:f1a413971403 376
FelipeVR 0:f1a413971403 377 This function acts as a special kind of Data Memory Barrier.
FelipeVR 0:f1a413971403 378 It completes when all explicit memory accesses before this instruction complete.
FelipeVR 0:f1a413971403 379 */
FelipeVR 0:f1a413971403 380 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
FelipeVR 0:f1a413971403 381 {
FelipeVR 0:f1a413971403 382 __ASM volatile ("dsb");
FelipeVR 0:f1a413971403 383 }
FelipeVR 0:f1a413971403 384
FelipeVR 0:f1a413971403 385
FelipeVR 0:f1a413971403 386 /** \brief Data Memory Barrier
FelipeVR 0:f1a413971403 387
FelipeVR 0:f1a413971403 388 This function ensures the apparent order of the explicit memory operations before
FelipeVR 0:f1a413971403 389 and after the instruction, without ensuring their completion.
FelipeVR 0:f1a413971403 390 */
FelipeVR 0:f1a413971403 391 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
FelipeVR 0:f1a413971403 392 {
FelipeVR 0:f1a413971403 393 __ASM volatile ("dmb");
FelipeVR 0:f1a413971403 394 }
FelipeVR 0:f1a413971403 395
FelipeVR 0:f1a413971403 396
FelipeVR 0:f1a413971403 397 /** \brief Reverse byte order (32 bit)
FelipeVR 0:f1a413971403 398
FelipeVR 0:f1a413971403 399 This function reverses the byte order in integer value.
FelipeVR 0:f1a413971403 400
FelipeVR 0:f1a413971403 401 \param [in] value Value to reverse
FelipeVR 0:f1a413971403 402 \return Reversed value
FelipeVR 0:f1a413971403 403 */
FelipeVR 0:f1a413971403 404 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
FelipeVR 0:f1a413971403 405 {
FelipeVR 0:f1a413971403 406 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
FelipeVR 0:f1a413971403 407 return __builtin_bswap32(value);
FelipeVR 0:f1a413971403 408 #else
FelipeVR 0:f1a413971403 409 uint32_t result;
FelipeVR 0:f1a413971403 410
FelipeVR 0:f1a413971403 411 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
FelipeVR 0:f1a413971403 412 return(result);
FelipeVR 0:f1a413971403 413 #endif
FelipeVR 0:f1a413971403 414 }
FelipeVR 0:f1a413971403 415
FelipeVR 0:f1a413971403 416
FelipeVR 0:f1a413971403 417 /** \brief Reverse byte order (16 bit)
FelipeVR 0:f1a413971403 418
FelipeVR 0:f1a413971403 419 This function reverses the byte order in two unsigned short values.
FelipeVR 0:f1a413971403 420
FelipeVR 0:f1a413971403 421 \param [in] value Value to reverse
FelipeVR 0:f1a413971403 422 \return Reversed value
FelipeVR 0:f1a413971403 423 */
FelipeVR 0:f1a413971403 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
FelipeVR 0:f1a413971403 425 {
FelipeVR 0:f1a413971403 426 uint32_t result;
FelipeVR 0:f1a413971403 427
FelipeVR 0:f1a413971403 428 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
FelipeVR 0:f1a413971403 429 return(result);
FelipeVR 0:f1a413971403 430 }
FelipeVR 0:f1a413971403 431
FelipeVR 0:f1a413971403 432
FelipeVR 0:f1a413971403 433 /** \brief Reverse byte order in signed short value
FelipeVR 0:f1a413971403 434
FelipeVR 0:f1a413971403 435 This function reverses the byte order in a signed short value with sign extension to integer.
FelipeVR 0:f1a413971403 436
FelipeVR 0:f1a413971403 437 \param [in] value Value to reverse
FelipeVR 0:f1a413971403 438 \return Reversed value
FelipeVR 0:f1a413971403 439 */
FelipeVR 0:f1a413971403 440 __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
FelipeVR 0:f1a413971403 441 {
FelipeVR 0:f1a413971403 442 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
FelipeVR 0:f1a413971403 443 return (short)__builtin_bswap16(value);
FelipeVR 0:f1a413971403 444 #else
FelipeVR 0:f1a413971403 445 uint32_t result;
FelipeVR 0:f1a413971403 446
FelipeVR 0:f1a413971403 447 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
FelipeVR 0:f1a413971403 448 return(result);
FelipeVR 0:f1a413971403 449 #endif
FelipeVR 0:f1a413971403 450 }
FelipeVR 0:f1a413971403 451
FelipeVR 0:f1a413971403 452
FelipeVR 0:f1a413971403 453 /** \brief Rotate Right in unsigned value (32 bit)
FelipeVR 0:f1a413971403 454
FelipeVR 0:f1a413971403 455 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
FelipeVR 0:f1a413971403 456
FelipeVR 0:f1a413971403 457 \param [in] value Value to rotate
FelipeVR 0:f1a413971403 458 \param [in] value Number of Bits to rotate
FelipeVR 0:f1a413971403 459 \return Rotated value
FelipeVR 0:f1a413971403 460 */
FelipeVR 0:f1a413971403 461 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
FelipeVR 0:f1a413971403 462 {
FelipeVR 0:f1a413971403 463 return (op1 >> op2) | (op1 << (32 - op2));
FelipeVR 0:f1a413971403 464 }
FelipeVR 0:f1a413971403 465
FelipeVR 0:f1a413971403 466
FelipeVR 0:f1a413971403 467 /** \brief Breakpoint
FelipeVR 0:f1a413971403 468
FelipeVR 0:f1a413971403 469 This function causes the processor to enter Debug state.
FelipeVR 0:f1a413971403 470 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
FelipeVR 0:f1a413971403 471
FelipeVR 0:f1a413971403 472 \param [in] value is ignored by the processor.
FelipeVR 0:f1a413971403 473 If required, a debugger can use it to store additional information about the breakpoint.
FelipeVR 0:f1a413971403 474 */
FelipeVR 0:f1a413971403 475 #define __BKPT(value) __ASM volatile ("bkpt "#value)
FelipeVR 0:f1a413971403 476
FelipeVR 0:f1a413971403 477
FelipeVR 0:f1a413971403 478 #if (__CORTEX_M >= 0x03)
FelipeVR 0:f1a413971403 479
FelipeVR 0:f1a413971403 480 /** \brief Reverse bit order of value
FelipeVR 0:f1a413971403 481
FelipeVR 0:f1a413971403 482 This function reverses the bit order of the given value.
FelipeVR 0:f1a413971403 483
FelipeVR 0:f1a413971403 484 \param [in] value Value to reverse
FelipeVR 0:f1a413971403 485 \return Reversed value
FelipeVR 0:f1a413971403 486 */
FelipeVR 0:f1a413971403 487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
FelipeVR 0:f1a413971403 488 {
FelipeVR 0:f1a413971403 489 uint32_t result;
FelipeVR 0:f1a413971403 490
FelipeVR 0:f1a413971403 491 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
FelipeVR 0:f1a413971403 492 return(result);
FelipeVR 0:f1a413971403 493 }
FelipeVR 0:f1a413971403 494
FelipeVR 0:f1a413971403 495
FelipeVR 0:f1a413971403 496 /** \brief LDR Exclusive (8 bit)
FelipeVR 0:f1a413971403 497
FelipeVR 0:f1a413971403 498 This function performs a exclusive LDR command for 8 bit value.
FelipeVR 0:f1a413971403 499
FelipeVR 0:f1a413971403 500 \param [in] ptr Pointer to data
FelipeVR 0:f1a413971403 501 \return value of type uint8_t at (*ptr)
FelipeVR 0:f1a413971403 502 */
FelipeVR 0:f1a413971403 503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
FelipeVR 0:f1a413971403 504 {
FelipeVR 0:f1a413971403 505 uint32_t result;
FelipeVR 0:f1a413971403 506
FelipeVR 0:f1a413971403 507 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
FelipeVR 0:f1a413971403 508 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
FelipeVR 0:f1a413971403 509 #else
FelipeVR 0:f1a413971403 510 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
FelipeVR 0:f1a413971403 511 accepted by assembler. So has to use following less efficient pattern.
FelipeVR 0:f1a413971403 512 */
FelipeVR 0:f1a413971403 513 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
FelipeVR 0:f1a413971403 514 #endif
FelipeVR 0:f1a413971403 515 return(result);
FelipeVR 0:f1a413971403 516 }
FelipeVR 0:f1a413971403 517
FelipeVR 0:f1a413971403 518
FelipeVR 0:f1a413971403 519 /** \brief LDR Exclusive (16 bit)
FelipeVR 0:f1a413971403 520
FelipeVR 0:f1a413971403 521 This function performs a exclusive LDR command for 16 bit values.
FelipeVR 0:f1a413971403 522
FelipeVR 0:f1a413971403 523 \param [in] ptr Pointer to data
FelipeVR 0:f1a413971403 524 \return value of type uint16_t at (*ptr)
FelipeVR 0:f1a413971403 525 */
FelipeVR 0:f1a413971403 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
FelipeVR 0:f1a413971403 527 {
FelipeVR 0:f1a413971403 528 uint32_t result;
FelipeVR 0:f1a413971403 529
FelipeVR 0:f1a413971403 530 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
FelipeVR 0:f1a413971403 531 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
FelipeVR 0:f1a413971403 532 #else
FelipeVR 0:f1a413971403 533 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
FelipeVR 0:f1a413971403 534 accepted by assembler. So has to use following less efficient pattern.
FelipeVR 0:f1a413971403 535 */
FelipeVR 0:f1a413971403 536 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
FelipeVR 0:f1a413971403 537 #endif
FelipeVR 0:f1a413971403 538 return(result);
FelipeVR 0:f1a413971403 539 }
FelipeVR 0:f1a413971403 540
FelipeVR 0:f1a413971403 541
FelipeVR 0:f1a413971403 542 /** \brief LDR Exclusive (32 bit)
FelipeVR 0:f1a413971403 543
FelipeVR 0:f1a413971403 544 This function performs a exclusive LDR command for 32 bit values.
FelipeVR 0:f1a413971403 545
FelipeVR 0:f1a413971403 546 \param [in] ptr Pointer to data
FelipeVR 0:f1a413971403 547 \return value of type uint32_t at (*ptr)
FelipeVR 0:f1a413971403 548 */
FelipeVR 0:f1a413971403 549 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
FelipeVR 0:f1a413971403 550 {
FelipeVR 0:f1a413971403 551 uint32_t result;
FelipeVR 0:f1a413971403 552
FelipeVR 0:f1a413971403 553 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
FelipeVR 0:f1a413971403 554 return(result);
FelipeVR 0:f1a413971403 555 }
FelipeVR 0:f1a413971403 556
FelipeVR 0:f1a413971403 557
FelipeVR 0:f1a413971403 558 /** \brief STR Exclusive (8 bit)
FelipeVR 0:f1a413971403 559
FelipeVR 0:f1a413971403 560 This function performs a exclusive STR command for 8 bit values.
FelipeVR 0:f1a413971403 561
FelipeVR 0:f1a413971403 562 \param [in] value Value to store
FelipeVR 0:f1a413971403 563 \param [in] ptr Pointer to location
FelipeVR 0:f1a413971403 564 \return 0 Function succeeded
FelipeVR 0:f1a413971403 565 \return 1 Function failed
FelipeVR 0:f1a413971403 566 */
FelipeVR 0:f1a413971403 567 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
FelipeVR 0:f1a413971403 568 {
FelipeVR 0:f1a413971403 569 uint32_t result;
FelipeVR 0:f1a413971403 570
FelipeVR 0:f1a413971403 571 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
FelipeVR 0:f1a413971403 572 return(result);
FelipeVR 0:f1a413971403 573 }
FelipeVR 0:f1a413971403 574
FelipeVR 0:f1a413971403 575
FelipeVR 0:f1a413971403 576 /** \brief STR Exclusive (16 bit)
FelipeVR 0:f1a413971403 577
FelipeVR 0:f1a413971403 578 This function performs a exclusive STR command for 16 bit values.
FelipeVR 0:f1a413971403 579
FelipeVR 0:f1a413971403 580 \param [in] value Value to store
FelipeVR 0:f1a413971403 581 \param [in] ptr Pointer to location
FelipeVR 0:f1a413971403 582 \return 0 Function succeeded
FelipeVR 0:f1a413971403 583 \return 1 Function failed
FelipeVR 0:f1a413971403 584 */
FelipeVR 0:f1a413971403 585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
FelipeVR 0:f1a413971403 586 {
FelipeVR 0:f1a413971403 587 uint32_t result;
FelipeVR 0:f1a413971403 588
FelipeVR 0:f1a413971403 589 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
FelipeVR 0:f1a413971403 590 return(result);
FelipeVR 0:f1a413971403 591 }
FelipeVR 0:f1a413971403 592
FelipeVR 0:f1a413971403 593
FelipeVR 0:f1a413971403 594 /** \brief STR Exclusive (32 bit)
FelipeVR 0:f1a413971403 595
FelipeVR 0:f1a413971403 596 This function performs a exclusive STR command for 32 bit values.
FelipeVR 0:f1a413971403 597
FelipeVR 0:f1a413971403 598 \param [in] value Value to store
FelipeVR 0:f1a413971403 599 \param [in] ptr Pointer to location
FelipeVR 0:f1a413971403 600 \return 0 Function succeeded
FelipeVR 0:f1a413971403 601 \return 1 Function failed
FelipeVR 0:f1a413971403 602 */
FelipeVR 0:f1a413971403 603 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
FelipeVR 0:f1a413971403 604 {
FelipeVR 0:f1a413971403 605 uint32_t result;
FelipeVR 0:f1a413971403 606
FelipeVR 0:f1a413971403 607 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
FelipeVR 0:f1a413971403 608 return(result);
FelipeVR 0:f1a413971403 609 }
FelipeVR 0:f1a413971403 610
FelipeVR 0:f1a413971403 611
FelipeVR 0:f1a413971403 612 /** \brief Remove the exclusive lock
FelipeVR 0:f1a413971403 613
FelipeVR 0:f1a413971403 614 This function removes the exclusive lock which is created by LDREX.
FelipeVR 0:f1a413971403 615
FelipeVR 0:f1a413971403 616 */
FelipeVR 0:f1a413971403 617 __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
FelipeVR 0:f1a413971403 618 {
FelipeVR 0:f1a413971403 619 __ASM volatile ("clrex" ::: "memory");
FelipeVR 0:f1a413971403 620 }
FelipeVR 0:f1a413971403 621
FelipeVR 0:f1a413971403 622
FelipeVR 0:f1a413971403 623 /** \brief Signed Saturate
FelipeVR 0:f1a413971403 624
FelipeVR 0:f1a413971403 625 This function saturates a signed value.
FelipeVR 0:f1a413971403 626
FelipeVR 0:f1a413971403 627 \param [in] value Value to be saturated
FelipeVR 0:f1a413971403 628 \param [in] sat Bit position to saturate to (1..32)
FelipeVR 0:f1a413971403 629 \return Saturated value
FelipeVR 0:f1a413971403 630 */
FelipeVR 0:f1a413971403 631 #define __SSAT(ARG1,ARG2) \
FelipeVR 0:f1a413971403 632 ({ \
FelipeVR 0:f1a413971403 633 uint32_t __RES, __ARG1 = (ARG1); \
FelipeVR 0:f1a413971403 634 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
FelipeVR 0:f1a413971403 635 __RES; \
FelipeVR 0:f1a413971403 636 })
FelipeVR 0:f1a413971403 637
FelipeVR 0:f1a413971403 638
FelipeVR 0:f1a413971403 639 /** \brief Unsigned Saturate
FelipeVR 0:f1a413971403 640
FelipeVR 0:f1a413971403 641 This function saturates an unsigned value.
FelipeVR 0:f1a413971403 642
FelipeVR 0:f1a413971403 643 \param [in] value Value to be saturated
FelipeVR 0:f1a413971403 644 \param [in] sat Bit position to saturate to (0..31)
FelipeVR 0:f1a413971403 645 \return Saturated value
FelipeVR 0:f1a413971403 646 */
FelipeVR 0:f1a413971403 647 #define __USAT(ARG1,ARG2) \
FelipeVR 0:f1a413971403 648 ({ \
FelipeVR 0:f1a413971403 649 uint32_t __RES, __ARG1 = (ARG1); \
FelipeVR 0:f1a413971403 650 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
FelipeVR 0:f1a413971403 651 __RES; \
FelipeVR 0:f1a413971403 652 })
FelipeVR 0:f1a413971403 653
FelipeVR 0:f1a413971403 654
FelipeVR 0:f1a413971403 655 /** \brief Count leading zeros
FelipeVR 0:f1a413971403 656
FelipeVR 0:f1a413971403 657 This function counts the number of leading zeros of a data value.
FelipeVR 0:f1a413971403 658
FelipeVR 0:f1a413971403 659 \param [in] value Value to count the leading zeros
FelipeVR 0:f1a413971403 660 \return number of leading zeros in value
FelipeVR 0:f1a413971403 661 */
FelipeVR 0:f1a413971403 662 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
FelipeVR 0:f1a413971403 663 {
FelipeVR 0:f1a413971403 664 uint32_t result;
FelipeVR 0:f1a413971403 665
FelipeVR 0:f1a413971403 666 __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
FelipeVR 0:f1a413971403 667 return(result);
FelipeVR 0:f1a413971403 668 }
FelipeVR 0:f1a413971403 669
FelipeVR 0:f1a413971403 670 #endif /* (__CORTEX_M >= 0x03) */
FelipeVR 0:f1a413971403 671
FelipeVR 0:f1a413971403 672
FelipeVR 0:f1a413971403 673
FelipeVR 0:f1a413971403 674
FelipeVR 0:f1a413971403 675 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
FelipeVR 0:f1a413971403 676 /* TASKING carm specific functions */
FelipeVR 0:f1a413971403 677
FelipeVR 0:f1a413971403 678 /*
FelipeVR 0:f1a413971403 679 * The CMSIS functions have been implemented as intrinsics in the compiler.
FelipeVR 0:f1a413971403 680 * Please use "carm -?i" to get an up to date list of all intrinsics,
FelipeVR 0:f1a413971403 681 * Including the CMSIS ones.
FelipeVR 0:f1a413971403 682 */
FelipeVR 0:f1a413971403 683
FelipeVR 0:f1a413971403 684 #endif
FelipeVR 0:f1a413971403 685
FelipeVR 0:f1a413971403 686 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
FelipeVR 0:f1a413971403 687
FelipeVR 0:f1a413971403 688 #endif /* __CORE_CMINSTR_H */