Felipe Velazquez / SMARTES_lib

SMARTEST lib for MPS2

Dependents:   MSP2_LCD_HOLA

core_cm3.h@0:f1a413971403, 2018-08-23 (annotated)

Committer:
FelipeVR
Date:
Thu Aug 23 13:39:38 2018 +0000
Revision:
0:f1a413971403
SMARTEST LCD

Who changed what in which revision?

UserRevisionLine numberNew contents of line
FelipeVR 0:f1a413971403 1 /**************************************************************************//**
FelipeVR 0:f1a413971403 2 * @file core_cm3.h
FelipeVR 0:f1a413971403 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
FelipeVR 0:f1a413971403 4 * @version V3.20
FelipeVR 0:f1a413971403 5 * @date 25. February 2013
FelipeVR 0:f1a413971403 6 *
FelipeVR 0:f1a413971403 7 * @note
FelipeVR 0:f1a413971403 8 *
FelipeVR 0:f1a413971403 9 ******************************************************************************/
FelipeVR 0:f1a413971403 10 /* Copyright (c) 2009-2013 ARM LIMITED
FelipeVR 0:f1a413971403 11
FelipeVR 0:f1a413971403 12 All rights reserved.
FelipeVR 0:f1a413971403 13 Redistribution and use in source and binary forms, with or without
FelipeVR 0:f1a413971403 14 modification, are permitted provided that the following conditions are met:
FelipeVR 0:f1a413971403 15 - Redistributions of source code must retain the above copyright
FelipeVR 0:f1a413971403 16 notice, this list of conditions and the following disclaimer.
FelipeVR 0:f1a413971403 17 - Redistributions in binary form must reproduce the above copyright
FelipeVR 0:f1a413971403 18 notice, this list of conditions and the following disclaimer in the
FelipeVR 0:f1a413971403 19 documentation and/or other materials provided with the distribution.
FelipeVR 0:f1a413971403 20 - Neither the name of ARM nor the names of its contributors may be used
FelipeVR 0:f1a413971403 21 to endorse or promote products derived from this software without
FelipeVR 0:f1a413971403 22 specific prior written permission.
FelipeVR 0:f1a413971403 23 *
FelipeVR 0:f1a413971403 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
FelipeVR 0:f1a413971403 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
FelipeVR 0:f1a413971403 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
FelipeVR 0:f1a413971403 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
FelipeVR 0:f1a413971403 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
FelipeVR 0:f1a413971403 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
FelipeVR 0:f1a413971403 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
FelipeVR 0:f1a413971403 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
FelipeVR 0:f1a413971403 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
FelipeVR 0:f1a413971403 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
FelipeVR 0:f1a413971403 34 POSSIBILITY OF SUCH DAMAGE.
FelipeVR 0:f1a413971403 35 ---------------------------------------------------------------------------*/
FelipeVR 0:f1a413971403 36
FelipeVR 0:f1a413971403 37
FelipeVR 0:f1a413971403 38 #if defined ( __ICCARM__ )
FelipeVR 0:f1a413971403 39 #pragma system_include /* treat file as system include file for MISRA check */
FelipeVR 0:f1a413971403 40 #endif
FelipeVR 0:f1a413971403 41
FelipeVR 0:f1a413971403 42 #ifdef __cplusplus
FelipeVR 0:f1a413971403 43 extern "C" {
FelipeVR 0:f1a413971403 44 #endif
FelipeVR 0:f1a413971403 45
FelipeVR 0:f1a413971403 46 #ifndef __CORE_CM3_H_GENERIC
FelipeVR 0:f1a413971403 47 #define __CORE_CM3_H_GENERIC
FelipeVR 0:f1a413971403 48
FelipeVR 0:f1a413971403 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
FelipeVR 0:f1a413971403 50 CMSIS violates the following MISRA-C:2004 rules:
FelipeVR 0:f1a413971403 51
FelipeVR 0:f1a413971403 52 \li Required Rule 8.5, object/function definition in header file.<br>
FelipeVR 0:f1a413971403 53 Function definitions in header files are used to allow 'inlining'.
FelipeVR 0:f1a413971403 54
FelipeVR 0:f1a413971403 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
FelipeVR 0:f1a413971403 56 Unions are used for effective representation of core registers.
FelipeVR 0:f1a413971403 57
FelipeVR 0:f1a413971403 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
FelipeVR 0:f1a413971403 59 Function-like macros are used to allow more efficient code.
FelipeVR 0:f1a413971403 60 */
FelipeVR 0:f1a413971403 61
FelipeVR 0:f1a413971403 62
FelipeVR 0:f1a413971403 63 /*******************************************************************************
FelipeVR 0:f1a413971403 64 * CMSIS definitions
FelipeVR 0:f1a413971403 65 ******************************************************************************/
FelipeVR 0:f1a413971403 66 /** \ingroup Cortex_M3
FelipeVR 0:f1a413971403 67 @{
FelipeVR 0:f1a413971403 68 */
FelipeVR 0:f1a413971403 69
FelipeVR 0:f1a413971403 70 /* CMSIS CM3 definitions */
FelipeVR 0:f1a413971403 71 #define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
FelipeVR 0:f1a413971403 72 #define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
FelipeVR 0:f1a413971403 73 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
FelipeVR 0:f1a413971403 74 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
FelipeVR 0:f1a413971403 75
FelipeVR 0:f1a413971403 76 #define __CORTEX_M (0x03) /*!< Cortex-M Core */
FelipeVR 0:f1a413971403 77
FelipeVR 0:f1a413971403 78
FelipeVR 0:f1a413971403 79 #if defined ( __CC_ARM )
FelipeVR 0:f1a413971403 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
FelipeVR 0:f1a413971403 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
FelipeVR 0:f1a413971403 82 #define __STATIC_INLINE static __inline
FelipeVR 0:f1a413971403 83
FelipeVR 0:f1a413971403 84 #elif defined ( __ICCARM__ )
FelipeVR 0:f1a413971403 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
FelipeVR 0:f1a413971403 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
FelipeVR 0:f1a413971403 87 #define __STATIC_INLINE static inline
FelipeVR 0:f1a413971403 88
FelipeVR 0:f1a413971403 89 #elif defined ( __TMS470__ )
FelipeVR 0:f1a413971403 90 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
FelipeVR 0:f1a413971403 91 #define __STATIC_INLINE static inline
FelipeVR 0:f1a413971403 92
FelipeVR 0:f1a413971403 93 #elif defined ( __GNUC__ )
FelipeVR 0:f1a413971403 94 #define __ASM __asm /*!< asm keyword for GNU Compiler */
FelipeVR 0:f1a413971403 95 #define __INLINE inline /*!< inline keyword for GNU Compiler */
FelipeVR 0:f1a413971403 96 #define __STATIC_INLINE static inline
FelipeVR 0:f1a413971403 97
FelipeVR 0:f1a413971403 98 #elif defined ( __TASKING__ )
FelipeVR 0:f1a413971403 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
FelipeVR 0:f1a413971403 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
FelipeVR 0:f1a413971403 101 #define __STATIC_INLINE static inline
FelipeVR 0:f1a413971403 102
FelipeVR 0:f1a413971403 103 #endif
FelipeVR 0:f1a413971403 104
FelipeVR 0:f1a413971403 105 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
FelipeVR 0:f1a413971403 106 */
FelipeVR 0:f1a413971403 107 #define __FPU_USED 0
FelipeVR 0:f1a413971403 108
FelipeVR 0:f1a413971403 109 #if defined ( __CC_ARM )
FelipeVR 0:f1a413971403 110 #if defined __TARGET_FPU_VFP
FelipeVR 0:f1a413971403 111 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
FelipeVR 0:f1a413971403 112 #endif
FelipeVR 0:f1a413971403 113
FelipeVR 0:f1a413971403 114 #elif defined ( __ICCARM__ )
FelipeVR 0:f1a413971403 115 #if defined __ARMVFP__
FelipeVR 0:f1a413971403 116 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
FelipeVR 0:f1a413971403 117 #endif
FelipeVR 0:f1a413971403 118
FelipeVR 0:f1a413971403 119 #elif defined ( __TMS470__ )
FelipeVR 0:f1a413971403 120 #if defined __TI__VFP_SUPPORT____
FelipeVR 0:f1a413971403 121 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
FelipeVR 0:f1a413971403 122 #endif
FelipeVR 0:f1a413971403 123
FelipeVR 0:f1a413971403 124 #elif defined ( __GNUC__ )
FelipeVR 0:f1a413971403 125 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
FelipeVR 0:f1a413971403 126 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
FelipeVR 0:f1a413971403 127 #endif
FelipeVR 0:f1a413971403 128
FelipeVR 0:f1a413971403 129 #elif defined ( __TASKING__ )
FelipeVR 0:f1a413971403 130 #if defined __FPU_VFP__
FelipeVR 0:f1a413971403 131 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
FelipeVR 0:f1a413971403 132 #endif
FelipeVR 0:f1a413971403 133 #endif
FelipeVR 0:f1a413971403 134
FelipeVR 0:f1a413971403 135 #include <stdint.h> /* standard types definitions */
FelipeVR 0:f1a413971403 136 #include <core_cmInstr.h> /* Core Instruction Access */
FelipeVR 0:f1a413971403 137 #include <core_cmFunc.h> /* Core Function Access */
FelipeVR 0:f1a413971403 138
FelipeVR 0:f1a413971403 139 #endif /* __CORE_CM3_H_GENERIC */
FelipeVR 0:f1a413971403 140
FelipeVR 0:f1a413971403 141 #ifndef __CMSIS_GENERIC
FelipeVR 0:f1a413971403 142
FelipeVR 0:f1a413971403 143 #ifndef __CORE_CM3_H_DEPENDANT
FelipeVR 0:f1a413971403 144 #define __CORE_CM3_H_DEPENDANT
FelipeVR 0:f1a413971403 145
FelipeVR 0:f1a413971403 146 /* check device defines and use defaults */
FelipeVR 0:f1a413971403 147 #if defined __CHECK_DEVICE_DEFINES
FelipeVR 0:f1a413971403 148 #ifndef __CM3_REV
FelipeVR 0:f1a413971403 149 #define __CM3_REV 0x0200
FelipeVR 0:f1a413971403 150 #warning "__CM3_REV not defined in device header file; using default!"
FelipeVR 0:f1a413971403 151 #endif
FelipeVR 0:f1a413971403 152
FelipeVR 0:f1a413971403 153 #ifndef __MPU_PRESENT
FelipeVR 0:f1a413971403 154 #define __MPU_PRESENT 0
FelipeVR 0:f1a413971403 155 #warning "__MPU_PRESENT not defined in device header file; using default!"
FelipeVR 0:f1a413971403 156 #endif
FelipeVR 0:f1a413971403 157
FelipeVR 0:f1a413971403 158 #ifndef __NVIC_PRIO_BITS
FelipeVR 0:f1a413971403 159 #define __NVIC_PRIO_BITS 4
FelipeVR 0:f1a413971403 160 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
FelipeVR 0:f1a413971403 161 #endif
FelipeVR 0:f1a413971403 162
FelipeVR 0:f1a413971403 163 #ifndef __Vendor_SysTickConfig
FelipeVR 0:f1a413971403 164 #define __Vendor_SysTickConfig 0
FelipeVR 0:f1a413971403 165 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
FelipeVR 0:f1a413971403 166 #endif
FelipeVR 0:f1a413971403 167 #endif
FelipeVR 0:f1a413971403 168
FelipeVR 0:f1a413971403 169 /* IO definitions (access restrictions to peripheral registers) */
FelipeVR 0:f1a413971403 170 /**
FelipeVR 0:f1a413971403 171 \defgroup CMSIS_glob_defs CMSIS Global Defines
FelipeVR 0:f1a413971403 172
FelipeVR 0:f1a413971403 173 <strong>IO Type Qualifiers</strong> are used
FelipeVR 0:f1a413971403 174 \li to specify the access to peripheral variables.
FelipeVR 0:f1a413971403 175 \li for automatic generation of peripheral register debug information.
FelipeVR 0:f1a413971403 176 */
FelipeVR 0:f1a413971403 177 #ifdef __cplusplus
FelipeVR 0:f1a413971403 178 #define __I volatile /*!< Defines 'read only' permissions */
FelipeVR 0:f1a413971403 179 #else
FelipeVR 0:f1a413971403 180 #define __I volatile const /*!< Defines 'read only' permissions */
FelipeVR 0:f1a413971403 181 #endif
FelipeVR 0:f1a413971403 182 #define __O volatile /*!< Defines 'write only' permissions */
FelipeVR 0:f1a413971403 183 #define __IO volatile /*!< Defines 'read / write' permissions */
FelipeVR 0:f1a413971403 184
FelipeVR 0:f1a413971403 185 /*@} end of group Cortex_M3 */
FelipeVR 0:f1a413971403 186
FelipeVR 0:f1a413971403 187
FelipeVR 0:f1a413971403 188
FelipeVR 0:f1a413971403 189 /*******************************************************************************
FelipeVR 0:f1a413971403 190 * Register Abstraction
FelipeVR 0:f1a413971403 191 Core Register contain:
FelipeVR 0:f1a413971403 192 - Core Register
FelipeVR 0:f1a413971403 193 - Core NVIC Register
FelipeVR 0:f1a413971403 194 - Core SCB Register
FelipeVR 0:f1a413971403 195 - Core SysTick Register
FelipeVR 0:f1a413971403 196 - Core Debug Register
FelipeVR 0:f1a413971403 197 - Core MPU Register
FelipeVR 0:f1a413971403 198 ******************************************************************************/
FelipeVR 0:f1a413971403 199 /** \defgroup CMSIS_core_register Defines and Type Definitions
FelipeVR 0:f1a413971403 200 \brief Type definitions and defines for Cortex-M processor based devices.
FelipeVR 0:f1a413971403 201 */
FelipeVR 0:f1a413971403 202
FelipeVR 0:f1a413971403 203 /** \ingroup CMSIS_core_register
FelipeVR 0:f1a413971403 204 \defgroup CMSIS_CORE Status and Control Registers
FelipeVR 0:f1a413971403 205 \brief Core Register type definitions.
FelipeVR 0:f1a413971403 206 @{
FelipeVR 0:f1a413971403 207 */
FelipeVR 0:f1a413971403 208
FelipeVR 0:f1a413971403 209 /** \brief Union type to access the Application Program Status Register (APSR).
FelipeVR 0:f1a413971403 210 */
FelipeVR 0:f1a413971403 211 typedef union
FelipeVR 0:f1a413971403 212 {
FelipeVR 0:f1a413971403 213 struct
FelipeVR 0:f1a413971403 214 {
FelipeVR 0:f1a413971403 215 #if (__CORTEX_M != 0x04)
FelipeVR 0:f1a413971403 216 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
FelipeVR 0:f1a413971403 217 #else
FelipeVR 0:f1a413971403 218 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
FelipeVR 0:f1a413971403 219 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
FelipeVR 0:f1a413971403 220 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
FelipeVR 0:f1a413971403 221 #endif
FelipeVR 0:f1a413971403 222 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
FelipeVR 0:f1a413971403 223 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
FelipeVR 0:f1a413971403 224 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
FelipeVR 0:f1a413971403 225 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
FelipeVR 0:f1a413971403 226 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
FelipeVR 0:f1a413971403 227 } b; /*!< Structure used for bit access */
FelipeVR 0:f1a413971403 228 uint32_t w; /*!< Type used for word access */
FelipeVR 0:f1a413971403 229 } APSR_Type;
FelipeVR 0:f1a413971403 230
FelipeVR 0:f1a413971403 231
FelipeVR 0:f1a413971403 232 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
FelipeVR 0:f1a413971403 233 */
FelipeVR 0:f1a413971403 234 typedef union
FelipeVR 0:f1a413971403 235 {
FelipeVR 0:f1a413971403 236 struct
FelipeVR 0:f1a413971403 237 {
FelipeVR 0:f1a413971403 238 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
FelipeVR 0:f1a413971403 239 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
FelipeVR 0:f1a413971403 240 } b; /*!< Structure used for bit access */
FelipeVR 0:f1a413971403 241 uint32_t w; /*!< Type used for word access */
FelipeVR 0:f1a413971403 242 } IPSR_Type;
FelipeVR 0:f1a413971403 243
FelipeVR 0:f1a413971403 244
FelipeVR 0:f1a413971403 245 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
FelipeVR 0:f1a413971403 246 */
FelipeVR 0:f1a413971403 247 typedef union
FelipeVR 0:f1a413971403 248 {
FelipeVR 0:f1a413971403 249 struct
FelipeVR 0:f1a413971403 250 {
FelipeVR 0:f1a413971403 251 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
FelipeVR 0:f1a413971403 252 #if (__CORTEX_M != 0x04)
FelipeVR 0:f1a413971403 253 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
FelipeVR 0:f1a413971403 254 #else
FelipeVR 0:f1a413971403 255 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
FelipeVR 0:f1a413971403 256 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
FelipeVR 0:f1a413971403 257 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
FelipeVR 0:f1a413971403 258 #endif
FelipeVR 0:f1a413971403 259 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
FelipeVR 0:f1a413971403 260 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
FelipeVR 0:f1a413971403 261 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
FelipeVR 0:f1a413971403 262 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
FelipeVR 0:f1a413971403 263 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
FelipeVR 0:f1a413971403 264 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
FelipeVR 0:f1a413971403 265 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
FelipeVR 0:f1a413971403 266 } b; /*!< Structure used for bit access */
FelipeVR 0:f1a413971403 267 uint32_t w; /*!< Type used for word access */
FelipeVR 0:f1a413971403 268 } xPSR_Type;
FelipeVR 0:f1a413971403 269
FelipeVR 0:f1a413971403 270
FelipeVR 0:f1a413971403 271 /** \brief Union type to access the Control Registers (CONTROL).
FelipeVR 0:f1a413971403 272 */
FelipeVR 0:f1a413971403 273 typedef union
FelipeVR 0:f1a413971403 274 {
FelipeVR 0:f1a413971403 275 struct
FelipeVR 0:f1a413971403 276 {
FelipeVR 0:f1a413971403 277 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
FelipeVR 0:f1a413971403 278 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
FelipeVR 0:f1a413971403 279 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
FelipeVR 0:f1a413971403 280 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
FelipeVR 0:f1a413971403 281 } b; /*!< Structure used for bit access */
FelipeVR 0:f1a413971403 282 uint32_t w; /*!< Type used for word access */
FelipeVR 0:f1a413971403 283 } CONTROL_Type;
FelipeVR 0:f1a413971403 284
FelipeVR 0:f1a413971403 285 /*@} end of group CMSIS_CORE */
FelipeVR 0:f1a413971403 286
FelipeVR 0:f1a413971403 287
FelipeVR 0:f1a413971403 288 /** \ingroup CMSIS_core_register
FelipeVR 0:f1a413971403 289 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
FelipeVR 0:f1a413971403 290 \brief Type definitions for the NVIC Registers
FelipeVR 0:f1a413971403 291 @{
FelipeVR 0:f1a413971403 292 */
FelipeVR 0:f1a413971403 293
FelipeVR 0:f1a413971403 294 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
FelipeVR 0:f1a413971403 295 */
FelipeVR 0:f1a413971403 296 typedef struct
FelipeVR 0:f1a413971403 297 {
FelipeVR 0:f1a413971403 298 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
FelipeVR 0:f1a413971403 299 uint32_t RESERVED0[24];
FelipeVR 0:f1a413971403 300 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
FelipeVR 0:f1a413971403 301 uint32_t RSERVED1[24];
FelipeVR 0:f1a413971403 302 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
FelipeVR 0:f1a413971403 303 uint32_t RESERVED2[24];
FelipeVR 0:f1a413971403 304 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
FelipeVR 0:f1a413971403 305 uint32_t RESERVED3[24];
FelipeVR 0:f1a413971403 306 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
FelipeVR 0:f1a413971403 307 uint32_t RESERVED4[56];
FelipeVR 0:f1a413971403 308 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
FelipeVR 0:f1a413971403 309 uint32_t RESERVED5[644];
FelipeVR 0:f1a413971403 310 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
FelipeVR 0:f1a413971403 311 } NVIC_Type;
FelipeVR 0:f1a413971403 312
FelipeVR 0:f1a413971403 313 /* Software Triggered Interrupt Register Definitions */
FelipeVR 0:f1a413971403 314 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
FelipeVR 0:f1a413971403 315 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
FelipeVR 0:f1a413971403 316
FelipeVR 0:f1a413971403 317 /*@} end of group CMSIS_NVIC */
FelipeVR 0:f1a413971403 318
FelipeVR 0:f1a413971403 319
FelipeVR 0:f1a413971403 320 /** \ingroup CMSIS_core_register
FelipeVR 0:f1a413971403 321 \defgroup CMSIS_SCB System Control Block (SCB)
FelipeVR 0:f1a413971403 322 \brief Type definitions for the System Control Block Registers
FelipeVR 0:f1a413971403 323 @{
FelipeVR 0:f1a413971403 324 */
FelipeVR 0:f1a413971403 325
FelipeVR 0:f1a413971403 326 /** \brief Structure type to access the System Control Block (SCB).
FelipeVR 0:f1a413971403 327 */
FelipeVR 0:f1a413971403 328 typedef struct
FelipeVR 0:f1a413971403 329 {
FelipeVR 0:f1a413971403 330 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
FelipeVR 0:f1a413971403 331 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
FelipeVR 0:f1a413971403 332 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
FelipeVR 0:f1a413971403 333 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
FelipeVR 0:f1a413971403 334 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
FelipeVR 0:f1a413971403 335 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
FelipeVR 0:f1a413971403 336 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
FelipeVR 0:f1a413971403 337 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
FelipeVR 0:f1a413971403 338 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
FelipeVR 0:f1a413971403 339 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
FelipeVR 0:f1a413971403 340 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
FelipeVR 0:f1a413971403 341 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
FelipeVR 0:f1a413971403 342 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
FelipeVR 0:f1a413971403 343 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
FelipeVR 0:f1a413971403 344 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
FelipeVR 0:f1a413971403 345 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
FelipeVR 0:f1a413971403 346 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
FelipeVR 0:f1a413971403 347 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
FelipeVR 0:f1a413971403 348 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
FelipeVR 0:f1a413971403 349 uint32_t RESERVED0[5];
FelipeVR 0:f1a413971403 350 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
FelipeVR 0:f1a413971403 351 } SCB_Type;
FelipeVR 0:f1a413971403 352
FelipeVR 0:f1a413971403 353 /* SCB CPUID Register Definitions */
FelipeVR 0:f1a413971403 354 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
FelipeVR 0:f1a413971403 355 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
FelipeVR 0:f1a413971403 356
FelipeVR 0:f1a413971403 357 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
FelipeVR 0:f1a413971403 358 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
FelipeVR 0:f1a413971403 359
FelipeVR 0:f1a413971403 360 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
FelipeVR 0:f1a413971403 361 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
FelipeVR 0:f1a413971403 362
FelipeVR 0:f1a413971403 363 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
FelipeVR 0:f1a413971403 364 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
FelipeVR 0:f1a413971403 365
FelipeVR 0:f1a413971403 366 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
FelipeVR 0:f1a413971403 367 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
FelipeVR 0:f1a413971403 368
FelipeVR 0:f1a413971403 369 /* SCB Interrupt Control State Register Definitions */
FelipeVR 0:f1a413971403 370 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
FelipeVR 0:f1a413971403 371 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
FelipeVR 0:f1a413971403 372
FelipeVR 0:f1a413971403 373 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
FelipeVR 0:f1a413971403 374 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
FelipeVR 0:f1a413971403 375
FelipeVR 0:f1a413971403 376 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
FelipeVR 0:f1a413971403 377 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
FelipeVR 0:f1a413971403 378
FelipeVR 0:f1a413971403 379 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
FelipeVR 0:f1a413971403 380 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
FelipeVR 0:f1a413971403 381
FelipeVR 0:f1a413971403 382 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
FelipeVR 0:f1a413971403 383 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
FelipeVR 0:f1a413971403 384
FelipeVR 0:f1a413971403 385 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
FelipeVR 0:f1a413971403 386 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
FelipeVR 0:f1a413971403 387
FelipeVR 0:f1a413971403 388 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
FelipeVR 0:f1a413971403 389 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
FelipeVR 0:f1a413971403 390
FelipeVR 0:f1a413971403 391 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
FelipeVR 0:f1a413971403 392 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
FelipeVR 0:f1a413971403 393
FelipeVR 0:f1a413971403 394 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
FelipeVR 0:f1a413971403 395 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
FelipeVR 0:f1a413971403 396
FelipeVR 0:f1a413971403 397 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
FelipeVR 0:f1a413971403 398 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
FelipeVR 0:f1a413971403 399
FelipeVR 0:f1a413971403 400 /* SCB Vector Table Offset Register Definitions */
FelipeVR 0:f1a413971403 401 #if (__CM3_REV < 0x0201) /* core r2p1 */
FelipeVR 0:f1a413971403 402 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
FelipeVR 0:f1a413971403 403 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
FelipeVR 0:f1a413971403 404
FelipeVR 0:f1a413971403 405 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
FelipeVR 0:f1a413971403 406 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
FelipeVR 0:f1a413971403 407 #else
FelipeVR 0:f1a413971403 408 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
FelipeVR 0:f1a413971403 409 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
FelipeVR 0:f1a413971403 410 #endif
FelipeVR 0:f1a413971403 411
FelipeVR 0:f1a413971403 412 /* SCB Application Interrupt and Reset Control Register Definitions */
FelipeVR 0:f1a413971403 413 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
FelipeVR 0:f1a413971403 414 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
FelipeVR 0:f1a413971403 415
FelipeVR 0:f1a413971403 416 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
FelipeVR 0:f1a413971403 417 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
FelipeVR 0:f1a413971403 418
FelipeVR 0:f1a413971403 419 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
FelipeVR 0:f1a413971403 420 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
FelipeVR 0:f1a413971403 421
FelipeVR 0:f1a413971403 422 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
FelipeVR 0:f1a413971403 423 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
FelipeVR 0:f1a413971403 424
FelipeVR 0:f1a413971403 425 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
FelipeVR 0:f1a413971403 426 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
FelipeVR 0:f1a413971403 427
FelipeVR 0:f1a413971403 428 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
FelipeVR 0:f1a413971403 429 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
FelipeVR 0:f1a413971403 430
FelipeVR 0:f1a413971403 431 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
FelipeVR 0:f1a413971403 432 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
FelipeVR 0:f1a413971403 433
FelipeVR 0:f1a413971403 434 /* SCB System Control Register Definitions */
FelipeVR 0:f1a413971403 435 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
FelipeVR 0:f1a413971403 436 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
FelipeVR 0:f1a413971403 437
FelipeVR 0:f1a413971403 438 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
FelipeVR 0:f1a413971403 439 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
FelipeVR 0:f1a413971403 440
FelipeVR 0:f1a413971403 441 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
FelipeVR 0:f1a413971403 442 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
FelipeVR 0:f1a413971403 443
FelipeVR 0:f1a413971403 444 /* SCB Configuration Control Register Definitions */
FelipeVR 0:f1a413971403 445 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
FelipeVR 0:f1a413971403 446 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
FelipeVR 0:f1a413971403 447
FelipeVR 0:f1a413971403 448 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
FelipeVR 0:f1a413971403 449 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
FelipeVR 0:f1a413971403 450
FelipeVR 0:f1a413971403 451 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
FelipeVR 0:f1a413971403 452 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
FelipeVR 0:f1a413971403 453
FelipeVR 0:f1a413971403 454 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
FelipeVR 0:f1a413971403 455 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
FelipeVR 0:f1a413971403 456
FelipeVR 0:f1a413971403 457 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
FelipeVR 0:f1a413971403 458 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
FelipeVR 0:f1a413971403 459
FelipeVR 0:f1a413971403 460 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
FelipeVR 0:f1a413971403 461 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
FelipeVR 0:f1a413971403 462
FelipeVR 0:f1a413971403 463 /* SCB System Handler Control and State Register Definitions */
FelipeVR 0:f1a413971403 464 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
FelipeVR 0:f1a413971403 465 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
FelipeVR 0:f1a413971403 466
FelipeVR 0:f1a413971403 467 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
FelipeVR 0:f1a413971403 468 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
FelipeVR 0:f1a413971403 469
FelipeVR 0:f1a413971403 470 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
FelipeVR 0:f1a413971403 471 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
FelipeVR 0:f1a413971403 472
FelipeVR 0:f1a413971403 473 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
FelipeVR 0:f1a413971403 474 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
FelipeVR 0:f1a413971403 475
FelipeVR 0:f1a413971403 476 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
FelipeVR 0:f1a413971403 477 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
FelipeVR 0:f1a413971403 478
FelipeVR 0:f1a413971403 479 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
FelipeVR 0:f1a413971403 480 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
FelipeVR 0:f1a413971403 481
FelipeVR 0:f1a413971403 482 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
FelipeVR 0:f1a413971403 483 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
FelipeVR 0:f1a413971403 484
FelipeVR 0:f1a413971403 485 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
FelipeVR 0:f1a413971403 486 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
FelipeVR 0:f1a413971403 487
FelipeVR 0:f1a413971403 488 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
FelipeVR 0:f1a413971403 489 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
FelipeVR 0:f1a413971403 490
FelipeVR 0:f1a413971403 491 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
FelipeVR 0:f1a413971403 492 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
FelipeVR 0:f1a413971403 493
FelipeVR 0:f1a413971403 494 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
FelipeVR 0:f1a413971403 495 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
FelipeVR 0:f1a413971403 496
FelipeVR 0:f1a413971403 497 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
FelipeVR 0:f1a413971403 498 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
FelipeVR 0:f1a413971403 499
FelipeVR 0:f1a413971403 500 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
FelipeVR 0:f1a413971403 501 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
FelipeVR 0:f1a413971403 502
FelipeVR 0:f1a413971403 503 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
FelipeVR 0:f1a413971403 504 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
FelipeVR 0:f1a413971403 505
FelipeVR 0:f1a413971403 506 /* SCB Configurable Fault Status Registers Definitions */
FelipeVR 0:f1a413971403 507 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
FelipeVR 0:f1a413971403 508 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
FelipeVR 0:f1a413971403 509
FelipeVR 0:f1a413971403 510 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
FelipeVR 0:f1a413971403 511 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
FelipeVR 0:f1a413971403 512
FelipeVR 0:f1a413971403 513 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
FelipeVR 0:f1a413971403 514 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
FelipeVR 0:f1a413971403 515
FelipeVR 0:f1a413971403 516 /* SCB Hard Fault Status Registers Definitions */
FelipeVR 0:f1a413971403 517 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
FelipeVR 0:f1a413971403 518 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
FelipeVR 0:f1a413971403 519
FelipeVR 0:f1a413971403 520 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
FelipeVR 0:f1a413971403 521 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
FelipeVR 0:f1a413971403 522
FelipeVR 0:f1a413971403 523 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
FelipeVR 0:f1a413971403 524 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
FelipeVR 0:f1a413971403 525
FelipeVR 0:f1a413971403 526 /* SCB Debug Fault Status Register Definitions */
FelipeVR 0:f1a413971403 527 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
FelipeVR 0:f1a413971403 528 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
FelipeVR 0:f1a413971403 529
FelipeVR 0:f1a413971403 530 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
FelipeVR 0:f1a413971403 531 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
FelipeVR 0:f1a413971403 532
FelipeVR 0:f1a413971403 533 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
FelipeVR 0:f1a413971403 534 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
FelipeVR 0:f1a413971403 535
FelipeVR 0:f1a413971403 536 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
FelipeVR 0:f1a413971403 537 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
FelipeVR 0:f1a413971403 538
FelipeVR 0:f1a413971403 539 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
FelipeVR 0:f1a413971403 540 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
FelipeVR 0:f1a413971403 541
FelipeVR 0:f1a413971403 542 /*@} end of group CMSIS_SCB */
FelipeVR 0:f1a413971403 543
FelipeVR 0:f1a413971403 544
FelipeVR 0:f1a413971403 545 /** \ingroup CMSIS_core_register
FelipeVR 0:f1a413971403 546 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
FelipeVR 0:f1a413971403 547 \brief Type definitions for the System Control and ID Register not in the SCB
FelipeVR 0:f1a413971403 548 @{
FelipeVR 0:f1a413971403 549 */
FelipeVR 0:f1a413971403 550
FelipeVR 0:f1a413971403 551 /** \brief Structure type to access the System Control and ID Register not in the SCB.
FelipeVR 0:f1a413971403 552 */
FelipeVR 0:f1a413971403 553 typedef struct
FelipeVR 0:f1a413971403 554 {
FelipeVR 0:f1a413971403 555 uint32_t RESERVED0[1];
FelipeVR 0:f1a413971403 556 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
FelipeVR 0:f1a413971403 557 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
FelipeVR 0:f1a413971403 558 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
FelipeVR 0:f1a413971403 559 #else
FelipeVR 0:f1a413971403 560 uint32_t RESERVED1[1];
FelipeVR 0:f1a413971403 561 #endif
FelipeVR 0:f1a413971403 562 } SCnSCB_Type;
FelipeVR 0:f1a413971403 563
FelipeVR 0:f1a413971403 564 /* Interrupt Controller Type Register Definitions */
FelipeVR 0:f1a413971403 565 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
FelipeVR 0:f1a413971403 566 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
FelipeVR 0:f1a413971403 567
FelipeVR 0:f1a413971403 568 /* Auxiliary Control Register Definitions */
FelipeVR 0:f1a413971403 569
FelipeVR 0:f1a413971403 570 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
FelipeVR 0:f1a413971403 571 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
FelipeVR 0:f1a413971403 572
FelipeVR 0:f1a413971403 573 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
FelipeVR 0:f1a413971403 574 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
FelipeVR 0:f1a413971403 575
FelipeVR 0:f1a413971403 576 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
FelipeVR 0:f1a413971403 577 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
FelipeVR 0:f1a413971403 578
FelipeVR 0:f1a413971403 579 /*@} end of group CMSIS_SCnotSCB */
FelipeVR 0:f1a413971403 580
FelipeVR 0:f1a413971403 581
FelipeVR 0:f1a413971403 582 /** \ingroup CMSIS_core_register
FelipeVR 0:f1a413971403 583 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
FelipeVR 0:f1a413971403 584 \brief Type definitions for the System Timer Registers.
FelipeVR 0:f1a413971403 585 @{
FelipeVR 0:f1a413971403 586 */
FelipeVR 0:f1a413971403 587
FelipeVR 0:f1a413971403 588 /** \brief Structure type to access the System Timer (SysTick).
FelipeVR 0:f1a413971403 589 */
FelipeVR 0:f1a413971403 590 typedef struct
FelipeVR 0:f1a413971403 591 {
FelipeVR 0:f1a413971403 592 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
FelipeVR 0:f1a413971403 593 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
FelipeVR 0:f1a413971403 594 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
FelipeVR 0:f1a413971403 595 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
FelipeVR 0:f1a413971403 596 } SysTick_Type;
FelipeVR 0:f1a413971403 597
FelipeVR 0:f1a413971403 598 /* SysTick Control / Status Register Definitions */
FelipeVR 0:f1a413971403 599 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
FelipeVR 0:f1a413971403 600 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
FelipeVR 0:f1a413971403 601
FelipeVR 0:f1a413971403 602 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
FelipeVR 0:f1a413971403 603 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
FelipeVR 0:f1a413971403 604
FelipeVR 0:f1a413971403 605 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
FelipeVR 0:f1a413971403 606 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
FelipeVR 0:f1a413971403 607
FelipeVR 0:f1a413971403 608 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
FelipeVR 0:f1a413971403 609 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
FelipeVR 0:f1a413971403 610
FelipeVR 0:f1a413971403 611 /* SysTick Reload Register Definitions */
FelipeVR 0:f1a413971403 612 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
FelipeVR 0:f1a413971403 613 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
FelipeVR 0:f1a413971403 614
FelipeVR 0:f1a413971403 615 /* SysTick Current Register Definitions */
FelipeVR 0:f1a413971403 616 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
FelipeVR 0:f1a413971403 617 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
FelipeVR 0:f1a413971403 618
FelipeVR 0:f1a413971403 619 /* SysTick Calibration Register Definitions */
FelipeVR 0:f1a413971403 620 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
FelipeVR 0:f1a413971403 621 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
FelipeVR 0:f1a413971403 622
FelipeVR 0:f1a413971403 623 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
FelipeVR 0:f1a413971403 624 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
FelipeVR 0:f1a413971403 625
FelipeVR 0:f1a413971403 626 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
FelipeVR 0:f1a413971403 627 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
FelipeVR 0:f1a413971403 628
FelipeVR 0:f1a413971403 629 /*@} end of group CMSIS_SysTick */
FelipeVR 0:f1a413971403 630
FelipeVR 0:f1a413971403 631
FelipeVR 0:f1a413971403 632 /** \ingroup CMSIS_core_register
FelipeVR 0:f1a413971403 633 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
FelipeVR 0:f1a413971403 634 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
FelipeVR 0:f1a413971403 635 @{
FelipeVR 0:f1a413971403 636 */
FelipeVR 0:f1a413971403 637
FelipeVR 0:f1a413971403 638 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
FelipeVR 0:f1a413971403 639 */
FelipeVR 0:f1a413971403 640 typedef struct
FelipeVR 0:f1a413971403 641 {
FelipeVR 0:f1a413971403 642 __O union
FelipeVR 0:f1a413971403 643 {
FelipeVR 0:f1a413971403 644 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
FelipeVR 0:f1a413971403 645 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
FelipeVR 0:f1a413971403 646 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
FelipeVR 0:f1a413971403 647 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
FelipeVR 0:f1a413971403 648 uint32_t RESERVED0[864];
FelipeVR 0:f1a413971403 649 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
FelipeVR 0:f1a413971403 650 uint32_t RESERVED1[15];
FelipeVR 0:f1a413971403 651 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
FelipeVR 0:f1a413971403 652 uint32_t RESERVED2[15];
FelipeVR 0:f1a413971403 653 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
FelipeVR 0:f1a413971403 654 uint32_t RESERVED3[29];
FelipeVR 0:f1a413971403 655 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
FelipeVR 0:f1a413971403 656 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
FelipeVR 0:f1a413971403 657 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
FelipeVR 0:f1a413971403 658 uint32_t RESERVED4[43];
FelipeVR 0:f1a413971403 659 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
FelipeVR 0:f1a413971403 660 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
FelipeVR 0:f1a413971403 661 uint32_t RESERVED5[6];
FelipeVR 0:f1a413971403 662 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
FelipeVR 0:f1a413971403 663 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
FelipeVR 0:f1a413971403 664 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
FelipeVR 0:f1a413971403 665 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
FelipeVR 0:f1a413971403 666 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
FelipeVR 0:f1a413971403 667 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
FelipeVR 0:f1a413971403 668 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
FelipeVR 0:f1a413971403 669 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
FelipeVR 0:f1a413971403 670 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
FelipeVR 0:f1a413971403 671 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
FelipeVR 0:f1a413971403 672 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
FelipeVR 0:f1a413971403 673 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
FelipeVR 0:f1a413971403 674 } ITM_Type;
FelipeVR 0:f1a413971403 675
FelipeVR 0:f1a413971403 676 /* ITM Trace Privilege Register Definitions */
FelipeVR 0:f1a413971403 677 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
FelipeVR 0:f1a413971403 678 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
FelipeVR 0:f1a413971403 679
FelipeVR 0:f1a413971403 680 /* ITM Trace Control Register Definitions */
FelipeVR 0:f1a413971403 681 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
FelipeVR 0:f1a413971403 682 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
FelipeVR 0:f1a413971403 683
FelipeVR 0:f1a413971403 684 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
FelipeVR 0:f1a413971403 685 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
FelipeVR 0:f1a413971403 686
FelipeVR 0:f1a413971403 687 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
FelipeVR 0:f1a413971403 688 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
FelipeVR 0:f1a413971403 689
FelipeVR 0:f1a413971403 690 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
FelipeVR 0:f1a413971403 691 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
FelipeVR 0:f1a413971403 692
FelipeVR 0:f1a413971403 693 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
FelipeVR 0:f1a413971403 694 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
FelipeVR 0:f1a413971403 695
FelipeVR 0:f1a413971403 696 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
FelipeVR 0:f1a413971403 697 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
FelipeVR 0:f1a413971403 698
FelipeVR 0:f1a413971403 699 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
FelipeVR 0:f1a413971403 700 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
FelipeVR 0:f1a413971403 701
FelipeVR 0:f1a413971403 702 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
FelipeVR 0:f1a413971403 703 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
FelipeVR 0:f1a413971403 704
FelipeVR 0:f1a413971403 705 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
FelipeVR 0:f1a413971403 706 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
FelipeVR 0:f1a413971403 707
FelipeVR 0:f1a413971403 708 /* ITM Integration Write Register Definitions */
FelipeVR 0:f1a413971403 709 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
FelipeVR 0:f1a413971403 710 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
FelipeVR 0:f1a413971403 711
FelipeVR 0:f1a413971403 712 /* ITM Integration Read Register Definitions */
FelipeVR 0:f1a413971403 713 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
FelipeVR 0:f1a413971403 714 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
FelipeVR 0:f1a413971403 715
FelipeVR 0:f1a413971403 716 /* ITM Integration Mode Control Register Definitions */
FelipeVR 0:f1a413971403 717 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
FelipeVR 0:f1a413971403 718 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
FelipeVR 0:f1a413971403 719
FelipeVR 0:f1a413971403 720 /* ITM Lock Status Register Definitions */
FelipeVR 0:f1a413971403 721 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
FelipeVR 0:f1a413971403 722 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
FelipeVR 0:f1a413971403 723
FelipeVR 0:f1a413971403 724 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
FelipeVR 0:f1a413971403 725 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
FelipeVR 0:f1a413971403 726
FelipeVR 0:f1a413971403 727 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
FelipeVR 0:f1a413971403 728 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
FelipeVR 0:f1a413971403 729
FelipeVR 0:f1a413971403 730 /*@}*/ /* end of group CMSIS_ITM */
FelipeVR 0:f1a413971403 731
FelipeVR 0:f1a413971403 732
FelipeVR 0:f1a413971403 733 /** \ingroup CMSIS_core_register
FelipeVR 0:f1a413971403 734 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
FelipeVR 0:f1a413971403 735 \brief Type definitions for the Data Watchpoint and Trace (DWT)
FelipeVR 0:f1a413971403 736 @{
FelipeVR 0:f1a413971403 737 */
FelipeVR 0:f1a413971403 738
FelipeVR 0:f1a413971403 739 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
FelipeVR 0:f1a413971403 740 */
FelipeVR 0:f1a413971403 741 typedef struct
FelipeVR 0:f1a413971403 742 {
FelipeVR 0:f1a413971403 743 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
FelipeVR 0:f1a413971403 744 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
FelipeVR 0:f1a413971403 745 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
FelipeVR 0:f1a413971403 746 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
FelipeVR 0:f1a413971403 747 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
FelipeVR 0:f1a413971403 748 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
FelipeVR 0:f1a413971403 749 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
FelipeVR 0:f1a413971403 750 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
FelipeVR 0:f1a413971403 751 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
FelipeVR 0:f1a413971403 752 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
FelipeVR 0:f1a413971403 753 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
FelipeVR 0:f1a413971403 754 uint32_t RESERVED0[1];
FelipeVR 0:f1a413971403 755 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
FelipeVR 0:f1a413971403 756 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
FelipeVR 0:f1a413971403 757 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
FelipeVR 0:f1a413971403 758 uint32_t RESERVED1[1];
FelipeVR 0:f1a413971403 759 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
FelipeVR 0:f1a413971403 760 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
FelipeVR 0:f1a413971403 761 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
FelipeVR 0:f1a413971403 762 uint32_t RESERVED2[1];
FelipeVR 0:f1a413971403 763 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
FelipeVR 0:f1a413971403 764 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
FelipeVR 0:f1a413971403 765 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
FelipeVR 0:f1a413971403 766 } DWT_Type;
FelipeVR 0:f1a413971403 767
FelipeVR 0:f1a413971403 768 /* DWT Control Register Definitions */
FelipeVR 0:f1a413971403 769 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
FelipeVR 0:f1a413971403 770 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
FelipeVR 0:f1a413971403 771
FelipeVR 0:f1a413971403 772 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
FelipeVR 0:f1a413971403 773 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
FelipeVR 0:f1a413971403 774
FelipeVR 0:f1a413971403 775 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
FelipeVR 0:f1a413971403 776 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
FelipeVR 0:f1a413971403 777
FelipeVR 0:f1a413971403 778 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
FelipeVR 0:f1a413971403 779 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
FelipeVR 0:f1a413971403 780
FelipeVR 0:f1a413971403 781 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
FelipeVR 0:f1a413971403 782 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
FelipeVR 0:f1a413971403 783
FelipeVR 0:f1a413971403 784 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
FelipeVR 0:f1a413971403 785 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
FelipeVR 0:f1a413971403 786
FelipeVR 0:f1a413971403 787 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
FelipeVR 0:f1a413971403 788 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
FelipeVR 0:f1a413971403 789
FelipeVR 0:f1a413971403 790 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
FelipeVR 0:f1a413971403 791 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
FelipeVR 0:f1a413971403 792
FelipeVR 0:f1a413971403 793 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
FelipeVR 0:f1a413971403 794 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
FelipeVR 0:f1a413971403 795
FelipeVR 0:f1a413971403 796 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
FelipeVR 0:f1a413971403 797 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
FelipeVR 0:f1a413971403 798
FelipeVR 0:f1a413971403 799 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
FelipeVR 0:f1a413971403 800 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
FelipeVR 0:f1a413971403 801
FelipeVR 0:f1a413971403 802 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
FelipeVR 0:f1a413971403 803 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
FelipeVR 0:f1a413971403 804
FelipeVR 0:f1a413971403 805 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
FelipeVR 0:f1a413971403 806 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
FelipeVR 0:f1a413971403 807
FelipeVR 0:f1a413971403 808 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
FelipeVR 0:f1a413971403 809 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
FelipeVR 0:f1a413971403 810
FelipeVR 0:f1a413971403 811 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
FelipeVR 0:f1a413971403 812 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
FelipeVR 0:f1a413971403 813
FelipeVR 0:f1a413971403 814 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
FelipeVR 0:f1a413971403 815 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
FelipeVR 0:f1a413971403 816
FelipeVR 0:f1a413971403 817 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
FelipeVR 0:f1a413971403 818 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
FelipeVR 0:f1a413971403 819
FelipeVR 0:f1a413971403 820 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
FelipeVR 0:f1a413971403 821 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
FelipeVR 0:f1a413971403 822
FelipeVR 0:f1a413971403 823 /* DWT CPI Count Register Definitions */
FelipeVR 0:f1a413971403 824 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
FelipeVR 0:f1a413971403 825 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
FelipeVR 0:f1a413971403 826
FelipeVR 0:f1a413971403 827 /* DWT Exception Overhead Count Register Definitions */
FelipeVR 0:f1a413971403 828 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
FelipeVR 0:f1a413971403 829 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
FelipeVR 0:f1a413971403 830
FelipeVR 0:f1a413971403 831 /* DWT Sleep Count Register Definitions */
FelipeVR 0:f1a413971403 832 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
FelipeVR 0:f1a413971403 833 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
FelipeVR 0:f1a413971403 834
FelipeVR 0:f1a413971403 835 /* DWT LSU Count Register Definitions */
FelipeVR 0:f1a413971403 836 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
FelipeVR 0:f1a413971403 837 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
FelipeVR 0:f1a413971403 838
FelipeVR 0:f1a413971403 839 /* DWT Folded-instruction Count Register Definitions */
FelipeVR 0:f1a413971403 840 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
FelipeVR 0:f1a413971403 841 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
FelipeVR 0:f1a413971403 842
FelipeVR 0:f1a413971403 843 /* DWT Comparator Mask Register Definitions */
FelipeVR 0:f1a413971403 844 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
FelipeVR 0:f1a413971403 845 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
FelipeVR 0:f1a413971403 846
FelipeVR 0:f1a413971403 847 /* DWT Comparator Function Register Definitions */
FelipeVR 0:f1a413971403 848 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
FelipeVR 0:f1a413971403 849 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
FelipeVR 0:f1a413971403 850
FelipeVR 0:f1a413971403 851 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
FelipeVR 0:f1a413971403 852 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
FelipeVR 0:f1a413971403 853
FelipeVR 0:f1a413971403 854 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
FelipeVR 0:f1a413971403 855 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
FelipeVR 0:f1a413971403 856
FelipeVR 0:f1a413971403 857 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
FelipeVR 0:f1a413971403 858 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
FelipeVR 0:f1a413971403 859
FelipeVR 0:f1a413971403 860 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
FelipeVR 0:f1a413971403 861 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
FelipeVR 0:f1a413971403 862
FelipeVR 0:f1a413971403 863 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
FelipeVR 0:f1a413971403 864 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
FelipeVR 0:f1a413971403 865
FelipeVR 0:f1a413971403 866 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
FelipeVR 0:f1a413971403 867 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
FelipeVR 0:f1a413971403 868
FelipeVR 0:f1a413971403 869 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
FelipeVR 0:f1a413971403 870 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
FelipeVR 0:f1a413971403 871
FelipeVR 0:f1a413971403 872 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
FelipeVR 0:f1a413971403 873 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
FelipeVR 0:f1a413971403 874
FelipeVR 0:f1a413971403 875 /*@}*/ /* end of group CMSIS_DWT */
FelipeVR 0:f1a413971403 876
FelipeVR 0:f1a413971403 877
FelipeVR 0:f1a413971403 878 /** \ingroup CMSIS_core_register
FelipeVR 0:f1a413971403 879 \defgroup CMSIS_TPI Trace Port Interface (TPI)
FelipeVR 0:f1a413971403 880 \brief Type definitions for the Trace Port Interface (TPI)
FelipeVR 0:f1a413971403 881 @{
FelipeVR 0:f1a413971403 882 */
FelipeVR 0:f1a413971403 883
FelipeVR 0:f1a413971403 884 /** \brief Structure type to access the Trace Port Interface Register (TPI).
FelipeVR 0:f1a413971403 885 */
FelipeVR 0:f1a413971403 886 typedef struct
FelipeVR 0:f1a413971403 887 {
FelipeVR 0:f1a413971403 888 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
FelipeVR 0:f1a413971403 889 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
FelipeVR 0:f1a413971403 890 uint32_t RESERVED0[2];
FelipeVR 0:f1a413971403 891 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
FelipeVR 0:f1a413971403 892 uint32_t RESERVED1[55];
FelipeVR 0:f1a413971403 893 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
FelipeVR 0:f1a413971403 894 uint32_t RESERVED2[131];
FelipeVR 0:f1a413971403 895 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
FelipeVR 0:f1a413971403 896 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
FelipeVR 0:f1a413971403 897 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
FelipeVR 0:f1a413971403 898 uint32_t RESERVED3[759];
FelipeVR 0:f1a413971403 899 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
FelipeVR 0:f1a413971403 900 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
FelipeVR 0:f1a413971403 901 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
FelipeVR 0:f1a413971403 902 uint32_t RESERVED4[1];
FelipeVR 0:f1a413971403 903 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
FelipeVR 0:f1a413971403 904 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
FelipeVR 0:f1a413971403 905 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
FelipeVR 0:f1a413971403 906 uint32_t RESERVED5[39];
FelipeVR 0:f1a413971403 907 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
FelipeVR 0:f1a413971403 908 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
FelipeVR 0:f1a413971403 909 uint32_t RESERVED7[8];
FelipeVR 0:f1a413971403 910 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
FelipeVR 0:f1a413971403 911 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
FelipeVR 0:f1a413971403 912 } TPI_Type;
FelipeVR 0:f1a413971403 913
FelipeVR 0:f1a413971403 914 /* TPI Asynchronous Clock Prescaler Register Definitions */
FelipeVR 0:f1a413971403 915 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
FelipeVR 0:f1a413971403 916 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
FelipeVR 0:f1a413971403 917
FelipeVR 0:f1a413971403 918 /* TPI Selected Pin Protocol Register Definitions */
FelipeVR 0:f1a413971403 919 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
FelipeVR 0:f1a413971403 920 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
FelipeVR 0:f1a413971403 921
FelipeVR 0:f1a413971403 922 /* TPI Formatter and Flush Status Register Definitions */
FelipeVR 0:f1a413971403 923 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
FelipeVR 0:f1a413971403 924 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
FelipeVR 0:f1a413971403 925
FelipeVR 0:f1a413971403 926 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
FelipeVR 0:f1a413971403 927 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
FelipeVR 0:f1a413971403 928
FelipeVR 0:f1a413971403 929 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
FelipeVR 0:f1a413971403 930 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
FelipeVR 0:f1a413971403 931
FelipeVR 0:f1a413971403 932 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
FelipeVR 0:f1a413971403 933 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
FelipeVR 0:f1a413971403 934
FelipeVR 0:f1a413971403 935 /* TPI Formatter and Flush Control Register Definitions */
FelipeVR 0:f1a413971403 936 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
FelipeVR 0:f1a413971403 937 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
FelipeVR 0:f1a413971403 938
FelipeVR 0:f1a413971403 939 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
FelipeVR 0:f1a413971403 940 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
FelipeVR 0:f1a413971403 941
FelipeVR 0:f1a413971403 942 /* TPI TRIGGER Register Definitions */
FelipeVR 0:f1a413971403 943 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
FelipeVR 0:f1a413971403 944 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
FelipeVR 0:f1a413971403 945
FelipeVR 0:f1a413971403 946 /* TPI Integration ETM Data Register Definitions (FIFO0) */
FelipeVR 0:f1a413971403 947 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
FelipeVR 0:f1a413971403 948 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
FelipeVR 0:f1a413971403 949
FelipeVR 0:f1a413971403 950 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
FelipeVR 0:f1a413971403 951 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
FelipeVR 0:f1a413971403 952
FelipeVR 0:f1a413971403 953 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
FelipeVR 0:f1a413971403 954 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
FelipeVR 0:f1a413971403 955
FelipeVR 0:f1a413971403 956 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
FelipeVR 0:f1a413971403 957 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
FelipeVR 0:f1a413971403 958
FelipeVR 0:f1a413971403 959 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
FelipeVR 0:f1a413971403 960 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
FelipeVR 0:f1a413971403 961
FelipeVR 0:f1a413971403 962 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
FelipeVR 0:f1a413971403 963 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
FelipeVR 0:f1a413971403 964
FelipeVR 0:f1a413971403 965 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
FelipeVR 0:f1a413971403 966 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
FelipeVR 0:f1a413971403 967
FelipeVR 0:f1a413971403 968 /* TPI ITATBCTR2 Register Definitions */
FelipeVR 0:f1a413971403 969 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
FelipeVR 0:f1a413971403 970 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
FelipeVR 0:f1a413971403 971
FelipeVR 0:f1a413971403 972 /* TPI Integration ITM Data Register Definitions (FIFO1) */
FelipeVR 0:f1a413971403 973 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
FelipeVR 0:f1a413971403 974 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
FelipeVR 0:f1a413971403 975
FelipeVR 0:f1a413971403 976 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
FelipeVR 0:f1a413971403 977 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
FelipeVR 0:f1a413971403 978
FelipeVR 0:f1a413971403 979 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
FelipeVR 0:f1a413971403 980 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
FelipeVR 0:f1a413971403 981
FelipeVR 0:f1a413971403 982 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
FelipeVR 0:f1a413971403 983 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
FelipeVR 0:f1a413971403 984
FelipeVR 0:f1a413971403 985 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
FelipeVR 0:f1a413971403 986 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
FelipeVR 0:f1a413971403 987
FelipeVR 0:f1a413971403 988 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
FelipeVR 0:f1a413971403 989 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
FelipeVR 0:f1a413971403 990
FelipeVR 0:f1a413971403 991 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
FelipeVR 0:f1a413971403 992 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
FelipeVR 0:f1a413971403 993
FelipeVR 0:f1a413971403 994 /* TPI ITATBCTR0 Register Definitions */
FelipeVR 0:f1a413971403 995 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
FelipeVR 0:f1a413971403 996 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
FelipeVR 0:f1a413971403 997
FelipeVR 0:f1a413971403 998 /* TPI Integration Mode Control Register Definitions */
FelipeVR 0:f1a413971403 999 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
FelipeVR 0:f1a413971403 1000 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
FelipeVR 0:f1a413971403 1001
FelipeVR 0:f1a413971403 1002 /* TPI DEVID Register Definitions */
FelipeVR 0:f1a413971403 1003 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
FelipeVR 0:f1a413971403 1004 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
FelipeVR 0:f1a413971403 1005
FelipeVR 0:f1a413971403 1006 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
FelipeVR 0:f1a413971403 1007 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
FelipeVR 0:f1a413971403 1008
FelipeVR 0:f1a413971403 1009 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
FelipeVR 0:f1a413971403 1010 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
FelipeVR 0:f1a413971403 1011
FelipeVR 0:f1a413971403 1012 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
FelipeVR 0:f1a413971403 1013 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
FelipeVR 0:f1a413971403 1014
FelipeVR 0:f1a413971403 1015 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
FelipeVR 0:f1a413971403 1016 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
FelipeVR 0:f1a413971403 1017
FelipeVR 0:f1a413971403 1018 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
FelipeVR 0:f1a413971403 1019 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
FelipeVR 0:f1a413971403 1020
FelipeVR 0:f1a413971403 1021 /* TPI DEVTYPE Register Definitions */
FelipeVR 0:f1a413971403 1022 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
FelipeVR 0:f1a413971403 1023 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
FelipeVR 0:f1a413971403 1024
FelipeVR 0:f1a413971403 1025 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
FelipeVR 0:f1a413971403 1026 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
FelipeVR 0:f1a413971403 1027
FelipeVR 0:f1a413971403 1028 /*@}*/ /* end of group CMSIS_TPI */
FelipeVR 0:f1a413971403 1029
FelipeVR 0:f1a413971403 1030
FelipeVR 0:f1a413971403 1031 #if (__MPU_PRESENT == 1)
FelipeVR 0:f1a413971403 1032 /** \ingroup CMSIS_core_register
FelipeVR 0:f1a413971403 1033 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
FelipeVR 0:f1a413971403 1034 \brief Type definitions for the Memory Protection Unit (MPU)
FelipeVR 0:f1a413971403 1035 @{
FelipeVR 0:f1a413971403 1036 */
FelipeVR 0:f1a413971403 1037
FelipeVR 0:f1a413971403 1038 /** \brief Structure type to access the Memory Protection Unit (MPU).
FelipeVR 0:f1a413971403 1039 */
FelipeVR 0:f1a413971403 1040 typedef struct
FelipeVR 0:f1a413971403 1041 {
FelipeVR 0:f1a413971403 1042 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
FelipeVR 0:f1a413971403 1043 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
FelipeVR 0:f1a413971403 1044 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
FelipeVR 0:f1a413971403 1045 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
FelipeVR 0:f1a413971403 1046 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
FelipeVR 0:f1a413971403 1047 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
FelipeVR 0:f1a413971403 1048 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
FelipeVR 0:f1a413971403 1049 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
FelipeVR 0:f1a413971403 1050 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
FelipeVR 0:f1a413971403 1051 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
FelipeVR 0:f1a413971403 1052 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
FelipeVR 0:f1a413971403 1053 } MPU_Type;
FelipeVR 0:f1a413971403 1054
FelipeVR 0:f1a413971403 1055 /* MPU Type Register */
FelipeVR 0:f1a413971403 1056 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
FelipeVR 0:f1a413971403 1057 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
FelipeVR 0:f1a413971403 1058
FelipeVR 0:f1a413971403 1059 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
FelipeVR 0:f1a413971403 1060 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
FelipeVR 0:f1a413971403 1061
FelipeVR 0:f1a413971403 1062 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
FelipeVR 0:f1a413971403 1063 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
FelipeVR 0:f1a413971403 1064
FelipeVR 0:f1a413971403 1065 /* MPU Control Register */
FelipeVR 0:f1a413971403 1066 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
FelipeVR 0:f1a413971403 1067 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
FelipeVR 0:f1a413971403 1068
FelipeVR 0:f1a413971403 1069 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
FelipeVR 0:f1a413971403 1070 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
FelipeVR 0:f1a413971403 1071
FelipeVR 0:f1a413971403 1072 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
FelipeVR 0:f1a413971403 1073 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
FelipeVR 0:f1a413971403 1074
FelipeVR 0:f1a413971403 1075 /* MPU Region Number Register */
FelipeVR 0:f1a413971403 1076 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
FelipeVR 0:f1a413971403 1077 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
FelipeVR 0:f1a413971403 1078
FelipeVR 0:f1a413971403 1079 /* MPU Region Base Address Register */
FelipeVR 0:f1a413971403 1080 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
FelipeVR 0:f1a413971403 1081 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
FelipeVR 0:f1a413971403 1082
FelipeVR 0:f1a413971403 1083 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
FelipeVR 0:f1a413971403 1084 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
FelipeVR 0:f1a413971403 1085
FelipeVR 0:f1a413971403 1086 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
FelipeVR 0:f1a413971403 1087 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
FelipeVR 0:f1a413971403 1088
FelipeVR 0:f1a413971403 1089 /* MPU Region Attribute and Size Register */
FelipeVR 0:f1a413971403 1090 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
FelipeVR 0:f1a413971403 1091 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
FelipeVR 0:f1a413971403 1092
FelipeVR 0:f1a413971403 1093 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
FelipeVR 0:f1a413971403 1094 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
FelipeVR 0:f1a413971403 1095
FelipeVR 0:f1a413971403 1096 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
FelipeVR 0:f1a413971403 1097 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
FelipeVR 0:f1a413971403 1098
FelipeVR 0:f1a413971403 1099 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
FelipeVR 0:f1a413971403 1100 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
FelipeVR 0:f1a413971403 1101
FelipeVR 0:f1a413971403 1102 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
FelipeVR 0:f1a413971403 1103 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
FelipeVR 0:f1a413971403 1104
FelipeVR 0:f1a413971403 1105 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
FelipeVR 0:f1a413971403 1106 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
FelipeVR 0:f1a413971403 1107
FelipeVR 0:f1a413971403 1108 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
FelipeVR 0:f1a413971403 1109 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
FelipeVR 0:f1a413971403 1110
FelipeVR 0:f1a413971403 1111 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
FelipeVR 0:f1a413971403 1112 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
FelipeVR 0:f1a413971403 1113
FelipeVR 0:f1a413971403 1114 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
FelipeVR 0:f1a413971403 1115 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
FelipeVR 0:f1a413971403 1116
FelipeVR 0:f1a413971403 1117 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
FelipeVR 0:f1a413971403 1118 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
FelipeVR 0:f1a413971403 1119
FelipeVR 0:f1a413971403 1120 /*@} end of group CMSIS_MPU */
FelipeVR 0:f1a413971403 1121 #endif
FelipeVR 0:f1a413971403 1122
FelipeVR 0:f1a413971403 1123
FelipeVR 0:f1a413971403 1124 /** \ingroup CMSIS_core_register
FelipeVR 0:f1a413971403 1125 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
FelipeVR 0:f1a413971403 1126 \brief Type definitions for the Core Debug Registers
FelipeVR 0:f1a413971403 1127 @{
FelipeVR 0:f1a413971403 1128 */
FelipeVR 0:f1a413971403 1129
FelipeVR 0:f1a413971403 1130 /** \brief Structure type to access the Core Debug Register (CoreDebug).
FelipeVR 0:f1a413971403 1131 */
FelipeVR 0:f1a413971403 1132 typedef struct
FelipeVR 0:f1a413971403 1133 {
FelipeVR 0:f1a413971403 1134 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
FelipeVR 0:f1a413971403 1135 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
FelipeVR 0:f1a413971403 1136 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
FelipeVR 0:f1a413971403 1137 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
FelipeVR 0:f1a413971403 1138 } CoreDebug_Type;
FelipeVR 0:f1a413971403 1139
FelipeVR 0:f1a413971403 1140 /* Debug Halting Control and Status Register */
FelipeVR 0:f1a413971403 1141 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
FelipeVR 0:f1a413971403 1142 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
FelipeVR 0:f1a413971403 1143
FelipeVR 0:f1a413971403 1144 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
FelipeVR 0:f1a413971403 1145 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
FelipeVR 0:f1a413971403 1146
FelipeVR 0:f1a413971403 1147 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
FelipeVR 0:f1a413971403 1148 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
FelipeVR 0:f1a413971403 1149
FelipeVR 0:f1a413971403 1150 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
FelipeVR 0:f1a413971403 1151 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
FelipeVR 0:f1a413971403 1152
FelipeVR 0:f1a413971403 1153 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
FelipeVR 0:f1a413971403 1154 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
FelipeVR 0:f1a413971403 1155
FelipeVR 0:f1a413971403 1156 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
FelipeVR 0:f1a413971403 1157 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
FelipeVR 0:f1a413971403 1158
FelipeVR 0:f1a413971403 1159 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
FelipeVR 0:f1a413971403 1160 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
FelipeVR 0:f1a413971403 1161
FelipeVR 0:f1a413971403 1162 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
FelipeVR 0:f1a413971403 1163 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
FelipeVR 0:f1a413971403 1164
FelipeVR 0:f1a413971403 1165 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
FelipeVR 0:f1a413971403 1166 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
FelipeVR 0:f1a413971403 1167
FelipeVR 0:f1a413971403 1168 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
FelipeVR 0:f1a413971403 1169 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
FelipeVR 0:f1a413971403 1170
FelipeVR 0:f1a413971403 1171 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
FelipeVR 0:f1a413971403 1172 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
FelipeVR 0:f1a413971403 1173
FelipeVR 0:f1a413971403 1174 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
FelipeVR 0:f1a413971403 1175 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
FelipeVR 0:f1a413971403 1176
FelipeVR 0:f1a413971403 1177 /* Debug Core Register Selector Register */
FelipeVR 0:f1a413971403 1178 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
FelipeVR 0:f1a413971403 1179 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
FelipeVR 0:f1a413971403 1180
FelipeVR 0:f1a413971403 1181 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
FelipeVR 0:f1a413971403 1182 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
FelipeVR 0:f1a413971403 1183
FelipeVR 0:f1a413971403 1184 /* Debug Exception and Monitor Control Register */
FelipeVR 0:f1a413971403 1185 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
FelipeVR 0:f1a413971403 1186 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
FelipeVR 0:f1a413971403 1187
FelipeVR 0:f1a413971403 1188 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
FelipeVR 0:f1a413971403 1189 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
FelipeVR 0:f1a413971403 1190
FelipeVR 0:f1a413971403 1191 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
FelipeVR 0:f1a413971403 1192 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
FelipeVR 0:f1a413971403 1193
FelipeVR 0:f1a413971403 1194 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
FelipeVR 0:f1a413971403 1195 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
FelipeVR 0:f1a413971403 1196
FelipeVR 0:f1a413971403 1197 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
FelipeVR 0:f1a413971403 1198 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
FelipeVR 0:f1a413971403 1199
FelipeVR 0:f1a413971403 1200 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
FelipeVR 0:f1a413971403 1201 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
FelipeVR 0:f1a413971403 1202
FelipeVR 0:f1a413971403 1203 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
FelipeVR 0:f1a413971403 1204 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
FelipeVR 0:f1a413971403 1205
FelipeVR 0:f1a413971403 1206 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
FelipeVR 0:f1a413971403 1207 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
FelipeVR 0:f1a413971403 1208
FelipeVR 0:f1a413971403 1209 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
FelipeVR 0:f1a413971403 1210 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
FelipeVR 0:f1a413971403 1211
FelipeVR 0:f1a413971403 1212 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
FelipeVR 0:f1a413971403 1213 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
FelipeVR 0:f1a413971403 1214
FelipeVR 0:f1a413971403 1215 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
FelipeVR 0:f1a413971403 1216 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
FelipeVR 0:f1a413971403 1217
FelipeVR 0:f1a413971403 1218 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
FelipeVR 0:f1a413971403 1219 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
FelipeVR 0:f1a413971403 1220
FelipeVR 0:f1a413971403 1221 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
FelipeVR 0:f1a413971403 1222 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
FelipeVR 0:f1a413971403 1223
FelipeVR 0:f1a413971403 1224 /*@} end of group CMSIS_CoreDebug */
FelipeVR 0:f1a413971403 1225
FelipeVR 0:f1a413971403 1226
FelipeVR 0:f1a413971403 1227 /** \ingroup CMSIS_core_register
FelipeVR 0:f1a413971403 1228 \defgroup CMSIS_core_base Core Definitions
FelipeVR 0:f1a413971403 1229 \brief Definitions for base addresses, unions, and structures.
FelipeVR 0:f1a413971403 1230 @{
FelipeVR 0:f1a413971403 1231 */
FelipeVR 0:f1a413971403 1232
FelipeVR 0:f1a413971403 1233 /* Memory mapping of Cortex-M3 Hardware */
FelipeVR 0:f1a413971403 1234 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
FelipeVR 0:f1a413971403 1235 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
FelipeVR 0:f1a413971403 1236 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
FelipeVR 0:f1a413971403 1237 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
FelipeVR 0:f1a413971403 1238 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
FelipeVR 0:f1a413971403 1239 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
FelipeVR 0:f1a413971403 1240 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
FelipeVR 0:f1a413971403 1241 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
FelipeVR 0:f1a413971403 1242
FelipeVR 0:f1a413971403 1243 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
FelipeVR 0:f1a413971403 1244 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
FelipeVR 0:f1a413971403 1245 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
FelipeVR 0:f1a413971403 1246 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
FelipeVR 0:f1a413971403 1247 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
FelipeVR 0:f1a413971403 1248 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
FelipeVR 0:f1a413971403 1249 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
FelipeVR 0:f1a413971403 1250 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
FelipeVR 0:f1a413971403 1251
FelipeVR 0:f1a413971403 1252 #if (__MPU_PRESENT == 1)
FelipeVR 0:f1a413971403 1253 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
FelipeVR 0:f1a413971403 1254 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
FelipeVR 0:f1a413971403 1255 #endif
FelipeVR 0:f1a413971403 1256
FelipeVR 0:f1a413971403 1257 /*@} */
FelipeVR 0:f1a413971403 1258
FelipeVR 0:f1a413971403 1259
FelipeVR 0:f1a413971403 1260
FelipeVR 0:f1a413971403 1261 /*******************************************************************************
FelipeVR 0:f1a413971403 1262 * Hardware Abstraction Layer
FelipeVR 0:f1a413971403 1263 Core Function Interface contains:
FelipeVR 0:f1a413971403 1264 - Core NVIC Functions
FelipeVR 0:f1a413971403 1265 - Core SysTick Functions
FelipeVR 0:f1a413971403 1266 - Core Debug Functions
FelipeVR 0:f1a413971403 1267 - Core Register Access Functions
FelipeVR 0:f1a413971403 1268 ******************************************************************************/
FelipeVR 0:f1a413971403 1269 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
FelipeVR 0:f1a413971403 1270 */
FelipeVR 0:f1a413971403 1271
FelipeVR 0:f1a413971403 1272
FelipeVR 0:f1a413971403 1273
FelipeVR 0:f1a413971403 1274 /* ########################## NVIC functions #################################### */
FelipeVR 0:f1a413971403 1275 /** \ingroup CMSIS_Core_FunctionInterface
FelipeVR 0:f1a413971403 1276 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
FelipeVR 0:f1a413971403 1277 \brief Functions that manage interrupts and exceptions via the NVIC.
FelipeVR 0:f1a413971403 1278 @{
FelipeVR 0:f1a413971403 1279 */
FelipeVR 0:f1a413971403 1280
FelipeVR 0:f1a413971403 1281 /** \brief Set Priority Grouping
FelipeVR 0:f1a413971403 1282
FelipeVR 0:f1a413971403 1283 The function sets the priority grouping field using the required unlock sequence.
FelipeVR 0:f1a413971403 1284 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
FelipeVR 0:f1a413971403 1285 Only values from 0..7 are used.
FelipeVR 0:f1a413971403 1286 In case of a conflict between priority grouping and available
FelipeVR 0:f1a413971403 1287 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
FelipeVR 0:f1a413971403 1288
FelipeVR 0:f1a413971403 1289 \param [in] PriorityGroup Priority grouping field.
FelipeVR 0:f1a413971403 1290 */
FelipeVR 0:f1a413971403 1291 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
FelipeVR 0:f1a413971403 1292 {
FelipeVR 0:f1a413971403 1293 uint32_t reg_value;
FelipeVR 0:f1a413971403 1294 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
FelipeVR 0:f1a413971403 1295
FelipeVR 0:f1a413971403 1296 reg_value = SCB->AIRCR; /* read old register configuration */
FelipeVR 0:f1a413971403 1297 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
FelipeVR 0:f1a413971403 1298 reg_value = (reg_value |
FelipeVR 0:f1a413971403 1299 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
FelipeVR 0:f1a413971403 1300 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
FelipeVR 0:f1a413971403 1301 SCB->AIRCR = reg_value;
FelipeVR 0:f1a413971403 1302 }
FelipeVR 0:f1a413971403 1303
FelipeVR 0:f1a413971403 1304
FelipeVR 0:f1a413971403 1305 /** \brief Get Priority Grouping
FelipeVR 0:f1a413971403 1306
FelipeVR 0:f1a413971403 1307 The function reads the priority grouping field from the NVIC Interrupt Controller.
FelipeVR 0:f1a413971403 1308
FelipeVR 0:f1a413971403 1309 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
FelipeVR 0:f1a413971403 1310 */
FelipeVR 0:f1a413971403 1311 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
FelipeVR 0:f1a413971403 1312 {
FelipeVR 0:f1a413971403 1313 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
FelipeVR 0:f1a413971403 1314 }
FelipeVR 0:f1a413971403 1315
FelipeVR 0:f1a413971403 1316
FelipeVR 0:f1a413971403 1317 /** \brief Enable External Interrupt
FelipeVR 0:f1a413971403 1318
FelipeVR 0:f1a413971403 1319 The function enables a device-specific interrupt in the NVIC interrupt controller.
FelipeVR 0:f1a413971403 1320
FelipeVR 0:f1a413971403 1321 \param [in] IRQn External interrupt number. Value cannot be negative.
FelipeVR 0:f1a413971403 1322 */
FelipeVR 0:f1a413971403 1323 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
FelipeVR 0:f1a413971403 1324 {
FelipeVR 0:f1a413971403 1325 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
FelipeVR 0:f1a413971403 1326 }
FelipeVR 0:f1a413971403 1327
FelipeVR 0:f1a413971403 1328
FelipeVR 0:f1a413971403 1329 /** \brief Disable External Interrupt
FelipeVR 0:f1a413971403 1330
FelipeVR 0:f1a413971403 1331 The function disables a device-specific interrupt in the NVIC interrupt controller.
FelipeVR 0:f1a413971403 1332
FelipeVR 0:f1a413971403 1333 \param [in] IRQn External interrupt number. Value cannot be negative.
FelipeVR 0:f1a413971403 1334 */
FelipeVR 0:f1a413971403 1335 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
FelipeVR 0:f1a413971403 1336 {
FelipeVR 0:f1a413971403 1337 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
FelipeVR 0:f1a413971403 1338 }
FelipeVR 0:f1a413971403 1339
FelipeVR 0:f1a413971403 1340
FelipeVR 0:f1a413971403 1341 /** \brief Get Pending Interrupt
FelipeVR 0:f1a413971403 1342
FelipeVR 0:f1a413971403 1343 The function reads the pending register in the NVIC and returns the pending bit
FelipeVR 0:f1a413971403 1344 for the specified interrupt.
FelipeVR 0:f1a413971403 1345
FelipeVR 0:f1a413971403 1346 \param [in] IRQn Interrupt number.
FelipeVR 0:f1a413971403 1347
FelipeVR 0:f1a413971403 1348 \return 0 Interrupt status is not pending.
FelipeVR 0:f1a413971403 1349 \return 1 Interrupt status is pending.
FelipeVR 0:f1a413971403 1350 */
FelipeVR 0:f1a413971403 1351 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
FelipeVR 0:f1a413971403 1352 {
FelipeVR 0:f1a413971403 1353 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
FelipeVR 0:f1a413971403 1354 }
FelipeVR 0:f1a413971403 1355
FelipeVR 0:f1a413971403 1356
FelipeVR 0:f1a413971403 1357 /** \brief Set Pending Interrupt
FelipeVR 0:f1a413971403 1358
FelipeVR 0:f1a413971403 1359 The function sets the pending bit of an external interrupt.
FelipeVR 0:f1a413971403 1360
FelipeVR 0:f1a413971403 1361 \param [in] IRQn Interrupt number. Value cannot be negative.
FelipeVR 0:f1a413971403 1362 */
FelipeVR 0:f1a413971403 1363 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
FelipeVR 0:f1a413971403 1364 {
FelipeVR 0:f1a413971403 1365 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
FelipeVR 0:f1a413971403 1366 }
FelipeVR 0:f1a413971403 1367
FelipeVR 0:f1a413971403 1368
FelipeVR 0:f1a413971403 1369 /** \brief Clear Pending Interrupt
FelipeVR 0:f1a413971403 1370
FelipeVR 0:f1a413971403 1371 The function clears the pending bit of an external interrupt.
FelipeVR 0:f1a413971403 1372
FelipeVR 0:f1a413971403 1373 \param [in] IRQn External interrupt number. Value cannot be negative.
FelipeVR 0:f1a413971403 1374 */
FelipeVR 0:f1a413971403 1375 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
FelipeVR 0:f1a413971403 1376 {
FelipeVR 0:f1a413971403 1377 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
FelipeVR 0:f1a413971403 1378 }
FelipeVR 0:f1a413971403 1379
FelipeVR 0:f1a413971403 1380
FelipeVR 0:f1a413971403 1381 /** \brief Get Active Interrupt
FelipeVR 0:f1a413971403 1382
FelipeVR 0:f1a413971403 1383 The function reads the active register in NVIC and returns the active bit.
FelipeVR 0:f1a413971403 1384
FelipeVR 0:f1a413971403 1385 \param [in] IRQn Interrupt number.
FelipeVR 0:f1a413971403 1386
FelipeVR 0:f1a413971403 1387 \return 0 Interrupt status is not active.
FelipeVR 0:f1a413971403 1388 \return 1 Interrupt status is active.
FelipeVR 0:f1a413971403 1389 */
FelipeVR 0:f1a413971403 1390 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
FelipeVR 0:f1a413971403 1391 {
FelipeVR 0:f1a413971403 1392 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
FelipeVR 0:f1a413971403 1393 }
FelipeVR 0:f1a413971403 1394
FelipeVR 0:f1a413971403 1395
FelipeVR 0:f1a413971403 1396 /** \brief Set Interrupt Priority
FelipeVR 0:f1a413971403 1397
FelipeVR 0:f1a413971403 1398 The function sets the priority of an interrupt.
FelipeVR 0:f1a413971403 1399
FelipeVR 0:f1a413971403 1400 \note The priority cannot be set for every core interrupt.
FelipeVR 0:f1a413971403 1401
FelipeVR 0:f1a413971403 1402 \param [in] IRQn Interrupt number.
FelipeVR 0:f1a413971403 1403 \param [in] priority Priority to set.
FelipeVR 0:f1a413971403 1404 */
FelipeVR 0:f1a413971403 1405 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
FelipeVR 0:f1a413971403 1406 {
FelipeVR 0:f1a413971403 1407 if(IRQn < 0) {
FelipeVR 0:f1a413971403 1408 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
FelipeVR 0:f1a413971403 1409 else {
FelipeVR 0:f1a413971403 1410 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
FelipeVR 0:f1a413971403 1411 }
FelipeVR 0:f1a413971403 1412
FelipeVR 0:f1a413971403 1413
FelipeVR 0:f1a413971403 1414 /** \brief Get Interrupt Priority
FelipeVR 0:f1a413971403 1415
FelipeVR 0:f1a413971403 1416 The function reads the priority of an interrupt. The interrupt
FelipeVR 0:f1a413971403 1417 number can be positive to specify an external (device specific)
FelipeVR 0:f1a413971403 1418 interrupt, or negative to specify an internal (core) interrupt.
FelipeVR 0:f1a413971403 1419
FelipeVR 0:f1a413971403 1420
FelipeVR 0:f1a413971403 1421 \param [in] IRQn Interrupt number.
FelipeVR 0:f1a413971403 1422 \return Interrupt Priority. Value is aligned automatically to the implemented
FelipeVR 0:f1a413971403 1423 priority bits of the microcontroller.
FelipeVR 0:f1a413971403 1424 */
FelipeVR 0:f1a413971403 1425 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
FelipeVR 0:f1a413971403 1426 {
FelipeVR 0:f1a413971403 1427
FelipeVR 0:f1a413971403 1428 if(IRQn < 0) {
FelipeVR 0:f1a413971403 1429 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
FelipeVR 0:f1a413971403 1430 else {
FelipeVR 0:f1a413971403 1431 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
FelipeVR 0:f1a413971403 1432 }
FelipeVR 0:f1a413971403 1433
FelipeVR 0:f1a413971403 1434
FelipeVR 0:f1a413971403 1435 /** \brief Encode Priority
FelipeVR 0:f1a413971403 1436
FelipeVR 0:f1a413971403 1437 The function encodes the priority for an interrupt with the given priority group,
FelipeVR 0:f1a413971403 1438 preemptive priority value, and subpriority value.
FelipeVR 0:f1a413971403 1439 In case of a conflict between priority grouping and available
FelipeVR 0:f1a413971403 1440 priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
FelipeVR 0:f1a413971403 1441
FelipeVR 0:f1a413971403 1442 \param [in] PriorityGroup Used priority group.
FelipeVR 0:f1a413971403 1443 \param [in] PreemptPriority Preemptive priority value (starting from 0).
FelipeVR 0:f1a413971403 1444 \param [in] SubPriority Subpriority value (starting from 0).
FelipeVR 0:f1a413971403 1445 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
FelipeVR 0:f1a413971403 1446 */
FelipeVR 0:f1a413971403 1447 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
FelipeVR 0:f1a413971403 1448 {
FelipeVR 0:f1a413971403 1449 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
FelipeVR 0:f1a413971403 1450 uint32_t PreemptPriorityBits;
FelipeVR 0:f1a413971403 1451 uint32_t SubPriorityBits;
FelipeVR 0:f1a413971403 1452
FelipeVR 0:f1a413971403 1453 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
FelipeVR 0:f1a413971403 1454 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
FelipeVR 0:f1a413971403 1455
FelipeVR 0:f1a413971403 1456 return (
FelipeVR 0:f1a413971403 1457 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
FelipeVR 0:f1a413971403 1458 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
FelipeVR 0:f1a413971403 1459 );
FelipeVR 0:f1a413971403 1460 }
FelipeVR 0:f1a413971403 1461
FelipeVR 0:f1a413971403 1462
FelipeVR 0:f1a413971403 1463 /** \brief Decode Priority
FelipeVR 0:f1a413971403 1464
FelipeVR 0:f1a413971403 1465 The function decodes an interrupt priority value with a given priority group to
FelipeVR 0:f1a413971403 1466 preemptive priority value and subpriority value.
FelipeVR 0:f1a413971403 1467 In case of a conflict between priority grouping and available
FelipeVR 0:f1a413971403 1468 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
FelipeVR 0:f1a413971403 1469
FelipeVR 0:f1a413971403 1470 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
FelipeVR 0:f1a413971403 1471 \param [in] PriorityGroup Used priority group.
FelipeVR 0:f1a413971403 1472 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
FelipeVR 0:f1a413971403 1473 \param [out] pSubPriority Subpriority value (starting from 0).
FelipeVR 0:f1a413971403 1474 */
FelipeVR 0:f1a413971403 1475 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
FelipeVR 0:f1a413971403 1476 {
FelipeVR 0:f1a413971403 1477 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
FelipeVR 0:f1a413971403 1478 uint32_t PreemptPriorityBits;
FelipeVR 0:f1a413971403 1479 uint32_t SubPriorityBits;
FelipeVR 0:f1a413971403 1480
FelipeVR 0:f1a413971403 1481 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
FelipeVR 0:f1a413971403 1482 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
FelipeVR 0:f1a413971403 1483
FelipeVR 0:f1a413971403 1484 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
FelipeVR 0:f1a413971403 1485 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
FelipeVR 0:f1a413971403 1486 }
FelipeVR 0:f1a413971403 1487
FelipeVR 0:f1a413971403 1488
FelipeVR 0:f1a413971403 1489 /** \brief System Reset
FelipeVR 0:f1a413971403 1490
FelipeVR 0:f1a413971403 1491 The function initiates a system reset request to reset the MCU.
FelipeVR 0:f1a413971403 1492 */
FelipeVR 0:f1a413971403 1493 __STATIC_INLINE void NVIC_SystemReset(void)
FelipeVR 0:f1a413971403 1494 {
FelipeVR 0:f1a413971403 1495 __DSB(); /* Ensure all outstanding memory accesses included
FelipeVR 0:f1a413971403 1496 buffered write are completed before reset */
FelipeVR 0:f1a413971403 1497 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
FelipeVR 0:f1a413971403 1498 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
FelipeVR 0:f1a413971403 1499 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
FelipeVR 0:f1a413971403 1500 __DSB(); /* Ensure completion of memory access */
FelipeVR 0:f1a413971403 1501 while(1); /* wait until reset */
FelipeVR 0:f1a413971403 1502 }
FelipeVR 0:f1a413971403 1503
FelipeVR 0:f1a413971403 1504 /*@} end of CMSIS_Core_NVICFunctions */
FelipeVR 0:f1a413971403 1505
FelipeVR 0:f1a413971403 1506
FelipeVR 0:f1a413971403 1507
FelipeVR 0:f1a413971403 1508 /* ################################## SysTick function ############################################ */
FelipeVR 0:f1a413971403 1509 /** \ingroup CMSIS_Core_FunctionInterface
FelipeVR 0:f1a413971403 1510 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
FelipeVR 0:f1a413971403 1511 \brief Functions that configure the System.
FelipeVR 0:f1a413971403 1512 @{
FelipeVR 0:f1a413971403 1513 */
FelipeVR 0:f1a413971403 1514
FelipeVR 0:f1a413971403 1515 #if (__Vendor_SysTickConfig == 0)
FelipeVR 0:f1a413971403 1516
FelipeVR 0:f1a413971403 1517 /** \brief System Tick Configuration
FelipeVR 0:f1a413971403 1518
FelipeVR 0:f1a413971403 1519 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
FelipeVR 0:f1a413971403 1520 Counter is in free running mode to generate periodic interrupts.
FelipeVR 0:f1a413971403 1521
FelipeVR 0:f1a413971403 1522 \param [in] ticks Number of ticks between two interrupts.
FelipeVR 0:f1a413971403 1523
FelipeVR 0:f1a413971403 1524 \return 0 Function succeeded.
FelipeVR 0:f1a413971403 1525 \return 1 Function failed.
FelipeVR 0:f1a413971403 1526
FelipeVR 0:f1a413971403 1527 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
FelipeVR 0:f1a413971403 1528 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
FelipeVR 0:f1a413971403 1529 must contain a vendor-specific implementation of this function.
FelipeVR 0:f1a413971403 1530
FelipeVR 0:f1a413971403 1531 */
FelipeVR 0:f1a413971403 1532 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
FelipeVR 0:f1a413971403 1533 {
FelipeVR 0:f1a413971403 1534 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
FelipeVR 0:f1a413971403 1535
FelipeVR 0:f1a413971403 1536 SysTick->LOAD = ticks - 1; /* set reload register */
FelipeVR 0:f1a413971403 1537 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
FelipeVR 0:f1a413971403 1538 SysTick->VAL = 0; /* Load the SysTick Counter Value */
FelipeVR 0:f1a413971403 1539 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
FelipeVR 0:f1a413971403 1540 SysTick_CTRL_TICKINT_Msk |
FelipeVR 0:f1a413971403 1541 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
FelipeVR 0:f1a413971403 1542 return (0); /* Function successful */
FelipeVR 0:f1a413971403 1543 }
FelipeVR 0:f1a413971403 1544
FelipeVR 0:f1a413971403 1545 #endif
FelipeVR 0:f1a413971403 1546
FelipeVR 0:f1a413971403 1547 /*@} end of CMSIS_Core_SysTickFunctions */
FelipeVR 0:f1a413971403 1548
FelipeVR 0:f1a413971403 1549
FelipeVR 0:f1a413971403 1550
FelipeVR 0:f1a413971403 1551 /* ##################################### Debug In/Output function ########################################### */
FelipeVR 0:f1a413971403 1552 /** \ingroup CMSIS_Core_FunctionInterface
FelipeVR 0:f1a413971403 1553 \defgroup CMSIS_core_DebugFunctions ITM Functions
FelipeVR 0:f1a413971403 1554 \brief Functions that access the ITM debug interface.
FelipeVR 0:f1a413971403 1555 @{
FelipeVR 0:f1a413971403 1556 */
FelipeVR 0:f1a413971403 1557
FelipeVR 0:f1a413971403 1558 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
FelipeVR 0:f1a413971403 1559 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
FelipeVR 0:f1a413971403 1560
FelipeVR 0:f1a413971403 1561
FelipeVR 0:f1a413971403 1562 /** \brief ITM Send Character
FelipeVR 0:f1a413971403 1563
FelipeVR 0:f1a413971403 1564 The function transmits a character via the ITM channel 0, and
FelipeVR 0:f1a413971403 1565 \li Just returns when no debugger is connected that has booked the output.
FelipeVR 0:f1a413971403 1566 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
FelipeVR 0:f1a413971403 1567
FelipeVR 0:f1a413971403 1568 \param [in] ch Character to transmit.
FelipeVR 0:f1a413971403 1569
FelipeVR 0:f1a413971403 1570 \returns Character to transmit.
FelipeVR 0:f1a413971403 1571 */
FelipeVR 0:f1a413971403 1572 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
FelipeVR 0:f1a413971403 1573 {
FelipeVR 0:f1a413971403 1574 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
FelipeVR 0:f1a413971403 1575 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
FelipeVR 0:f1a413971403 1576 {
FelipeVR 0:f1a413971403 1577 while (ITM->PORT[0].u32 == 0);
FelipeVR 0:f1a413971403 1578 ITM->PORT[0].u8 = (uint8_t) ch;
FelipeVR 0:f1a413971403 1579 }
FelipeVR 0:f1a413971403 1580 return (ch);
FelipeVR 0:f1a413971403 1581 }
FelipeVR 0:f1a413971403 1582
FelipeVR 0:f1a413971403 1583
FelipeVR 0:f1a413971403 1584 /** \brief ITM Receive Character
FelipeVR 0:f1a413971403 1585
FelipeVR 0:f1a413971403 1586 The function inputs a character via the external variable \ref ITM_RxBuffer.
FelipeVR 0:f1a413971403 1587
FelipeVR 0:f1a413971403 1588 \return Received character.
FelipeVR 0:f1a413971403 1589 \return -1 No character pending.
FelipeVR 0:f1a413971403 1590 */
FelipeVR 0:f1a413971403 1591 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
FelipeVR 0:f1a413971403 1592 int32_t ch = -1; /* no character available */
FelipeVR 0:f1a413971403 1593
FelipeVR 0:f1a413971403 1594 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
FelipeVR 0:f1a413971403 1595 ch = ITM_RxBuffer;
FelipeVR 0:f1a413971403 1596 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
FelipeVR 0:f1a413971403 1597 }
FelipeVR 0:f1a413971403 1598
FelipeVR 0:f1a413971403 1599 return (ch);
FelipeVR 0:f1a413971403 1600 }
FelipeVR 0:f1a413971403 1601
FelipeVR 0:f1a413971403 1602
FelipeVR 0:f1a413971403 1603 /** \brief ITM Check Character
FelipeVR 0:f1a413971403 1604
FelipeVR 0:f1a413971403 1605 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
FelipeVR 0:f1a413971403 1606
FelipeVR 0:f1a413971403 1607 \return 0 No character available.
FelipeVR 0:f1a413971403 1608 \return 1 Character available.
FelipeVR 0:f1a413971403 1609 */
FelipeVR 0:f1a413971403 1610 __STATIC_INLINE int32_t ITM_CheckChar (void) {
FelipeVR 0:f1a413971403 1611
FelipeVR 0:f1a413971403 1612 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
FelipeVR 0:f1a413971403 1613 return (0); /* no character available */
FelipeVR 0:f1a413971403 1614 } else {
FelipeVR 0:f1a413971403 1615 return (1); /* character available */
FelipeVR 0:f1a413971403 1616 }
FelipeVR 0:f1a413971403 1617 }
FelipeVR 0:f1a413971403 1618
FelipeVR 0:f1a413971403 1619 /*@} end of CMSIS_core_DebugFunctions */
FelipeVR 0:f1a413971403 1620
FelipeVR 0:f1a413971403 1621 #endif /* __CORE_CM3_H_DEPENDANT */
FelipeVR 0:f1a413971403 1622
FelipeVR 0:f1a413971403 1623 #endif /* __CMSIS_GENERIC */
FelipeVR 0:f1a413971403 1624
FelipeVR 0:f1a413971403 1625 #ifdef __cplusplus
FelipeVR 0:f1a413971403 1626 }
FelipeVR 0:f1a413971403 1627 #endif