Felipe Velazquez / SMARTES_lib

SMARTEST lib for MPS2

Dependents:   MSP2_LCD_HOLA

CMSDK_CM3.h@0:f1a413971403, 2018-08-23 (annotated)

Committer:
FelipeVR
Date:
Thu Aug 23 13:39:38 2018 +0000
Revision:
0:f1a413971403
SMARTEST LCD

Who changed what in which revision?

UserRevisionLine numberNew contents of line
FelipeVR 0:f1a413971403 1 /**************************************************************************//**
FelipeVR 0:f1a413971403 2 * @file CMSDK_CM3.h
FelipeVR 0:f1a413971403 3 * @brief CMSIS Core Peripheral Access Layer Header File for
FelipeVR 0:f1a413971403 4 * CMSDK_CM3 Device
FelipeVR 0:f1a413971403 5 * @version V3.02
FelipeVR 0:f1a413971403 6 * @date 15. November 2013
FelipeVR 0:f1a413971403 7 *
FelipeVR 0:f1a413971403 8 * @note
FelipeVR 0:f1a413971403 9 *
FelipeVR 0:f1a413971403 10 ******************************************************************************/
FelipeVR 0:f1a413971403 11 /* Copyright (c) 2011 - 2013 ARM LIMITED
FelipeVR 0:f1a413971403 12
FelipeVR 0:f1a413971403 13 All rights reserved.
FelipeVR 0:f1a413971403 14 Redistribution and use in source and binary forms, with or without
FelipeVR 0:f1a413971403 15 modification, are permitted provided that the following conditions are met:
FelipeVR 0:f1a413971403 16 - Redistributions of source code must retain the above copyright
FelipeVR 0:f1a413971403 17 notice, this list of conditions and the following disclaimer.
FelipeVR 0:f1a413971403 18 - Redistributions in binary form must reproduce the above copyright
FelipeVR 0:f1a413971403 19 notice, this list of conditions and the following disclaimer in the
FelipeVR 0:f1a413971403 20 documentation and/or other materials provided with the distribution.
FelipeVR 0:f1a413971403 21 - Neither the name of ARM nor the names of its contributors may be used
FelipeVR 0:f1a413971403 22 to endorse or promote products derived from this software without
FelipeVR 0:f1a413971403 23 specific prior written permission.
FelipeVR 0:f1a413971403 24 *
FelipeVR 0:f1a413971403 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
FelipeVR 0:f1a413971403 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
FelipeVR 0:f1a413971403 27 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
FelipeVR 0:f1a413971403 28 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
FelipeVR 0:f1a413971403 29 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
FelipeVR 0:f1a413971403 30 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
FelipeVR 0:f1a413971403 31 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
FelipeVR 0:f1a413971403 32 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
FelipeVR 0:f1a413971403 33 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
FelipeVR 0:f1a413971403 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
FelipeVR 0:f1a413971403 35 POSSIBILITY OF SUCH DAMAGE.
FelipeVR 0:f1a413971403 36 ---------------------------------------------------------------------------*/
FelipeVR 0:f1a413971403 37
FelipeVR 0:f1a413971403 38
FelipeVR 0:f1a413971403 39 #ifndef CMSDK_CM3_H
FelipeVR 0:f1a413971403 40 #define CMSDK_CM3_H
FelipeVR 0:f1a413971403 41
FelipeVR 0:f1a413971403 42 #ifdef __cplusplus
FelipeVR 0:f1a413971403 43 extern "C" {
FelipeVR 0:f1a413971403 44 #endif
FelipeVR 0:f1a413971403 45
FelipeVR 0:f1a413971403 46
FelipeVR 0:f1a413971403 47 /* ------------------------- Interrupt Number Definition ------------------------ */
FelipeVR 0:f1a413971403 48
FelipeVR 0:f1a413971403 49 typedef enum IRQn
FelipeVR 0:f1a413971403 50 {
FelipeVR 0:f1a413971403 51 /* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
FelipeVR 0:f1a413971403 52 NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
FelipeVR 0:f1a413971403 53 HardFault_IRQn = -13, /* 3 HardFault Interrupt */
FelipeVR 0:f1a413971403 54 MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
FelipeVR 0:f1a413971403 55 BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
FelipeVR 0:f1a413971403 56 UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
FelipeVR 0:f1a413971403 57 SVCall_IRQn = -5, /* 11 SV Call Interrupt */
FelipeVR 0:f1a413971403 58 DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
FelipeVR 0:f1a413971403 59 PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
FelipeVR 0:f1a413971403 60 SysTick_IRQn = -1, /* 15 System Tick Interrupt */
FelipeVR 0:f1a413971403 61
FelipeVR 0:f1a413971403 62 /* ---------------------- CMSDK_CM3 Specific Interrupt Numbers ------------------ */
FelipeVR 0:f1a413971403 63 UART0_IRQn = 0, /* UART 0 RX and TX Combined Interrupt */
FelipeVR 0:f1a413971403 64 Spare_IRQn = 1, /* Undefined */
FelipeVR 0:f1a413971403 65 UART1_IRQn = 2, /* UART 1 RX and TX Combined Interrupt */
FelipeVR 0:f1a413971403 66 I2C0_IRQn = 3, /* I2C 0 Interrupt */
FelipeVR 0:f1a413971403 67 I2C1_IRQn = 4, /* I2C 1 Interrupt */
FelipeVR 0:f1a413971403 68 RTC_IRQn = 5, /* RTC Interrupt */
FelipeVR 0:f1a413971403 69 PORT0_ALL_IRQn = 6, /* GPIO Port 0 combined Interrupt */
FelipeVR 0:f1a413971403 70 PORT1_ALL_IRQn = 7, /* GPIO Port 1 combined Interrupt */
FelipeVR 0:f1a413971403 71 TIMER0_IRQn = 8, /* TIMER 0 Interrupt */
FelipeVR 0:f1a413971403 72 TIMER1_IRQn = 9, /* TIMER 1 Interrupt */
FelipeVR 0:f1a413971403 73 DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */
FelipeVR 0:f1a413971403 74 SPI0_IRQn = 11, /* SPI 0 Interrupt */
FelipeVR 0:f1a413971403 75 UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */
FelipeVR 0:f1a413971403 76 SPI1_IRQn = 13, /* SPI 1 Interrupt */
FelipeVR 0:f1a413971403 77 QSPI_IRQn = 14, /* QUAD SPI Interrupt */
FelipeVR 0:f1a413971403 78 TSC_IRQn = 15, /* Touch Screen Interrupt */
FelipeVR 0:f1a413971403 79 PORT01_0_IRQn = 16, /* All P0 and P1I/O pins used as irq source */
FelipeVR 0:f1a413971403 80 PORT01_1_IRQn = 17, /* There are 16 pins in total */
FelipeVR 0:f1a413971403 81 PORT01_2_IRQn = 18,
FelipeVR 0:f1a413971403 82 PORT01_3_IRQn = 19,
FelipeVR 0:f1a413971403 83 PORT01_4_IRQn = 20,
FelipeVR 0:f1a413971403 84 PORT01_5_IRQn = 21,
FelipeVR 0:f1a413971403 85 PORT01_6_IRQn = 22,
FelipeVR 0:f1a413971403 86 PORT01_7_IRQn = 23,
FelipeVR 0:f1a413971403 87 PORT01_8_IRQn = 24,
FelipeVR 0:f1a413971403 88 PORT01_9_IRQn = 25,
FelipeVR 0:f1a413971403 89 PORT01_10_IRQn = 26,
FelipeVR 0:f1a413971403 90 PORT01_11_IRQn = 27,
FelipeVR 0:f1a413971403 91 PORT01_12_IRQn = 28,
FelipeVR 0:f1a413971403 92 PORT01_13_IRQn = 29,
FelipeVR 0:f1a413971403 93 PORT01_14_IRQn = 30,
FelipeVR 0:f1a413971403 94 PORT01_15_IRQn = 31,
FelipeVR 0:f1a413971403 95 SYSERROR_IRQn = 32, /* System Error Interrupt */
FelipeVR 0:f1a413971403 96 EFLASH_IRQn = 33, /* Embedded Flash Interrupt */
FelipeVR 0:f1a413971403 97 CORDIO0_IRQn = 34, /* t.b.a */
FelipeVR 0:f1a413971403 98 CORDIO1_IRQn = 35, /* t.b.a */
FelipeVR 0:f1a413971403 99 CORDIO2_IRQn = 36, /* t.b.a */
FelipeVR 0:f1a413971403 100 CORDIO3_IRQn = 37, /* t.b.a */
FelipeVR 0:f1a413971403 101 CORDIO4_IRQn = 38, /* t.b.a */
FelipeVR 0:f1a413971403 102 CORDIO5_IRQn = 39, /* t.b.a */
FelipeVR 0:f1a413971403 103 CORDIO6_IRQn = 40, /* t.b.a */
FelipeVR 0:f1a413971403 104 CORDIO7_IRQn = 41, /* t.b.a */
FelipeVR 0:f1a413971403 105 PORT2_ALL_IRQn = 42, /* GPIO Port 2 combined Interrupt */
FelipeVR 0:f1a413971403 106 PORT3_ALL_IRQn = 43, /* GPIO Port 3 combined Interrupt */
FelipeVR 0:f1a413971403 107 TRNG_IRQn = 44, /* Random number generator Interrupt */
FelipeVR 0:f1a413971403 108 UART2_IRQn = 45, /* UART 2 RX and TX Combined Interrupt */
FelipeVR 0:f1a413971403 109 UART3_IRQn = 46, /* UART 3 RX and TX Combined Interrupt */
FelipeVR 0:f1a413971403 110 ETHERNET_IRQn = 47, /* Ethernet interrupt t.b.a. */
FelipeVR 0:f1a413971403 111 I2S_IRQn = 48, /* I2S Interrupt */
FelipeVR 0:f1a413971403 112 MPS2_SPI0_IRQn = 49, /* SPI Interrupt (spi header) */
FelipeVR 0:f1a413971403 113 MPS2_SPI1_IRQn = 50, /* SPI Interrupt (clcd) */
FelipeVR 0:f1a413971403 114 MPS2_SPI2_IRQn = 51, /* SPI Interrupt (spi 1 ADC replacement) */
FelipeVR 0:f1a413971403 115 MPS2_SPI3_IRQn = 52, /* SPI Interrupt (spi 0 shield 0 replacement) */
FelipeVR 0:f1a413971403 116 MPS2_SPI4_IRQn = 53 /* SPI Interrupt (shield 1) */
FelipeVR 0:f1a413971403 117 } IRQn_Type;
FelipeVR 0:f1a413971403 118
FelipeVR 0:f1a413971403 119
FelipeVR 0:f1a413971403 120 /* ================================================================================ */
FelipeVR 0:f1a413971403 121 /* ================ Processor and Core Peripheral Section ================ */
FelipeVR 0:f1a413971403 122 /* ================================================================================ */
FelipeVR 0:f1a413971403 123
FelipeVR 0:f1a413971403 124 /* -------- Configuration of the Cortex-M3 Processor and Core Peripherals ------- */
FelipeVR 0:f1a413971403 125 #define __CM3_REV 0x0201 /* Core revision r2p1 */
FelipeVR 0:f1a413971403 126 #define __MPU_PRESENT 1 /* MPU present or not */
FelipeVR 0:f1a413971403 127 #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
FelipeVR 0:f1a413971403 128 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
FelipeVR 0:f1a413971403 129
FelipeVR 0:f1a413971403 130 #include <core_cm3.h> /* Processor and core peripherals */
FelipeVR 0:f1a413971403 131 #include "system_CMSDK_CM3.h" /* System Header */
FelipeVR 0:f1a413971403 132
FelipeVR 0:f1a413971403 133
FelipeVR 0:f1a413971403 134 /* ================================================================================ */
FelipeVR 0:f1a413971403 135 /* ================ Device Specific Peripheral Section ================ */
FelipeVR 0:f1a413971403 136 /* ================================================================================ */
FelipeVR 0:f1a413971403 137
FelipeVR 0:f1a413971403 138 /* ------------------- Start of section using anonymous unions ------------------ */
FelipeVR 0:f1a413971403 139 #if defined ( __CC_ARM )
FelipeVR 0:f1a413971403 140 #pragma push
FelipeVR 0:f1a413971403 141 #pragma anon_unions
FelipeVR 0:f1a413971403 142 #elif defined(__ICCARM__)
FelipeVR 0:f1a413971403 143 #pragma language=extended
FelipeVR 0:f1a413971403 144 #elif defined(__GNUC__)
FelipeVR 0:f1a413971403 145 /* anonymous unions are enabled by default */
FelipeVR 0:f1a413971403 146 #elif defined(__TMS470__)
FelipeVR 0:f1a413971403 147 /* anonymous unions are enabled by default */
FelipeVR 0:f1a413971403 148 #elif defined(__TASKING__)
FelipeVR 0:f1a413971403 149 #pragma warning 586
FelipeVR 0:f1a413971403 150 #else
FelipeVR 0:f1a413971403 151 #warning Not supported compiler type
FelipeVR 0:f1a413971403 152 #endif
FelipeVR 0:f1a413971403 153
FelipeVR 0:f1a413971403 154 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
FelipeVR 0:f1a413971403 155 typedef struct
FelipeVR 0:f1a413971403 156 {
FelipeVR 0:f1a413971403 157 __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
FelipeVR 0:f1a413971403 158 __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
FelipeVR 0:f1a413971403 159 __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
FelipeVR 0:f1a413971403 160 union {
FelipeVR 0:f1a413971403 161 __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
FelipeVR 0:f1a413971403 162 __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
FelipeVR 0:f1a413971403 163 };
FelipeVR 0:f1a413971403 164 __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */
FelipeVR 0:f1a413971403 165
FelipeVR 0:f1a413971403 166 } CMSDK_UART_TypeDef;
FelipeVR 0:f1a413971403 167
FelipeVR 0:f1a413971403 168 /* CMSDK_UART DATA Register Definitions */
FelipeVR 0:f1a413971403 169
FelipeVR 0:f1a413971403 170 #define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */
FelipeVR 0:f1a413971403 171 #define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */
FelipeVR 0:f1a413971403 172
FelipeVR 0:f1a413971403 173 #define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */
FelipeVR 0:f1a413971403 174 #define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */
FelipeVR 0:f1a413971403 175
FelipeVR 0:f1a413971403 176 #define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */
FelipeVR 0:f1a413971403 177 #define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */
FelipeVR 0:f1a413971403 178
FelipeVR 0:f1a413971403 179 #define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */
FelipeVR 0:f1a413971403 180 #define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */
FelipeVR 0:f1a413971403 181
FelipeVR 0:f1a413971403 182 #define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */
FelipeVR 0:f1a413971403 183 #define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */
FelipeVR 0:f1a413971403 184
FelipeVR 0:f1a413971403 185 #define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */
FelipeVR 0:f1a413971403 186 #define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */
FelipeVR 0:f1a413971403 187
FelipeVR 0:f1a413971403 188 #define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */
FelipeVR 0:f1a413971403 189 #define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */
FelipeVR 0:f1a413971403 190
FelipeVR 0:f1a413971403 191 #define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */
FelipeVR 0:f1a413971403 192 #define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */
FelipeVR 0:f1a413971403 193
FelipeVR 0:f1a413971403 194 #define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */
FelipeVR 0:f1a413971403 195 #define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */
FelipeVR 0:f1a413971403 196
FelipeVR 0:f1a413971403 197 #define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */
FelipeVR 0:f1a413971403 198 #define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */
FelipeVR 0:f1a413971403 199
FelipeVR 0:f1a413971403 200 #define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */
FelipeVR 0:f1a413971403 201 #define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */
FelipeVR 0:f1a413971403 202
FelipeVR 0:f1a413971403 203 #define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */
FelipeVR 0:f1a413971403 204 #define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */
FelipeVR 0:f1a413971403 205
FelipeVR 0:f1a413971403 206 #define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */
FelipeVR 0:f1a413971403 207 #define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */
FelipeVR 0:f1a413971403 208
FelipeVR 0:f1a413971403 209 #define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */
FelipeVR 0:f1a413971403 210 #define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */
FelipeVR 0:f1a413971403 211
FelipeVR 0:f1a413971403 212 #define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */
FelipeVR 0:f1a413971403 213 #define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */
FelipeVR 0:f1a413971403 214
FelipeVR 0:f1a413971403 215 #define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */
FelipeVR 0:f1a413971403 216 #define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */
FelipeVR 0:f1a413971403 217
FelipeVR 0:f1a413971403 218 #define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */
FelipeVR 0:f1a413971403 219 #define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */
FelipeVR 0:f1a413971403 220
FelipeVR 0:f1a413971403 221
FelipeVR 0:f1a413971403 222 /*----------------------------- Timer (TIMER) -------------------------------*/
FelipeVR 0:f1a413971403 223 typedef struct
FelipeVR 0:f1a413971403 224 {
FelipeVR 0:f1a413971403 225 __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
FelipeVR 0:f1a413971403 226 __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
FelipeVR 0:f1a413971403 227 __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
FelipeVR 0:f1a413971403 228 union {
FelipeVR 0:f1a413971403 229 __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
FelipeVR 0:f1a413971403 230 __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
FelipeVR 0:f1a413971403 231 };
FelipeVR 0:f1a413971403 232
FelipeVR 0:f1a413971403 233 } CMSDK_TIMER_TypeDef;
FelipeVR 0:f1a413971403 234
FelipeVR 0:f1a413971403 235 /* CMSDK_TIMER CTRL Register Definitions */
FelipeVR 0:f1a413971403 236
FelipeVR 0:f1a413971403 237 #define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */
FelipeVR 0:f1a413971403 238 #define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */
FelipeVR 0:f1a413971403 239
FelipeVR 0:f1a413971403 240 #define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */
FelipeVR 0:f1a413971403 241 #define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */
FelipeVR 0:f1a413971403 242
FelipeVR 0:f1a413971403 243 #define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */
FelipeVR 0:f1a413971403 244 #define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */
FelipeVR 0:f1a413971403 245
FelipeVR 0:f1a413971403 246 #define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */
FelipeVR 0:f1a413971403 247 #define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */
FelipeVR 0:f1a413971403 248
FelipeVR 0:f1a413971403 249 #define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */
FelipeVR 0:f1a413971403 250 #define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */
FelipeVR 0:f1a413971403 251
FelipeVR 0:f1a413971403 252 #define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */
FelipeVR 0:f1a413971403 253 #define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */
FelipeVR 0:f1a413971403 254
FelipeVR 0:f1a413971403 255 #define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */
FelipeVR 0:f1a413971403 256 #define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */
FelipeVR 0:f1a413971403 257
FelipeVR 0:f1a413971403 258 #define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */
FelipeVR 0:f1a413971403 259 #define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */
FelipeVR 0:f1a413971403 260
FelipeVR 0:f1a413971403 261
FelipeVR 0:f1a413971403 262 /*------------- Timer (TIM) --------------------------------------------------*/
FelipeVR 0:f1a413971403 263 typedef struct
FelipeVR 0:f1a413971403 264 {
FelipeVR 0:f1a413971403 265 __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
FelipeVR 0:f1a413971403 266 __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
FelipeVR 0:f1a413971403 267 __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
FelipeVR 0:f1a413971403 268 __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
FelipeVR 0:f1a413971403 269 __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
FelipeVR 0:f1a413971403 270 __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
FelipeVR 0:f1a413971403 271 __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
FelipeVR 0:f1a413971403 272 uint32_t RESERVED0;
FelipeVR 0:f1a413971403 273 __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
FelipeVR 0:f1a413971403 274 __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
FelipeVR 0:f1a413971403 275 __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
FelipeVR 0:f1a413971403 276 __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
FelipeVR 0:f1a413971403 277 __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
FelipeVR 0:f1a413971403 278 __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
FelipeVR 0:f1a413971403 279 __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
FelipeVR 0:f1a413971403 280 uint32_t RESERVED1[945];
FelipeVR 0:f1a413971403 281 __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
FelipeVR 0:f1a413971403 282 __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
FelipeVR 0:f1a413971403 283 } CMSDK_DUALTIMER_BOTH_TypeDef;
FelipeVR 0:f1a413971403 284
FelipeVR 0:f1a413971403 285 #define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */
FelipeVR 0:f1a413971403 286 #define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */
FelipeVR 0:f1a413971403 287
FelipeVR 0:f1a413971403 288 #define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */
FelipeVR 0:f1a413971403 289 #define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */
FelipeVR 0:f1a413971403 290
FelipeVR 0:f1a413971403 291 #define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */
FelipeVR 0:f1a413971403 292 #define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */
FelipeVR 0:f1a413971403 293
FelipeVR 0:f1a413971403 294 #define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */
FelipeVR 0:f1a413971403 295 #define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */
FelipeVR 0:f1a413971403 296
FelipeVR 0:f1a413971403 297 #define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */
FelipeVR 0:f1a413971403 298 #define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */
FelipeVR 0:f1a413971403 299
FelipeVR 0:f1a413971403 300 #define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */
FelipeVR 0:f1a413971403 301 #define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */
FelipeVR 0:f1a413971403 302
FelipeVR 0:f1a413971403 303 #define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */
FelipeVR 0:f1a413971403 304 #define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */
FelipeVR 0:f1a413971403 305
FelipeVR 0:f1a413971403 306 #define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */
FelipeVR 0:f1a413971403 307 #define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
FelipeVR 0:f1a413971403 308
FelipeVR 0:f1a413971403 309 #define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */
FelipeVR 0:f1a413971403 310 #define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */
FelipeVR 0:f1a413971403 311
FelipeVR 0:f1a413971403 312 #define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */
FelipeVR 0:f1a413971403 313 #define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */
FelipeVR 0:f1a413971403 314
FelipeVR 0:f1a413971403 315 #define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */
FelipeVR 0:f1a413971403 316 #define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */
FelipeVR 0:f1a413971403 317
FelipeVR 0:f1a413971403 318 #define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */
FelipeVR 0:f1a413971403 319 #define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */
FelipeVR 0:f1a413971403 320
FelipeVR 0:f1a413971403 321 #define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */
FelipeVR 0:f1a413971403 322 #define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */
FelipeVR 0:f1a413971403 323
FelipeVR 0:f1a413971403 324 #define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */
FelipeVR 0:f1a413971403 325 #define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */
FelipeVR 0:f1a413971403 326
FelipeVR 0:f1a413971403 327 #define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */
FelipeVR 0:f1a413971403 328 #define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */
FelipeVR 0:f1a413971403 329
FelipeVR 0:f1a413971403 330 #define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */
FelipeVR 0:f1a413971403 331 #define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */
FelipeVR 0:f1a413971403 332
FelipeVR 0:f1a413971403 333 #define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */
FelipeVR 0:f1a413971403 334 #define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */
FelipeVR 0:f1a413971403 335
FelipeVR 0:f1a413971403 336 #define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */
FelipeVR 0:f1a413971403 337 #define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */
FelipeVR 0:f1a413971403 338
FelipeVR 0:f1a413971403 339 #define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */
FelipeVR 0:f1a413971403 340 #define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */
FelipeVR 0:f1a413971403 341
FelipeVR 0:f1a413971403 342 #define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */
FelipeVR 0:f1a413971403 343 #define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
FelipeVR 0:f1a413971403 344
FelipeVR 0:f1a413971403 345 #define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */
FelipeVR 0:f1a413971403 346 #define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */
FelipeVR 0:f1a413971403 347
FelipeVR 0:f1a413971403 348 #define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */
FelipeVR 0:f1a413971403 349 #define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */
FelipeVR 0:f1a413971403 350
FelipeVR 0:f1a413971403 351 #define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */
FelipeVR 0:f1a413971403 352 #define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */
FelipeVR 0:f1a413971403 353
FelipeVR 0:f1a413971403 354 #define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */
FelipeVR 0:f1a413971403 355 #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
FelipeVR 0:f1a413971403 356
FelipeVR 0:f1a413971403 357
FelipeVR 0:f1a413971403 358 typedef struct
FelipeVR 0:f1a413971403 359 {
FelipeVR 0:f1a413971403 360 __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
FelipeVR 0:f1a413971403 361 __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
FelipeVR 0:f1a413971403 362 __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
FelipeVR 0:f1a413971403 363 __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
FelipeVR 0:f1a413971403 364 __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
FelipeVR 0:f1a413971403 365 __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
FelipeVR 0:f1a413971403 366 __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
FelipeVR 0:f1a413971403 367 } CMSDK_DUALTIMER_SINGLE_TypeDef;
FelipeVR 0:f1a413971403 368
FelipeVR 0:f1a413971403 369 #define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */
FelipeVR 0:f1a413971403 370 #define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */
FelipeVR 0:f1a413971403 371
FelipeVR 0:f1a413971403 372 #define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */
FelipeVR 0:f1a413971403 373 #define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */
FelipeVR 0:f1a413971403 374
FelipeVR 0:f1a413971403 375 #define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */
FelipeVR 0:f1a413971403 376 #define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */
FelipeVR 0:f1a413971403 377
FelipeVR 0:f1a413971403 378 #define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */
FelipeVR 0:f1a413971403 379 #define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */
FelipeVR 0:f1a413971403 380
FelipeVR 0:f1a413971403 381 #define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */
FelipeVR 0:f1a413971403 382 #define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */
FelipeVR 0:f1a413971403 383
FelipeVR 0:f1a413971403 384 #define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */
FelipeVR 0:f1a413971403 385 #define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */
FelipeVR 0:f1a413971403 386
FelipeVR 0:f1a413971403 387 #define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */
FelipeVR 0:f1a413971403 388 #define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */
FelipeVR 0:f1a413971403 389
FelipeVR 0:f1a413971403 390 #define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */
FelipeVR 0:f1a413971403 391 #define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */
FelipeVR 0:f1a413971403 392
FelipeVR 0:f1a413971403 393 #define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */
FelipeVR 0:f1a413971403 394 #define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */
FelipeVR 0:f1a413971403 395
FelipeVR 0:f1a413971403 396 #define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */
FelipeVR 0:f1a413971403 397 #define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */
FelipeVR 0:f1a413971403 398
FelipeVR 0:f1a413971403 399 #define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */
FelipeVR 0:f1a413971403 400 #define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */
FelipeVR 0:f1a413971403 401
FelipeVR 0:f1a413971403 402 #define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */
FelipeVR 0:f1a413971403 403 #define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */
FelipeVR 0:f1a413971403 404
FelipeVR 0:f1a413971403 405
FelipeVR 0:f1a413971403 406 /*-------------------- General Purpose Input Output (GPIO) -------------------*/
FelipeVR 0:f1a413971403 407 typedef struct
FelipeVR 0:f1a413971403 408 {
FelipeVR 0:f1a413971403 409 __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
FelipeVR 0:f1a413971403 410 __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
FelipeVR 0:f1a413971403 411 uint32_t RESERVED0[2];
FelipeVR 0:f1a413971403 412 __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */
FelipeVR 0:f1a413971403 413 __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
FelipeVR 0:f1a413971403 414 __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
FelipeVR 0:f1a413971403 415 __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
FelipeVR 0:f1a413971403 416 __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
FelipeVR 0:f1a413971403 417 __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
FelipeVR 0:f1a413971403 418 __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
FelipeVR 0:f1a413971403 419 __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
FelipeVR 0:f1a413971403 420 __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
FelipeVR 0:f1a413971403 421 __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
FelipeVR 0:f1a413971403 422 union {
FelipeVR 0:f1a413971403 423 __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
FelipeVR 0:f1a413971403 424 __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
FelipeVR 0:f1a413971403 425 };
FelipeVR 0:f1a413971403 426 uint32_t RESERVED1[241];
FelipeVR 0:f1a413971403 427 __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
FelipeVR 0:f1a413971403 428 __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
FelipeVR 0:f1a413971403 429 } CMSDK_GPIO_TypeDef;
FelipeVR 0:f1a413971403 430
FelipeVR 0:f1a413971403 431 #define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */
FelipeVR 0:f1a413971403 432 #define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */
FelipeVR 0:f1a413971403 433
FelipeVR 0:f1a413971403 434 #define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */
FelipeVR 0:f1a413971403 435 #define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */
FelipeVR 0:f1a413971403 436
FelipeVR 0:f1a413971403 437 #define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
FelipeVR 0:f1a413971403 438 #define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
FelipeVR 0:f1a413971403 439
FelipeVR 0:f1a413971403 440 #define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
FelipeVR 0:f1a413971403 441 #define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
FelipeVR 0:f1a413971403 442
FelipeVR 0:f1a413971403 443 #define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
FelipeVR 0:f1a413971403 444 #define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
FelipeVR 0:f1a413971403 445
FelipeVR 0:f1a413971403 446 #define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
FelipeVR 0:f1a413971403 447 #define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
FelipeVR 0:f1a413971403 448
FelipeVR 0:f1a413971403 449 #define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
FelipeVR 0:f1a413971403 450 #define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
FelipeVR 0:f1a413971403 451
FelipeVR 0:f1a413971403 452 #define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
FelipeVR 0:f1a413971403 453 #define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
FelipeVR 0:f1a413971403 454
FelipeVR 0:f1a413971403 455 #define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
FelipeVR 0:f1a413971403 456 #define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
FelipeVR 0:f1a413971403 457
FelipeVR 0:f1a413971403 458 #define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
FelipeVR 0:f1a413971403 459 #define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
FelipeVR 0:f1a413971403 460
FelipeVR 0:f1a413971403 461 #define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
FelipeVR 0:f1a413971403 462 #define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
FelipeVR 0:f1a413971403 463
FelipeVR 0:f1a413971403 464 #define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
FelipeVR 0:f1a413971403 465 #define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
FelipeVR 0:f1a413971403 466
FelipeVR 0:f1a413971403 467 #define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */
FelipeVR 0:f1a413971403 468 #define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */
FelipeVR 0:f1a413971403 469
FelipeVR 0:f1a413971403 470 #define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */
FelipeVR 0:f1a413971403 471 #define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */
FelipeVR 0:f1a413971403 472
FelipeVR 0:f1a413971403 473 #define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */
FelipeVR 0:f1a413971403 474 #define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */
FelipeVR 0:f1a413971403 475
FelipeVR 0:f1a413971403 476 #define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */
FelipeVR 0:f1a413971403 477 #define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */
FelipeVR 0:f1a413971403 478
FelipeVR 0:f1a413971403 479
FelipeVR 0:f1a413971403 480 /*------------- System Control (SYSCON) --------------------------------------*/
FelipeVR 0:f1a413971403 481 typedef struct
FelipeVR 0:f1a413971403 482 {
FelipeVR 0:f1a413971403 483 __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
FelipeVR 0:f1a413971403 484 __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
FelipeVR 0:f1a413971403 485 __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
FelipeVR 0:f1a413971403 486 __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
FelipeVR 0:f1a413971403 487 __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
FelipeVR 0:f1a413971403 488 uint32_t RESERVED0[3];
FelipeVR 0:f1a413971403 489 __IO uint32_t AHBPER0SET; /* Offset: 0x020 (R/W)AHB peripheral access control set */
FelipeVR 0:f1a413971403 490 __IO uint32_t AHBPER0CLR; /* Offset: 0x024 (R/W)AHB peripheral access control clear */
FelipeVR 0:f1a413971403 491 uint32_t RESERVED1[2];
FelipeVR 0:f1a413971403 492 __IO uint32_t APBPER0SET; /* Offset: 0x030 (R/W)APB peripheral access control set */
FelipeVR 0:f1a413971403 493 __IO uint32_t APBPER0CLR; /* Offset: 0x034 (R/W)APB peripheral access control clear */
FelipeVR 0:f1a413971403 494 uint32_t RESERVED2[2];
FelipeVR 0:f1a413971403 495 __IO uint32_t MAINCLK; /* Offset: 0x040 (R/W) Main Clock Control Register */
FelipeVR 0:f1a413971403 496 __IO uint32_t AUXCLK; /* Offset: 0x044 (R/W) Auxiliary / RTC Control Register */
FelipeVR 0:f1a413971403 497 __IO uint32_t PLLCTRL; /* Offset: 0x048 (R/W) PLL Control Register */
FelipeVR 0:f1a413971403 498 __IO uint32_t PLLSTATUS; /* Offset: 0x04C (R/W) PLL Status Register */
FelipeVR 0:f1a413971403 499 __IO uint32_t SLEEPCFG; /* Offset: 0x050 (R/W) Sleep Control Register */
FelipeVR 0:f1a413971403 500 __IO uint32_t FLASHAUXCFG; /* Offset: 0x054 (R/W) Flash auxiliary settings Control Register */
FelipeVR 0:f1a413971403 501 uint32_t RESERVED3[10];
FelipeVR 0:f1a413971403 502 __IO uint32_t AHBCLKCFG0SET; /* Offset: 0x080 (R/W) AHB Peripheral Clock set in Active state */
FelipeVR 0:f1a413971403 503 __IO uint32_t AHBCLKCFG0CLR; /* Offset: 0x084 (R/W) AHB Peripheral Clock clear in Active state */
FelipeVR 0:f1a413971403 504 __IO uint32_t AHBCLKCFG1SET; /* Offset: 0x088 (R/W) AHB Peripheral Clock set in Sleep state */
FelipeVR 0:f1a413971403 505 __IO uint32_t AHBCLKCFG1CLR; /* Offset: 0x08C (R/W) AHB Peripheral Clock clear in Sleep state */
FelipeVR 0:f1a413971403 506 __IO uint32_t AHBCLKCFG2SET; /* Offset: 0x090 (R/W) AHB Peripheral Clock set in Deep Sleep state */
FelipeVR 0:f1a413971403 507 __IO uint32_t AHBCLKCFG2CLR; /* Offset: 0x094 (R/W) AHB Peripheral Clock clear in Deep Sleep state */
FelipeVR 0:f1a413971403 508 uint32_t RESERVED4[2];
FelipeVR 0:f1a413971403 509 __IO uint32_t APBCLKCFG0SET; /* Offset: 0x0A0 (R/W) APB Peripheral Clock set in Active state */
FelipeVR 0:f1a413971403 510 __IO uint32_t APBCLKCFG0CLR; /* Offset: 0x0A4 (R/W) APB Peripheral Clock clear in Active state */
FelipeVR 0:f1a413971403 511 __IO uint32_t APBCLKCFG1SET; /* Offset: 0x0A8 (R/W) APB Peripheral Clock set in Sleep state */
FelipeVR 0:f1a413971403 512 __IO uint32_t APBCLKCFG1CLR; /* Offset: 0x0AC (R/W) APB Peripheral Clock clear in Sleep state */
FelipeVR 0:f1a413971403 513 __IO uint32_t APBCLKCFG2SET; /* Offset: 0x0B0 (R/W) APB Peripheral Clock set in Deep Sleep state */
FelipeVR 0:f1a413971403 514 __IO uint32_t APBCLKCFG2CLR; /* Offset: 0x0B4 (R/W) APB Peripheral Clock clear in Deep Sleep state */
FelipeVR 0:f1a413971403 515 uint32_t RESERVED5[2];
FelipeVR 0:f1a413971403 516 __IO uint32_t AHBPRST0SET; /* Offset: 0x0C0 (R/W) AHB Peripheral reset select set */
FelipeVR 0:f1a413971403 517 __IO uint32_t AHBPRST0CLR; /* Offset: 0x0C4 (R/W) AHB Peripheral reset select clear */
FelipeVR 0:f1a413971403 518 __IO uint32_t APBPRST0SET; /* Offset: 0x0C8 (R/W) APB Peripheral reset select set */
FelipeVR 0:f1a413971403 519 __IO uint32_t APBPRST0CLR; /* Offset: 0x0CC (R/W) APB Peripheral reset select clear */
FelipeVR 0:f1a413971403 520 __IO uint32_t PWRDNCFG0SET; /* Offset: 0x0D0 (R/W) AHB Power down sleep wakeup source set */
FelipeVR 0:f1a413971403 521 __IO uint32_t PWRDNCFG0CLR; /* Offset: 0x0D4 (R/W) AHB Power down sleep wakeup source clear */
FelipeVR 0:f1a413971403 522 __IO uint32_t PWRDNCFG1SET; /* Offset: 0x0D8 (R/W) APB Power down sleep wakeup source set */
FelipeVR 0:f1a413971403 523 __IO uint32_t PWRDNCFG1CLR; /* Offset: 0x0DC (R/W) APB Power down sleep wakeup source clear */
FelipeVR 0:f1a413971403 524 __O uint32_t RTCRESET; /* Offset: 0x0E0 ( /W) RTC reset */
FelipeVR 0:f1a413971403 525 __IO uint32_t EVENTCFG; /* Offset: 0x0E4 (R/W) Event interface Control Register */
FelipeVR 0:f1a413971403 526 uint32_t RESERVED6[2];
FelipeVR 0:f1a413971403 527 __IO uint32_t PWROVRIDE0; /* Offset: 0x0F0 (R/W) SRAM Power control overide */
FelipeVR 0:f1a413971403 528 __IO uint32_t PWROVRIDE1; /* Offset: 0x0F4 (R/W) Embedded Flash Power control overide */
FelipeVR 0:f1a413971403 529 __I uint32_t MEMORYSTATUS; /* Offset: 0x0F8 (R/ ) Memory Status Register */
FelipeVR 0:f1a413971403 530 uint32_t RESERVED7[1];
FelipeVR 0:f1a413971403 531 __IO uint32_t GPIOPADCFG0; /* Offset: 0x100 (R/W) IO pad settings */
FelipeVR 0:f1a413971403 532 __IO uint32_t GPIOPADCFG1; /* Offset: 0x104 (R/W) IO pad settings */
FelipeVR 0:f1a413971403 533 __IO uint32_t TESTMODECFG; /* Offset: 0x108 (R/W) Testmode boot bypass */
FelipeVR 0:f1a413971403 534 } CMSDK_SYSCON_TypeDef;
FelipeVR 0:f1a413971403 535
FelipeVR 0:f1a413971403 536 #define CMSDK_SYSCON_REMAP_Pos 0
FelipeVR 0:f1a413971403 537 #define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */
FelipeVR 0:f1a413971403 538
FelipeVR 0:f1a413971403 539 #define CMSDK_SYSCON_PMUCTRL_EN_Pos 0
FelipeVR 0:f1a413971403 540 #define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */
FelipeVR 0:f1a413971403 541
FelipeVR 0:f1a413971403 542 #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0
FelipeVR 0:f1a413971403 543 #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */
FelipeVR 0:f1a413971403 544
FelipeVR 0:f1a413971403 545 #define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24
FelipeVR 0:f1a413971403 546 #define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */
FelipeVR 0:f1a413971403 547
FelipeVR 0:f1a413971403 548 #define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16
FelipeVR 0:f1a413971403 549 #define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */
FelipeVR 0:f1a413971403 550
FelipeVR 0:f1a413971403 551 #define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8
FelipeVR 0:f1a413971403 552 #define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */
FelipeVR 0:f1a413971403 553
FelipeVR 0:f1a413971403 554 #define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0
FelipeVR 0:f1a413971403 555 #define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */
FelipeVR 0:f1a413971403 556
FelipeVR 0:f1a413971403 557 #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0
FelipeVR 0:f1a413971403 558 #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */
FelipeVR 0:f1a413971403 559
FelipeVR 0:f1a413971403 560 #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1
FelipeVR 0:f1a413971403 561 #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */
FelipeVR 0:f1a413971403 562
FelipeVR 0:f1a413971403 563 #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2
FelipeVR 0:f1a413971403 564 #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */
FelipeVR 0:f1a413971403 565
FelipeVR 0:f1a413971403 566
FelipeVR 0:f1a413971403 567 /*------------- PL230 uDMA (PL230) --------------------------------------*/
FelipeVR 0:f1a413971403 568 typedef struct
FelipeVR 0:f1a413971403 569 {
FelipeVR 0:f1a413971403 570 __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
FelipeVR 0:f1a413971403 571 __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
FelipeVR 0:f1a413971403 572 __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
FelipeVR 0:f1a413971403 573 __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */
FelipeVR 0:f1a413971403 574 __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */
FelipeVR 0:f1a413971403 575 __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */
FelipeVR 0:f1a413971403 576 __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */
FelipeVR 0:f1a413971403 577 __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */
FelipeVR 0:f1a413971403 578 __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */
FelipeVR 0:f1a413971403 579 __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */
FelipeVR 0:f1a413971403 580 __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */
FelipeVR 0:f1a413971403 581 __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */
FelipeVR 0:f1a413971403 582 __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */
FelipeVR 0:f1a413971403 583 __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */
FelipeVR 0:f1a413971403 584 __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */
FelipeVR 0:f1a413971403 585 __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */
FelipeVR 0:f1a413971403 586 uint32_t RESERVED0[3];
FelipeVR 0:f1a413971403 587 __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */
FelipeVR 0:f1a413971403 588
FelipeVR 0:f1a413971403 589 } CMSDK_PL230_TypeDef;
FelipeVR 0:f1a413971403 590
FelipeVR 0:f1a413971403 591 #define PL230_DMA_CHNL_BITS 0
FelipeVR 0:f1a413971403 592
FelipeVR 0:f1a413971403 593 #define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */
FelipeVR 0:f1a413971403 594 #define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */
FelipeVR 0:f1a413971403 595
FelipeVR 0:f1a413971403 596 #define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */
FelipeVR 0:f1a413971403 597 #define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */
FelipeVR 0:f1a413971403 598
FelipeVR 0:f1a413971403 599 #define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */
FelipeVR 0:f1a413971403 600 #define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */
FelipeVR 0:f1a413971403 601
FelipeVR 0:f1a413971403 602 #define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */
FelipeVR 0:f1a413971403 603 #define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */
FelipeVR 0:f1a413971403 604
FelipeVR 0:f1a413971403 605 #define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */
FelipeVR 0:f1a413971403 606 #define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */
FelipeVR 0:f1a413971403 607
FelipeVR 0:f1a413971403 608 #define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */
FelipeVR 0:f1a413971403 609 #define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */
FelipeVR 0:f1a413971403 610
FelipeVR 0:f1a413971403 611 #define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */
FelipeVR 0:f1a413971403 612 #define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */
FelipeVR 0:f1a413971403 613
FelipeVR 0:f1a413971403 614 #define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */
FelipeVR 0:f1a413971403 615 #define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */
FelipeVR 0:f1a413971403 616
FelipeVR 0:f1a413971403 617 #define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */
FelipeVR 0:f1a413971403 618 #define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */
FelipeVR 0:f1a413971403 619
FelipeVR 0:f1a413971403 620 #define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */
FelipeVR 0:f1a413971403 621 #define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */
FelipeVR 0:f1a413971403 622
FelipeVR 0:f1a413971403 623 #define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */
FelipeVR 0:f1a413971403 624 #define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */
FelipeVR 0:f1a413971403 625
FelipeVR 0:f1a413971403 626 #define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */
FelipeVR 0:f1a413971403 627 #define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */
FelipeVR 0:f1a413971403 628
FelipeVR 0:f1a413971403 629 #define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */
FelipeVR 0:f1a413971403 630 #define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */
FelipeVR 0:f1a413971403 631
FelipeVR 0:f1a413971403 632 #define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */
FelipeVR 0:f1a413971403 633 #define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */
FelipeVR 0:f1a413971403 634
FelipeVR 0:f1a413971403 635 #define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */
FelipeVR 0:f1a413971403 636 #define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */
FelipeVR 0:f1a413971403 637
FelipeVR 0:f1a413971403 638 #define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */
FelipeVR 0:f1a413971403 639 #define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */
FelipeVR 0:f1a413971403 640
FelipeVR 0:f1a413971403 641 #define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */
FelipeVR 0:f1a413971403 642 #define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */
FelipeVR 0:f1a413971403 643
FelipeVR 0:f1a413971403 644 #define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */
FelipeVR 0:f1a413971403 645 #define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */
FelipeVR 0:f1a413971403 646
FelipeVR 0:f1a413971403 647 #define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */
FelipeVR 0:f1a413971403 648 #define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */
FelipeVR 0:f1a413971403 649
FelipeVR 0:f1a413971403 650 #define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */
FelipeVR 0:f1a413971403 651 #define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */
FelipeVR 0:f1a413971403 652
FelipeVR 0:f1a413971403 653 #define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */
FelipeVR 0:f1a413971403 654 #define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */
FelipeVR 0:f1a413971403 655
FelipeVR 0:f1a413971403 656 #define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */
FelipeVR 0:f1a413971403 657 #define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */
FelipeVR 0:f1a413971403 658
FelipeVR 0:f1a413971403 659 #define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */
FelipeVR 0:f1a413971403 660 #define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */
FelipeVR 0:f1a413971403 661
FelipeVR 0:f1a413971403 662
FelipeVR 0:f1a413971403 663 /*------------------- Watchdog ----------------------------------------------*/
FelipeVR 0:f1a413971403 664 typedef struct
FelipeVR 0:f1a413971403 665 {
FelipeVR 0:f1a413971403 666
FelipeVR 0:f1a413971403 667 __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
FelipeVR 0:f1a413971403 668 __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
FelipeVR 0:f1a413971403 669 __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
FelipeVR 0:f1a413971403 670 __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
FelipeVR 0:f1a413971403 671 __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
FelipeVR 0:f1a413971403 672 __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
FelipeVR 0:f1a413971403 673 uint32_t RESERVED0[762];
FelipeVR 0:f1a413971403 674 __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
FelipeVR 0:f1a413971403 675 uint32_t RESERVED1[191];
FelipeVR 0:f1a413971403 676 __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
FelipeVR 0:f1a413971403 677 __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
FelipeVR 0:f1a413971403 678 }CMSDK_WATCHDOG_TypeDef;
FelipeVR 0:f1a413971403 679
FelipeVR 0:f1a413971403 680 #define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
FelipeVR 0:f1a413971403 681 #define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */
FelipeVR 0:f1a413971403 682
FelipeVR 0:f1a413971403 683 #define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */
FelipeVR 0:f1a413971403 684 #define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */
FelipeVR 0:f1a413971403 685
FelipeVR 0:f1a413971403 686 #define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */
FelipeVR 0:f1a413971403 687 #define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */
FelipeVR 0:f1a413971403 688
FelipeVR 0:f1a413971403 689 #define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */
FelipeVR 0:f1a413971403 690 #define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */
FelipeVR 0:f1a413971403 691
FelipeVR 0:f1a413971403 692 #define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */
FelipeVR 0:f1a413971403 693 #define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */
FelipeVR 0:f1a413971403 694
FelipeVR 0:f1a413971403 695 #define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */
FelipeVR 0:f1a413971403 696 #define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */
FelipeVR 0:f1a413971403 697
FelipeVR 0:f1a413971403 698 #define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */
FelipeVR 0:f1a413971403 699 #define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */
FelipeVR 0:f1a413971403 700
FelipeVR 0:f1a413971403 701 #define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */
FelipeVR 0:f1a413971403 702 #define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */
FelipeVR 0:f1a413971403 703
FelipeVR 0:f1a413971403 704 #define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */
FelipeVR 0:f1a413971403 705 #define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */
FelipeVR 0:f1a413971403 706
FelipeVR 0:f1a413971403 707 #define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */
FelipeVR 0:f1a413971403 708 #define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */
FelipeVR 0:f1a413971403 709
FelipeVR 0:f1a413971403 710
FelipeVR 0:f1a413971403 711
FelipeVR 0:f1a413971403 712 /* -------------------- End of section using anonymous unions ------------------- */
FelipeVR 0:f1a413971403 713 #if defined ( __CC_ARM )
FelipeVR 0:f1a413971403 714 #pragma pop
FelipeVR 0:f1a413971403 715 #elif defined(__ICCARM__)
FelipeVR 0:f1a413971403 716 /* leave anonymous unions enabled */
FelipeVR 0:f1a413971403 717 #elif defined(__GNUC__)
FelipeVR 0:f1a413971403 718 /* anonymous unions are enabled by default */
FelipeVR 0:f1a413971403 719 #elif defined(__TMS470__)
FelipeVR 0:f1a413971403 720 /* anonymous unions are enabled by default */
FelipeVR 0:f1a413971403 721 #elif defined(__TASKING__)
FelipeVR 0:f1a413971403 722 #pragma warning restore
FelipeVR 0:f1a413971403 723 #else
FelipeVR 0:f1a413971403 724 #warning Not supported compiler type
FelipeVR 0:f1a413971403 725 #endif
FelipeVR 0:f1a413971403 726
FelipeVR 0:f1a413971403 727
FelipeVR 0:f1a413971403 728
FelipeVR 0:f1a413971403 729
FelipeVR 0:f1a413971403 730 /* ================================================================================ */
FelipeVR 0:f1a413971403 731 /* ================ Peripheral memory map ================ */
FelipeVR 0:f1a413971403 732 /* ================================================================================ */
FelipeVR 0:f1a413971403 733
FelipeVR 0:f1a413971403 734 /* Peripheral and SRAM base address */
FelipeVR 0:f1a413971403 735 #define CMSDK_FLASH_BASE (0x00000000UL)
FelipeVR 0:f1a413971403 736 #define CMSDK_SRAM_BASE (0x20000000UL)
FelipeVR 0:f1a413971403 737 #define CMSDK_PERIPH_BASE (0x40000000UL)
FelipeVR 0:f1a413971403 738
FelipeVR 0:f1a413971403 739 #define CMSDK_RAM_BASE (0x20000000UL)
FelipeVR 0:f1a413971403 740 #define CMSDK_APB_BASE (0x40000000UL)
FelipeVR 0:f1a413971403 741 #define CMSDK_AHB_BASE (0x40010000UL)
FelipeVR 0:f1a413971403 742
FelipeVR 0:f1a413971403 743 /* APB peripherals */
FelipeVR 0:f1a413971403 744 #define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL)
FelipeVR 0:f1a413971403 745 #define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL)
FelipeVR 0:f1a413971403 746 #define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL)
FelipeVR 0:f1a413971403 747 #define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE)
FelipeVR 0:f1a413971403 748 #define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL)
FelipeVR 0:f1a413971403 749 #define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
FelipeVR 0:f1a413971403 750 #define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
FelipeVR 0:f1a413971403 751 #define CMSDK_UART2_BASE (0x4002C000UL)
FelipeVR 0:f1a413971403 752 #define CMSDK_UART3_BASE (0x4002D000UL)
FelipeVR 0:f1a413971403 753 #define CMSDK_UART4_BASE (0x4002E000UL)
FelipeVR 0:f1a413971403 754 #define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
FelipeVR 0:f1a413971403 755 //#define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL)
FelipeVR 0:f1a413971403 756
FelipeVR 0:f1a413971403 757 /* AHB peripherals */
FelipeVR 0:f1a413971403 758 #define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL)
FelipeVR 0:f1a413971403 759 #define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL)
FelipeVR 0:f1a413971403 760 #define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL)
FelipeVR 0:f1a413971403 761 #define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL)
FelipeVR 0:f1a413971403 762 #define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL)
FelipeVR 0:f1a413971403 763
FelipeVR 0:f1a413971403 764
FelipeVR 0:f1a413971403 765 /* ================================================================================ */
FelipeVR 0:f1a413971403 766 /* ================ Peripheral declaration ================ */
FelipeVR 0:f1a413971403 767 /* ================================================================================ */
FelipeVR 0:f1a413971403 768
FelipeVR 0:f1a413971403 769 #define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
FelipeVR 0:f1a413971403 770 #define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
FelipeVR 0:f1a413971403 771 #define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
FelipeVR 0:f1a413971403 772 #define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE )
FelipeVR 0:f1a413971403 773 #define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
FelipeVR 0:f1a413971403 774 #define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
FelipeVR 0:f1a413971403 775 #define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
FelipeVR 0:f1a413971403 776 #define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
FelipeVR 0:f1a413971403 777 #define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
FelipeVR 0:f1a413971403 778 #define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
FelipeVR 0:f1a413971403 779 //#define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE )
FelipeVR 0:f1a413971403 780 #define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
FelipeVR 0:f1a413971403 781 #define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
FelipeVR 0:f1a413971403 782 #define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE )
FelipeVR 0:f1a413971403 783 #define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE )
FelipeVR 0:f1a413971403 784 #define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
FelipeVR 0:f1a413971403 785
FelipeVR 0:f1a413971403 786
FelipeVR 0:f1a413971403 787 #ifdef __cplusplus
FelipeVR 0:f1a413971403 788 }
FelipeVR 0:f1a413971403 789 #endif
FelipeVR 0:f1a413971403 790
FelipeVR 0:f1a413971403 791 #endif /* CMSDK_CM3_H */