Newhaven NHD-2.23-12832UCY3-2 OLED Display
WORK IN PROGRESS
This is a running information of information from the datasheets for my project.
You're welcome to follow along, but it is by no means complete.
The module is an OLED display, which I'm attempting to setup via a I2C interface.
The reason for I2C bus interface selection is that it only requires 6 pins, consisting
of: 2 pins I2C, 2 pins mode select, 1 pin reset, 1 pin address select
Device
MFG: Newhaven Display
MFG P/N: NHD-2.23-12832UCY3
Desc: OLED Displays OLED 128 x 32 Yellow 63.2 x 43.1 x 6.0
Module Datasheet: link
Onboard Controller Datasheet: link
Electrical Information
VDDmin: 2.4v
VDDmax: 3.5v
IDDtyp: 180uA (logic)
ICCtyp: 28mA (display 100% on)
Pinout
Display Pin | mbed Pin | Description |
---|---|---|
1 | 1 | VSS/Ground |
2 | 40 | VDD/3v Supply |
4 | 26 | SA0/Slave Address Selection signal |
5 | 1 | VSS/Ground |
6 | 1 | VSS/Ground |
7 | 27 | SCL/I2C Clock - Pull up to VDD |
8 | 28 | SDAin/I2C Data - Pull up to VDD |
9 | 28 | SDAout/I2C Data |
10 | 1 | VSS/Ground |
11 | 1 | VSS/Ground |
12 | 1 | VSS/Ground |
13 | 1 | VSS/Ground |
14 | 1 | VSS/Ground |
16 | 25 | !RES/Active LOW Reset |
17 | 1 | VSS/Ground |
19 | 24 | BS2/MPU Interface Select signal |
20 | 23 | BS1/MPU Interface Select signal |
MPU Interface Summary
Onboard SSD1305 consists of 8 data and 5 control pins
Layout specifically for I2C Bus Interface
D7 - Tie LOW
D6 - Tie LOW
D5 - Tie LOW
D4 - Tie LOW
D3 - Tie LOW
D2 - SDAin - Pull up to VDD
D1 - SDAout - tie to SDAin for SDA, or NC to ignore ACK
D0 - SCL - Pull up to VDD
E - Tie LOW
R/W - Tie LOW
!CS - Tie LOW
D/C - SA0
!RES - !RES
Application Notes
For pull up resistors, I had some 3.9k5% laying around.
MCU I2C Interface
- Must recognize SD0 before transmitting or receiving any information on I2C bus.
- Will respond to slave address following by slave address bit, and r/w select bit
- Response format: b7 b6 b5 b4 b3 b2 b1 b0 : 0 1 1 1 1 0 SA0 R/W#
- 0111100 or 0111101 can be selected as slave address of SSD1305
- R/W# bit is used to determine operation mode of I2C interface 1=read 0=write
- SDA pins cannot output logic 0
- SDAout may be NC, ack will be ignored
- Transmission of information is followed by a clock signal on SCL
- Each bit takes place during a single clock period of SCL
I2C Write Data
Slave | m>=0words | 1 byte | n>=0bytes | |||
---|---|---|---|---|---|---|
S | 011110(SA0) | (R/W)(ACK) | (Co)(D/C)( )(5b control byte)(ACK)( )(7b data byte)(ACK) | (Co)(D/C)( )(5b control byte)(ACK) | ( )(7b data byte)(ACK) | P |
Co: Continuation bit
D/C: Data/Command selection bit
ACK: Acknowledgement
SA0: Slave address bit
R/W: Read Write selection bit
S: Start condition
P: Stop condition
- Master device initiates data communication by a start condition. Established by pulling SDA to LOW while SCL stays HIGH.
- Slave address follows start condition for recognition. Slave address is either b0111100 or b0111101.
- Write mode is established with R/W bit to logic 0
- ACK will be generated after receiving one byte of data, including slave address and R/W bit.
- After transmission of slave address, either the control byte or the data byte may be sent across SDA.
- Control byte consists of Co and D/C bits followed by six 0's
- If the Co bit is 0, the transmission of following information will contain data bytes only
- The D/C bit determins the next data byte as command or data. 0=command, 1=data to be stored in GDDRAM.
- GDDRAM Pointer increases automatically after each write.
- Ack will be generated after receiving each control or data byte
- Write will finish when stop condition is applied. Established by SDAin from LOW to HIGH while SCL stays HIGH.
Command Decoder
If D/C pin (connected to SA0) is HIGH, data is interpreted as data display data written to GDDRAM. If D/C pin (connected to SA0) is LOW, data is interpreted as a command, written to command register.
Reset Circuit
When RES is LOW, the chip is initialized with status:
- Display OFF
- 132x64 display mode
- Normal segment and display data column address and row address mapping (SEG0=00h, COM0=00h)
- Shift register data clear
- Display start line is set to RAM address 0
- Column address counter is set to 0
- Normal scan direction of COM outputs
- Contrast control register is set at 80h
- Normal display mode (A4h command)
Power ON sequence
- VDD power on
- Set RES to LOW for at least 3us then HIGH
- Send command 0xAF for diaplay ON, SEG/COM will be ON after 100ms
Power OFF sequence
- Send command AEh for display OFF
- Power OFF VDD
7 comments on Newhaven NHD-2.23-12832UCY3-2 OLED Display:
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Hello,
i'm looking for a driver for SSD1305 with densitron display. Is your driver already working? if so can you publish it?
thanks in advance