Eric Lewiston
Hal Drivers for L4
Dependents: BSP OneHopeOnePrayer FINAL_AUDIO_RECORD AudioDemo
Fork of
STM32L4xx_HAL_Driver
by 
Senior Design: Sound Monitor
Embed:
(wiki syntax)
Show/hide line numbers
stm32l4xx_ll_exti.h
Go to the documentation of this file.
00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_exti.h 00004 * @author MCD Application Team 00005 * @version V1.1.0 00006 * @date 16-September-2015 00007 * @brief Header file of EXTI LL module. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> 00012 * 00013 * Redistribution and use in source and binary forms, with or without modification, 00014 * are permitted provided that the following conditions are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright notice, 00018 * this list of conditions and the following disclaimer in the documentation 00019 * and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00021 * may be used to endorse or promote products derived from this software 00022 * without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00027 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00028 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00029 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00030 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00031 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00032 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00033 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 00038 /* Define to prevent recursive inclusion -------------------------------------*/ 00039 #ifndef __STM32L4xx_LL_EXTI_H 00040 #define __STM32L4xx_LL_EXTI_H 00041 00042 #ifdef __cplusplus 00043 extern "C" { 00044 #endif 00045 00046 /* Includes ------------------------------------------------------------------*/ 00047 #include "stm32l4xx.h" 00048 00049 /** @addtogroup STM32L4xx_LL_Driver 00050 * @{ 00051 */ 00052 00053 #if defined (EXTI) 00054 00055 /** @defgroup EXTI_LL EXTI 00056 * @{ 00057 */ 00058 00059 /* Private types -------------------------------------------------------------*/ 00060 /* Private variables ---------------------------------------------------------*/ 00061 00062 /* Private constants ---------------------------------------------------------*/ 00063 00064 /* Private macros ------------------------------------------------------------*/ 00065 00066 /* Exported types ------------------------------------------------------------*/ 00067 /* Exported constants --------------------------------------------------------*/ 00068 /** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants 00069 * @{ 00070 */ 00071 00072 /** @defgroup EXTI_LL_EC_LINE LINE 00073 * @{ 00074 */ 00075 #define LL_EXTI_LINE_0 EXTI_IMR1_IM0 /*!< Extended line 0 */ 00076 #define LL_EXTI_LINE_1 EXTI_IMR1_IM1 /*!< Extended line 1 */ 00077 #define LL_EXTI_LINE_2 EXTI_IMR1_IM2 /*!< Extended line 2 */ 00078 #define LL_EXTI_LINE_3 EXTI_IMR1_IM3 /*!< Extended line 3 */ 00079 #define LL_EXTI_LINE_4 EXTI_IMR1_IM4 /*!< Extended line 4 */ 00080 #define LL_EXTI_LINE_5 EXTI_IMR1_IM5 /*!< Extended line 5 */ 00081 #define LL_EXTI_LINE_6 EXTI_IMR1_IM6 /*!< Extended line 6 */ 00082 #define LL_EXTI_LINE_7 EXTI_IMR1_IM7 /*!< Extended line 7 */ 00083 #define LL_EXTI_LINE_8 EXTI_IMR1_IM8 /*!< Extended line 8 */ 00084 #define LL_EXTI_LINE_9 EXTI_IMR1_IM9 /*!< Extended line 9 */ 00085 #define LL_EXTI_LINE_10 EXTI_IMR1_IM10 /*!< Extended line 10 */ 00086 #define LL_EXTI_LINE_11 EXTI_IMR1_IM11 /*!< Extended line 11 */ 00087 #define LL_EXTI_LINE_12 EXTI_IMR1_IM12 /*!< Extended line 12 */ 00088 #define LL_EXTI_LINE_13 EXTI_IMR1_IM13 /*!< Extended line 13 */ 00089 #define LL_EXTI_LINE_14 EXTI_IMR1_IM14 /*!< Extended line 14 */ 00090 #define LL_EXTI_LINE_15 EXTI_IMR1_IM15 /*!< Extended line 15 */ 00091 #define LL_EXTI_LINE_16 EXTI_IMR1_IM16 /*!< Extended line 16 */ 00092 #define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */ 00093 #define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */ 00094 #define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */ 00095 #define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */ 00096 #define LL_EXTI_LINE_21 EXTI_IMR1_IM21 /*!< Extended line 21 */ 00097 #define LL_EXTI_LINE_22 EXTI_IMR1_IM22 /*!< Extended line 22 */ 00098 #define LL_EXTI_LINE_23 EXTI_IMR1_IM23 /*!< Extended line 23 */ 00099 #define LL_EXTI_LINE_24 EXTI_IMR1_IM24 /*!< Extended line 24 */ 00100 #define LL_EXTI_LINE_25 EXTI_IMR1_IM25 /*!< Extended line 25 */ 00101 #define LL_EXTI_LINE_26 EXTI_IMR1_IM26 /*!< Extended line 26 */ 00102 #define LL_EXTI_LINE_27 EXTI_IMR1_IM27 /*!< Extended line 27 */ 00103 #define LL_EXTI_LINE_28 EXTI_IMR1_IM28 /*!< Extended line 28 */ 00104 #define LL_EXTI_LINE_29 EXTI_IMR1_IM29 /*!< Extended line 29 */ 00105 #define LL_EXTI_LINE_30 EXTI_IMR1_IM30 /*!< Extended line 30 */ 00106 #define LL_EXTI_LINE_31 EXTI_IMR1_IM31 /*!< Extended line 31 */ 00107 #define LL_EXTI_LINE_ALL_0_31 ((uint32_t)0xFFFFFFFF) /*!< All Extended line */ 00108 00109 00110 /** 00111 * @} 00112 */ 00113 00114 /** @addtogroup EXTI_LL_EC_LINE 00115 * @{ 00116 */ 00117 #define LL_EXTI_LINE_32 EXTI_IMR2_IM32 /*!< Extended line 32 */ 00118 #define LL_EXTI_LINE_33 EXTI_IMR2_IM33 /*!< Extended line 33 */ 00119 #define LL_EXTI_LINE_34 EXTI_IMR2_IM34 /*!< Extended line 34 */ 00120 #define LL_EXTI_LINE_35 EXTI_IMR2_IM35 /*!< Extended line 35 */ 00121 #define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */ 00122 #define LL_EXTI_LINE_37 EXTI_IMR2_IM37 /*!< Extended line 37 */ 00123 #define LL_EXTI_LINE_38 EXTI_IMR2_IM38 /*!< Extended line 38 */ 00124 #define LL_EXTI_LINE_39 EXTI_IMR2_IM39 /*!< Extended line 39 */ 00125 #define LL_EXTI_LINE_ALL_32_63 ((uint32_t)0x000000FF) /*!< All Extended line */ 00126 /** 00127 * @} 00128 */ 00129 00130 /** @addtogroup EXTI_LL_EC_LINE 00131 * @{ 00132 */ 00133 #define LL_EXTI_LINE_ALL ((uint32_t)0xFFFFFFFF) /*!< All Extended line */ 00134 /** 00135 * @} 00136 */ 00137 00138 /** 00139 * @} 00140 */ 00141 00142 /* Exported macro ------------------------------------------------------------*/ 00143 /** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros 00144 * @{ 00145 */ 00146 00147 /** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros 00148 * @{ 00149 */ 00150 00151 /** 00152 * @brief Write a value in EXTI register 00153 * @param __REG__ Register to be written 00154 * @param __VALUE__ Value to be written in the register 00155 * @retval None 00156 */ 00157 #define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) 00158 00159 /** 00160 * @brief Read a value in EXTI register 00161 * @param __REG__ Register to be read 00162 * @retval Register value 00163 */ 00164 #define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) 00165 /** 00166 * @} 00167 */ 00168 00169 00170 /** 00171 * @} 00172 */ 00173 00174 00175 00176 /* Exported functions --------------------------------------------------------*/ 00177 /** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions 00178 * @{ 00179 */ 00180 /** @defgroup EXTI_LL_EF_IT_Management IT_Management 00181 * @{ 00182 */ 00183 00184 /** 00185 * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 00186 * @note The reset value for the direct lines (line 17, lines from 23 to 31) 00187 * is set to 1 in order to enable the interrupt by default. 00188 * Bits are set automatically at Power on. 00189 * @rmtoll IMR1 IMx LL_EXTI_EnableIT_0_31 00190 * @param ExtiLine This parameter can be one of the following values: 00191 * @arg @ref LL_EXTI_LINE_0 00192 * @arg @ref LL_EXTI_LINE_1 00193 * @arg @ref LL_EXTI_LINE_2 00194 * @arg @ref LL_EXTI_LINE_3 00195 * @arg @ref LL_EXTI_LINE_4 00196 * @arg @ref LL_EXTI_LINE_5 00197 * @arg @ref LL_EXTI_LINE_6 00198 * @arg @ref LL_EXTI_LINE_7 00199 * @arg @ref LL_EXTI_LINE_8 00200 * @arg @ref LL_EXTI_LINE_9 00201 * @arg @ref LL_EXTI_LINE_10 00202 * @arg @ref LL_EXTI_LINE_11 00203 * @arg @ref LL_EXTI_LINE_12 00204 * @arg @ref LL_EXTI_LINE_13 00205 * @arg @ref LL_EXTI_LINE_14 00206 * @arg @ref LL_EXTI_LINE_15 00207 * @arg @ref LL_EXTI_LINE_16 00208 * @arg @ref LL_EXTI_LINE_17 00209 * @arg @ref LL_EXTI_LINE_18 00210 * @arg @ref LL_EXTI_LINE_19 00211 * @arg @ref LL_EXTI_LINE_20 00212 * @arg @ref LL_EXTI_LINE_21 00213 * @arg @ref LL_EXTI_LINE_22 00214 * @arg @ref LL_EXTI_LINE_23 00215 * @arg @ref LL_EXTI_LINE_24 00216 * @arg @ref LL_EXTI_LINE_25 00217 * @arg @ref LL_EXTI_LINE_26 00218 * @arg @ref LL_EXTI_LINE_27 00219 * @arg @ref LL_EXTI_LINE_28 00220 * @arg @ref LL_EXTI_LINE_29 00221 * @arg @ref LL_EXTI_LINE_30 00222 * @arg @ref LL_EXTI_LINE_31 00223 * @arg @ref LL_EXTI_LINE_ALL_0_31 00224 * @retval None 00225 */ 00226 __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) 00227 { 00228 SET_BIT(EXTI->IMR1, ExtiLine); 00229 } 00230 /** 00231 * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63 00232 * @note The reset value for the direct lines (lines from 32 to 34, line 00233 * 39) is set to 1 in order to enable the interrupt by default. 00234 * Bits are set automatically at Power on. 00235 * @rmtoll IMR2 IMx LL_EXTI_EnableIT_32_63 00236 * @param ExtiLine This parameter can be one of the following values: 00237 * @arg @ref LL_EXTI_LINE_32 00238 * @arg @ref LL_EXTI_LINE_33 00239 * @arg @ref LL_EXTI_LINE_34 00240 * @arg @ref LL_EXTI_LINE_35 00241 * @arg @ref LL_EXTI_LINE_36 00242 * @arg @ref LL_EXTI_LINE_37 00243 * @arg @ref LL_EXTI_LINE_38 00244 * @arg @ref LL_EXTI_LINE_39 00245 * @arg @ref LL_EXTI_LINE_ALL_32_63 00246 * @retval None 00247 */ 00248 __STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) 00249 { 00250 SET_BIT(EXTI->IMR2, ExtiLine); 00251 } 00252 00253 /** 00254 * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 00255 * @note The reset value for the direct lines (line 17, lines from 23 to 31) 00256 * is set to 1 in order to enable the interrupt by default. 00257 * Bits are set automatically at Power on. 00258 * @rmtoll IMR1 IMx LL_EXTI_DisableIT_0_31 00259 * @param ExtiLine This parameter can be one of the following values: 00260 * @arg @ref LL_EXTI_LINE_0 00261 * @arg @ref LL_EXTI_LINE_1 00262 * @arg @ref LL_EXTI_LINE_2 00263 * @arg @ref LL_EXTI_LINE_3 00264 * @arg @ref LL_EXTI_LINE_4 00265 * @arg @ref LL_EXTI_LINE_5 00266 * @arg @ref LL_EXTI_LINE_6 00267 * @arg @ref LL_EXTI_LINE_7 00268 * @arg @ref LL_EXTI_LINE_8 00269 * @arg @ref LL_EXTI_LINE_9 00270 * @arg @ref LL_EXTI_LINE_10 00271 * @arg @ref LL_EXTI_LINE_11 00272 * @arg @ref LL_EXTI_LINE_12 00273 * @arg @ref LL_EXTI_LINE_13 00274 * @arg @ref LL_EXTI_LINE_14 00275 * @arg @ref LL_EXTI_LINE_15 00276 * @arg @ref LL_EXTI_LINE_16 00277 * @arg @ref LL_EXTI_LINE_17 00278 * @arg @ref LL_EXTI_LINE_18 00279 * @arg @ref LL_EXTI_LINE_19 00280 * @arg @ref LL_EXTI_LINE_20 00281 * @arg @ref LL_EXTI_LINE_21 00282 * @arg @ref LL_EXTI_LINE_22 00283 * @arg @ref LL_EXTI_LINE_23 00284 * @arg @ref LL_EXTI_LINE_24 00285 * @arg @ref LL_EXTI_LINE_25 00286 * @arg @ref LL_EXTI_LINE_26 00287 * @arg @ref LL_EXTI_LINE_27 00288 * @arg @ref LL_EXTI_LINE_28 00289 * @arg @ref LL_EXTI_LINE_29 00290 * @arg @ref LL_EXTI_LINE_30 00291 * @arg @ref LL_EXTI_LINE_31 00292 * @arg @ref LL_EXTI_LINE_ALL_0_31 00293 * @retval None 00294 */ 00295 __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) 00296 { 00297 CLEAR_BIT(EXTI->IMR1, ExtiLine); 00298 } 00299 00300 /** 00301 * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63 00302 * @note The reset value for the direct lines (lines from 32 to 34, line 00303 * 39) is set to 1 in order to enable the interrupt by default. 00304 * Bits are set automatically at Power on. 00305 * @rmtoll IMR2 IMx LL_EXTI_DisableIT_32_63 00306 * @param ExtiLine This parameter can be one of the following values: 00307 * @arg @ref LL_EXTI_LINE_32 00308 * @arg @ref LL_EXTI_LINE_33 00309 * @arg @ref LL_EXTI_LINE_34 00310 * @arg @ref LL_EXTI_LINE_35 00311 * @arg @ref LL_EXTI_LINE_36 00312 * @arg @ref LL_EXTI_LINE_37 00313 * @arg @ref LL_EXTI_LINE_38 00314 * @arg @ref LL_EXTI_LINE_39 00315 * @arg @ref LL_EXTI_LINE_ALL_32_63 00316 * @retval None 00317 */ 00318 __STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine) 00319 { 00320 CLEAR_BIT(EXTI->IMR2, ExtiLine); 00321 } 00322 00323 /** 00324 * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 00325 * @note The reset value for the direct lines (line 17, lines from 23 to 31) 00326 * is set to 1 in order to enable the interrupt by default. 00327 * Bits are set automatically at Power on. 00328 * @rmtoll IMR1 IMx LL_EXTI_IsEnabledIT_0_31 00329 * @param ExtiLine This parameter can be one of the following values: 00330 * @arg @ref LL_EXTI_LINE_0 00331 * @arg @ref LL_EXTI_LINE_1 00332 * @arg @ref LL_EXTI_LINE_2 00333 * @arg @ref LL_EXTI_LINE_3 00334 * @arg @ref LL_EXTI_LINE_4 00335 * @arg @ref LL_EXTI_LINE_5 00336 * @arg @ref LL_EXTI_LINE_6 00337 * @arg @ref LL_EXTI_LINE_7 00338 * @arg @ref LL_EXTI_LINE_8 00339 * @arg @ref LL_EXTI_LINE_9 00340 * @arg @ref LL_EXTI_LINE_10 00341 * @arg @ref LL_EXTI_LINE_11 00342 * @arg @ref LL_EXTI_LINE_12 00343 * @arg @ref LL_EXTI_LINE_13 00344 * @arg @ref LL_EXTI_LINE_14 00345 * @arg @ref LL_EXTI_LINE_15 00346 * @arg @ref LL_EXTI_LINE_16 00347 * @arg @ref LL_EXTI_LINE_17 00348 * @arg @ref LL_EXTI_LINE_18 00349 * @arg @ref LL_EXTI_LINE_19 00350 * @arg @ref LL_EXTI_LINE_20 00351 * @arg @ref LL_EXTI_LINE_21 00352 * @arg @ref LL_EXTI_LINE_22 00353 * @arg @ref LL_EXTI_LINE_23 00354 * @arg @ref LL_EXTI_LINE_24 00355 * @arg @ref LL_EXTI_LINE_25 00356 * @arg @ref LL_EXTI_LINE_26 00357 * @arg @ref LL_EXTI_LINE_27 00358 * @arg @ref LL_EXTI_LINE_28 00359 * @arg @ref LL_EXTI_LINE_29 00360 * @arg @ref LL_EXTI_LINE_30 00361 * @arg @ref LL_EXTI_LINE_31 00362 * @arg @ref LL_EXTI_LINE_ALL_0_31 00363 * @retval State of bit (1 or 0). 00364 */ 00365 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) 00366 { 00367 return (READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)); 00368 } 00369 00370 /** 00371 * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 00372 * @note The reset value for the direct lines (lines from 32 to 34, line 00373 * 39) is set to 1 in order to enable the interrupt by default. 00374 * Bits are set automatically at Power on. 00375 * @rmtoll IMR2 IMx LL_EXTI_IsEnabledIT_32_63 00376 * @param ExtiLine This parameter can be one of the following values: 00377 * @arg @ref LL_EXTI_LINE_32 00378 * @arg @ref LL_EXTI_LINE_33 00379 * @arg @ref LL_EXTI_LINE_34 00380 * @arg @ref LL_EXTI_LINE_35 00381 * @arg @ref LL_EXTI_LINE_36 00382 * @arg @ref LL_EXTI_LINE_37 00383 * @arg @ref LL_EXTI_LINE_38 00384 * @arg @ref LL_EXTI_LINE_39 00385 * @arg @ref LL_EXTI_LINE_ALL_32_63 00386 * @retval State of bit (1 or 0). 00387 */ 00388 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) 00389 { 00390 return (READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)); 00391 } 00392 00393 /** 00394 * @} 00395 */ 00396 00397 /** @defgroup EXTI_LL_EF_Event_Management Event_Management 00398 * @{ 00399 */ 00400 00401 /** 00402 * @brief Enable ExtiLine Event request for Lines in range 0 to 31 00403 * @rmtoll EMR1 EMx LL_EXTI_EnableEvent_0_31 00404 * @param ExtiLine This parameter can be a combination of the following values: 00405 * @arg @ref LL_EXTI_LINE_0 00406 * @arg @ref LL_EXTI_LINE_1 00407 * @arg @ref LL_EXTI_LINE_2 00408 * @arg @ref LL_EXTI_LINE_3 00409 * @arg @ref LL_EXTI_LINE_4 00410 * @arg @ref LL_EXTI_LINE_5 00411 * @arg @ref LL_EXTI_LINE_6 00412 * @arg @ref LL_EXTI_LINE_7 00413 * @arg @ref LL_EXTI_LINE_8 00414 * @arg @ref LL_EXTI_LINE_9 00415 * @arg @ref LL_EXTI_LINE_10 00416 * @arg @ref LL_EXTI_LINE_11 00417 * @arg @ref LL_EXTI_LINE_12 00418 * @arg @ref LL_EXTI_LINE_13 00419 * @arg @ref LL_EXTI_LINE_14 00420 * @arg @ref LL_EXTI_LINE_15 00421 * @arg @ref LL_EXTI_LINE_16 00422 * @arg @ref LL_EXTI_LINE_17 00423 * @arg @ref LL_EXTI_LINE_18 00424 * @arg @ref LL_EXTI_LINE_19 00425 * @arg @ref LL_EXTI_LINE_20 00426 * @arg @ref LL_EXTI_LINE_21 00427 * @arg @ref LL_EXTI_LINE_22 00428 * @arg @ref LL_EXTI_LINE_23 00429 * @arg @ref LL_EXTI_LINE_24 00430 * @arg @ref LL_EXTI_LINE_25 00431 * @arg @ref LL_EXTI_LINE_26 00432 * @arg @ref LL_EXTI_LINE_27 00433 * @arg @ref LL_EXTI_LINE_28 00434 * @arg @ref LL_EXTI_LINE_29 00435 * @arg @ref LL_EXTI_LINE_30 00436 * @arg @ref LL_EXTI_LINE_31 00437 * @arg @ref LL_EXTI_LINE_ALL_0_31 00438 * @retval None 00439 */ 00440 __STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) 00441 { 00442 SET_BIT(EXTI->EMR1, ExtiLine); 00443 00444 } 00445 00446 /** 00447 * @brief Enable ExtiLine Event request for Lines in range 32 to 63 00448 * @rmtoll EMR2 EMx LL_EXTI_EnableEvent_32_63 00449 * @param ExtiLine This parameter can be a combination of the following values: 00450 * @arg @ref LL_EXTI_LINE_32 00451 * @arg @ref LL_EXTI_LINE_33 00452 * @arg @ref LL_EXTI_LINE_34 00453 * @arg @ref LL_EXTI_LINE_35 00454 * @arg @ref LL_EXTI_LINE_36 00455 * @arg @ref LL_EXTI_LINE_37 00456 * @arg @ref LL_EXTI_LINE_38 00457 * @arg @ref LL_EXTI_LINE_39 00458 * @arg @ref LL_EXTI_LINE_ALL_32_63 00459 * @retval None 00460 */ 00461 __STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine) 00462 { 00463 SET_BIT(EXTI->EMR2, ExtiLine); 00464 } 00465 00466 /** 00467 * @brief Disable ExtiLine Event request for Lines in range 0 to 31 00468 * @rmtoll EMR1 EMx LL_EXTI_DisableEvent_0_31 00469 * @param ExtiLine This parameter can be a combination of the following values: 00470 * @arg @ref LL_EXTI_LINE_0 00471 * @arg @ref LL_EXTI_LINE_1 00472 * @arg @ref LL_EXTI_LINE_2 00473 * @arg @ref LL_EXTI_LINE_3 00474 * @arg @ref LL_EXTI_LINE_4 00475 * @arg @ref LL_EXTI_LINE_5 00476 * @arg @ref LL_EXTI_LINE_6 00477 * @arg @ref LL_EXTI_LINE_7 00478 * @arg @ref LL_EXTI_LINE_8 00479 * @arg @ref LL_EXTI_LINE_9 00480 * @arg @ref LL_EXTI_LINE_10 00481 * @arg @ref LL_EXTI_LINE_11 00482 * @arg @ref LL_EXTI_LINE_12 00483 * @arg @ref LL_EXTI_LINE_13 00484 * @arg @ref LL_EXTI_LINE_14 00485 * @arg @ref LL_EXTI_LINE_15 00486 * @arg @ref LL_EXTI_LINE_16 00487 * @arg @ref LL_EXTI_LINE_17 00488 * @arg @ref LL_EXTI_LINE_18 00489 * @arg @ref LL_EXTI_LINE_19 00490 * @arg @ref LL_EXTI_LINE_20 00491 * @arg @ref LL_EXTI_LINE_21 00492 * @arg @ref LL_EXTI_LINE_22 00493 * @arg @ref LL_EXTI_LINE_23 00494 * @arg @ref LL_EXTI_LINE_24 00495 * @arg @ref LL_EXTI_LINE_25 00496 * @arg @ref LL_EXTI_LINE_26 00497 * @arg @ref LL_EXTI_LINE_27 00498 * @arg @ref LL_EXTI_LINE_28 00499 * @arg @ref LL_EXTI_LINE_29 00500 * @arg @ref LL_EXTI_LINE_30 00501 * @arg @ref LL_EXTI_LINE_31 00502 * @arg @ref LL_EXTI_LINE_ALL 00503 * @retval None 00504 */ 00505 __STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) 00506 { 00507 CLEAR_BIT(EXTI->EMR1, ExtiLine); 00508 } 00509 00510 /** 00511 * @brief Disable ExtiLine Event request for Lines in range 32 to 63 00512 * @rmtoll EMR2 EMx LL_EXTI_DisableEvent_32_63 00513 * @param ExtiLine This parameter can be a combination of the following values: 00514 * @arg @ref LL_EXTI_LINE_32 00515 * @arg @ref LL_EXTI_LINE_33 00516 * @arg @ref LL_EXTI_LINE_34 00517 * @arg @ref LL_EXTI_LINE_35 00518 * @arg @ref LL_EXTI_LINE_36 00519 * @arg @ref LL_EXTI_LINE_37 00520 * @arg @ref LL_EXTI_LINE_38 00521 * @arg @ref LL_EXTI_LINE_39 00522 * @arg @ref LL_EXTI_LINE_ALL_32_63 00523 * @retval None 00524 */ 00525 __STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine) 00526 { 00527 CLEAR_BIT(EXTI->EMR2, ExtiLine); 00528 } 00529 00530 /** 00531 * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 00532 * @rmtoll EMR1 EMx LL_EXTI_IsEnabledEvent_0_31 00533 * @param ExtiLine This parameter can be a combination of the following values: 00534 * @arg @ref LL_EXTI_LINE_0 00535 * @arg @ref LL_EXTI_LINE_1 00536 * @arg @ref LL_EXTI_LINE_2 00537 * @arg @ref LL_EXTI_LINE_3 00538 * @arg @ref LL_EXTI_LINE_4 00539 * @arg @ref LL_EXTI_LINE_5 00540 * @arg @ref LL_EXTI_LINE_6 00541 * @arg @ref LL_EXTI_LINE_7 00542 * @arg @ref LL_EXTI_LINE_8 00543 * @arg @ref LL_EXTI_LINE_9 00544 * @arg @ref LL_EXTI_LINE_10 00545 * @arg @ref LL_EXTI_LINE_11 00546 * @arg @ref LL_EXTI_LINE_12 00547 * @arg @ref LL_EXTI_LINE_13 00548 * @arg @ref LL_EXTI_LINE_14 00549 * @arg @ref LL_EXTI_LINE_15 00550 * @arg @ref LL_EXTI_LINE_16 00551 * @arg @ref LL_EXTI_LINE_17 00552 * @arg @ref LL_EXTI_LINE_18 00553 * @arg @ref LL_EXTI_LINE_19 00554 * @arg @ref LL_EXTI_LINE_20 00555 * @arg @ref LL_EXTI_LINE_21 00556 * @arg @ref LL_EXTI_LINE_22 00557 * @arg @ref LL_EXTI_LINE_23 00558 * @arg @ref LL_EXTI_LINE_24 00559 * @arg @ref LL_EXTI_LINE_25 00560 * @arg @ref LL_EXTI_LINE_26 00561 * @arg @ref LL_EXTI_LINE_27 00562 * @arg @ref LL_EXTI_LINE_28 00563 * @arg @ref LL_EXTI_LINE_29 00564 * @arg @ref LL_EXTI_LINE_30 00565 * @arg @ref LL_EXTI_LINE_31 00566 * @arg @ref LL_EXTI_LINE_ALL_0_31 00567 * @retval State of bit (1 or 0). 00568 */ 00569 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) 00570 { 00571 return (READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)); 00572 00573 } 00574 00575 /** 00576 * @brief Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63 00577 * @rmtoll EMR2 EMx LL_EXTI_IsEnabledEvent_32_63 00578 * @param ExtiLine This parameter can be a combination of the following values: 00579 * @arg @ref LL_EXTI_LINE_32 00580 * @arg @ref LL_EXTI_LINE_33 00581 * @arg @ref LL_EXTI_LINE_34 00582 * @arg @ref LL_EXTI_LINE_35 00583 * @arg @ref LL_EXTI_LINE_36 00584 * @arg @ref LL_EXTI_LINE_37 00585 * @arg @ref LL_EXTI_LINE_38 00586 * @arg @ref LL_EXTI_LINE_39 00587 * @arg @ref LL_EXTI_LINE_ALL_32_63 00588 * @retval State of bit (1 or 0). 00589 */ 00590 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) 00591 { 00592 return (READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)); 00593 } 00594 00595 /** 00596 * @} 00597 */ 00598 00599 /** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management 00600 * @{ 00601 */ 00602 00603 /** 00604 * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 00605 * @note The configurable wakeup lines are edge-triggered. No glitch must be 00606 * generated on these lines. If a rising edge on a configurable interrupt 00607 * line occurs during a write operation in the EXTI_RTSR register, the 00608 * pending bit is not set. 00609 * Rising and falling edge triggers can be set for 00610 * the same interrupt line. In this case, both generate a trigger 00611 * condition. 00612 * @rmtoll RTSR1 RTx LL_EXTI_EnableRisingTrig_0_31 00613 * @param ExtiLine This parameter can be a combination of the following values: 00614 * @arg @ref LL_EXTI_LINE_0 00615 * @arg @ref LL_EXTI_LINE_1 00616 * @arg @ref LL_EXTI_LINE_2 00617 * @arg @ref LL_EXTI_LINE_3 00618 * @arg @ref LL_EXTI_LINE_4 00619 * @arg @ref LL_EXTI_LINE_5 00620 * @arg @ref LL_EXTI_LINE_6 00621 * @arg @ref LL_EXTI_LINE_7 00622 * @arg @ref LL_EXTI_LINE_8 00623 * @arg @ref LL_EXTI_LINE_9 00624 * @arg @ref LL_EXTI_LINE_10 00625 * @arg @ref LL_EXTI_LINE_11 00626 * @arg @ref LL_EXTI_LINE_12 00627 * @arg @ref LL_EXTI_LINE_13 00628 * @arg @ref LL_EXTI_LINE_14 00629 * @arg @ref LL_EXTI_LINE_15 00630 * @arg @ref LL_EXTI_LINE_16 00631 * @arg @ref LL_EXTI_LINE_18 00632 * @arg @ref LL_EXTI_LINE_19 00633 * @arg @ref LL_EXTI_LINE_20 00634 * @arg @ref LL_EXTI_LINE_21 00635 * @arg @ref LL_EXTI_LINE_22 00636 * @retval None 00637 */ 00638 __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) 00639 { 00640 SET_BIT(EXTI->RTSR1, ExtiLine); 00641 00642 } 00643 00644 /** 00645 * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63 00646 * @note The configurable wakeup lines are edge-triggered. No glitch must be 00647 * generated on these lines. If a rising edge on a configurable interrupt 00648 * line occurs during a write operation in the EXTI_RTSR register, the 00649 * pending bit is not set.Rising and falling edge triggers can be set for 00650 * the same interrupt line. In this case, both generate a trigger 00651 * condition. 00652 * @rmtoll RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63 00653 * @param ExtiLine This parameter can be a combination of the following values: 00654 * @arg @ref LL_EXTI_LINE_35 00655 * @arg @ref LL_EXTI_LINE_36 00656 * @arg @ref LL_EXTI_LINE_37 00657 * @arg @ref LL_EXTI_LINE_38 00658 * @retval None 00659 */ 00660 __STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine) 00661 { 00662 SET_BIT(EXTI->RTSR2, ExtiLine); 00663 } 00664 00665 /** 00666 * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 00667 * @note The configurable wakeup lines are edge-triggered. No glitch must be 00668 * generated on these lines. If a rising edge on a configurable interrupt 00669 * line occurs during a write operation in the EXTI_RTSR register, the 00670 * pending bit is not set. 00671 * Rising and falling edge triggers can be set for 00672 * the same interrupt line. In this case, both generate a trigger 00673 * condition. 00674 * @rmtoll RTSR1 RTx LL_EXTI_DisableRisingTrig_0_31 00675 * @param ExtiLine This parameter can be a combination of the following values: 00676 * @arg @ref LL_EXTI_LINE_0 00677 * @arg @ref LL_EXTI_LINE_1 00678 * @arg @ref LL_EXTI_LINE_2 00679 * @arg @ref LL_EXTI_LINE_3 00680 * @arg @ref LL_EXTI_LINE_4 00681 * @arg @ref LL_EXTI_LINE_5 00682 * @arg @ref LL_EXTI_LINE_6 00683 * @arg @ref LL_EXTI_LINE_7 00684 * @arg @ref LL_EXTI_LINE_8 00685 * @arg @ref LL_EXTI_LINE_9 00686 * @arg @ref LL_EXTI_LINE_10 00687 * @arg @ref LL_EXTI_LINE_11 00688 * @arg @ref LL_EXTI_LINE_12 00689 * @arg @ref LL_EXTI_LINE_13 00690 * @arg @ref LL_EXTI_LINE_14 00691 * @arg @ref LL_EXTI_LINE_15 00692 * @arg @ref LL_EXTI_LINE_16 00693 * @arg @ref LL_EXTI_LINE_18 00694 * @arg @ref LL_EXTI_LINE_19 00695 * @arg @ref LL_EXTI_LINE_20 00696 * @arg @ref LL_EXTI_LINE_21 00697 * @arg @ref LL_EXTI_LINE_22 00698 * @retval None 00699 */ 00700 __STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) 00701 { 00702 CLEAR_BIT(EXTI->RTSR1, ExtiLine); 00703 00704 } 00705 00706 /** 00707 * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63 00708 * @note The configurable wakeup lines are edge-triggered. No glitch must be 00709 * generated on these lines. If a rising edge on a configurable interrupt 00710 * line occurs during a write operation in the EXTI_RTSR register, the 00711 * pending bit is not set. 00712 * Rising and falling edge triggers can be set for 00713 * the same interrupt line. In this case, both generate a trigger 00714 * condition. 00715 * @rmtoll RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63 00716 * @param ExtiLine This parameter can be a combination of the following values: 00717 * @arg @ref LL_EXTI_LINE_35 00718 * @arg @ref LL_EXTI_LINE_36 00719 * @arg @ref LL_EXTI_LINE_37 00720 * @arg @ref LL_EXTI_LINE_38 00721 * @retval None 00722 */ 00723 __STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine) 00724 { 00725 CLEAR_BIT(EXTI->RTSR2, ExtiLine); 00726 } 00727 00728 /** 00729 * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 00730 * @rmtoll RTSR1 RTx LL_EXTI_IsEnabledRisingTrig_0_31 00731 * @param ExtiLine This parameter can be a combination of the following values: 00732 * @arg @ref LL_EXTI_LINE_0 00733 * @arg @ref LL_EXTI_LINE_1 00734 * @arg @ref LL_EXTI_LINE_2 00735 * @arg @ref LL_EXTI_LINE_3 00736 * @arg @ref LL_EXTI_LINE_4 00737 * @arg @ref LL_EXTI_LINE_5 00738 * @arg @ref LL_EXTI_LINE_6 00739 * @arg @ref LL_EXTI_LINE_7 00740 * @arg @ref LL_EXTI_LINE_8 00741 * @arg @ref LL_EXTI_LINE_9 00742 * @arg @ref LL_EXTI_LINE_10 00743 * @arg @ref LL_EXTI_LINE_11 00744 * @arg @ref LL_EXTI_LINE_12 00745 * @arg @ref LL_EXTI_LINE_13 00746 * @arg @ref LL_EXTI_LINE_14 00747 * @arg @ref LL_EXTI_LINE_15 00748 * @arg @ref LL_EXTI_LINE_16 00749 * @arg @ref LL_EXTI_LINE_18 00750 * @arg @ref LL_EXTI_LINE_19 00751 * @arg @ref LL_EXTI_LINE_20 00752 * @arg @ref LL_EXTI_LINE_21 00753 * @arg @ref LL_EXTI_LINE_22 00754 * @retval State of bit (1 or 0). 00755 */ 00756 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) 00757 { 00758 return (READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)); 00759 } 00760 00761 /** 00762 * @brief Check if rising edge trigger is enabled for Lines in range 32 to 63 00763 * @rmtoll RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63 00764 * @param ExtiLine This parameter can be a combination of the following values: 00765 * @arg @ref LL_EXTI_LINE_35 00766 * @arg @ref LL_EXTI_LINE_36 00767 * @arg @ref LL_EXTI_LINE_37 00768 * @arg @ref LL_EXTI_LINE_38 00769 * @retval State of bit (1 or 0). 00770 */ 00771 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine) 00772 { 00773 return (READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)); 00774 } 00775 00776 /** 00777 * @} 00778 */ 00779 00780 /** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management 00781 * @{ 00782 */ 00783 00784 /** 00785 * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 00786 * @note The configurable wakeup lines are edge-triggered. No glitch must be 00787 * generated on these lines. If a falling edge on a configurable interrupt 00788 * line occurs during a write operation in the EXTI_FTSR register, the 00789 * pending bit is not set. 00790 * Rising and falling edge triggers can be set for 00791 * the same interrupt line. In this case, both generate a trigger 00792 * condition. 00793 * @rmtoll FTSR1 FTx LL_EXTI_EnableFallingTrig_0_31 00794 * @param ExtiLine This parameter can be a combination of the following values: 00795 * @arg @ref LL_EXTI_LINE_0 00796 * @arg @ref LL_EXTI_LINE_1 00797 * @arg @ref LL_EXTI_LINE_2 00798 * @arg @ref LL_EXTI_LINE_3 00799 * @arg @ref LL_EXTI_LINE_4 00800 * @arg @ref LL_EXTI_LINE_5 00801 * @arg @ref LL_EXTI_LINE_6 00802 * @arg @ref LL_EXTI_LINE_7 00803 * @arg @ref LL_EXTI_LINE_8 00804 * @arg @ref LL_EXTI_LINE_9 00805 * @arg @ref LL_EXTI_LINE_10 00806 * @arg @ref LL_EXTI_LINE_11 00807 * @arg @ref LL_EXTI_LINE_12 00808 * @arg @ref LL_EXTI_LINE_13 00809 * @arg @ref LL_EXTI_LINE_14 00810 * @arg @ref LL_EXTI_LINE_15 00811 * @arg @ref LL_EXTI_LINE_16 00812 * @arg @ref LL_EXTI_LINE_18 00813 * @arg @ref LL_EXTI_LINE_19 00814 * @arg @ref LL_EXTI_LINE_20 00815 * @arg @ref LL_EXTI_LINE_21 00816 * @arg @ref LL_EXTI_LINE_22 00817 * @retval None 00818 */ 00819 __STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) 00820 { 00821 SET_BIT(EXTI->FTSR1, ExtiLine); 00822 } 00823 00824 /** 00825 * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63 00826 * @note The configurable wakeup lines are edge-triggered. No glitch must be 00827 * generated on these lines. If a Falling edge on a configurable interrupt 00828 * line occurs during a write operation in the EXTI_FTSR register, the 00829 * pending bit is not set. 00830 * Rising and falling edge triggers can be set for 00831 * the same interrupt line. In this case, both generate a trigger 00832 * condition. 00833 * @rmtoll FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63 00834 * @param ExtiLine This parameter can be a combination of the following values: 00835 * @arg @ref LL_EXTI_LINE_35 00836 * @arg @ref LL_EXTI_LINE_36 00837 * @arg @ref LL_EXTI_LINE_37 00838 * @arg @ref LL_EXTI_LINE_38 00839 * @retval None 00840 */ 00841 __STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine) 00842 { 00843 SET_BIT(EXTI->FTSR2, ExtiLine); 00844 } 00845 00846 /** 00847 * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 00848 * @note The configurable wakeup lines are edge-triggered. No glitch must be 00849 * generated on these lines. If a Falling edge on a configurable interrupt 00850 * line occurs during a write operation in the EXTI_FTSR register, the 00851 * pending bit is not set. 00852 * Rising and falling edge triggers can be set for the same interrupt line. 00853 * In this case, both generate a trigger condition. 00854 * @rmtoll FTSR1 FTx LL_EXTI_DisableFallingTrig_0_31 00855 * @param ExtiLine This parameter can be a combination of the following values: 00856 * @arg @ref LL_EXTI_LINE_0 00857 * @arg @ref LL_EXTI_LINE_1 00858 * @arg @ref LL_EXTI_LINE_2 00859 * @arg @ref LL_EXTI_LINE_3 00860 * @arg @ref LL_EXTI_LINE_4 00861 * @arg @ref LL_EXTI_LINE_5 00862 * @arg @ref LL_EXTI_LINE_6 00863 * @arg @ref LL_EXTI_LINE_7 00864 * @arg @ref LL_EXTI_LINE_8 00865 * @arg @ref LL_EXTI_LINE_9 00866 * @arg @ref LL_EXTI_LINE_10 00867 * @arg @ref LL_EXTI_LINE_11 00868 * @arg @ref LL_EXTI_LINE_12 00869 * @arg @ref LL_EXTI_LINE_13 00870 * @arg @ref LL_EXTI_LINE_14 00871 * @arg @ref LL_EXTI_LINE_15 00872 * @arg @ref LL_EXTI_LINE_16 00873 * @arg @ref LL_EXTI_LINE_18 00874 * @arg @ref LL_EXTI_LINE_19 00875 * @arg @ref LL_EXTI_LINE_20 00876 * @arg @ref LL_EXTI_LINE_21 00877 * @arg @ref LL_EXTI_LINE_22 00878 * @retval None 00879 */ 00880 __STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) 00881 { 00882 CLEAR_BIT(EXTI->FTSR1, ExtiLine); 00883 } 00884 00885 /** 00886 * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63 00887 * @note The configurable wakeup lines are edge-triggered. No glitch must be 00888 * generated on these lines. If a Falling edge on a configurable interrupt 00889 * line occurs during a write operation in the EXTI_FTSR register, the 00890 * pending bit is not set. 00891 * Rising and falling edge triggers can be set for the same interrupt line. 00892 * In this case, both generate a trigger condition. 00893 * @rmtoll FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63 00894 * @param ExtiLine This parameter can be a combination of the following values: 00895 * @arg @ref LL_EXTI_LINE_35 00896 * @arg @ref LL_EXTI_LINE_36 00897 * @arg @ref LL_EXTI_LINE_37 00898 * @arg @ref LL_EXTI_LINE_38 00899 * @retval None 00900 */ 00901 __STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine) 00902 { 00903 CLEAR_BIT(EXTI->FTSR2, ExtiLine); 00904 } 00905 00906 /** 00907 * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 00908 * @rmtoll FTSR1 FTx LL_EXTI_IsEnabledFallingTrig_0_31 00909 * @param ExtiLine This parameter can be a combination of the following values: 00910 * @arg @ref LL_EXTI_LINE_0 00911 * @arg @ref LL_EXTI_LINE_1 00912 * @arg @ref LL_EXTI_LINE_2 00913 * @arg @ref LL_EXTI_LINE_3 00914 * @arg @ref LL_EXTI_LINE_4 00915 * @arg @ref LL_EXTI_LINE_5 00916 * @arg @ref LL_EXTI_LINE_6 00917 * @arg @ref LL_EXTI_LINE_7 00918 * @arg @ref LL_EXTI_LINE_8 00919 * @arg @ref LL_EXTI_LINE_9 00920 * @arg @ref LL_EXTI_LINE_10 00921 * @arg @ref LL_EXTI_LINE_11 00922 * @arg @ref LL_EXTI_LINE_12 00923 * @arg @ref LL_EXTI_LINE_13 00924 * @arg @ref LL_EXTI_LINE_14 00925 * @arg @ref LL_EXTI_LINE_15 00926 * @arg @ref LL_EXTI_LINE_16 00927 * @arg @ref LL_EXTI_LINE_18 00928 * @arg @ref LL_EXTI_LINE_19 00929 * @arg @ref LL_EXTI_LINE_20 00930 * @arg @ref LL_EXTI_LINE_21 00931 * @arg @ref LL_EXTI_LINE_22 00932 * @retval State of bit (1 or 0). 00933 */ 00934 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) 00935 { 00936 return (READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)); 00937 } 00938 00939 /** 00940 * @brief Check if falling edge trigger is enabled for Lines in range 32 to 63 00941 * @rmtoll FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63 00942 * @param ExtiLine This parameter can be a combination of the following values: 00943 * @arg @ref LL_EXTI_LINE_35 00944 * @arg @ref LL_EXTI_LINE_36 00945 * @arg @ref LL_EXTI_LINE_37 00946 * @arg @ref LL_EXTI_LINE_38 00947 * @retval State of bit (1 or 0). 00948 */ 00949 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine) 00950 { 00951 return (READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)); 00952 } 00953 00954 /** 00955 * @} 00956 */ 00957 00958 /** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management 00959 * @{ 00960 */ 00961 00962 /** 00963 * @brief Generate a software Interrupt Event for Lines in range 0 to 31 00964 * @note If the interrupt is enabled on this line inthe EXTI_IMR, writing a 1 to 00965 * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR 00966 * resulting in an interrupt request generation. 00967 * This bit is cleared by clearing the corresponding bit in the EXTI_PR 00968 * register (by writing a 1 into the bit) 00969 * @rmtoll SWIER1 SWIx LL_EXTI_GenerateSWI_0_31 00970 * @param ExtiLine This parameter can be a combination of the following values: 00971 * @arg @ref LL_EXTI_LINE_0 00972 * @arg @ref LL_EXTI_LINE_1 00973 * @arg @ref LL_EXTI_LINE_2 00974 * @arg @ref LL_EXTI_LINE_3 00975 * @arg @ref LL_EXTI_LINE_4 00976 * @arg @ref LL_EXTI_LINE_5 00977 * @arg @ref LL_EXTI_LINE_6 00978 * @arg @ref LL_EXTI_LINE_7 00979 * @arg @ref LL_EXTI_LINE_8 00980 * @arg @ref LL_EXTI_LINE_9 00981 * @arg @ref LL_EXTI_LINE_10 00982 * @arg @ref LL_EXTI_LINE_11 00983 * @arg @ref LL_EXTI_LINE_12 00984 * @arg @ref LL_EXTI_LINE_13 00985 * @arg @ref LL_EXTI_LINE_14 00986 * @arg @ref LL_EXTI_LINE_15 00987 * @arg @ref LL_EXTI_LINE_16 00988 * @arg @ref LL_EXTI_LINE_18 00989 * @arg @ref LL_EXTI_LINE_19 00990 * @arg @ref LL_EXTI_LINE_20 00991 * @arg @ref LL_EXTI_LINE_21 00992 * @arg @ref LL_EXTI_LINE_22 00993 * @retval None 00994 */ 00995 __STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) 00996 { 00997 SET_BIT(EXTI->SWIER1, ExtiLine); 00998 } 00999 01000 /** 01001 * @brief Generate a software Interrupt Event for Lines in range 32 to 63 01002 * @note If the interrupt is enabled on this line inthe EXTI_IMR, writing a 1 to 01003 * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR 01004 * resulting in an interrupt request generation. 01005 * This bit is cleared by clearing the corresponding bit in the EXTI_PR 01006 * register (by writing a 1 into the bit) 01007 * @rmtoll SWIER2 SWIx LL_EXTI_GenerateSWI_32_63 01008 * @param ExtiLine This parameter can be a combination of the following values: 01009 * @arg @ref LL_EXTI_LINE_35 01010 * @arg @ref LL_EXTI_LINE_36 01011 * @arg @ref LL_EXTI_LINE_37 01012 * @arg @ref LL_EXTI_LINE_38 01013 * @retval None 01014 */ 01015 __STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine) 01016 { 01017 SET_BIT(EXTI->SWIER2, ExtiLine); 01018 } 01019 01020 /** 01021 * @} 01022 */ 01023 01024 /** @defgroup EXTI_LL_EF_Flag_Management Flag_Management 01025 * @{ 01026 */ 01027 01028 /** 01029 * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 01030 * @note This bit is set when the selected edge event arrives on the interrupt 01031 * line. This bit is cleared by writing a 1 to the bit. 01032 * @rmtoll PR1 PRx LL_EXTI_IsActiveFlag_0_31 01033 * @param ExtiLine This parameter can be a combination of the following values: 01034 * @arg @ref LL_EXTI_LINE_0 01035 * @arg @ref LL_EXTI_LINE_1 01036 * @arg @ref LL_EXTI_LINE_2 01037 * @arg @ref LL_EXTI_LINE_3 01038 * @arg @ref LL_EXTI_LINE_4 01039 * @arg @ref LL_EXTI_LINE_5 01040 * @arg @ref LL_EXTI_LINE_6 01041 * @arg @ref LL_EXTI_LINE_7 01042 * @arg @ref LL_EXTI_LINE_8 01043 * @arg @ref LL_EXTI_LINE_9 01044 * @arg @ref LL_EXTI_LINE_10 01045 * @arg @ref LL_EXTI_LINE_11 01046 * @arg @ref LL_EXTI_LINE_12 01047 * @arg @ref LL_EXTI_LINE_13 01048 * @arg @ref LL_EXTI_LINE_14 01049 * @arg @ref LL_EXTI_LINE_15 01050 * @arg @ref LL_EXTI_LINE_16 01051 * @arg @ref LL_EXTI_LINE_18 01052 * @arg @ref LL_EXTI_LINE_19 01053 * @arg @ref LL_EXTI_LINE_20 01054 * @arg @ref LL_EXTI_LINE_21 01055 * @arg @ref LL_EXTI_LINE_22 01056 * @retval State of bit (1 or 0). 01057 */ 01058 __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) 01059 { 01060 return (READ_BIT(EXTI->PR1, ExtiLine) == (ExtiLine)); 01061 } 01062 01063 /** 01064 * @brief Check if the ExtLine Flag is set or not for Lines in range 32 to 63 01065 * @note This bit is set when the selected edge event arrives on the interrupt 01066 * line. This bit is cleared by writing a 1 to the bit. 01067 * @rmtoll PR2 PRx LL_EXTI_IsActiveFlag_32_63 01068 * @param ExtiLine This parameter can be a combination of the following values: 01069 * @arg @ref LL_EXTI_LINE_35 01070 * @arg @ref LL_EXTI_LINE_36 01071 * @arg @ref LL_EXTI_LINE_37 01072 * @arg @ref LL_EXTI_LINE_38 01073 * @retval State of bit (1 or 0). 01074 */ 01075 __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine) 01076 { 01077 return (READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine)); 01078 } 01079 01080 /** 01081 * @brief Read ExtLine Combination Flag for Lines in range 0 to 31 01082 * @note This bit is set when the selected edge event arrives on the interrupt 01083 * line. This bit is cleared by writing a 1 to the bit. 01084 * @rmtoll PR1 PRx LL_EXTI_ReadFlag_0_31 01085 * @param ExtiLine This parameter can be a combination of the following values: 01086 * @arg @ref LL_EXTI_LINE_0 01087 * @arg @ref LL_EXTI_LINE_1 01088 * @arg @ref LL_EXTI_LINE_2 01089 * @arg @ref LL_EXTI_LINE_3 01090 * @arg @ref LL_EXTI_LINE_4 01091 * @arg @ref LL_EXTI_LINE_5 01092 * @arg @ref LL_EXTI_LINE_6 01093 * @arg @ref LL_EXTI_LINE_7 01094 * @arg @ref LL_EXTI_LINE_8 01095 * @arg @ref LL_EXTI_LINE_9 01096 * @arg @ref LL_EXTI_LINE_10 01097 * @arg @ref LL_EXTI_LINE_11 01098 * @arg @ref LL_EXTI_LINE_12 01099 * @arg @ref LL_EXTI_LINE_13 01100 * @arg @ref LL_EXTI_LINE_14 01101 * @arg @ref LL_EXTI_LINE_15 01102 * @arg @ref LL_EXTI_LINE_16 01103 * @arg @ref LL_EXTI_LINE_18 01104 * @arg @ref LL_EXTI_LINE_19 01105 * @arg @ref LL_EXTI_LINE_20 01106 * @arg @ref LL_EXTI_LINE_21 01107 * @arg @ref LL_EXTI_LINE_22 01108 * @retval @note This bit is set when the selected edge event arrives on the interrupt 01109 */ 01110 __STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) 01111 { 01112 return (uint32_t)(READ_BIT(EXTI->PR1, ExtiLine)); 01113 } 01114 01115 01116 /** 01117 * @brief Read ExtLine Combination Flag for Lines in range 32 to 63 01118 * @note This bit is set when the selected edge event arrives on the interrupt 01119 * line. This bit is cleared by writing a 1 to the bit. 01120 * @rmtoll PR2 PRx LL_EXTI_ReadFlag_32_63 01121 * @param ExtiLine This parameter can be a combination of the following values: 01122 * @arg @ref LL_EXTI_LINE_35 01123 * @arg @ref LL_EXTI_LINE_36 01124 * @arg @ref LL_EXTI_LINE_37 01125 * @arg @ref LL_EXTI_LINE_38 01126 * @retval @note This bit is set when the selected edge event arrives on the interrupt 01127 */ 01128 __STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine) 01129 { 01130 return (uint32_t)(READ_BIT(EXTI->PR2, ExtiLine)); 01131 } 01132 01133 /** 01134 * @brief Clear ExtLine Flags for Lines in range 0 to 31 01135 * @note This bit is set when the selected edge event arrives on the interrupt 01136 * line. This bit is cleared by writing a 1 to the bit. 01137 * @rmtoll PR1 PRx LL_EXTI_ClearFlag_0_31 01138 * @param ExtiLine This parameter can be a combination of the following values: 01139 * @arg @ref LL_EXTI_LINE_0 01140 * @arg @ref LL_EXTI_LINE_1 01141 * @arg @ref LL_EXTI_LINE_2 01142 * @arg @ref LL_EXTI_LINE_3 01143 * @arg @ref LL_EXTI_LINE_4 01144 * @arg @ref LL_EXTI_LINE_5 01145 * @arg @ref LL_EXTI_LINE_6 01146 * @arg @ref LL_EXTI_LINE_7 01147 * @arg @ref LL_EXTI_LINE_8 01148 * @arg @ref LL_EXTI_LINE_9 01149 * @arg @ref LL_EXTI_LINE_10 01150 * @arg @ref LL_EXTI_LINE_11 01151 * @arg @ref LL_EXTI_LINE_12 01152 * @arg @ref LL_EXTI_LINE_13 01153 * @arg @ref LL_EXTI_LINE_14 01154 * @arg @ref LL_EXTI_LINE_15 01155 * @arg @ref LL_EXTI_LINE_16 01156 * @arg @ref LL_EXTI_LINE_18 01157 * @arg @ref LL_EXTI_LINE_19 01158 * @arg @ref LL_EXTI_LINE_20 01159 * @arg @ref LL_EXTI_LINE_21 01160 * @arg @ref LL_EXTI_LINE_22 01161 * @retval None 01162 */ 01163 __STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) 01164 { 01165 WRITE_REG(EXTI->PR1, ExtiLine); 01166 } 01167 01168 /** 01169 * @brief Clear ExtLine Flags for Lines in range 32 to 63 01170 * @note This bit is set when the selected edge event arrives on the interrupt 01171 * line. This bit is cleared by writing a 1 to the bit. 01172 * @rmtoll PR2 PRx LL_EXTI_ClearFlag_32_63 01173 * @param ExtiLine This parameter can be a combination of the following values: 01174 * @arg @ref LL_EXTI_LINE_35 01175 * @arg @ref LL_EXTI_LINE_36 01176 * @arg @ref LL_EXTI_LINE_37 01177 * @arg @ref LL_EXTI_LINE_38 01178 * @retval None 01179 */ 01180 __STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine) 01181 { 01182 WRITE_REG(EXTI->PR2, ExtiLine); 01183 } 01184 01185 /** 01186 * @} 01187 */ 01188 01189 01190 /** 01191 * @} 01192 */ 01193 01194 /** 01195 * @} 01196 */ 01197 01198 #endif /* EXTI */ 01199 01200 /** 01201 * @} 01202 */ 01203 01204 #ifdef __cplusplus 01205 } 01206 #endif 01207 01208 #endif /* __STM32L4xx_LL_EXTI_H */ 01209 01210 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 01211
Generated on Tue Jul 12 2022 11:35:16 by
1.7.2