Eric Lewiston
Hal Drivers for L4
Dependents: BSP OneHopeOnePrayer FINAL_AUDIO_RECORD AudioDemo
Fork of
STM32L4xx_HAL_Driver
by 
Senior Design: Sound Monitor
Embed:
(wiki syntax)
Show/hide line numbers
stm32l4xx_ll_dma.h
Go to the documentation of this file.
00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_dma.h 00004 * @author MCD Application Team 00005 * @version V1.1.0 00006 * @date 16-September-2015 00007 * @brief Header file of DMA LL module. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> 00012 * 00013 * Redistribution and use in source and binary forms, with or without modification, 00014 * are permitted provided that the following conditions are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright notice, 00018 * this list of conditions and the following disclaimer in the documentation 00019 * and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00021 * may be used to endorse or promote products derived from this software 00022 * without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00027 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00028 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00029 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00030 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00031 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00032 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00033 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 00038 /* Define to prevent recursive inclusion -------------------------------------*/ 00039 #ifndef __STM32L4xx_LL_DMA_H 00040 #define __STM32L4xx_LL_DMA_H 00041 00042 #ifdef __cplusplus 00043 extern "C" { 00044 #endif 00045 00046 /* Includes ------------------------------------------------------------------*/ 00047 #include "stm32l4xx.h" 00048 00049 /** @addtogroup STM32L4xx_LL_Driver 00050 * @{ 00051 */ 00052 00053 #if defined (DMA1) || defined (DMA2) 00054 00055 /** @defgroup DMA_LL DMA 00056 * @{ 00057 */ 00058 00059 /* Private types -------------------------------------------------------------*/ 00060 /* Private variables ---------------------------------------------------------*/ 00061 /** @defgroup DMA_LL_Private_Variables DMA Private Variables 00062 * @{ 00063 */ 00064 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */ 00065 static const uint8_t CHANNEL_OFFSET_TAB[] = 00066 { 00067 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), 00068 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), 00069 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), 00070 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), 00071 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), 00072 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), 00073 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE) 00074 }; 00075 /** 00076 * @} 00077 */ 00078 00079 /* Private constants ---------------------------------------------------------*/ 00080 /** @defgroup DMA_LL_Private_Constants DMA Private Constants 00081 * @{ 00082 */ 00083 /* Define used to get CSELR register offset */ 00084 #define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE) 00085 /** 00086 * @} 00087 */ 00088 00089 /* Private macros ------------------------------------------------------------*/ 00090 00091 /* Exported types ------------------------------------------------------------*/ 00092 /* Exported constants --------------------------------------------------------*/ 00093 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants 00094 * @{ 00095 */ 00096 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines 00097 * @brief Flags defines which can be used with LL_DMA_WriteReg function 00098 * @{ 00099 */ 00100 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 00101 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 00102 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 00103 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 00104 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 00105 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 00106 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 00107 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 00108 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 00109 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 00110 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 00111 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 00112 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 00113 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 00114 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 00115 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 00116 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 00117 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 00118 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 00119 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 00120 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 00121 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 00122 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 00123 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 00124 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 00125 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 00126 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 00127 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 00128 /** 00129 * @} 00130 */ 00131 00132 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines 00133 * @brief Flags defines which can be used with LL_DMA_ReadReg function 00134 * @{ 00135 */ 00136 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 00137 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 00138 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 00139 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 00140 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 00141 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 00142 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 00143 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 00144 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 00145 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 00146 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 00147 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 00148 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 00149 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 00150 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 00151 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 00152 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 00153 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 00154 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 00155 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 00156 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 00157 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 00158 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 00159 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 00160 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 00161 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 00162 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 00163 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 00164 /** 00165 * @} 00166 */ 00167 00168 /** @defgroup DMA_LL_EC_IT IT Defines 00169 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions 00170 * @{ 00171 */ 00172 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE 00173 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE 00174 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE 00175 /** 00176 * @} 00177 */ 00178 00179 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL 00180 * @{ 00181 */ 00182 #define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001) 00183 #define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002) 00184 #define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003) 00185 #define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004) 00186 #define LL_DMA_CHANNEL_5 ((uint32_t)0x00000005) 00187 #define LL_DMA_CHANNEL_6 ((uint32_t)0x00000006) 00188 #define LL_DMA_CHANNEL_7 ((uint32_t)0x00000007) 00189 /** 00190 * @} 00191 */ 00192 00193 /** @defgroup DMA_LL_EC_DIRECTION DIRECTION 00194 * @{ 00195 */ 00196 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ 00197 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ 00198 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ 00199 /** 00200 * @} 00201 */ 00202 00203 /** @defgroup DMA_LL_EC_MODE MODE 00204 * @{ 00205 */ 00206 #define LL_DMA_MODE_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */ 00207 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ 00208 /** 00209 * @} 00210 */ 00211 00212 /** @defgroup DMA_LL_EC_PERIPH PERIPH 00213 * @{ 00214 */ 00215 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ 00216 #define LL_DMA_PERIPH_NOINCREMENT ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */ 00217 /** 00218 * @} 00219 */ 00220 00221 /** @defgroup DMA_LL_EC_MEMORY MEMORY 00222 * @{ 00223 */ 00224 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ 00225 #define LL_DMA_MEMORY_NOINCREMENT ((uint32_t)0x00000000) /*!< Memory increment mode Disable */ 00226 /** 00227 * @} 00228 */ 00229 00230 /** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN 00231 * @{ 00232 */ 00233 #define LL_DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */ 00234 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ 00235 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ 00236 /** 00237 * @} 00238 */ 00239 00240 /** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN 00241 * @{ 00242 */ 00243 #define LL_DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */ 00244 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ 00245 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ 00246 /** 00247 * @} 00248 */ 00249 00250 /** @defgroup DMA_LL_EC_PRIORITY PRIORITY 00251 * @{ 00252 */ 00253 #define LL_DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */ 00254 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ 00255 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ 00256 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ 00257 /** 00258 * @} 00259 */ 00260 00261 /** @defgroup DMA_LL_EC_REQUEST REQUEST 00262 * @{ 00263 */ 00264 #define LL_DMA_REQUEST_0 ((uint32_t)0x00000000) 00265 #define LL_DMA_REQUEST_1 ((uint32_t)0x00000001) 00266 #define LL_DMA_REQUEST_2 ((uint32_t)0x00000002) 00267 #define LL_DMA_REQUEST_3 ((uint32_t)0x00000003) 00268 #define LL_DMA_REQUEST_4 ((uint32_t)0x00000004) 00269 #define LL_DMA_REQUEST_5 ((uint32_t)0x00000005) 00270 #define LL_DMA_REQUEST_6 ((uint32_t)0x00000006) 00271 #define LL_DMA_REQUEST_7 ((uint32_t)0x00000007) 00272 /** 00273 * @} 00274 */ 00275 00276 /** 00277 * @} 00278 */ 00279 00280 /* Exported macro ------------------------------------------------------------*/ 00281 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros 00282 * @{ 00283 */ 00284 00285 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros 00286 * @{ 00287 */ 00288 /** 00289 * @brief Write a value in DMA register 00290 * @param __INSTANCE__ DMA Instance 00291 * @param __REG__ Register to be written 00292 * @param __VALUE__ Value to be written in the register 00293 * @retval None 00294 */ 00295 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 00296 00297 /** 00298 * @brief Read a value in DMA register 00299 * @param __INSTANCE__ DMA Instance 00300 * @param __REG__ Register to be read 00301 * @retval Register value 00302 */ 00303 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 00304 /** 00305 * @} 00306 */ 00307 00308 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely 00309 * @{ 00310 */ 00311 /** 00312 * @brief Convert DMAx_Channely into DMAx 00313 * @param __CHANNEL_INSTANCE__ DMAx_Channely 00314 * @retval DMAx 00315 */ 00316 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ 00317 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1) 00318 00319 /** 00320 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y 00321 * @param __CHANNEL_INSTANCE__ DMAx_Channely 00322 * @retval LL_DMA_CHANNEL_y 00323 */ 00324 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ 00325 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ 00326 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ 00327 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ 00328 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ 00329 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ 00330 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ 00331 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ 00332 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ 00333 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ 00334 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ 00335 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ 00336 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \ 00337 LL_DMA_CHANNEL_7) 00338 00339 /** 00340 * @} 00341 */ 00342 00343 /** 00344 * @} 00345 */ 00346 00347 /* Exported functions --------------------------------------------------------*/ 00348 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions 00349 * @{ 00350 */ 00351 00352 /** @defgroup DMA_LL_EF_Configuration Configuration 00353 * @{ 00354 */ 00355 /** 00356 * @brief Enable DMA channel. 00357 * @rmtoll CCR EN LL_DMA_EnableChannel 00358 * @param DMAx DMAx Instance 00359 * @param Channel This parameter can be one of the following values: 00360 * @arg @ref LL_DMA_CHANNEL_1 00361 * @arg @ref LL_DMA_CHANNEL_2 00362 * @arg @ref LL_DMA_CHANNEL_3 00363 * @arg @ref LL_DMA_CHANNEL_4 00364 * @arg @ref LL_DMA_CHANNEL_5 00365 * @arg @ref LL_DMA_CHANNEL_6 00366 * @arg @ref LL_DMA_CHANNEL_7 00367 * @retval None 00368 */ 00369 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) 00370 { 00371 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1])))->CCR, DMA_CCR_EN); 00372 } 00373 00374 /** 00375 * @brief Disable DMA channel. 00376 * @rmtoll CCR EN LL_DMA_DisableChannel 00377 * @param DMAx DMAx Instance 00378 * @param Channel This parameter can be one of the following values: 00379 * @arg @ref LL_DMA_CHANNEL_1 00380 * @arg @ref LL_DMA_CHANNEL_2 00381 * @arg @ref LL_DMA_CHANNEL_3 00382 * @arg @ref LL_DMA_CHANNEL_4 00383 * @arg @ref LL_DMA_CHANNEL_5 00384 * @arg @ref LL_DMA_CHANNEL_6 00385 * @arg @ref LL_DMA_CHANNEL_7 00386 * @retval None 00387 */ 00388 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) 00389 { 00390 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1])))->CCR, DMA_CCR_EN); 00391 } 00392 00393 /** 00394 * @brief Check if DMA channel is enabled or disabled. 00395 * @rmtoll CCR EN LL_DMA_IsEnabledChannel 00396 * @param DMAx DMAx Instance 00397 * @param Channel This parameter can be one of the following values: 00398 * @arg @ref LL_DMA_CHANNEL_1 00399 * @arg @ref LL_DMA_CHANNEL_2 00400 * @arg @ref LL_DMA_CHANNEL_3 00401 * @arg @ref LL_DMA_CHANNEL_4 00402 * @arg @ref LL_DMA_CHANNEL_5 00403 * @arg @ref LL_DMA_CHANNEL_6 00404 * @arg @ref LL_DMA_CHANNEL_7 00405 * @retval State of bit (1 or 0). 00406 */ 00407 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) 00408 { 00409 return (READ_BIT(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CCR, DMA_CCR_EN) == (DMA_CCR_EN)); 00410 } 00411 00412 /** 00413 * @brief Configure all parameters link to DMA transfer. 00414 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n 00415 * CCR MEM2MEM LL_DMA_ConfigTransfer\n 00416 * CCR CIRC LL_DMA_ConfigTransfer\n 00417 * CCR PINC LL_DMA_ConfigTransfer\n 00418 * CCR MINC LL_DMA_ConfigTransfer\n 00419 * CCR PSIZE LL_DMA_ConfigTransfer\n 00420 * CCR MSIZE LL_DMA_ConfigTransfer\n 00421 * CCR PL LL_DMA_ConfigTransfer 00422 * @param DMAx DMAx Instance 00423 * @param Channel This parameter can be one of the following values: 00424 * @arg @ref LL_DMA_CHANNEL_1 00425 * @arg @ref LL_DMA_CHANNEL_2 00426 * @arg @ref LL_DMA_CHANNEL_3 00427 * @arg @ref LL_DMA_CHANNEL_4 00428 * @arg @ref LL_DMA_CHANNEL_5 00429 * @arg @ref LL_DMA_CHANNEL_6 00430 * @arg @ref LL_DMA_CHANNEL_7 00431 * @param Configuration This parameter must be a combination of all the following values: 00432 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 00433 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR 00434 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT 00435 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT 00436 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD 00437 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD 00438 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH 00439 * @retval None 00440 */ 00441 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef* DMAx, uint32_t Channel, uint32_t Configuration) 00442 { 00443 MODIFY_REG(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, Configuration); 00444 } 00445 00446 /** 00447 * @brief Set Data transfer direction (read from peripheral or from memory). 00448 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n 00449 * CCR MEM2MEM LL_DMA_SetDataTransferDirection 00450 * @param DMAx DMAx Instance 00451 * @param Channel This parameter can be one of the following values: 00452 * @arg @ref LL_DMA_CHANNEL_1 00453 * @arg @ref LL_DMA_CHANNEL_2 00454 * @arg @ref LL_DMA_CHANNEL_3 00455 * @arg @ref LL_DMA_CHANNEL_4 00456 * @arg @ref LL_DMA_CHANNEL_5 00457 * @arg @ref LL_DMA_CHANNEL_6 00458 * @arg @ref LL_DMA_CHANNEL_7 00459 * @param Direction This parameter can be one of the following values: 00460 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 00461 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 00462 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 00463 * @retval None 00464 */ 00465 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) 00466 { 00467 MODIFY_REG(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); 00468 } 00469 00470 /** 00471 * @brief Get Data transfer direction (read from peripheral or from memory). 00472 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n 00473 * CCR MEM2MEM LL_DMA_GetDataTransferDirection 00474 * @param DMAx DMAx Instance 00475 * @param Channel This parameter can be one of the following values: 00476 * @arg @ref LL_DMA_CHANNEL_1 00477 * @arg @ref LL_DMA_CHANNEL_2 00478 * @arg @ref LL_DMA_CHANNEL_3 00479 * @arg @ref LL_DMA_CHANNEL_4 00480 * @arg @ref LL_DMA_CHANNEL_5 00481 * @arg @ref LL_DMA_CHANNEL_6 00482 * @arg @ref LL_DMA_CHANNEL_7 00483 * @retval Returned value can be one of the following values: 00484 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 00485 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 00486 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 00487 */ 00488 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) 00489 { 00490 return (READ_BIT(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM)); 00491 } 00492 00493 /** 00494 * @brief Set DMA mode circular or normal. 00495 * @note The circular buffer mode cannot be used if the memory-to-memory 00496 * data transfer is configured on the selected Channel. 00497 * @rmtoll CCR CIRC LL_DMA_SetMode 00498 * @param DMAx DMAx Instance 00499 * @param Channel This parameter can be one of the following values: 00500 * @arg @ref LL_DMA_CHANNEL_1 00501 * @arg @ref LL_DMA_CHANNEL_2 00502 * @arg @ref LL_DMA_CHANNEL_3 00503 * @arg @ref LL_DMA_CHANNEL_4 00504 * @arg @ref LL_DMA_CHANNEL_5 00505 * @arg @ref LL_DMA_CHANNEL_6 00506 * @arg @ref LL_DMA_CHANNEL_7 00507 * @param Mode This parameter can be one of the following values: 00508 * @arg @ref LL_DMA_MODE_NORMAL 00509 * @arg @ref LL_DMA_MODE_CIRCULAR 00510 * @retval None 00511 */ 00512 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) 00513 { 00514 MODIFY_REG(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CCR, DMA_CCR_CIRC, Mode); 00515 } 00516 00517 /** 00518 * @brief Get DMA mode circular or normal. 00519 * @rmtoll CCR CIRC LL_DMA_GetMode 00520 * @param DMAx DMAx Instance 00521 * @param Channel This parameter can be one of the following values: 00522 * @arg @ref LL_DMA_CHANNEL_1 00523 * @arg @ref LL_DMA_CHANNEL_2 00524 * @arg @ref LL_DMA_CHANNEL_3 00525 * @arg @ref LL_DMA_CHANNEL_4 00526 * @arg @ref LL_DMA_CHANNEL_5 00527 * @arg @ref LL_DMA_CHANNEL_6 00528 * @arg @ref LL_DMA_CHANNEL_7 00529 * @retval Returned value can be one of the following values: 00530 * @arg @ref LL_DMA_MODE_NORMAL 00531 * @arg @ref LL_DMA_MODE_CIRCULAR 00532 */ 00533 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) 00534 { 00535 return (READ_BIT(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CCR, DMA_CCR_CIRC)); 00536 } 00537 00538 /** 00539 * @brief Set Peripheral increment mode. 00540 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode 00541 * @param DMAx DMAx Instance 00542 * @param Channel This parameter can be one of the following values: 00543 * @arg @ref LL_DMA_CHANNEL_1 00544 * @arg @ref LL_DMA_CHANNEL_2 00545 * @arg @ref LL_DMA_CHANNEL_3 00546 * @arg @ref LL_DMA_CHANNEL_4 00547 * @arg @ref LL_DMA_CHANNEL_5 00548 * @arg @ref LL_DMA_CHANNEL_6 00549 * @arg @ref LL_DMA_CHANNEL_7 00550 * @param IncrementMode This parameter can be one of the following values: 00551 * @arg @ref LL_DMA_PERIPH_INCREMENT 00552 * @arg @ref LL_DMA_PERIPH_NOINCREMENT 00553 * @retval None 00554 */ 00555 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t IncrementMode) 00556 { 00557 MODIFY_REG(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CCR, DMA_CCR_PINC, IncrementMode); 00558 } 00559 00560 /** 00561 * @brief Get Peripheral increment mode. 00562 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode 00563 * @param DMAx DMAx Instance 00564 * @param Channel This parameter can be one of the following values: 00565 * @arg @ref LL_DMA_CHANNEL_1 00566 * @arg @ref LL_DMA_CHANNEL_2 00567 * @arg @ref LL_DMA_CHANNEL_3 00568 * @arg @ref LL_DMA_CHANNEL_4 00569 * @arg @ref LL_DMA_CHANNEL_5 00570 * @arg @ref LL_DMA_CHANNEL_6 00571 * @arg @ref LL_DMA_CHANNEL_7 00572 * @retval Returned value can be one of the following values: 00573 * @arg @ref LL_DMA_PERIPH_INCREMENT 00574 * @arg @ref LL_DMA_PERIPH_NOINCREMENT 00575 */ 00576 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) 00577 { 00578 return (READ_BIT(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CCR, DMA_CCR_PINC)); 00579 } 00580 00581 /** 00582 * @brief Set Memory increment mode. 00583 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode 00584 * @param DMAx DMAx Instance 00585 * @param Channel This parameter can be one of the following values: 00586 * @arg @ref LL_DMA_CHANNEL_1 00587 * @arg @ref LL_DMA_CHANNEL_2 00588 * @arg @ref LL_DMA_CHANNEL_3 00589 * @arg @ref LL_DMA_CHANNEL_4 00590 * @arg @ref LL_DMA_CHANNEL_5 00591 * @arg @ref LL_DMA_CHANNEL_6 00592 * @arg @ref LL_DMA_CHANNEL_7 00593 * @param IncrementMode This parameter can be one of the following values: 00594 * @arg @ref LL_DMA_MEMORY_INCREMENT 00595 * @arg @ref LL_DMA_MEMORY_NOINCREMENT 00596 * @retval None 00597 */ 00598 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t IncrementMode) 00599 { 00600 MODIFY_REG(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CCR, DMA_CCR_MINC, IncrementMode); 00601 } 00602 00603 /** 00604 * @brief Get Memory increment mode. 00605 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode 00606 * @param DMAx DMAx Instance 00607 * @param Channel This parameter can be one of the following values: 00608 * @arg @ref LL_DMA_CHANNEL_1 00609 * @arg @ref LL_DMA_CHANNEL_2 00610 * @arg @ref LL_DMA_CHANNEL_3 00611 * @arg @ref LL_DMA_CHANNEL_4 00612 * @arg @ref LL_DMA_CHANNEL_5 00613 * @arg @ref LL_DMA_CHANNEL_6 00614 * @arg @ref LL_DMA_CHANNEL_7 00615 * @retval Returned value can be one of the following values: 00616 * @arg @ref LL_DMA_MEMORY_INCREMENT 00617 * @arg @ref LL_DMA_MEMORY_NOINCREMENT 00618 */ 00619 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) 00620 { 00621 return (READ_BIT(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CCR, DMA_CCR_MINC)); 00622 } 00623 00624 /** 00625 * @brief Set Peripheral size. 00626 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize 00627 * @param DMAx DMAx Instance 00628 * @param Channel This parameter can be one of the following values: 00629 * @arg @ref LL_DMA_CHANNEL_1 00630 * @arg @ref LL_DMA_CHANNEL_2 00631 * @arg @ref LL_DMA_CHANNEL_3 00632 * @arg @ref LL_DMA_CHANNEL_4 00633 * @arg @ref LL_DMA_CHANNEL_5 00634 * @arg @ref LL_DMA_CHANNEL_6 00635 * @arg @ref LL_DMA_CHANNEL_7 00636 * @param Size This parameter can be one of the following values: 00637 * @arg @ref LL_DMA_PDATAALIGN_BYTE 00638 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD 00639 * @arg @ref LL_DMA_PDATAALIGN_WORD 00640 * @retval None 00641 */ 00642 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Size) 00643 { 00644 MODIFY_REG(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CCR, DMA_CCR_PSIZE, Size); 00645 } 00646 00647 /** 00648 * @brief Get Peripheral size. 00649 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize 00650 * @param DMAx DMAx Instance 00651 * @param Channel This parameter can be one of the following values: 00652 * @arg @ref LL_DMA_CHANNEL_1 00653 * @arg @ref LL_DMA_CHANNEL_2 00654 * @arg @ref LL_DMA_CHANNEL_3 00655 * @arg @ref LL_DMA_CHANNEL_4 00656 * @arg @ref LL_DMA_CHANNEL_5 00657 * @arg @ref LL_DMA_CHANNEL_6 00658 * @arg @ref LL_DMA_CHANNEL_7 00659 * @retval Returned value can be one of the following values: 00660 * @arg @ref LL_DMA_PDATAALIGN_BYTE 00661 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD 00662 * @arg @ref LL_DMA_PDATAALIGN_WORD 00663 */ 00664 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) 00665 { 00666 return (READ_BIT(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CCR, DMA_CCR_PSIZE)); 00667 } 00668 00669 /** 00670 * @brief Set Memory size. 00671 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize 00672 * @param DMAx DMAx Instance 00673 * @param Channel This parameter can be one of the following values: 00674 * @arg @ref LL_DMA_CHANNEL_1 00675 * @arg @ref LL_DMA_CHANNEL_2 00676 * @arg @ref LL_DMA_CHANNEL_3 00677 * @arg @ref LL_DMA_CHANNEL_4 00678 * @arg @ref LL_DMA_CHANNEL_5 00679 * @arg @ref LL_DMA_CHANNEL_6 00680 * @arg @ref LL_DMA_CHANNEL_7 00681 * @param Size This parameter can be one of the following values: 00682 * @arg @ref LL_DMA_MDATAALIGN_BYTE 00683 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD 00684 * @arg @ref LL_DMA_MDATAALIGN_WORD 00685 * @retval None 00686 */ 00687 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Size) 00688 { 00689 MODIFY_REG(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CCR, DMA_CCR_MSIZE, Size); 00690 } 00691 00692 /** 00693 * @brief Get Memory size. 00694 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize 00695 * @param DMAx DMAx Instance 00696 * @param Channel This parameter can be one of the following values: 00697 * @arg @ref LL_DMA_CHANNEL_1 00698 * @arg @ref LL_DMA_CHANNEL_2 00699 * @arg @ref LL_DMA_CHANNEL_3 00700 * @arg @ref LL_DMA_CHANNEL_4 00701 * @arg @ref LL_DMA_CHANNEL_5 00702 * @arg @ref LL_DMA_CHANNEL_6 00703 * @arg @ref LL_DMA_CHANNEL_7 00704 * @retval Returned value can be one of the following values: 00705 * @arg @ref LL_DMA_MDATAALIGN_BYTE 00706 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD 00707 * @arg @ref LL_DMA_MDATAALIGN_WORD 00708 */ 00709 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) 00710 { 00711 return (READ_BIT(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CCR, DMA_CCR_MSIZE)); 00712 } 00713 00714 /** 00715 * @brief Set Channel priority level. 00716 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel 00717 * @param DMAx DMAx Instance 00718 * @param Channel This parameter can be one of the following values: 00719 * @arg @ref LL_DMA_CHANNEL_1 00720 * @arg @ref LL_DMA_CHANNEL_2 00721 * @arg @ref LL_DMA_CHANNEL_3 00722 * @arg @ref LL_DMA_CHANNEL_4 00723 * @arg @ref LL_DMA_CHANNEL_5 00724 * @arg @ref LL_DMA_CHANNEL_6 00725 * @arg @ref LL_DMA_CHANNEL_7 00726 * @param Priority This parameter can be one of the following values: 00727 * @arg @ref LL_DMA_PRIORITY_LOW 00728 * @arg @ref LL_DMA_PRIORITY_MEDIUM 00729 * @arg @ref LL_DMA_PRIORITY_HIGH 00730 * @arg @ref LL_DMA_PRIORITY_VERYHIGH 00731 * @retval None 00732 */ 00733 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) 00734 { 00735 MODIFY_REG(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CCR, DMA_CCR_PL, Priority); 00736 } 00737 00738 /** 00739 * @brief Get Channel priority level. 00740 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel 00741 * @param DMAx DMAx Instance 00742 * @param Channel This parameter can be one of the following values: 00743 * @arg @ref LL_DMA_CHANNEL_1 00744 * @arg @ref LL_DMA_CHANNEL_2 00745 * @arg @ref LL_DMA_CHANNEL_3 00746 * @arg @ref LL_DMA_CHANNEL_4 00747 * @arg @ref LL_DMA_CHANNEL_5 00748 * @arg @ref LL_DMA_CHANNEL_6 00749 * @arg @ref LL_DMA_CHANNEL_7 00750 * @retval Returned value can be one of the following values: 00751 * @arg @ref LL_DMA_PRIORITY_LOW 00752 * @arg @ref LL_DMA_PRIORITY_MEDIUM 00753 * @arg @ref LL_DMA_PRIORITY_HIGH 00754 * @arg @ref LL_DMA_PRIORITY_VERYHIGH 00755 */ 00756 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) 00757 { 00758 return (READ_BIT(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CCR, DMA_CCR_PL)); 00759 } 00760 00761 /** 00762 * @brief Set Number of data to transfer. 00763 * @note This action has no effect if 00764 * channel is enabled. 00765 * @rmtoll CNDTR NDT LL_DMA_SetDataLength 00766 * @param DMAx DMAx Instance 00767 * @param Channel This parameter can be one of the following values: 00768 * @arg @ref LL_DMA_CHANNEL_1 00769 * @arg @ref LL_DMA_CHANNEL_2 00770 * @arg @ref LL_DMA_CHANNEL_3 00771 * @arg @ref LL_DMA_CHANNEL_4 00772 * @arg @ref LL_DMA_CHANNEL_5 00773 * @arg @ref LL_DMA_CHANNEL_6 00774 * @arg @ref LL_DMA_CHANNEL_7 00775 * @param NbData Between 0 to 0xFFFFFFFF 00776 * @retval None 00777 */ 00778 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) 00779 { 00780 MODIFY_REG(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CNDTR, DMA_CNDTR_NDT, NbData); 00781 } 00782 00783 /** 00784 * @brief Get Number of data to transfer. 00785 * @note Once the channel is enabled, the return value indicate the 00786 * remaining bytes to be transmitted. 00787 * @rmtoll CNDTR NDT LL_DMA_GetDataLength 00788 * @param DMAx DMAx Instance 00789 * @param Channel This parameter can be one of the following values: 00790 * @arg @ref LL_DMA_CHANNEL_1 00791 * @arg @ref LL_DMA_CHANNEL_2 00792 * @arg @ref LL_DMA_CHANNEL_3 00793 * @arg @ref LL_DMA_CHANNEL_4 00794 * @arg @ref LL_DMA_CHANNEL_5 00795 * @arg @ref LL_DMA_CHANNEL_6 00796 * @arg @ref LL_DMA_CHANNEL_7 00797 * @retval Between 0 to 0xFFFFFFFF 00798 */ 00799 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) 00800 { 00801 return (READ_BIT(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CNDTR, DMA_CNDTR_NDT)); 00802 } 00803 00804 /** 00805 * @brief Configure the Source and Destination addresses. 00806 * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr) 00807 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n 00808 * CMAR MA LL_DMA_ConfigAddresses 00809 * @param DMAx DMAx Instance 00810 * @param Channel This parameter can be one of the following values: 00811 * @arg @ref LL_DMA_CHANNEL_1 00812 * @arg @ref LL_DMA_CHANNEL_2 00813 * @arg @ref LL_DMA_CHANNEL_3 00814 * @arg @ref LL_DMA_CHANNEL_4 00815 * @arg @ref LL_DMA_CHANNEL_5 00816 * @arg @ref LL_DMA_CHANNEL_6 00817 * @arg @ref LL_DMA_CHANNEL_7 00818 * @param SrcAddress Between 0 to 0xFFFFFFFF 00819 * @param DstAddress Between 0 to 0xFFFFFFFF 00820 * @param Direction This parameter can be one of the following values: 00821 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 00822 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 00823 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 00824 * @retval None 00825 */ 00826 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) 00827 { 00828 /* Direction Memory to Periph */ 00829 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) 00830 { 00831 MODIFY_REG(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CMAR, DMA_CMAR_MA, SrcAddress); 00832 MODIFY_REG(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CPAR, DMA_CPAR_PA, DstAddress); 00833 } 00834 /* Direction Periph to Memory and Memory to Memory */ 00835 else 00836 { 00837 MODIFY_REG(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CPAR, DMA_CPAR_PA, SrcAddress); 00838 MODIFY_REG(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CMAR, DMA_CMAR_MA, DstAddress); 00839 } 00840 } 00841 00842 /** 00843 * @brief Set the Memory address. 00844 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 00845 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress 00846 * @param DMAx DMAx Instance 00847 * @param Channel This parameter can be one of the following values: 00848 * @arg @ref LL_DMA_CHANNEL_1 00849 * @arg @ref LL_DMA_CHANNEL_2 00850 * @arg @ref LL_DMA_CHANNEL_3 00851 * @arg @ref LL_DMA_CHANNEL_4 00852 * @arg @ref LL_DMA_CHANNEL_5 00853 * @arg @ref LL_DMA_CHANNEL_6 00854 * @arg @ref LL_DMA_CHANNEL_7 00855 * @param MemoryAddress Between 0 to 0xFFFFFFFF 00856 * @retval None 00857 */ 00858 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Channel, uint32_t MemoryAddress) 00859 { 00860 MODIFY_REG(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CMAR, DMA_CMAR_MA, MemoryAddress); 00861 } 00862 00863 /** 00864 * @brief Set the Peripheral address. 00865 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 00866 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress 00867 * @param DMAx DMAx Instance 00868 * @param Channel This parameter can be one of the following values: 00869 * @arg @ref LL_DMA_CHANNEL_1 00870 * @arg @ref LL_DMA_CHANNEL_2 00871 * @arg @ref LL_DMA_CHANNEL_3 00872 * @arg @ref LL_DMA_CHANNEL_4 00873 * @arg @ref LL_DMA_CHANNEL_5 00874 * @arg @ref LL_DMA_CHANNEL_6 00875 * @arg @ref LL_DMA_CHANNEL_7 00876 * @param PeriphAddress Between 0 to 0xFFFFFFFF 00877 * @retval None 00878 */ 00879 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Channel, uint32_t PeriphAddress) 00880 { 00881 MODIFY_REG(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CPAR, DMA_CPAR_PA, PeriphAddress); 00882 } 00883 00884 /** 00885 * @brief Get Memory address. 00886 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 00887 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress 00888 * @param DMAx DMAx Instance 00889 * @param Channel This parameter can be one of the following values: 00890 * @arg @ref LL_DMA_CHANNEL_1 00891 * @arg @ref LL_DMA_CHANNEL_2 00892 * @arg @ref LL_DMA_CHANNEL_3 00893 * @arg @ref LL_DMA_CHANNEL_4 00894 * @arg @ref LL_DMA_CHANNEL_5 00895 * @arg @ref LL_DMA_CHANNEL_6 00896 * @arg @ref LL_DMA_CHANNEL_7 00897 * @retval Between 0 to 0xFFFFFFFF 00898 */ 00899 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Channel) 00900 { 00901 return (READ_BIT(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CMAR, DMA_CMAR_MA)); 00902 } 00903 00904 /** 00905 * @brief Get Peripheral address. 00906 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 00907 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress 00908 * @param DMAx DMAx Instance 00909 * @param Channel This parameter can be one of the following values: 00910 * @arg @ref LL_DMA_CHANNEL_1 00911 * @arg @ref LL_DMA_CHANNEL_2 00912 * @arg @ref LL_DMA_CHANNEL_3 00913 * @arg @ref LL_DMA_CHANNEL_4 00914 * @arg @ref LL_DMA_CHANNEL_5 00915 * @arg @ref LL_DMA_CHANNEL_6 00916 * @arg @ref LL_DMA_CHANNEL_7 00917 * @retval Between 0 to 0xFFFFFFFF 00918 */ 00919 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Channel) 00920 { 00921 return (READ_BIT(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CPAR, DMA_CPAR_PA)); 00922 } 00923 00924 /** 00925 * @brief Set the Memory to Memory Source address. 00926 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 00927 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress 00928 * @param DMAx DMAx Instance 00929 * @param Channel This parameter can be one of the following values: 00930 * @arg @ref LL_DMA_CHANNEL_1 00931 * @arg @ref LL_DMA_CHANNEL_2 00932 * @arg @ref LL_DMA_CHANNEL_3 00933 * @arg @ref LL_DMA_CHANNEL_4 00934 * @arg @ref LL_DMA_CHANNEL_5 00935 * @arg @ref LL_DMA_CHANNEL_6 00936 * @arg @ref LL_DMA_CHANNEL_7 00937 * @param MemoryAddress Between 0 to 0xFFFFFFFF 00938 * @retval None 00939 */ 00940 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Channel, uint32_t MemoryAddress) 00941 { 00942 MODIFY_REG(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CPAR, DMA_CPAR_PA, MemoryAddress); 00943 } 00944 00945 /** 00946 * @brief Set the Memory to Memory Destination address. 00947 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 00948 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress 00949 * @param DMAx DMAx Instance 00950 * @param Channel This parameter can be one of the following values: 00951 * @arg @ref LL_DMA_CHANNEL_1 00952 * @arg @ref LL_DMA_CHANNEL_2 00953 * @arg @ref LL_DMA_CHANNEL_3 00954 * @arg @ref LL_DMA_CHANNEL_4 00955 * @arg @ref LL_DMA_CHANNEL_5 00956 * @arg @ref LL_DMA_CHANNEL_6 00957 * @arg @ref LL_DMA_CHANNEL_7 00958 * @param MemoryAddress Between 0 to 0xFFFFFFFF 00959 * @retval None 00960 */ 00961 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Channel, uint32_t MemoryAddress) 00962 { 00963 MODIFY_REG(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CMAR, DMA_CMAR_MA, MemoryAddress); 00964 } 00965 00966 /** 00967 * @brief Get the Memory to Memory Source address. 00968 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 00969 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress 00970 * @param DMAx DMAx Instance 00971 * @param Channel This parameter can be one of the following values: 00972 * @arg @ref LL_DMA_CHANNEL_1 00973 * @arg @ref LL_DMA_CHANNEL_2 00974 * @arg @ref LL_DMA_CHANNEL_3 00975 * @arg @ref LL_DMA_CHANNEL_4 00976 * @arg @ref LL_DMA_CHANNEL_5 00977 * @arg @ref LL_DMA_CHANNEL_6 00978 * @arg @ref LL_DMA_CHANNEL_7 00979 * @retval Between 0 to 0xFFFFFFFF 00980 */ 00981 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Channel) 00982 { 00983 return (READ_BIT(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CPAR, DMA_CPAR_PA)); 00984 } 00985 00986 /** 00987 * @brief Get the Memory to Memory Destination address. 00988 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 00989 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress 00990 * @param DMAx DMAx Instance 00991 * @param Channel This parameter can be one of the following values: 00992 * @arg @ref LL_DMA_CHANNEL_1 00993 * @arg @ref LL_DMA_CHANNEL_2 00994 * @arg @ref LL_DMA_CHANNEL_3 00995 * @arg @ref LL_DMA_CHANNEL_4 00996 * @arg @ref LL_DMA_CHANNEL_5 00997 * @arg @ref LL_DMA_CHANNEL_6 00998 * @arg @ref LL_DMA_CHANNEL_7 00999 * @retval Between 0 to 0xFFFFFFFF 01000 */ 01001 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Channel) 01002 { 01003 return (READ_BIT(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CMAR, DMA_CMAR_MA)); 01004 } 01005 01006 /** 01007 * @brief Set DMA request for DMA instance on Channel x. 01008 * @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection. 01009 * @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n 01010 * CSELR C2S LL_DMA_SetPeriphRequest\n 01011 * CSELR C3S LL_DMA_SetPeriphRequest\n 01012 * CSELR C4S LL_DMA_SetPeriphRequest\n 01013 * CSELR C5S LL_DMA_SetPeriphRequest\n 01014 * CSELR C6S LL_DMA_SetPeriphRequest\n 01015 * CSELR C7S LL_DMA_SetPeriphRequest 01016 * @param DMAx DMAx Instance 01017 * @param Channel This parameter can be one of the following values: 01018 * @arg @ref LL_DMA_CHANNEL_1 01019 * @arg @ref LL_DMA_CHANNEL_2 01020 * @arg @ref LL_DMA_CHANNEL_3 01021 * @arg @ref LL_DMA_CHANNEL_4 01022 * @arg @ref LL_DMA_CHANNEL_5 01023 * @arg @ref LL_DMA_CHANNEL_6 01024 * @arg @ref LL_DMA_CHANNEL_7 01025 * @param Request This parameter can be one of the following values: 01026 * @arg @ref LL_DMA_REQUEST_0 01027 * @arg @ref LL_DMA_REQUEST_1 01028 * @arg @ref LL_DMA_REQUEST_2 01029 * @arg @ref LL_DMA_REQUEST_3 01030 * @arg @ref LL_DMA_REQUEST_4 01031 * @arg @ref LL_DMA_REQUEST_5 01032 * @arg @ref LL_DMA_REQUEST_6 01033 * @arg @ref LL_DMA_REQUEST_7 01034 * @retval None 01035 */ 01036 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) 01037 { 01038 MODIFY_REG(((DMA_request_TypeDef*)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR, DMA_CSELR_C1S << ((Channel-1)*4), Request << POSITION_VAL(DMA_CSELR_C1S << ((Channel-1)*4))); 01039 } 01040 01041 /** 01042 * @brief Get DMA request for DMA instance on Channel x. 01043 * @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n 01044 * CSELR C2S LL_DMA_GetPeriphRequest\n 01045 * CSELR C3S LL_DMA_GetPeriphRequest\n 01046 * CSELR C4S LL_DMA_GetPeriphRequest\n 01047 * CSELR C5S LL_DMA_GetPeriphRequest\n 01048 * CSELR C6S LL_DMA_GetPeriphRequest\n 01049 * CSELR C7S LL_DMA_GetPeriphRequest 01050 * @param DMAx DMAx Instance 01051 * @param Channel This parameter can be one of the following values: 01052 * @arg @ref LL_DMA_CHANNEL_1 01053 * @arg @ref LL_DMA_CHANNEL_2 01054 * @arg @ref LL_DMA_CHANNEL_3 01055 * @arg @ref LL_DMA_CHANNEL_4 01056 * @arg @ref LL_DMA_CHANNEL_5 01057 * @arg @ref LL_DMA_CHANNEL_6 01058 * @arg @ref LL_DMA_CHANNEL_7 01059 * @retval Returned value can be one of the following values: 01060 * @arg @ref LL_DMA_REQUEST_0 01061 * @arg @ref LL_DMA_REQUEST_1 01062 * @arg @ref LL_DMA_REQUEST_2 01063 * @arg @ref LL_DMA_REQUEST_3 01064 * @arg @ref LL_DMA_REQUEST_4 01065 * @arg @ref LL_DMA_REQUEST_5 01066 * @arg @ref LL_DMA_REQUEST_6 01067 * @arg @ref LL_DMA_REQUEST_7 01068 */ 01069 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) 01070 { 01071 return (READ_BIT(((DMA_request_TypeDef*)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR, DMA_CSELR_C1S << ((Channel-1)*4)) >> POSITION_VAL(DMA_CSELR_C1S << ((Channel-1)*4))); 01072 } 01073 01074 /** 01075 * @} 01076 */ 01077 01078 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management 01079 * @{ 01080 */ 01081 01082 /** 01083 * @brief Get Channel 1 global interrupt flag. 01084 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1 01085 * @param DMAx DMAx Instance 01086 * @retval State of bit (1 or 0). 01087 */ 01088 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef* DMAx) 01089 { 01090 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)); 01091 } 01092 01093 /** 01094 * @brief Get Channel 2 global interrupt flag. 01095 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2 01096 * @param DMAx DMAx Instance 01097 * @retval State of bit (1 or 0). 01098 */ 01099 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef* DMAx) 01100 { 01101 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)); 01102 } 01103 01104 /** 01105 * @brief Get Channel 3 global interrupt flag. 01106 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3 01107 * @param DMAx DMAx Instance 01108 * @retval State of bit (1 or 0). 01109 */ 01110 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef* DMAx) 01111 { 01112 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)); 01113 } 01114 01115 /** 01116 * @brief Get Channel 4 global interrupt flag. 01117 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4 01118 * @param DMAx DMAx Instance 01119 * @retval State of bit (1 or 0). 01120 */ 01121 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef* DMAx) 01122 { 01123 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)); 01124 } 01125 01126 /** 01127 * @brief Get Channel 5 global interrupt flag. 01128 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5 01129 * @param DMAx DMAx Instance 01130 * @retval State of bit (1 or 0). 01131 */ 01132 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef* DMAx) 01133 { 01134 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)); 01135 } 01136 01137 /** 01138 * @brief Get Channel 6 global interrupt flag. 01139 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6 01140 * @param DMAx DMAx Instance 01141 * @retval State of bit (1 or 0). 01142 */ 01143 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef* DMAx) 01144 { 01145 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)); 01146 } 01147 01148 /** 01149 * @brief Get Channel 7 global interrupt flag. 01150 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7 01151 * @param DMAx DMAx Instance 01152 * @retval State of bit (1 or 0). 01153 */ 01154 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef* DMAx) 01155 { 01156 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)); 01157 } 01158 01159 /** 01160 * @brief Get Channel 1 transfer complete flag. 01161 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1 01162 * @param DMAx DMAx Instance 01163 * @retval State of bit (1 or 0). 01164 */ 01165 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef* DMAx) 01166 { 01167 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)); 01168 } 01169 01170 /** 01171 * @brief Get Channel 2 transfer complete flag. 01172 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2 01173 * @param DMAx DMAx Instance 01174 * @retval State of bit (1 or 0). 01175 */ 01176 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef* DMAx) 01177 { 01178 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)); 01179 } 01180 01181 /** 01182 * @brief Get Channel 3 transfer complete flag. 01183 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3 01184 * @param DMAx DMAx Instance 01185 * @retval State of bit (1 or 0). 01186 */ 01187 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef* DMAx) 01188 { 01189 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)); 01190 } 01191 01192 /** 01193 * @brief Get Channel 4 transfer complete flag. 01194 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4 01195 * @param DMAx DMAx Instance 01196 * @retval State of bit (1 or 0). 01197 */ 01198 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef* DMAx) 01199 { 01200 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)); 01201 } 01202 01203 /** 01204 * @brief Get Channel 5 transfer complete flag. 01205 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5 01206 * @param DMAx DMAx Instance 01207 * @retval State of bit (1 or 0). 01208 */ 01209 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef* DMAx) 01210 { 01211 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)); 01212 } 01213 01214 /** 01215 * @brief Get Channel 6 transfer complete flag. 01216 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6 01217 * @param DMAx DMAx Instance 01218 * @retval State of bit (1 or 0). 01219 */ 01220 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef* DMAx) 01221 { 01222 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)); 01223 } 01224 01225 /** 01226 * @brief Get Channel 7 transfer complete flag. 01227 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7 01228 * @param DMAx DMAx Instance 01229 * @retval State of bit (1 or 0). 01230 */ 01231 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef* DMAx) 01232 { 01233 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)); 01234 } 01235 01236 /** 01237 * @brief Get Channel 1 half transfer flag. 01238 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1 01239 * @param DMAx DMAx Instance 01240 * @retval State of bit (1 or 0). 01241 */ 01242 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef* DMAx) 01243 { 01244 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)); 01245 } 01246 01247 /** 01248 * @brief Get Channel 2 half transfer flag. 01249 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2 01250 * @param DMAx DMAx Instance 01251 * @retval State of bit (1 or 0). 01252 */ 01253 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef* DMAx) 01254 { 01255 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)); 01256 } 01257 01258 /** 01259 * @brief Get Channel 3 half transfer flag. 01260 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3 01261 * @param DMAx DMAx Instance 01262 * @retval State of bit (1 or 0). 01263 */ 01264 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef* DMAx) 01265 { 01266 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)); 01267 } 01268 01269 /** 01270 * @brief Get Channel 4 half transfer flag. 01271 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4 01272 * @param DMAx DMAx Instance 01273 * @retval State of bit (1 or 0). 01274 */ 01275 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef* DMAx) 01276 { 01277 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)); 01278 } 01279 01280 /** 01281 * @brief Get Channel 5 half transfer flag. 01282 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5 01283 * @param DMAx DMAx Instance 01284 * @retval State of bit (1 or 0). 01285 */ 01286 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef* DMAx) 01287 { 01288 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)); 01289 } 01290 01291 /** 01292 * @brief Get Channel 6 half transfer flag. 01293 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6 01294 * @param DMAx DMAx Instance 01295 * @retval State of bit (1 or 0). 01296 */ 01297 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef* DMAx) 01298 { 01299 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)); 01300 } 01301 01302 /** 01303 * @brief Get Channel 7 half transfer flag. 01304 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7 01305 * @param DMAx DMAx Instance 01306 * @retval State of bit (1 or 0). 01307 */ 01308 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef* DMAx) 01309 { 01310 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)); 01311 } 01312 01313 /** 01314 * @brief Get Channel 1 transfer error flag. 01315 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1 01316 * @param DMAx DMAx Instance 01317 * @retval State of bit (1 or 0). 01318 */ 01319 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef* DMAx) 01320 { 01321 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)); 01322 } 01323 01324 /** 01325 * @brief Get Channel 2 transfer error flag. 01326 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2 01327 * @param DMAx DMAx Instance 01328 * @retval State of bit (1 or 0). 01329 */ 01330 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef* DMAx) 01331 { 01332 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)); 01333 } 01334 01335 /** 01336 * @brief Get Channel 3 transfer error flag. 01337 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3 01338 * @param DMAx DMAx Instance 01339 * @retval State of bit (1 or 0). 01340 */ 01341 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef* DMAx) 01342 { 01343 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)); 01344 } 01345 01346 /** 01347 * @brief Get Channel 4 transfer error flag. 01348 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4 01349 * @param DMAx DMAx Instance 01350 * @retval State of bit (1 or 0). 01351 */ 01352 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef* DMAx) 01353 { 01354 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)); 01355 } 01356 01357 /** 01358 * @brief Get Channel 5 transfer error flag. 01359 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5 01360 * @param DMAx DMAx Instance 01361 * @retval State of bit (1 or 0). 01362 */ 01363 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef* DMAx) 01364 { 01365 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)); 01366 } 01367 01368 /** 01369 * @brief Get Channel 6 transfer error flag. 01370 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6 01371 * @param DMAx DMAx Instance 01372 * @retval State of bit (1 or 0). 01373 */ 01374 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef* DMAx) 01375 { 01376 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)); 01377 } 01378 01379 /** 01380 * @brief Get Channel 7 transfer error flag. 01381 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7 01382 * @param DMAx DMAx Instance 01383 * @retval State of bit (1 or 0). 01384 */ 01385 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef* DMAx) 01386 { 01387 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)); 01388 } 01389 01390 /** 01391 * @brief Clear Channel 1 global interrupt flag. 01392 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 01393 * @param DMAx DMAx Instance 01394 * @retval None 01395 */ 01396 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef* DMAx) 01397 { 01398 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF1); 01399 } 01400 01401 /** 01402 * @brief Clear Channel 2 global interrupt flag. 01403 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 01404 * @param DMAx DMAx Instance 01405 * @retval None 01406 */ 01407 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef* DMAx) 01408 { 01409 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF2); 01410 } 01411 01412 /** 01413 * @brief Clear Channel 3 global interrupt flag. 01414 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 01415 * @param DMAx DMAx Instance 01416 * @retval None 01417 */ 01418 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef* DMAx) 01419 { 01420 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF3); 01421 } 01422 01423 /** 01424 * @brief Clear Channel 4 global interrupt flag. 01425 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4 01426 * @param DMAx DMAx Instance 01427 * @retval None 01428 */ 01429 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef* DMAx) 01430 { 01431 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF4); 01432 } 01433 01434 /** 01435 * @brief Clear Channel 5 global interrupt flag. 01436 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5 01437 * @param DMAx DMAx Instance 01438 * @retval None 01439 */ 01440 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef* DMAx) 01441 { 01442 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF5); 01443 } 01444 01445 /** 01446 * @brief Clear Channel 6 global interrupt flag. 01447 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6 01448 * @param DMAx DMAx Instance 01449 * @retval None 01450 */ 01451 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef* DMAx) 01452 { 01453 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF6); 01454 } 01455 01456 /** 01457 * @brief Clear Channel 7 global interrupt flag. 01458 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7 01459 * @param DMAx DMAx Instance 01460 * @retval None 01461 */ 01462 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef* DMAx) 01463 { 01464 SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF7); 01465 } 01466 01467 /** 01468 * @brief Clear Channel 1 transfer complete flag. 01469 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1 01470 * @param DMAx DMAx Instance 01471 * @retval None 01472 */ 01473 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef* DMAx) 01474 { 01475 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF1); 01476 } 01477 01478 /** 01479 * @brief Clear Channel 2 transfer complete flag. 01480 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2 01481 * @param DMAx DMAx Instance 01482 * @retval None 01483 */ 01484 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef* DMAx) 01485 { 01486 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF2); 01487 } 01488 01489 /** 01490 * @brief Clear Channel 3 transfer complete flag. 01491 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3 01492 * @param DMAx DMAx Instance 01493 * @retval None 01494 */ 01495 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef* DMAx) 01496 { 01497 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF3); 01498 } 01499 01500 /** 01501 * @brief Clear Channel 4 transfer complete flag. 01502 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4 01503 * @param DMAx DMAx Instance 01504 * @retval None 01505 */ 01506 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef* DMAx) 01507 { 01508 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF4); 01509 } 01510 01511 /** 01512 * @brief Clear Channel 5 transfer complete flag. 01513 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5 01514 * @param DMAx DMAx Instance 01515 * @retval None 01516 */ 01517 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef* DMAx) 01518 { 01519 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF5); 01520 } 01521 01522 /** 01523 * @brief Clear Channel 6 transfer complete flag. 01524 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6 01525 * @param DMAx DMAx Instance 01526 * @retval None 01527 */ 01528 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef* DMAx) 01529 { 01530 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF6); 01531 } 01532 01533 /** 01534 * @brief Clear Channel 7 transfer complete flag. 01535 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7 01536 * @param DMAx DMAx Instance 01537 * @retval None 01538 */ 01539 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef* DMAx) 01540 { 01541 SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF7); 01542 } 01543 01544 /** 01545 * @brief Clear Channel 1 half transfer flag. 01546 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1 01547 * @param DMAx DMAx Instance 01548 * @retval None 01549 */ 01550 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef* DMAx) 01551 { 01552 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF1); 01553 } 01554 01555 /** 01556 * @brief Clear Channel 2 half transfer flag. 01557 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2 01558 * @param DMAx DMAx Instance 01559 * @retval None 01560 */ 01561 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef* DMAx) 01562 { 01563 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF2); 01564 } 01565 01566 /** 01567 * @brief Clear Channel 3 half transfer flag. 01568 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3 01569 * @param DMAx DMAx Instance 01570 * @retval None 01571 */ 01572 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef* DMAx) 01573 { 01574 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF3); 01575 } 01576 01577 /** 01578 * @brief Clear Channel 4 half transfer flag. 01579 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4 01580 * @param DMAx DMAx Instance 01581 * @retval None 01582 */ 01583 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef* DMAx) 01584 { 01585 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF4); 01586 } 01587 01588 /** 01589 * @brief Clear Channel 5 half transfer flag. 01590 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5 01591 * @param DMAx DMAx Instance 01592 * @retval None 01593 */ 01594 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef* DMAx) 01595 { 01596 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF5); 01597 } 01598 01599 /** 01600 * @brief Clear Channel 6 half transfer flag. 01601 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6 01602 * @param DMAx DMAx Instance 01603 * @retval None 01604 */ 01605 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef* DMAx) 01606 { 01607 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF6); 01608 } 01609 01610 /** 01611 * @brief Clear Channel 7 half transfer flag. 01612 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7 01613 * @param DMAx DMAx Instance 01614 * @retval None 01615 */ 01616 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef* DMAx) 01617 { 01618 SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF7); 01619 } 01620 01621 /** 01622 * @brief Clear Channel 1 transfer error flag. 01623 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1 01624 * @param DMAx DMAx Instance 01625 * @retval None 01626 */ 01627 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef* DMAx) 01628 { 01629 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF1); 01630 } 01631 01632 /** 01633 * @brief Clear Channel 2 transfer error flag. 01634 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2 01635 * @param DMAx DMAx Instance 01636 * @retval None 01637 */ 01638 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef* DMAx) 01639 { 01640 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF2); 01641 } 01642 01643 /** 01644 * @brief Clear Channel 3 transfer error flag. 01645 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3 01646 * @param DMAx DMAx Instance 01647 * @retval None 01648 */ 01649 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef* DMAx) 01650 { 01651 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF3); 01652 } 01653 01654 /** 01655 * @brief Clear Channel 4 transfer error flag. 01656 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4 01657 * @param DMAx DMAx Instance 01658 * @retval None 01659 */ 01660 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef* DMAx) 01661 { 01662 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF4); 01663 } 01664 01665 /** 01666 * @brief Clear Channel 5 transfer error flag. 01667 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5 01668 * @param DMAx DMAx Instance 01669 * @retval None 01670 */ 01671 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef* DMAx) 01672 { 01673 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF5); 01674 } 01675 01676 /** 01677 * @brief Clear Channel 6 transfer error flag. 01678 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6 01679 * @param DMAx DMAx Instance 01680 * @retval None 01681 */ 01682 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef* DMAx) 01683 { 01684 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF6); 01685 } 01686 01687 /** 01688 * @brief Clear Channel 7 transfer error flag. 01689 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7 01690 * @param DMAx DMAx Instance 01691 * @retval None 01692 */ 01693 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef* DMAx) 01694 { 01695 SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF7); 01696 } 01697 01698 /** 01699 * @} 01700 */ 01701 01702 /** @defgroup DMA_LL_EF_IT_Management IT_Management 01703 * @{ 01704 */ 01705 /** 01706 * @brief Enable Transfer complete interrupt. 01707 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC 01708 * @param DMAx DMAx Instance 01709 * @param Channel This parameter can be one of the following values: 01710 * @arg @ref LL_DMA_CHANNEL_1 01711 * @arg @ref LL_DMA_CHANNEL_2 01712 * @arg @ref LL_DMA_CHANNEL_3 01713 * @arg @ref LL_DMA_CHANNEL_4 01714 * @arg @ref LL_DMA_CHANNEL_5 01715 * @arg @ref LL_DMA_CHANNEL_6 01716 * @arg @ref LL_DMA_CHANNEL_7 01717 * @retval None 01718 */ 01719 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) 01720 { 01721 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1])))->CCR, DMA_CCR_TCIE); 01722 } 01723 01724 /** 01725 * @brief Enable Half transfer interrupt. 01726 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT 01727 * @param DMAx DMAx Instance 01728 * @param Channel This parameter can be one of the following values: 01729 * @arg @ref LL_DMA_CHANNEL_1 01730 * @arg @ref LL_DMA_CHANNEL_2 01731 * @arg @ref LL_DMA_CHANNEL_3 01732 * @arg @ref LL_DMA_CHANNEL_4 01733 * @arg @ref LL_DMA_CHANNEL_5 01734 * @arg @ref LL_DMA_CHANNEL_6 01735 * @arg @ref LL_DMA_CHANNEL_7 01736 * @retval None 01737 */ 01738 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) 01739 { 01740 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1])))->CCR, DMA_CCR_HTIE); 01741 } 01742 01743 /** 01744 * @brief Enable Transfer error interrupt. 01745 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE 01746 * @param DMAx DMAx Instance 01747 * @param Channel This parameter can be one of the following values: 01748 * @arg @ref LL_DMA_CHANNEL_1 01749 * @arg @ref LL_DMA_CHANNEL_2 01750 * @arg @ref LL_DMA_CHANNEL_3 01751 * @arg @ref LL_DMA_CHANNEL_4 01752 * @arg @ref LL_DMA_CHANNEL_5 01753 * @arg @ref LL_DMA_CHANNEL_6 01754 * @arg @ref LL_DMA_CHANNEL_7 01755 * @retval None 01756 */ 01757 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) 01758 { 01759 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1])))->CCR, DMA_CCR_TEIE); 01760 } 01761 01762 /** 01763 * @brief Disable Transfer complete interrupt. 01764 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC 01765 * @param DMAx DMAx Instance 01766 * @param Channel This parameter can be one of the following values: 01767 * @arg @ref LL_DMA_CHANNEL_1 01768 * @arg @ref LL_DMA_CHANNEL_2 01769 * @arg @ref LL_DMA_CHANNEL_3 01770 * @arg @ref LL_DMA_CHANNEL_4 01771 * @arg @ref LL_DMA_CHANNEL_5 01772 * @arg @ref LL_DMA_CHANNEL_6 01773 * @arg @ref LL_DMA_CHANNEL_7 01774 * @retval None 01775 */ 01776 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) 01777 { 01778 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1])))->CCR, DMA_CCR_TCIE); 01779 } 01780 01781 /** 01782 * @brief Disable Half transfer interrupt. 01783 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT 01784 * @param DMAx DMAx Instance 01785 * @param Channel This parameter can be one of the following values: 01786 * @arg @ref LL_DMA_CHANNEL_1 01787 * @arg @ref LL_DMA_CHANNEL_2 01788 * @arg @ref LL_DMA_CHANNEL_3 01789 * @arg @ref LL_DMA_CHANNEL_4 01790 * @arg @ref LL_DMA_CHANNEL_5 01791 * @arg @ref LL_DMA_CHANNEL_6 01792 * @arg @ref LL_DMA_CHANNEL_7 01793 * @retval None 01794 */ 01795 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) 01796 { 01797 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1])))->CCR, DMA_CCR_HTIE); 01798 } 01799 01800 /** 01801 * @brief Disable Transfer error interrupt. 01802 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE 01803 * @param DMAx DMAx Instance 01804 * @param Channel This parameter can be one of the following values: 01805 * @arg @ref LL_DMA_CHANNEL_1 01806 * @arg @ref LL_DMA_CHANNEL_2 01807 * @arg @ref LL_DMA_CHANNEL_3 01808 * @arg @ref LL_DMA_CHANNEL_4 01809 * @arg @ref LL_DMA_CHANNEL_5 01810 * @arg @ref LL_DMA_CHANNEL_6 01811 * @arg @ref LL_DMA_CHANNEL_7 01812 * @retval None 01813 */ 01814 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) 01815 { 01816 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1])))->CCR, DMA_CCR_TEIE); 01817 } 01818 01819 /** 01820 * @brief Check if Transfer complete Interrup is enabled. 01821 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC 01822 * @param DMAx DMAx Instance 01823 * @param Channel This parameter can be one of the following values: 01824 * @arg @ref LL_DMA_CHANNEL_1 01825 * @arg @ref LL_DMA_CHANNEL_2 01826 * @arg @ref LL_DMA_CHANNEL_3 01827 * @arg @ref LL_DMA_CHANNEL_4 01828 * @arg @ref LL_DMA_CHANNEL_5 01829 * @arg @ref LL_DMA_CHANNEL_6 01830 * @arg @ref LL_DMA_CHANNEL_7 01831 * @retval State of bit (1 or 0). 01832 */ 01833 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) 01834 { 01835 return (READ_BIT(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CCR, DMA_CCR_TCIE) == (DMA_CCR_TCIE)); 01836 } 01837 01838 /** 01839 * @brief Check if Half transfer Interrup is enabled. 01840 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT 01841 * @param DMAx DMAx Instance 01842 * @param Channel This parameter can be one of the following values: 01843 * @arg @ref LL_DMA_CHANNEL_1 01844 * @arg @ref LL_DMA_CHANNEL_2 01845 * @arg @ref LL_DMA_CHANNEL_3 01846 * @arg @ref LL_DMA_CHANNEL_4 01847 * @arg @ref LL_DMA_CHANNEL_5 01848 * @arg @ref LL_DMA_CHANNEL_6 01849 * @arg @ref LL_DMA_CHANNEL_7 01850 * @retval State of bit (1 or 0). 01851 */ 01852 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) 01853 { 01854 return (READ_BIT(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CCR, DMA_CCR_HTIE) == (DMA_CCR_HTIE)); 01855 } 01856 01857 /** 01858 * @brief Check if Transfer error Interrup is enabled. 01859 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE 01860 * @param DMAx DMAx Instance 01861 * @param Channel This parameter can be one of the following values: 01862 * @arg @ref LL_DMA_CHANNEL_1 01863 * @arg @ref LL_DMA_CHANNEL_2 01864 * @arg @ref LL_DMA_CHANNEL_3 01865 * @arg @ref LL_DMA_CHANNEL_4 01866 * @arg @ref LL_DMA_CHANNEL_5 01867 * @arg @ref LL_DMA_CHANNEL_6 01868 * @arg @ref LL_DMA_CHANNEL_7 01869 * @retval State of bit (1 or 0). 01870 */ 01871 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) 01872 { 01873 return (READ_BIT(((DMA_Channel_TypeDef*)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel-1])))->CCR, DMA_CCR_TEIE) == (DMA_CCR_TEIE)); 01874 } 01875 01876 /** 01877 * @} 01878 */ 01879 01880 01881 /** 01882 * @} 01883 */ 01884 01885 /** 01886 * @} 01887 */ 01888 01889 #endif /* DMA1 || DMA2 */ 01890 01891 /** 01892 * @} 01893 */ 01894 01895 #ifdef __cplusplus 01896 } 01897 #endif 01898 01899 #endif /* __STM32L4xx_LL_DMA_H */ 01900 01901 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 01902
Generated on Tue Jul 12 2022 11:35:16 by
1.7.2