stm32l4xx_ll_adc.h

00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_adc.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    16-September-2015
00007   * @brief   Header file of ADC LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_ADC_H
00040 #define __STM32L4xx_LL_ADC_H
00041 
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045 
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048 
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052 
00053 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
00054 
00055 /** @defgroup ADC_LL ADC
00056   * @{
00057   */
00058 
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 
00062 /* Private constants ---------------------------------------------------------*/
00063 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
00064   * @{
00065   */
00066 
00067 /* Internal mask for ADC group regular sequencer:                             */
00068 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for:            */
00069 /* - sequencer register offset                                                */
00070 /* - sequencer rank bits position into the selected register                  */
00071 
00072 /* Internal register offset for ADC group regular sequencer configuration */
00073 /* (offset placed into a spare area of literal definition) */
00074 #define ADC_SQR1_REGOFFSET                 ((uint32_t)0x00000000)
00075 #define ADC_SQR2_REGOFFSET                 ((uint32_t)0x00000100)
00076 #define ADC_SQR3_REGOFFSET                 ((uint32_t)0x00000200)
00077 #define ADC_SQR4_REGOFFSET                 ((uint32_t)0x00000300)
00078 
00079 #define ADC_REG_SQRX_REGOFFSET_MASK        (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
00080 #define ADC_REG_RANK_ID_SQRX_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
00081 
00082 /* Definition of ADC group regular sequencer bits information to be inserted  */
00083 /* into ADC group regular sequencer ranks literals definition.                */
00084 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS  ((uint32_t) 6) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ1) */
00085 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS  ((uint32_t)12) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ2) */
00086 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS  ((uint32_t)18) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ3) */
00087 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS  ((uint32_t)24) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ4) */
00088 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS  ((uint32_t) 0) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ5) */
00089 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS  ((uint32_t) 6) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ6) */
00090 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS  ((uint32_t)12) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
00091 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS  ((uint32_t)18) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
00092 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS  ((uint32_t)24) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
00093 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ((uint32_t) 0) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ10) */
00094 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ((uint32_t) 6) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ11) */
00095 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS ((uint32_t)12) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ12) */
00096 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ((uint32_t)18) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ13) */
00097 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ((uint32_t)24) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ14) */
00098 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ((uint32_t) 0) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ15) */
00099 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ((uint32_t) 6) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ16) */
00100 
00101 
00102 
00103 /* Internal mask for ADC group injected sequencer:                            */
00104 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for:            */
00105 /* - data register offset                                                     */
00106 /* - sequencer rank bits position into the selected register                  */
00107 
00108 /* Internal register offset for ADC group injected data register */
00109 /* (offset placed into a spare area of literal definition) */
00110 #define ADC_JDR1_REGOFFSET                 ((uint32_t)0x00000000)
00111 #define ADC_JDR2_REGOFFSET                 ((uint32_t)0x00000100)
00112 #define ADC_JDR3_REGOFFSET                 ((uint32_t)0x00000200)
00113 #define ADC_JDR4_REGOFFSET                 ((uint32_t)0x00000300)
00114 
00115 #define ADC_INJ_JDRX_REGOFFSET_MASK        (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
00116 #define ADC_INJ_RANK_ID_JSQR_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
00117 
00118 /* Definition of ADC group injected sequencer bits information to be inserted */
00119 /* into ADC group injected sequencer ranks literals definition.               */
00120 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS  ((uint32_t) 8) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */
00121 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS  ((uint32_t)14) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */
00122 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS  ((uint32_t)20) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */
00123 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS  ((uint32_t)26) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */
00124 
00125 
00126 
00127 /* Internal mask for ADC group regular trigger:                               */
00128 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for:            */
00129 /* - regular trigger source                                                   */
00130 /* - regular trigger edge                                                     */
00131 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT       (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
00132 
00133 /* Mask containing trigger source masks for each of possible                  */
00134 /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
00135 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
00136 #define ADC_REG_TRIG_SOURCE_MASK            (((LL_ADC_REG_TRIG_SW_START & ADC_CFGR_EXTSEL) << (4 * 0)) | \
00137                                              ((ADC_CFGR_EXTSEL)                            << (4 * 1)) | \
00138                                              ((ADC_CFGR_EXTSEL)                            << (4 * 2)) | \
00139                                              ((ADC_CFGR_EXTSEL)                            << (4 * 3))  )
00140 
00141 /* Mask containing trigger edge masks for each of possible                    */
00142 /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
00143 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
00144 #define ADC_REG_TRIG_EDGE_MASK              (((LL_ADC_REG_TRIG_SW_START & ADC_CFGR_EXTEN) << (4 * 0)) | \
00145                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4 * 1)) | \
00146                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4 * 2)) | \
00147                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4 * 3))  )
00148 
00149 /* Definition of ADC group regular trigger bits information.                  */
00150 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS  ((uint32_t) 6) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTSEL) */
00151 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   ((uint32_t)10) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTEN) */
00152 
00153 
00154 
00155 /* Internal mask for ADC group injected trigger:                              */
00156 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for:            */
00157 /* - injected trigger source                                                  */
00158 /* - injected trigger edge                                                    */
00159 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT      (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
00160 
00161 /* Mask containing trigger source masks for each of possible                  */
00162 /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
00163 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
00164 #define ADC_INJ_TRIG_SOURCE_MASK            (((LL_ADC_INJ_TRIG_SW_START & ADC_JSQR_JEXTSEL) << (4 * 0)) | \
00165                                             ((ADC_JSQR_JEXTSEL)                             << (4 * 1)) | \
00166                                             ((ADC_JSQR_JEXTSEL)                             << (4 * 2)) | \
00167                                             ((ADC_JSQR_JEXTSEL)                             << (4 * 3))  )
00168 
00169 /* Mask containing trigger edge masks for each of possible                    */
00170 /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
00171 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
00172 #define ADC_INJ_TRIG_EDGE_MASK              (((LL_ADC_INJ_TRIG_SW_START & ADC_JSQR_JEXTEN) << (4 * 0)) | \
00173                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4 * 1)) | \
00174                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4 * 2)) | \
00175                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4 * 3))  )
00176 
00177 /* Definition of ADC group injected trigger bits information.                 */
00178 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS  ((uint32_t) 2) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTSEL) */
00179 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS   ((uint32_t) 6) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTEN) */
00180 
00181 
00182 
00183 /* Internal register offset for ADC group regular sequencer configuration */
00184 /* (offset placed into a spare area of literal definition) */
00185 #define ADC_SQR1_REGOFFSET                 ((uint32_t)0x00000000)
00186 #define ADC_SQR2_REGOFFSET                 ((uint32_t)0x00000100)
00187 #define ADC_SQR3_REGOFFSET                 ((uint32_t)0x00000200)
00188 #define ADC_SQR4_REGOFFSET                 ((uint32_t)0x00000300)
00189 
00190 #define ADC_REG_SQRX_REGOFFSET_MASK        (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
00191 #define ADC_REG_RANK_ID_SQRX_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
00192 
00193 
00194 
00195 /* Internal mask for ADC channel:                                             */
00196 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for:             */
00197 /* - channel identifier defined by number                                     */
00198 /* - channel identifier defined by bitfield                                   */
00199 /* - channel differentiation between external channels (connected to          */
00200 /*   GPIO pins) and internal channels (connected to internal paths)           */
00201 /* - channel sampling time defined by SMPRx register offset                   */
00202 /*   and SMPx bits positions into SMPRx register                              */
00203 #define ADC_CHANNEL_ID_NUMBER_MASK         (ADC_CFGR_AWD1CH)
00204 #define ADC_CHANNEL_ID_BITFIELD_MASK       (ADC_AWD2CR_AWD2CH)
00205 #define ADC_CHANNEL_ID_MASK                (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
00206 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
00207 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
00208 
00209 /* Channel differentiation between external and internal channels */
00210 #define ADC_CHANNEL_ID_INTERNAL_CH         ((uint32_t)0x80000000) /* Marker of internal channel */
00211 #define ADC_CHANNEL_ID_INTERNAL_CH_2       ((uint32_t)0x02000000) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
00212 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK    (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
00213 
00214 /* Internal register offset for ADC channel sampling time configuration */
00215 /* (offset placed into a spare area of literal definition) */
00216 #define ADC_SMPR1_REGOFFSET                ((uint32_t)0x00000000)
00217 #define ADC_SMPR2_REGOFFSET                ((uint32_t)0x01000000)
00218 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK   (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
00219 
00220 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK    ((uint32_t)0x00F80000)
00221 #define ADC_CHANNEL_SMPx_BITOFFSET_POS     ((uint32_t)19)           /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
00222 
00223 /* Definition of channels ID number information to be inserted into           */
00224 /* channels literals definition.                                              */
00225 #define ADC_CHANNEL_0_NUMBER               ((uint32_t)0x00000000)
00226 #define ADC_CHANNEL_1_NUMBER               (                                                                                ADC_CFGR_AWD1CH_0)
00227 #define ADC_CHANNEL_2_NUMBER               (                                                            ADC_CFGR_AWD1CH_1                    )
00228 #define ADC_CHANNEL_3_NUMBER               (                                                            ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
00229 #define ADC_CHANNEL_4_NUMBER               (                                        ADC_CFGR_AWD1CH_2                                        )
00230 #define ADC_CHANNEL_5_NUMBER               (                                        ADC_CFGR_AWD1CH_2                     | ADC_CFGR_AWD1CH_0)
00231 #define ADC_CHANNEL_6_NUMBER               (                                        ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1                    )
00232 #define ADC_CHANNEL_7_NUMBER               (                                        ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
00233 #define ADC_CHANNEL_8_NUMBER               (                    ADC_CFGR_AWD1CH_3                                                            )
00234 #define ADC_CHANNEL_9_NUMBER               (                    ADC_CFGR_AWD1CH_3                                         | ADC_CFGR_AWD1CH_0)
00235 #define ADC_CHANNEL_10_NUMBER              (                    ADC_CFGR_AWD1CH_3                     | ADC_CFGR_AWD1CH_1                    )
00236 #define ADC_CHANNEL_11_NUMBER              (                    ADC_CFGR_AWD1CH_3                     | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
00237 #define ADC_CHANNEL_12_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2                                        )
00238 #define ADC_CHANNEL_13_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2                     | ADC_CFGR_AWD1CH_0)
00239 #define ADC_CHANNEL_14_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1                    )
00240 #define ADC_CHANNEL_15_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
00241 #define ADC_CHANNEL_16_NUMBER              (ADC_CFGR_AWD1CH_4                                                                                )
00242 #define ADC_CHANNEL_17_NUMBER              (ADC_CFGR_AWD1CH_4                                                             | ADC_CFGR_AWD1CH_0)
00243 #define ADC_CHANNEL_18_NUMBER              (ADC_CFGR_AWD1CH_4                                         | ADC_CFGR_AWD1CH_1                    )
00244 
00245 /* Definition of channels ID bitfield information to be inserted into         */
00246 /* channels literals definition.                                              */
00247 #define ADC_CHANNEL_0_BITFIELD             (ADC_AWD2CR_AWD2CH_0)
00248 #define ADC_CHANNEL_1_BITFIELD             (ADC_AWD2CR_AWD2CH_1)
00249 #define ADC_CHANNEL_2_BITFIELD             (ADC_AWD2CR_AWD2CH_2)
00250 #define ADC_CHANNEL_3_BITFIELD             (ADC_AWD2CR_AWD2CH_3)
00251 #define ADC_CHANNEL_4_BITFIELD             (ADC_AWD2CR_AWD2CH_4)
00252 #define ADC_CHANNEL_5_BITFIELD             (ADC_AWD2CR_AWD2CH_5)
00253 #define ADC_CHANNEL_6_BITFIELD             (ADC_AWD2CR_AWD2CH_6)
00254 #define ADC_CHANNEL_7_BITFIELD             (ADC_AWD2CR_AWD2CH_7)
00255 #define ADC_CHANNEL_8_BITFIELD             (ADC_AWD2CR_AWD2CH_8)
00256 #define ADC_CHANNEL_9_BITFIELD             (ADC_AWD2CR_AWD2CH_9)
00257 #define ADC_CHANNEL_10_BITFIELD            (ADC_AWD2CR_AWD2CH_10)
00258 #define ADC_CHANNEL_11_BITFIELD            (ADC_AWD2CR_AWD2CH_11)
00259 #define ADC_CHANNEL_12_BITFIELD            (ADC_AWD2CR_AWD2CH_12)
00260 #define ADC_CHANNEL_13_BITFIELD            (ADC_AWD2CR_AWD2CH_13)
00261 #define ADC_CHANNEL_14_BITFIELD            (ADC_AWD2CR_AWD2CH_14)
00262 #define ADC_CHANNEL_15_BITFIELD            (ADC_AWD2CR_AWD2CH_15)
00263 #define ADC_CHANNEL_16_BITFIELD            (ADC_AWD2CR_AWD2CH_16)
00264 #define ADC_CHANNEL_17_BITFIELD            (ADC_AWD2CR_AWD2CH_17)
00265 #define ADC_CHANNEL_18_BITFIELD            (ADC_AWD2CR_AWD2CH_18)
00266 
00267 /* Definition of channels sampling time information to be inserted into       */
00268 /* channels literals definition.                                              */
00269 #define ADC_CHANNEL_0_SMP                  (ADC_SMPR1_REGOFFSET | (((uint32_t) 0) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP0) */
00270 #define ADC_CHANNEL_1_SMP                  (ADC_SMPR1_REGOFFSET | (((uint32_t) 3) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP1) */
00271 #define ADC_CHANNEL_2_SMP                  (ADC_SMPR1_REGOFFSET | (((uint32_t) 6) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP2) */
00272 #define ADC_CHANNEL_3_SMP                  (ADC_SMPR1_REGOFFSET | (((uint32_t) 9) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP3) */
00273 #define ADC_CHANNEL_4_SMP                  (ADC_SMPR1_REGOFFSET | (((uint32_t)12) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP4) */
00274 #define ADC_CHANNEL_5_SMP                  (ADC_SMPR1_REGOFFSET | (((uint32_t)15) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP5) */
00275 #define ADC_CHANNEL_6_SMP                  (ADC_SMPR1_REGOFFSET | (((uint32_t)18) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP6) */
00276 #define ADC_CHANNEL_7_SMP                  (ADC_SMPR1_REGOFFSET | (((uint32_t)21) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP7) */
00277 #define ADC_CHANNEL_8_SMP                  (ADC_SMPR1_REGOFFSET | (((uint32_t)24) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP8) */
00278 #define ADC_CHANNEL_9_SMP                  (ADC_SMPR1_REGOFFSET | (((uint32_t)27) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP9) */
00279 #define ADC_CHANNEL_10_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t) 0) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP10) */
00280 #define ADC_CHANNEL_11_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t) 3) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP11) */
00281 #define ADC_CHANNEL_12_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t) 6) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP12) */
00282 #define ADC_CHANNEL_13_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t) 9) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP13) */
00283 #define ADC_CHANNEL_14_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t)12) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP14) */
00284 #define ADC_CHANNEL_15_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t)15) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP15) */
00285 #define ADC_CHANNEL_16_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t)18) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP16) */
00286 #define ADC_CHANNEL_17_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t)21) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP17) */
00287 #define ADC_CHANNEL_18_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t)24) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP18) */
00288 
00289 
00290 /* Internal mask for ADC mode single or differential ended:                   */
00291 /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL  */
00292 /* the relevant bits for:                                                     */
00293 /* (concatenation of multiple bits used in different registers)               */
00294 /* - ADC calibration: calibration start, calibration factor get or set        */
00295 /* - ADC channels: set each ADC channel ending mode                           */
00296 #define ADC_SINGLEDIFF_CALIB_START_MASK    (ADC_CR_ADCALDIF)
00297 #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK   (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
00298 #define ADC_SINGLEDIFF_CHANNEL_MASK        (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
00299 #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK  (ADC_CALFACT_CALFACT_S_5) /* Bit chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
00300 
00301 
00302 /* Internal mask for ADC analog watchdog:                                     */
00303 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for:     */
00304 /* (concatenation of multiple bits used in different analog watchdogs,        */
00305 /* (feature of several watchdogs not available on all STM32 families)).       */
00306 /* - analog watchdog 1: monitored channel defined by number,                  */
00307 /*   selection of ADC group (ADC groups regular and-or injected).             */
00308 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no       */
00309 /*   selection on groups.                                                     */
00310 
00311 /* Internal register offset for ADC analog watchdog channel configuration */
00312 #define ADC_AWD_CR1_REGOFFSET              ((uint32_t)0x00000000)
00313 #define ADC_AWD_CR2_REGOFFSET              ((uint32_t)0x00080000)
00314 #define ADC_AWD_CR3_REGOFFSET              ((uint32_t)0x00100000)
00315 
00316 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
00317 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
00318 #define ADC_AWD_CR12_REGOFFSETGAP_MASK     (ADC_AWD2CR_AWD2CH_0)
00319 #define ADC_AWD_CR12_REGOFFSETGAP_VAL      ((uint32_t)0x00000024)
00320 
00321 #define ADC_AWD_CRX_REGOFFSET_MASK         (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
00322 
00323 #define ADC_AWD_CR1_CHANNEL_MASK           (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
00324 #define ADC_AWD_CR23_CHANNEL_MASK          (ADC_AWD2CR_AWD2CH)
00325 #define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
00326 
00327 /* Internal register offset for ADC analog watchdog threshold configuration */
00328 #define ADC_AWD_TR1_REGOFFSET              (ADC_AWD_CR1_REGOFFSET)
00329 #define ADC_AWD_TR2_REGOFFSET              (ADC_AWD_CR2_REGOFFSET)
00330 #define ADC_AWD_TR3_REGOFFSET              (ADC_AWD_CR3_REGOFFSET)
00331 #define ADC_AWD_TRX_REGOFFSET_MASK         (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
00332 
00333 
00334 /* Internal mask for ADC offset:                                              */
00335 /* Internal register offset for ADC offset number configuration */
00336 #define ADC_OFR1_REGOFFSET                 ((uint32_t)0x00000000)
00337 #define ADC_OFR2_REGOFFSET                 ((uint32_t)0x00000001)
00338 #define ADC_OFR3_REGOFFSET                 ((uint32_t)0x00000002)
00339 #define ADC_OFR4_REGOFFSET                 ((uint32_t)0x00000003)
00340 #define ADC_OFRx_REGOFFSET_MASK            (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
00341 
00342 
00343 /* ADC registers bits positions */
00344 #define ADC_CFGR_RES_BITOFFSET_POS         ((uint32_t) 3) /* Value equivalent to POSITION_VAL(ADC_CFGR_RES) */
00345 #define ADC_TR1_HT1_BITOFFSET_POS          ((uint32_t)16) /* Value equivalent to POSITION_VAL(ADC_TR1_HT1) */
00346 
00347 
00348 /* ADC registers bits groups */
00349 #define ADC_CR_BITS_PROPERTY_RS            (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
00350 
00351 
00352 /* ADC internal channels related definitions */
00353 /* Internal voltage reference VrefInt */
00354 #define VREFINT_CAL_ADDR                   ((uint16_t*) ((uint32_t)0x1FFF75AA)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
00355 #define VREFINT_CAL_VREF                   ((uint32_t) 3000)                    /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
00356 /* Temperature sensor */
00357 #define TEMPSENSOR_CAL1_ADDR               ((uint16_t*) ((uint32_t)0x1FFF75A8)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L4, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
00358 #define TEMPSENSOR_CAL2_ADDR               ((uint16_t*) ((uint32_t)0x1FFF75CA)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
00359 #define TEMPSENSOR_CAL1_TEMP               (( int32_t)   30)                    /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
00360 #define TEMPSENSOR_CAL2_TEMP               (( int32_t)  110)                    /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
00361 #define TEMPSENSOR_CAL_VREFANALOG          ((uint32_t) 3000)                    /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
00362 
00363 
00364 /**
00365   * @}
00366   */
00367 
00368 
00369 /* Private macros ------------------------------------------------------------*/
00370 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
00371   * @{
00372   */
00373 
00374 /**
00375   * @brief  Driver macro reserved for internal use: isolate bits with the
00376   *         selected mask and shift them to the register LSB
00377   *         (shift mask on register position bit 0).
00378   * @param  __BITS__ Bits in register 32 bits
00379   * @param  __MASK__ Mask in register 32 bits
00380   * @retval Bits in register 32 bits
00381 */
00382 #define __ADC_MASK_SHIFT(__BITS__, __MASK__)                                   \
00383   (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
00384 
00385 /**
00386   * @brief  Driver macro reserved for internal use: set a pointer to
00387   *         a register from a register basis from which an offset
00388   *         is applied.
00389   * @param  __REG__ Register basis from which the offset is applied.
00390   * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
00391   * @retval Pointer to register address
00392 */
00393 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
00394  ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2))))
00395 
00396 /**
00397   * @}
00398   */
00399 
00400 
00401 /* Exported types ------------------------------------------------------------*/
00402 /* Exported constants --------------------------------------------------------*/
00403 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
00404   * @{
00405   */
00406 
00407 /** @defgroup ADC_LL_EC_GET_FLAG ADC flags
00408   * @brief    Flags defines which can be used with LL_ADC_ReadReg function
00409   * @{
00410   */
00411 #define LL_ADC_ISR_ADRDY                   ADC_ISR_ADRDY      /*!< ADC flag ADC instance ready */
00412 #define LL_ADC_ISR_EOC                     ADC_ISR_EOC        /*!< ADC flag ADC group regular end of unitary conversion */
00413 #define LL_ADC_ISR_EOS                     ADC_ISR_EOS        /*!< ADC flag ADC group regular end of sequence conversions */
00414 #define LL_ADC_ISR_OVR                     ADC_ISR_OVR        /*!< ADC flag ADC group regular overrun */
00415 #define LL_ADC_ISR_EOSMP                   ADC_ISR_EOSMP      /*!< ADC flag ADC group regular end of sampling phase */
00416 #define LL_ADC_ISR_JEOC                    ADC_ISR_JEOC       /*!< ADC flag ADC group injected end of unitary conversion */
00417 #define LL_ADC_ISR_JEOS                    ADC_ISR_JEOS       /*!< ADC flag ADC group injected end of sequence conversions */
00418 #define LL_ADC_ISR_JQOVF                   ADC_ISR_JQOVF      /*!< ADC flag ADC group injected contexts queue overflow */
00419 #define LL_ADC_ISR_AWD1                    ADC_ISR_AWD1       /*!< ADC flag ADC analog watchdog 1 */
00420 #define LL_ADC_ISR_AWD2                    ADC_ISR_AWD2       /*!< ADC flag ADC analog watchdog 2 */
00421 #define LL_ADC_ISR_AWD3                    ADC_ISR_AWD3       /*!< ADC flag ADC analog watchdog 3 */
00422 #define LL_ADC_CSR_ADRDY_MST               ADC_CSR_ADRDY_MST  /*!< ADC flag ADC instance ready of the ADC master */
00423 #define LL_ADC_CSR_ADRDY_SLV               ADC_CSR_ADRDY_SLV  /*!< ADC flag ADC instance ready of the ADC slave */
00424 #if defined(ADC2)
00425 #define LL_ADC_CSR_EOC_MST                 ADC_CSR_EOC_MST    /*!< ADC flag multimode ADC group regular end of unitary conversion of the ADC master */
00426 #define LL_ADC_CSR_EOC_SLV                 ADC_CSR_EOC_SLV    /*!< ADC flag multimode ADC group regular end of unitary conversion of the ADC slave */
00427 #define LL_ADC_CSR_EOS_MST                 ADC_CSR_EOS_MST    /*!< ADC flag multimode ADC group regular end of sequence conversions of the ADC master */
00428 #define LL_ADC_CSR_EOS_SLV                 ADC_CSR_EOS_SLV    /*!< ADC flag multimode ADC group regular end of sequence conversions of the ADC slave */
00429 #define LL_ADC_CSR_OVR_MST                 ADC_CSR_OVR_MST    /*!< ADC flag multimode ADC group regular overrun of the ADC master */
00430 #define LL_ADC_CSR_OVR_SLV                 ADC_CSR_OVR_SLV    /*!< ADC flag multimode ADC group regular overrun of the ADC slave */
00431 #define LL_ADC_CSR_EOSMP_MST               ADC_CSR_EOSMP_MST  /*!< ADC flag multimode ADC group regular end of sampling phase of the ADC master */
00432 #define LL_ADC_CSR_EOSMP_SLV               ADC_CSR_EOSMP_SLV  /*!< ADC flag multimode ADC group regular end of sampling phase of the ADC slave */
00433 #define LL_ADC_CSR_JEOC_MST                ADC_CSR_JEOC_MST   /*!< ADC flag multimode ADC group injected end of unitary conversion of the ADC master */
00434 #define LL_ADC_CSR_JEOC_SLV                ADC_CSR_JEOC_SLV   /*!< ADC flag multimode ADC group injected end of unitary conversion of the ADC slave */
00435 #define LL_ADC_CSR_JEOS_MST                ADC_CSR_JEOS_MST   /*!< ADC flag multimode ADC group injected end of sequence conversions of the ADC master */
00436 #define LL_ADC_CSR_JEOS_SLV                ADC_CSR_JEOS_SLV   /*!< ADC flag multimode ADC group injected end of sequence conversions of the ADC slave */
00437 #define LL_ADC_CSR_JQOVF_MST               ADC_CSR_JQOVF_MST  /*!< ADC flag multimode ADC group injected contexts queue overflow of the ADC master */
00438 #define LL_ADC_CSR_JQOVF_SLV               ADC_CSR_JQOVF_SLV  /*!< ADC flag multimode ADC group injected contexts queue overflow of the ADC slave */
00439 #define LL_ADC_CSR_AWD1_MST                ADC_CSR_AWD1_MST   /*!< ADC flag multimode ADC analog watchdog 1 of the ADC master */
00440 #define LL_ADC_CSR_AWD1_SLV                ADC_CSR_AWD1_SLV   /*!< ADC flag multimode ADC analog watchdog 1 of the ADC slave */
00441 #define LL_ADC_CSR_AWD2_MST                ADC_CSR_AWD2_MST   /*!< ADC flag multimode ADC analog watchdog 2 of the ADC master */
00442 #define LL_ADC_CSR_AWD2_SLV                ADC_CSR_AWD2_SLV   /*!< ADC flag multimode ADC analog watchdog 2 of the ADC slave */
00443 #define LL_ADC_CSR_AWD3_MST                ADC_CSR_AWD3_MST   /*!< ADC flag multimode ADC analog watchdog 3 of the ADC master */
00444 #define LL_ADC_CSR_AWD3_SLV                ADC_CSR_AWD3_SLV   /*!< ADC flag multimode ADC analog watchdog 3 of the ADC slave */
00445 #endif
00446 /**
00447   * @}
00448   */
00449 
00450 /** @defgroup ADC_LL_EC_IT ADC interruptions
00451   * @brief    IT defines which can be used with LL_ADC_ReadReg and  LL_ADC_WriteReg functions
00452   * @{
00453   */
00454 #define LL_ADC_IER_ADRDY                   ADC_IER_ADRDY  /*!< ADC interruption ADC instance ready */
00455 #define LL_ADC_IER_EOC                     ADC_IER_EOC    /*!< ADC interruption ADC group regular end of unitary conversion */
00456 #define LL_ADC_IER_EOS                     ADC_IER_EOS    /*!< ADC interruption ADC group regular end of sequence conversions */
00457 #define LL_ADC_IER_OVR                     ADC_IER_OVR    /*!< ADC interruption ADC group regular overrun */
00458 #define LL_ADC_IER_EOSMP                   ADC_IER_EOSMP  /*!< ADC interruption ADC group regular end of sampling phase */
00459 #define LL_ADC_IER_JEOC                    ADC_IER_JEOC   /*!< ADC interruption ADC group injected end of unitary conversion */
00460 #define LL_ADC_IER_JEOS                    ADC_IER_JEOS   /*!< ADC interruption ADC group injected end of sequence conversions */
00461 #define LL_ADC_IER_JQOVF                   ADC_IER_JQOVF  /*!< ADC interruption ADC group injected contexts queue overflow */
00462 #define LL_ADC_IER_AWD1                    ADC_IER_AWD1   /*!< ADC interruption ADC analog watchdog 1 */
00463 #define LL_ADC_IER_AWD2                    ADC_IER_AWD2   /*!< ADC interruption ADC analog watchdog 2 */
00464 #define LL_ADC_IER_AWD3                    ADC_IER_AWD3   /*!< ADC interruption ADC analog watchdog 3 */
00465 /**
00466   * @}
00467   */
00468 
00469 /** @defgroup ADC_LL_EC_REGISTERS  ADC instance - Registers compliant with specific purpose
00470   * @{
00471   */
00472 /* List of ADC registers intended to be used (most commonly) with             */
00473 /* DMA transfer.                                                              */
00474 /* Refer to function @ref LL_ADC_DMA_GetRegAddr().                            */
00475 #define LL_ADC_DMA_REG_REGULAR_DATA          ((uint32_t)0x00000000) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
00476 #if defined(ADC2)
00477 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI    ((uint32_t)0x00000001) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
00478 #endif
00479 /**
00480   * @}
00481   */
00482 
00483 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source
00484   * @{
00485   */
00486 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1        (ADC_CCR_CKMODE_0)                                    /*!< ADC synchronous clock derived from AHB clock not divided  */
00487 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2        (ADC_CCR_CKMODE_1                   )                 /*!< ADC synchronous clock derived from AHB clock divided by 2 */
00488 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4        (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0)                 /*!< ADC synchronous clock derived from AHB clock divided by 4 */
00489 #define LL_ADC_CLOCK_ASYNC_DIV1            ((uint32_t)0x00000000)                                /*!< ADC asynchronous clock not divided    */
00490 #define LL_ADC_CLOCK_ASYNC_DIV2            (ADC_CCR_PRESC_0)                                     /*!< ADC asynchronous clock divided by 2   */
00491 #define LL_ADC_CLOCK_ASYNC_DIV4            (ADC_CCR_PRESC_1                  )                   /*!< ADC asynchronous clock divided by 4   */
00492 #define LL_ADC_CLOCK_ASYNC_DIV6            (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock divided by 6   */
00493 #define LL_ADC_CLOCK_ASYNC_DIV8            (ADC_CCR_PRESC_2                                    ) /*!< ADC asynchronous clock divided by 8   */
00494 #define LL_ADC_CLOCK_ASYNC_DIV10           (ADC_CCR_PRESC_2                   | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock divided by 10  */
00495 #define LL_ADC_CLOCK_ASYNC_DIV12           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1                  ) /*!< ADC asynchronous clock divided by 12  */
00496 #define LL_ADC_CLOCK_ASYNC_DIV16           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock divided by 16  */
00497 #define LL_ADC_CLOCK_ASYNC_DIV32           (ADC_CCR_PRESC_3)                                     /*!< ADC asynchronous clock divided by 32  */
00498 #define LL_ADC_CLOCK_ASYNC_DIV64           (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock divided by 64  */
00499 #define LL_ADC_CLOCK_ASYNC_DIV128          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)                   /*!< ADC asynchronous clock divided by 128 */
00500 #define LL_ADC_CLOCK_ASYNC_DIV256          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock divided by 256 */
00501 /**
00502   * @}
00503   */
00504 
00505 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL  ADC common - Measurement path to internal channels
00506   * @{
00507   */
00508 /* Note: Other measurement paths to internal channels may be available        */
00509 /*       (connections to other peripherals).                                  */
00510 /*       If they are not listed below, they do not require any specific       */
00511 /*       path enable. In this case, Access to measurement path is done        */
00512 /*       only by selecting the corresponding ADC internal channel.            */
00513 #define LL_ADC_PATH_INTERNAL_NONE          ((uint32_t)0x00000000) /*!< ADC measurement pathes all disabled */
00514 #define LL_ADC_PATH_INTERNAL_VREFINT       (ADC_CCR_VREFEN)       /*!< ADC measurement path to internal channel VrefInt */
00515 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR    (ADC_CCR_TSEN)         /*!< ADC measurement path to internal channel temperature sensor */
00516 #define LL_ADC_PATH_INTERNAL_VBAT          (ADC_CCR_VBATEN)       /*!< ADC measurement path to internal channel Vbat */
00517 /**
00518   * @}
00519   */
00520 
00521 /** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution
00522   * @{
00523   */
00524 #define LL_ADC_RESOLUTION_12B              ((uint32_t)0x00000000)              /*!< ADC resolution 12 bits */
00525 #define LL_ADC_RESOLUTION_10B              (                 ADC_CFGR_RES_0)   /*!< ADC resolution 10 bits */
00526 #define LL_ADC_RESOLUTION_8B               (ADC_CFGR_RES_1                 )   /*!< ADC resolution  8 bits */
00527 #define LL_ADC_RESOLUTION_6B               (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)   /*!< ADC resolution  6 bits */
00528 /**
00529   * @}
00530   */
00531 
00532 /** @defgroup ADC_LL_EC_DATA_ALIGN  ADC instance - Data alignment
00533   * @{
00534   */
00535 #define LL_ADC_DATA_ALIGN_RIGHT            ((uint32_t)0x00000000) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
00536 #define LL_ADC_DATA_ALIGN_LEFT             (ADC_CFGR_ALIGN)       /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
00537 /**
00538   * @}
00539   */
00540 
00541 /** @defgroup ADC_LL_EC_LP_MODE  ADC instance - Low power mode
00542   * @{
00543   */
00544 #define LL_ADC_LP_MODE_NONE                ((uint32_t)0x00000000) /*!< No ADC low power mode activated */
00545 #define LL_ADC_LP_AUTOWAIT                 (ADC_CFGR_AUTDLY)      /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary. See description with function @ref LL_ADC_SetLowPowerMode(). */
00546 /**
00547   * @}
00548   */
00549 
00550 /** @defgroup ADC_LL_EC_OFFSET_NB  ADC instance - Offset number
00551   * @{
00552   */
00553 #define LL_ADC_OFFSET_1                    ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
00554 #define LL_ADC_OFFSET_2                    ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
00555 #define LL_ADC_OFFSET_3                    ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
00556 #define LL_ADC_OFFSET_4                    ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
00557 /**
00558   * @}
00559   */
00560 
00561 /** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
00562   * @{
00563   */
00564 #define LL_ADC_OFFSET_DISABLE              ((uint32_t)0x00000000) /*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */
00565 #define LL_ADC_OFFSET_ENABLE               (ADC_OFR1_OFFSET1_EN)  /*!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) */
00566 /**
00567   * @}
00568   */
00569 
00570 /** @defgroup ADC_LL_EC_GROUPS  ADC instance - Groups
00571   * @{
00572   */
00573 #define LL_ADC_GROUP_REGULAR               ((uint32_t)0x00000001) /*!< ADC group regular (available on all STM32 devices) */
00574 #define LL_ADC_GROUP_INJECTED              ((uint32_t)0x00000002) /*!< ADC group injected (not available on all STM32 devices)*/
00575 #define LL_ADC_GROUP_REGULAR_INJECTED      ((uint32_t)0x00000003) /*!< ADC both groups regular and injected */
00576 /**
00577   * @}
00578   */
00579 
00580 /** @defgroup ADC_LL_EC_CHANNEL  ADC instance - Channel number
00581   * @{
00582   */
00583 #define LL_ADC_CHANNEL_0                   (ADC_CHANNEL_0_NUMBER  | ADC_CHANNEL_0_SMP  | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0  */
00584 #define LL_ADC_CHANNEL_1                   (ADC_CHANNEL_1_NUMBER  | ADC_CHANNEL_1_SMP  | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1  */
00585 #define LL_ADC_CHANNEL_2                   (ADC_CHANNEL_2_NUMBER  | ADC_CHANNEL_2_SMP  | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2  */
00586 #define LL_ADC_CHANNEL_3                   (ADC_CHANNEL_3_NUMBER  | ADC_CHANNEL_3_SMP  | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3  */
00587 #define LL_ADC_CHANNEL_4                   (ADC_CHANNEL_4_NUMBER  | ADC_CHANNEL_4_SMP  | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4  */
00588 #define LL_ADC_CHANNEL_5                   (ADC_CHANNEL_5_NUMBER  | ADC_CHANNEL_5_SMP  | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5  */
00589 #define LL_ADC_CHANNEL_6                   (ADC_CHANNEL_6_NUMBER  | ADC_CHANNEL_6_SMP  | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6  */
00590 #define LL_ADC_CHANNEL_7                   (ADC_CHANNEL_7_NUMBER  | ADC_CHANNEL_7_SMP  | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7  */
00591 #define LL_ADC_CHANNEL_8                   (ADC_CHANNEL_8_NUMBER  | ADC_CHANNEL_8_SMP  | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8  */
00592 #define LL_ADC_CHANNEL_9                   (ADC_CHANNEL_9_NUMBER  | ADC_CHANNEL_9_SMP  | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9  */
00593 #define LL_ADC_CHANNEL_10                  (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
00594 #define LL_ADC_CHANNEL_11                  (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
00595 #define LL_ADC_CHANNEL_12                  (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
00596 #define LL_ADC_CHANNEL_13                  (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
00597 #define LL_ADC_CHANNEL_14                  (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
00598 #define LL_ADC_CHANNEL_15                  (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
00599 #define LL_ADC_CHANNEL_16                  (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
00600 #define LL_ADC_CHANNEL_17                  (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
00601 #define LL_ADC_CHANNEL_18                  (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
00602 #define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_0  | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32L4, ADC channel available only on ADC instance: ADC1. */
00603 #define LL_ADC_CHANNEL_TEMPSENSOR          (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32L4, ADC channel available only on ADC instances: ADC1, ADC3. */
00604 #define LL_ADC_CHANNEL_VBAT                (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through an dividor ladder of factor 1/3 to have Vbat always below Vdda. On STM32L4, ADC channel available only on ADC instances: ADC1, ADC3. */
00605 #define LL_ADC_CHANNEL_DAC1CH1_ADC2        (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */
00606 #define LL_ADC_CHANNEL_DAC1CH2_ADC2        (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */
00607 #define LL_ADC_CHANNEL_DAC1CH1_ADC3        (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC3 */
00608 #define LL_ADC_CHANNEL_DAC1CH2_ADC3        (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC3 */
00609 /**
00610   * @}
00611   */
00612 
00613 /** @defgroup ADC_LL_EC_REG_TRIG_SOURCE  ADC group regular - Trigger source
00614   * @{
00615   */
00616 #define LL_ADC_REG_TRIG_SW_START           ((uint32_t)0x00000000)                                                                                          /*!< ADC group regular conversion trigger internal (SW start) */
00617 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger external from TIM1 TRGO. Trigger edge set to rising edge (default setting). */
00618 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger external from TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
00619 #define LL_ADC_REG_TRIG_EXT_TIM1_CC1       (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                                                 /*!< ADC group regular conversion trigger external from TIM1 CC1. Trigger edge set to rising edge (default setting). */
00620 #define LL_ADC_REG_TRIG_EXT_TIM1_CC2       (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group regular conversion trigger external from TIM1 CC2. Trigger edge set to rising edge (default setting). */
00621 #define LL_ADC_REG_TRIG_EXT_TIM1_CC3       (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group regular conversion trigger external from TIM1 CC3. Trigger edge set to rising edge (default setting). */
00622 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group regular conversion trigger external from TIM2 TRGO. Trigger edge set to rising edge (default setting). */
00623 #define LL_ADC_REG_TRIG_EXT_TIM2_CC2       (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger external from TIM2 CC2. Trigger edge set to rising edge (default setting). */
00624 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO      (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group regular conversion trigger external from TIM3 TRGO. Trigger edge set to rising edge (default setting). */
00625 #define LL_ADC_REG_TRIG_EXT_TIM3_CC4       (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger external from TIM3 CC4. Trigger edge set to rising edge (default setting). */
00626 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger external from TIM4 TRGO. Trigger edge set to rising edge (default setting). */
00627 #define LL_ADC_REG_TRIG_EXT_TIM4_CC4       (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger external from TIM4 CC4. Trigger edge set to rising edge (default setting). */
00628 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group regular conversion trigger external from TIM6 TRGO. Trigger edge set to rising edge (default setting). */
00629 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO      (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group regular conversion trigger external from TIM8 TRGO. Trigger edge set to rising edge (default setting). */
00630 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2     (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group regular conversion trigger external from TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
00631 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group regular conversion trigger external from TIM15 TRGO. Trigger edge set to rising edge (default setting). */
00632 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11    (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger external from external interrupt line 11. Trigger edge set to rising edge (default setting). */
00633 /**
00634   * @}
00635   */
00636 
00637 /** @defgroup ADC_LL_EC_REG_TRIG_EDGE  ADC group regular - Trigger edge
00638   * @{
00639   */
00640 #define LL_ADC_REG_TRIG_EXT_RISING         (                   ADC_CFGR_EXTEN_0)   /*!< ADC group regular conversion trigger polarity set to rising edge */
00641 #define LL_ADC_REG_TRIG_EXT_FALLING        (ADC_CFGR_EXTEN_1                   )   /*!< ADC group regular conversion trigger polarity set to falling edge */
00642 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING  (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)   /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
00643 /**
00644   * @}
00645   */
00646 
00647 /** @defgroup ADC_LL_EC_REG_CONV  ADC group regular - Continuous mode
00648 * @{
00649 */
00650 #define LL_ADC_REG_CONV_SINGLE             ((uint32_t)0x00000000) /*!< ADC conversions are performed in single mode: one conversion per trigger */
00651 #define LL_ADC_REG_CONV_CONTINUOUS         (ADC_CFGR_CONT)        /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
00652 /**
00653   * @}
00654   */
00655 
00656 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER  ADC group regular - DMA transfer
00657   * @{
00658   */
00659 #define LL_ADC_REG_DMA_TRANSFER_NONE       ((uint32_t)0x00000000)               /*!< ADC conversions are not transferred by DMA */
00660 #define LL_ADC_REG_DMA_TRANSFER_LIMITED    (                  ADC_CFGR_DMAEN)   /*!< ADC conversions are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
00661 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED  (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN)   /*!< ADC conversions are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
00662 /**
00663   * @}
00664   */
00665 
00666 /** @defgroup ADC_LL_EC_REG_OVR  ADC group regular - Overrun
00667 * @{
00668 */
00669 #define LL_ADC_REG_OVR_DATA_PRESERVED      ((uint32_t)0x00000000) /*!< ADC group regular behaviour in case of overrun: data preserved */
00670 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN    (ADC_CFGR_OVRMOD)      /*!< ADC group regular behaviour in case of overrun: data overwritten */
00671 /**
00672   * @}
00673   */
00674 
00675 /** @defgroup ADC_LL_EC_REG_SEQ_LENGTH  ADC group regular - Sequencer length
00676   * @{
00677   */
00678 #define LL_ADC_REG_SEQ_SCAN_DISABLE        ((uint32_t)0x00000000)                                      /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
00679 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS  (                                             ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
00680 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS  (                              ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
00681 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS  (                              ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
00682 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS  (               ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
00683 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS  (               ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
00684 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
00685 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
00686 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS  (ADC_SQR1_L_3                                             ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
00687 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3                               | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
00688 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
00689 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
00690 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
00691 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
00692 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
00693 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
00694 /**
00695   * @}
00696   */
00697 
00698 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT  ADC group regular - Sequencer discontinuous mode
00699   * @{
00700   */
00701 #define LL_ADC_REG_SEQ_DISCONT_DISABLE     ((uint32_t)0x00000000)                                                           /*!< ADC group regular sequencer discontinuous mode disable */
00702 #define LL_ADC_REG_SEQ_DISCONT_1RANK       (                                                               ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
00703 #define LL_ADC_REG_SEQ_DISCONT_2RANKS      (                                          ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
00704 #define LL_ADC_REG_SEQ_DISCONT_3RANKS      (                     ADC_CFGR_DISCNUM_1                      | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
00705 #define LL_ADC_REG_SEQ_DISCONT_4RANKS      (                     ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
00706 #define LL_ADC_REG_SEQ_DISCONT_5RANKS      (ADC_CFGR_DISCNUM_2                                           | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
00707 #define LL_ADC_REG_SEQ_DISCONT_6RANKS      (ADC_CFGR_DISCNUM_2                      | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
00708 #define LL_ADC_REG_SEQ_DISCONT_7RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1                      | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
00709 #define LL_ADC_REG_SEQ_DISCONT_8RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
00710 /**
00711   * @}
00712   */
00713 
00714 /** @defgroup ADC_LL_EC_REG_RANKS  ADC group regular - Sequencer ranks
00715   * @{
00716   */
00717 #define LL_ADC_REG_RANK_1                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 1 */
00718 #define LL_ADC_REG_RANK_2                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 2 */
00719 #define LL_ADC_REG_RANK_3                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 3 */
00720 #define LL_ADC_REG_RANK_4                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 4 */
00721 #define LL_ADC_REG_RANK_5                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 5 */
00722 #define LL_ADC_REG_RANK_6                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 6 */
00723 #define LL_ADC_REG_RANK_7                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 7 */
00724 #define LL_ADC_REG_RANK_8                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 8 */
00725 #define LL_ADC_REG_RANK_9                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 9 */
00726 #define LL_ADC_REG_RANK_10                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
00727 #define LL_ADC_REG_RANK_11                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
00728 #define LL_ADC_REG_RANK_12                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
00729 #define LL_ADC_REG_RANK_13                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
00730 #define LL_ADC_REG_RANK_14                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
00731 #define LL_ADC_REG_RANK_15                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
00732 #define LL_ADC_REG_RANK_16                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
00733 /**
00734   * @}
00735   */
00736 
00737 /** @defgroup ADC_LL_EC_INJ_TRIG_SOURCE  ADC group injected - Trigger source
00738   * @{
00739   */
00740 #define LL_ADC_INJ_TRIG_SW_START           ((uint32_t)0x00000000)                                                                                              /*!< ADC group injected conversion trigger internal (SW start). Trigger edge set to rising edge (default setting). */
00741 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO      (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                                     /*!< ADC group injected conversion trigger external from TIM1 TRGO. Trigger edge set to rising edge (default setting). */
00742 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2     (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!< ADC group injected conversion trigger external from TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
00743 #define LL_ADC_INJ_TRIG_EXT_TIM1_CC4       (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!< ADC group injected conversion trigger external from TIM1 CC4. Trigger edge set to rising edge (default setting). */
00744 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO      (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!< ADC group injected conversion trigger external from TIM2 TRGO. Trigger edge set to rising edge (default setting). */
00745 #define LL_ADC_INJ_TRIG_EXT_TIM2_CC1       (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger external from TIM2 CC1. Trigger edge set to rising edge (default setting). */
00746 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger external from TIM3 TRGO. Trigger edge set to rising edge (default setting). */
00747 #define LL_ADC_INJ_TRIG_EXT_TIM3_CC1       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger external from TIM3 CC1. Trigger edge set to rising edge (default setting). */
00748 #define LL_ADC_INJ_TRIG_EXT_TIM3_CC3       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger external from TIM3 CC3. Trigger edge set to rising edge (default setting). */
00749 #define LL_ADC_INJ_TRIG_EXT_TIM3_CC4       (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!< ADC group injected conversion trigger external from TIM3 CC4. Trigger edge set to rising edge (default setting). */
00750 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO      (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger external from TIM4 TRGO. Trigger edge set to rising edge (default setting). */
00751 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger external from TIM6 TRGO. Trigger edge set to rising edge (default setting). */
00752 #define LL_ADC_INJ_TRIG_EXT_TIM8_CC4       (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger external from TIM8 CC4. Trigger edge set to rising edge (default setting). */
00753 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger external from TIM8 TRGO. Trigger edge set to rising edge (default setting). */
00754 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger external from TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
00755 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger external from TIM15 TRGO. Trigger edge set to rising edge (default setting). */
00756 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15    (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger external from external interrupt line 15. Trigger edge set to rising edge (default setting). */
00757 /**
00758   * @}
00759   */
00760 
00761 /** @defgroup ADC_LL_EC_INJ_TRIG_EDGE  ADC group injected - Trigger edge
00762   * @{
00763   */
00764 #define LL_ADC_INJ_TRIG_EXT_RISING         (                    ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
00765 #define LL_ADC_INJ_TRIG_EXT_FALLING        (ADC_JSQR_JEXTEN_1                    ) /*!< ADC group injected conversion trigger polarity set to falling edge */
00766 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING  (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
00767 /**
00768   * @}
00769   */
00770 
00771 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO  ADC group injected - Trigger automatic mode
00772 * @{
00773 */
00774 #define LL_ADC_INJ_TRIG_INDEPENDENT        ((uint32_t)0x00000000) /*!< ADC group injected conversion trigger independent */
00775 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR   (ADC_CFGR_JAUTO)       /*!< ADC group injected conversion trigger from ADC group regular */
00776 /**
00777   * @}
00778   */
00779 
00780 /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE  ADC group injected - Context queue mode
00781   * @{
00782   */
00783 #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE ((uint32_t)0x00000000) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
00784 #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY   (ADC_CFGR_JQM)         /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
00785 #define LL_ADC_INJ_QUEUE_DISABLE               (ADC_CFGR_JQDIS)       /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */
00786 /**
00787   * @}
00788   */
00789 
00790 /** @defgroup ADC_LL_EC_INJ_SEQ_LENGTH  ADC group injected - Sequencer length
00791   * @{
00792   */
00793 #define LL_ADC_INJ_SEQ_SCAN_DISABLE        ((uint32_t)0x00000000)          /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
00794 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS  (                ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
00795 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS  (ADC_JSQR_JL_1                ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
00796 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS  (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
00797 /**
00798   * @}
00799   */
00800 
00801 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT  ADC group injected - Sequencer discontinuous mode
00802   * @{
00803   */
00804 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE     ((uint32_t)0x00000000) /*!< ADC group injected sequencer discontinuous mode disable */
00805 #define LL_ADC_INJ_SEQ_DISCONT_1RANK       (ADC_CFGR_JDISCEN)     /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
00806 /**
00807   * @}
00808   */
00809 
00810 /** @defgroup ADC_LL_EC_INJ_RANKS  ADC group injected - Sequencer ranks
00811   * @{
00812   */
00813 #define LL_ADC_INJ_RANK_1                  (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
00814 #define LL_ADC_INJ_RANK_2                  (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
00815 #define LL_ADC_INJ_RANK_3                  (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
00816 #define LL_ADC_INJ_RANK_4                  (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
00817 /**
00818   * @}
00819   */
00820 
00821 /** @defgroup ADC_LL_EC_SAMPLINGTIME  Channel - Sampling time
00822   * @{
00823   */
00824 #define LL_ADC_SAMPLINGTIME_2CYCLES_5      (0x00000000)                                                /*!< Sampling time 2.5 ADC clock cycle */
00825 #define LL_ADC_SAMPLINGTIME_6CYCLES_5      (                                        ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */
00826 #define LL_ADC_SAMPLINGTIME_12CYCLES_5     (                    ADC_SMPR2_SMP10_1                    ) /*!< Sampling time 12.5 ADC clock cycles */
00827 #define LL_ADC_SAMPLINGTIME_24CYCLES_5     (                    ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */
00828 #define LL_ADC_SAMPLINGTIME_47CYCLES_5     (ADC_SMPR2_SMP10_2                                        ) /*!< Sampling time 47.5 ADC clock cycles */
00829 #define LL_ADC_SAMPLINGTIME_92CYCLES_5     (ADC_SMPR2_SMP10_2                     | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */
00830 #define LL_ADC_SAMPLINGTIME_247CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1                    ) /*!< Sampling time 247.5 ADC clock cycles */
00831 #define LL_ADC_SAMPLINGTIME_640CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */
00832 /**
00833   * @}
00834   */
00835 
00836 /** @defgroup ADC_LL_EC_SINGLE_DIFF_ENDING  Channel - Single or differential ending
00837   * @{
00838   */
00839 #define LL_ADC_SINGLE_ENDED                (                  ADC_CALFACT_CALFACT_S)         /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
00840 #define LL_ADC_DIFFERENTIAL_ENDED          (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)         /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
00841 #define LL_ADC_BOTH_SINGLE_DIFF_ENDED      (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */
00842 /**
00843   * @}
00844   */
00845 
00846 /** @defgroup ADC_LL_EC_AWD Analog watchdog - Analog watchdog number
00847   * @{
00848   */
00849 #define LL_ADC_AWD1                        (ADC_AWD_CR1_CHANNEL_MASK  | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
00850 #define LL_ADC_AWD2                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
00851 #define LL_ADC_AWD3                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
00852 /**
00853   * @}
00854   */
00855 
00856 /** @defgroup ADC_LL_EC_AWD_CHANNELS  Analog watchdog - Monitored channels
00857   * @{
00858   */
00859 #define LL_ADC_AWD_DISABLE                 ((uint32_t)0x00000000)
00860 #define LL_ADC_AWD_ALL_CHANNELS_REG        (ADC_AWD_CR23_CHANNEL_MASK                                    | ADC_CFGR_AWD1EN                   ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
00861 #define LL_ADC_AWD_ALL_CHANNELS_INJ        (ADC_AWD_CR23_CHANNEL_MASK                 | ADC_CFGR_JAWD1EN                                     ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
00862 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ    (ADC_AWD_CR23_CHANNEL_MASK                 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN                   ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
00863 #define LL_ADC_AWD_CHANNEL_0_REG           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
00864 #define LL_ADC_AWD_CHANNEL_0_INJ           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
00865 #define LL_ADC_AWD_CHANNEL_0_REG_INJ       ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
00866 #define LL_ADC_AWD_CHANNEL_1_REG           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
00867 #define LL_ADC_AWD_CHANNEL_1_INJ           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
00868 #define LL_ADC_AWD_CHANNEL_1_REG_INJ       ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
00869 #define LL_ADC_AWD_CHANNEL_2_REG           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
00870 #define LL_ADC_AWD_CHANNEL_2_INJ           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
00871 #define LL_ADC_AWD_CHANNEL_2_REG_INJ       ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
00872 #define LL_ADC_AWD_CHANNEL_3_REG           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
00873 #define LL_ADC_AWD_CHANNEL_3_INJ           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
00874 #define LL_ADC_AWD_CHANNEL_3_REG_INJ       ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
00875 #define LL_ADC_AWD_CHANNEL_4_REG           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
00876 #define LL_ADC_AWD_CHANNEL_4_INJ           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
00877 #define LL_ADC_AWD_CHANNEL_4_REG_INJ       ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
00878 #define LL_ADC_AWD_CHANNEL_5_REG           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
00879 #define LL_ADC_AWD_CHANNEL_5_INJ           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
00880 #define LL_ADC_AWD_CHANNEL_5_REG_INJ       ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
00881 #define LL_ADC_AWD_CHANNEL_6_REG           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
00882 #define LL_ADC_AWD_CHANNEL_6_INJ           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
00883 #define LL_ADC_AWD_CHANNEL_6_REG_INJ       ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
00884 #define LL_ADC_AWD_CHANNEL_7_REG           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
00885 #define LL_ADC_AWD_CHANNEL_7_INJ           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
00886 #define LL_ADC_AWD_CHANNEL_7_REG_INJ       ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
00887 #define LL_ADC_AWD_CHANNEL_8_REG           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
00888 #define LL_ADC_AWD_CHANNEL_8_INJ           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
00889 #define LL_ADC_AWD_CHANNEL_8_REG_INJ       ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
00890 #define LL_ADC_AWD_CHANNEL_9_REG           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
00891 #define LL_ADC_AWD_CHANNEL_9_INJ           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
00892 #define LL_ADC_AWD_CHANNEL_9_REG_INJ       ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
00893 #define LL_ADC_AWD_CHANNEL_10_REG          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
00894 #define LL_ADC_AWD_CHANNEL_10_INJ          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
00895 #define LL_ADC_AWD_CHANNEL_10_REG_INJ      ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
00896 #define LL_ADC_AWD_CHANNEL_11_REG          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
00897 #define LL_ADC_AWD_CHANNEL_11_INJ          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
00898 #define LL_ADC_AWD_CHANNEL_11_REG_INJ      ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
00899 #define LL_ADC_AWD_CHANNEL_12_REG          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
00900 #define LL_ADC_AWD_CHANNEL_12_INJ          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
00901 #define LL_ADC_AWD_CHANNEL_12_REG_INJ      ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
00902 #define LL_ADC_AWD_CHANNEL_13_REG          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
00903 #define LL_ADC_AWD_CHANNEL_13_INJ          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
00904 #define LL_ADC_AWD_CHANNEL_13_REG_INJ      ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
00905 #define LL_ADC_AWD_CHANNEL_14_REG          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
00906 #define LL_ADC_AWD_CHANNEL_14_INJ          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
00907 #define LL_ADC_AWD_CHANNEL_14_REG_INJ      ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
00908 #define LL_ADC_AWD_CHANNEL_15_REG          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
00909 #define LL_ADC_AWD_CHANNEL_15_INJ          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
00910 #define LL_ADC_AWD_CHANNEL_15_REG_INJ      ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
00911 #define LL_ADC_AWD_CHANNEL_16_REG          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
00912 #define LL_ADC_AWD_CHANNEL_16_INJ          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
00913 #define LL_ADC_AWD_CHANNEL_16_REG_INJ      ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
00914 #define LL_ADC_AWD_CHANNEL_17_REG          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
00915 #define LL_ADC_AWD_CHANNEL_17_INJ          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
00916 #define LL_ADC_AWD_CHANNEL_17_REG_INJ      ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
00917 #define LL_ADC_AWD_CHANNEL_18_REG          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
00918 #define LL_ADC_AWD_CHANNEL_18_INJ          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
00919 #define LL_ADC_AWD_CHANNEL_18_REG_INJ      ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
00920 #define LL_ADC_AWD_CH_VREFINT_REG          ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
00921 #define LL_ADC_AWD_CH_VREFINT_INJ          ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
00922 #define LL_ADC_AWD_CH_VREFINT_REG_INJ      ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
00923 #define LL_ADC_AWD_CH_TEMPSENSOR_REG       ((LL_ADC_CHANNEL_TEMPSENSOR    & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
00924 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ       ((LL_ADC_CHANNEL_TEMPSENSOR    & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
00925 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   ((LL_ADC_CHANNEL_TEMPSENSOR    & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
00926 #define LL_ADC_AWD_CH_VBAT_REG             ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through an dividor ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
00927 #define LL_ADC_AWD_CH_VBAT_INJ             ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through an dividor ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
00928 #define LL_ADC_AWD_CH_VBAT_REG_INJ         ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through an dividor ladder of factor 1/3 to have Vbat always below Vdda */
00929 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG     ((LL_ADC_CHANNEL_DAC1CH1_ADC2  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
00930 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ     ((LL_ADC_CHANNEL_DAC1CH1_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
00931 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
00932 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG     ((LL_ADC_CHANNEL_DAC1CH2_ADC2  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
00933 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ     ((LL_ADC_CHANNEL_DAC1CH2_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
00934 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
00935 #define LL_ADC_AWD_CH_DAC1CH1_ADC3_REG     ((LL_ADC_CHANNEL_DAC1CH1_ADC3  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only */
00936 #define LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ     ((LL_ADC_CHANNEL_DAC1CH1_ADC3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only */
00937 #define LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected */
00938 #define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG     ((LL_ADC_CHANNEL_DAC1CH2_ADC3  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only */
00939 #define LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ     ((LL_ADC_CHANNEL_DAC1CH2_ADC3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only */
00940 #define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected */
00941 /**
00942   * @}
00943   */
00944 
00945 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS  Analog watchdog - Thresholds
00946   * @{
00947   */
00948 #define LL_ADC_AWD_THRESHOLD_HIGH          (ADC_TR1_HT1              ) /*!< ADC analog watchdog threshold high */
00949 #define LL_ADC_AWD_THRESHOLD_LOW           (              ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */
00950 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW     (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
00951 /**
00952   * @}
00953   */
00954 
00955 /** @defgroup ADC_LL_EC_OVS  Oversampling - Oversampling scope
00956   * @{
00957   */
00958 #define LL_ADC_OVS_DISABLE                 ((uint32_t)0x00000000)
00959 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED   (                                    ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued. */
00960 #define LL_ADC_OVS_GRP_REGULAR_RESUMED     (ADC_CFGR2_ROVSM |                   ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
00961 #define LL_ADC_OVS_GRP_INJECTED            (                  ADC_CFGR2_JOVSE                  ) /*!< ADC oversampling on conversions of ADC group injected */
00962 #define LL_ADC_OVS_GRP_INJ_REG_RESUMED     (                  ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
00963 /**
00964   * @}
00965   */
00966 
00967 /** @defgroup ADC_LL_EC_OVS_DISCONT  Oversampling - Discontinuous mode
00968   * @{
00969   */
00970 #define LL_ADC_OVS_REG_CONT                ((uint32_t)0x00000000) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
00971 #define LL_ADC_OVS_REG_DISCONT             (ADC_CFGR2_TROVS)      /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
00972 /**
00973   * @}
00974   */
00975 
00976 /** @defgroup ADC_LL_EC_OVS_RATIO  Oversampling - Ratio
00977   * @{
00978   */
00979 #define LL_ADC_OVS_RATIO_2                 ((uint32_t)0x00000000)                                   /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00980 #define LL_ADC_OVS_RATIO_4                 (                                      ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00981 #define LL_ADC_OVS_RATIO_8                 (                   ADC_CFGR2_OVSR_1                   ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00982 #define LL_ADC_OVS_RATIO_16                (                   ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00983 #define LL_ADC_OVS_RATIO_32                (ADC_CFGR2_OVSR_2                                      ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00984 #define LL_ADC_OVS_RATIO_64                (ADC_CFGR2_OVSR_2                    | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00985 #define LL_ADC_OVS_RATIO_128               (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1                   ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00986 #define LL_ADC_OVS_RATIO_256               (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
00987 /**
00988   * @}
00989   */
00990 
00991 /** @defgroup ADC_LL_EC_OVS_RIGHTBITSHIFT  Oversampling - Data right shift
00992   * @{
00993   */
00994 #define LL_ADC_OVS_DATA_SHIFT_NONE         ((uint32_t)0x00000000)                                                      /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
00995 #define LL_ADC_OVS_DATA_SHIFT_1            (                                                         ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
00996 #define LL_ADC_OVS_DATA_SHIFT_2            (                                      ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
00997 #define LL_ADC_OVS_DATA_SHIFT_3            (                                      ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
00998 #define LL_ADC_OVS_DATA_SHIFT_4            (                   ADC_CFGR2_OVSS_2                                      ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
00999 #define LL_ADC_OVS_DATA_SHIFT_5            (                   ADC_CFGR2_OVSS_2                    | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
01000 #define LL_ADC_OVS_DATA_SHIFT_6            (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
01001 #define LL_ADC_OVS_DATA_SHIFT_7            (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
01002 #define LL_ADC_OVS_DATA_SHIFT_8            (ADC_CFGR2_OVSS_3                                                         ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
01003 /**
01004   * @}
01005   */
01006 
01007 #if defined(ADC2)
01008 /** @defgroup ADC_LL_EC_MULTI  Multimode - Mode
01009   * @{
01010   */
01011 #define LL_ADC_MULTI_INDEPENDENT           ((uint32_t)0x00000000)                                              /*!< ADC dual mode disabled (ADC independent mode) */
01012 #define LL_ADC_MULTI_DUAL_REG_SIMULT       (                 ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1                 ) /*!< ADC dual mode enabled: group regular simultaneous */
01013 #define LL_ADC_MULTI_DUAL_REG_INTERL       (                 ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
01014 #define LL_ADC_MULTI_DUAL_INJ_SIMULT       (                 ADC_CCR_DUAL_2                  | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */
01015 #define LL_ADC_MULTI_DUAL_INJ_ALTERN       (ADC_CCR_DUAL_3                                   | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
01016 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM  (                                                   ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
01017 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT  (                                  ADC_CCR_DUAL_1                 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
01018 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM  (                                  ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
01019 /**
01020   * @}
01021   */
01022 
01023 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER  Multimode - DMA transfer
01024   * @{
01025   */
01026 #define LL_ADC_MULTI_REG_DMA_EACH_ADC        ((uint32_t)0x00000000)                             /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
01027 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B (                 ADC_CCR_MDMA_1                 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits */
01028 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B   (                 ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits */
01029 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1                 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits */
01030 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B   (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 8 and 6 bits */
01031 /**
01032   * @}
01033   */
01034 
01035 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY  Multimode - Delay between two sampling phases
01036   * @{
01037   */
01038 #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE   ((uint32_t)0x00000000)                                                  /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */
01039 #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES  (                                                      ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */
01040 #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES  (                                    ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */
01041 #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES  (                                    ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */
01042 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES  (                  ADC_CCR_DELAY_2                                    ) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */
01043 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (                  ADC_CCR_DELAY_2                   | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
01044 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
01045 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
01046 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (ADC_CCR_DELAY_3                                                      ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
01047 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3                                     | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
01048 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3                   | ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
01049 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3                   | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
01050 /**
01051   * @}
01052   */
01053 
01054 /** @defgroup ADC_LL_EC_MULTI_CONV_DATA  Multimode - ADC master or slave
01055   * @{
01056   */
01057 #define LL_ADC_MULTI_MASTER                (                    ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
01058 #define LL_ADC_MULTI_SLAVE                 (ADC_CDR_RDATA_SLV                    ) /*!< In multimode, selection among several ADC instances: ADC slave */
01059 #define LL_ADC_MULTI_MASTER_SLAVE          (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
01060 /**
01061   * @}
01062   */
01063 
01064 #endif /* ADC2 */
01065 
01066 /**
01067   * @}
01068   */
01069 
01070 
01071 /* Exported macro ------------------------------------------------------------*/
01072 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
01073   * @{
01074   */
01075 
01076 /** @defgroup ADC_LL_EM_WRITE_READ Common Write and read registers Macros
01077   * @{
01078   */
01079 
01080 /**
01081   * @brief  Write a value in ADC register
01082   * @param  __INSTANCE__ ADC Instance
01083   * @param  __REG__ Register to be written
01084   * @param  __VALUE__ Value to be written in the register
01085   * @retval None
01086   */
01087 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
01088 
01089 /**
01090   * @brief  Read a value in ADC register
01091   * @param  __INSTANCE__ ADC Instance
01092   * @param  __REG__ Register to be read
01093   * @retval Register value
01094   */
01095 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
01096 /**
01097   * @}
01098   */
01099 
01100 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
01101   * @{
01102   */
01103 
01104 /**
01105   * @brief  Helper macro to get ADC channel number in decimal format
01106   *         from literals LL_ADC_CHANNEL_x.
01107   * @note   Example:
01108   *            __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
01109   *            will return decimal number "4".
01110   * @note   The input can be a value from functions where a channel
01111   *         number is returned, either defined with number
01112   *         or with bitfield (only one bit must be set).
01113   * @param  __CHANNEL__ This parameter can be one of the following values:
01114   *         @arg @ref LL_ADC_CHANNEL_0
01115   *         @arg @ref LL_ADC_CHANNEL_1           (5)
01116   *         @arg @ref LL_ADC_CHANNEL_2           (5)
01117   *         @arg @ref LL_ADC_CHANNEL_3           (5)
01118   *         @arg @ref LL_ADC_CHANNEL_4           (5)
01119   *         @arg @ref LL_ADC_CHANNEL_5           (5)
01120   *         @arg @ref LL_ADC_CHANNEL_6
01121   *         @arg @ref LL_ADC_CHANNEL_7
01122   *         @arg @ref LL_ADC_CHANNEL_8
01123   *         @arg @ref LL_ADC_CHANNEL_9
01124   *         @arg @ref LL_ADC_CHANNEL_10
01125   *         @arg @ref LL_ADC_CHANNEL_11
01126   *         @arg @ref LL_ADC_CHANNEL_12
01127   *         @arg @ref LL_ADC_CHANNEL_13
01128   *         @arg @ref LL_ADC_CHANNEL_14
01129   *         @arg @ref LL_ADC_CHANNEL_15
01130   *         @arg @ref LL_ADC_CHANNEL_16
01131   *         @arg @ref LL_ADC_CHANNEL_17
01132   *         @arg @ref LL_ADC_CHANNEL_18
01133   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
01134   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
01135   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
01136   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
01137   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
01138   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
01139   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
01140   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.
01141   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.
01142   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.
01143   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
01144   *         (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
01145   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
01146   * @retval 0...18
01147   */
01148 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                                             \
01149   ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) != 0)                                        \
01150     ? (                                                                                         \
01151        POSITION_VAL((__CHANNEL__))                                                              \
01152       )                                                                                         \
01153       :                                                                                         \
01154       (                                                                                         \
01155        ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) \
01156       )                                                                                         \
01157   )
01158 
01159 /**
01160   * @brief  Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
01161   *         from number in decimal format.
01162   * @note   Example:
01163   *           __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
01164   *           will return a data equivalent to "LL_ADC_CHANNEL_4".
01165   * @param  __DECIMAL_NB__: 0...18
01166   * @retval Returned value can be one of the following values:
01167   *         @arg @ref LL_ADC_CHANNEL_0
01168   *         @arg @ref LL_ADC_CHANNEL_1           (5)
01169   *         @arg @ref LL_ADC_CHANNEL_2           (5)
01170   *         @arg @ref LL_ADC_CHANNEL_3           (5)
01171   *         @arg @ref LL_ADC_CHANNEL_4           (5)
01172   *         @arg @ref LL_ADC_CHANNEL_5           (5)
01173   *         @arg @ref LL_ADC_CHANNEL_6
01174   *         @arg @ref LL_ADC_CHANNEL_7
01175   *         @arg @ref LL_ADC_CHANNEL_8
01176   *         @arg @ref LL_ADC_CHANNEL_9
01177   *         @arg @ref LL_ADC_CHANNEL_10
01178   *         @arg @ref LL_ADC_CHANNEL_11
01179   *         @arg @ref LL_ADC_CHANNEL_12
01180   *         @arg @ref LL_ADC_CHANNEL_13
01181   *         @arg @ref LL_ADC_CHANNEL_14
01182   *         @arg @ref LL_ADC_CHANNEL_15
01183   *         @arg @ref LL_ADC_CHANNEL_16
01184   *         @arg @ref LL_ADC_CHANNEL_17
01185   *         @arg @ref LL_ADC_CHANNEL_18
01186   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
01187   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
01188   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
01189   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
01190   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
01191   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
01192   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
01193   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.
01194   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.
01195   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.
01196   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
01197   *         (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
01198   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
01199   *         (1, 2, 3, 4) For ADC channel read back from ADC register,
01200   *                      comparison with internal channel parameter to be done
01201   *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
01202   */
01203 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                                                          \
01204   (((__DECIMAL_NB__) <= 9)                                                                                      \
01205     ? (                                                                                                         \
01206        ((__DECIMAL_NB__) << POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK))                                  |        \
01207        (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                                       |        \
01208        (ADC_SMPR1_REGOFFSET | (((uint32_t) (3 * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))          \
01209       )                                                                                                         \
01210       :                                                                                                         \
01211       (                                                                                                         \
01212        ((__DECIMAL_NB__) << POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK))                                         | \
01213        (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                                              | \
01214        (ADC_SMPR2_REGOFFSET | (((uint32_t) (3 * ((__DECIMAL_NB__) - 10))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))   \
01215       )                                                                                                         \
01216   )
01217 
01218 /**
01219   * @brief  Helper macro to determine whether the channel corresponds to
01220   *         parameters definitions of driver:
01221   *          * Parameter definition of a ADC internal channel
01222   *            (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...)
01223   *          * Parameter definition of a ADC external channel (channel connected
01224   *            to a GPIO pin) (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
01225   * @note   The channel parameter must be a value defined from parameter
01226   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
01227   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
01228   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
01229   *         must not be a value from functions where a channel number is
01230   *         returned from ADC registers,
01231   *         because internal and external channels share the same channel
01232   *         number in ADC registers. The differentiation is made only with
01233   *         parameters definitions of driver.
01234   * @param  __CHANNEL__ This parameter can be one of the following values:
01235   *         @arg @ref LL_ADC_CHANNEL_0
01236   *         @arg @ref LL_ADC_CHANNEL_1           (5)
01237   *         @arg @ref LL_ADC_CHANNEL_2           (5)
01238   *         @arg @ref LL_ADC_CHANNEL_3           (5)
01239   *         @arg @ref LL_ADC_CHANNEL_4           (5)
01240   *         @arg @ref LL_ADC_CHANNEL_5           (5)
01241   *         @arg @ref LL_ADC_CHANNEL_6
01242   *         @arg @ref LL_ADC_CHANNEL_7
01243   *         @arg @ref LL_ADC_CHANNEL_8
01244   *         @arg @ref LL_ADC_CHANNEL_9
01245   *         @arg @ref LL_ADC_CHANNEL_10
01246   *         @arg @ref LL_ADC_CHANNEL_11
01247   *         @arg @ref LL_ADC_CHANNEL_12
01248   *         @arg @ref LL_ADC_CHANNEL_13
01249   *         @arg @ref LL_ADC_CHANNEL_14
01250   *         @arg @ref LL_ADC_CHANNEL_15
01251   *         @arg @ref LL_ADC_CHANNEL_16
01252   *         @arg @ref LL_ADC_CHANNEL_17
01253   *         @arg @ref LL_ADC_CHANNEL_18
01254   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
01255   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
01256   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
01257   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
01258   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
01259   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
01260   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
01261   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.
01262   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.
01263   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.
01264   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
01265   *         (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
01266   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
01267   * @retval 0 if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin)
01268   *         1 if the channel corresponds to a parameter definition of a ADC internal channel
01269   */
01270 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                              \
01271   (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0)
01272 
01273 /**
01274   * @brief  Helper macro to convert a channel defined from parameter
01275   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
01276   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
01277   *         to its equivalent parameter definition of a ADC external channel
01278   *         (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
01279   * @note   The channel parameter can be, additionally to a value 
01280   *         defined from parameter definition of a ADC internal channel
01281   *         (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
01282   *         a value defined from parameter definition of
01283   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
01284   *         or a value from functions where a channel number is returned
01285   *         from ADC registers.
01286   * @param  __CHANNEL__ This parameter can be one of the following values:
01287   *         @arg @ref LL_ADC_CHANNEL_0
01288   *         @arg @ref LL_ADC_CHANNEL_1           (5)
01289   *         @arg @ref LL_ADC_CHANNEL_2           (5)
01290   *         @arg @ref LL_ADC_CHANNEL_3           (5)
01291   *         @arg @ref LL_ADC_CHANNEL_4           (5)
01292   *         @arg @ref LL_ADC_CHANNEL_5           (5)
01293   *         @arg @ref LL_ADC_CHANNEL_6
01294   *         @arg @ref LL_ADC_CHANNEL_7
01295   *         @arg @ref LL_ADC_CHANNEL_8
01296   *         @arg @ref LL_ADC_CHANNEL_9
01297   *         @arg @ref LL_ADC_CHANNEL_10
01298   *         @arg @ref LL_ADC_CHANNEL_11
01299   *         @arg @ref LL_ADC_CHANNEL_12
01300   *         @arg @ref LL_ADC_CHANNEL_13
01301   *         @arg @ref LL_ADC_CHANNEL_14
01302   *         @arg @ref LL_ADC_CHANNEL_15
01303   *         @arg @ref LL_ADC_CHANNEL_16
01304   *         @arg @ref LL_ADC_CHANNEL_17
01305   *         @arg @ref LL_ADC_CHANNEL_18
01306   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
01307   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
01308   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
01309   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
01310   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
01311   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
01312   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
01313   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.
01314   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.
01315   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.
01316   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
01317   *         (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
01318   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
01319   * @retval Returned value can be one of the following values:
01320   *         @arg @ref LL_ADC_CHANNEL_0
01321   *         @arg @ref LL_ADC_CHANNEL_1
01322   *         @arg @ref LL_ADC_CHANNEL_2
01323   *         @arg @ref LL_ADC_CHANNEL_3
01324   *         @arg @ref LL_ADC_CHANNEL_4
01325   *         @arg @ref LL_ADC_CHANNEL_5
01326   *         @arg @ref LL_ADC_CHANNEL_6
01327   *         @arg @ref LL_ADC_CHANNEL_7
01328   *         @arg @ref LL_ADC_CHANNEL_8
01329   *         @arg @ref LL_ADC_CHANNEL_9
01330   *         @arg @ref LL_ADC_CHANNEL_10
01331   *         @arg @ref LL_ADC_CHANNEL_11
01332   *         @arg @ref LL_ADC_CHANNEL_12
01333   *         @arg @ref LL_ADC_CHANNEL_13
01334   *         @arg @ref LL_ADC_CHANNEL_14
01335   *         @arg @ref LL_ADC_CHANNEL_15
01336   *         @arg @ref LL_ADC_CHANNEL_16
01337   *         @arg @ref LL_ADC_CHANNEL_17
01338   *         @arg @ref LL_ADC_CHANNEL_18
01339   */
01340 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                     \
01341   ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
01342 
01343 /**
01344   * @brief  Helper macro to determine whether the internal channel
01345   *         selected is available on the ADC instance selected.
01346   * @note   The channel parameter must be a value defined from parameter
01347   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
01348   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
01349   *         must not be a value defined from parameter definition of
01350   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
01351   *         or a value from functions where a channel number is
01352   *         returned from ADC registers,
01353   *         because internal and external channels share the same channel
01354   *         number in ADC registers. The differentiation is made only with
01355   *         parameters definitions of driver.
01356   * @param  __ADC_INSTANCE__ ADC instance
01357   * @param  __CHANNEL__ This parameter can be one of the following values:
01358   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
01359   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
01360   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
01361   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
01362   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
01363   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
01364   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
01365   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.
01366   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.
01367   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.
01368   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
01369   * @retval 0 if the internal channel selected is not available on the ADC instance selected.
01370   *         1 if the internal channel selected is available on the ADC instance selected.
01371   */
01372 #if defined (ADC1) && defined (ADC2) && defined (ADC3)
01373 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
01374   (((__ADC_INSTANCE__) == ADC1)                                                \
01375     ? (                                                                        \
01376        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                         \
01377        ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                         \
01378        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)                                  \
01379       )                                                                        \
01380       :                                                                        \
01381       ((__ADC_INSTANCE__) == ADC2)                                             \
01382       ? (                                                                      \
01383          ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)      ||                     \
01384          ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) ||                     \
01385          ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2)                        \
01386         )                                                                      \
01387         :                                                                      \
01388         ((__ADC_INSTANCE__) == ADC3)                                           \
01389         ? (                                                                    \
01390            ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)      ||                   \
01391            ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR)   ||                   \
01392            ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)         ||                   \
01393            ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC3) ||                   \
01394            ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC3)                      \
01395           )                                                                    \
01396           :                                                                    \
01397           (0)                                                                  \
01398   )
01399 #elif defined (ADC1) && defined (ADC2)
01400 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
01401   (((__ADC_INSTANCE__) == ADC1)                                                \
01402     ? (                                                                        \
01403        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                         \
01404        ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                         \
01405        ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)                                  \
01406       )                                                                        \
01407       :                                                                        \
01408       ((__ADC_INSTANCE__) == ADC2)                                             \
01409       ? (                                                                      \
01410          ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)      ||                     \
01411          ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) ||                     \
01412          ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2)                        \
01413         )                                                                      \
01414         :                                                                      \
01415         (0)                                                                    \
01416   )
01417 #elif defined (ADC1)
01418 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
01419   (                                                                            \
01420     ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                            \
01421     ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                            \
01422     ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)                                     \
01423   )
01424 #endif
01425 
01426 /**
01427   * @brief  Helper macro to define ADC analog watchdog parameter:
01428   *         define a single channel to monitor with analog watchdog
01429   *         from sequencer channel and groups definition.
01430   * @note   To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
01431   *         Example:
01432   *           LL_ADC_SetAnalogWDMonitChannels(
01433   *             ADC1, LL_ADC_AWD1,
01434   *             __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_REGULAR_GROUP))
01435   * @param  __CHANNEL__ This parameter can be one of the following values:
01436   *         @arg @ref LL_ADC_CHANNEL_0
01437   *         @arg @ref LL_ADC_CHANNEL_1           (5)
01438   *         @arg @ref LL_ADC_CHANNEL_2           (5)
01439   *         @arg @ref LL_ADC_CHANNEL_3           (5)
01440   *         @arg @ref LL_ADC_CHANNEL_4           (5)
01441   *         @arg @ref LL_ADC_CHANNEL_5           (5)
01442   *         @arg @ref LL_ADC_CHANNEL_6
01443   *         @arg @ref LL_ADC_CHANNEL_7
01444   *         @arg @ref LL_ADC_CHANNEL_8
01445   *         @arg @ref LL_ADC_CHANNEL_9
01446   *         @arg @ref LL_ADC_CHANNEL_10
01447   *         @arg @ref LL_ADC_CHANNEL_11
01448   *         @arg @ref LL_ADC_CHANNEL_12
01449   *         @arg @ref LL_ADC_CHANNEL_13
01450   *         @arg @ref LL_ADC_CHANNEL_14
01451   *         @arg @ref LL_ADC_CHANNEL_15
01452   *         @arg @ref LL_ADC_CHANNEL_16
01453   *         @arg @ref LL_ADC_CHANNEL_17
01454   *         @arg @ref LL_ADC_CHANNEL_18
01455   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
01456   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
01457   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
01458   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
01459   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
01460   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
01461   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
01462   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.
01463   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.
01464   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.
01465   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
01466   *         (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
01467   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
01468   *         (1, 2, 3, 4) For ADC channel read back from ADC register,
01469   *                      comparison with internal channel parameter to be done
01470   *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
01471   * @param  __GROUP__ This parameter can be one of the following values:
01472   *         @arg @ref LL_ADC_GROUP_REGULAR
01473   *         @arg @ref LL_ADC_GROUP_INJECTED
01474   *         @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
01475   * @retval Returned value can be one of the following values:
01476   *         @arg @ref LL_ADC_AWD_DISABLE
01477   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
01478   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
01479   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
01480   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
01481   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
01482   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
01483   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
01484   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
01485   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
01486   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
01487   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
01488   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
01489   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
01490   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
01491   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
01492   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
01493   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
01494   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
01495   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
01496   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
01497   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
01498   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
01499   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
01500   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
01501   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
01502   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
01503   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
01504   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
01505   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
01506   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
01507   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
01508   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
01509   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
01510   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
01511   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
01512   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
01513   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
01514   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
01515   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
01516   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
01517   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
01518   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
01519   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
01520   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
01521   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
01522   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
01523   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
01524   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
01525   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
01526   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
01527   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
01528   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
01529   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
01530   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
01531   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
01532   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
01533   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
01534   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
01535   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
01536   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
01537   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)(1)
01538   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)(1)
01539   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ         (1)
01540   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (0)(4)
01541   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (4)(4)
01542   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ      (4)
01543   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(4)
01544   *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(4)
01545   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (4)
01546   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG     (0)(2)
01547   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ     (0)(2)
01548   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ    (2)
01549   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG     (0)(2)
01550   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ     (0)(2)
01551   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ    (2)
01552   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG     (0)(3)
01553   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ     (0)(3)
01554   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ    (3)
01555   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG     (0)(3)
01556   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ     (0)(3)
01557   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ    (3)
01558   *         (0) On STM32L4, parameter available only on analog watchdog number: AWD1.
01559   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.
01560   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.
01561   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.
01562   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
01563   */
01564 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)                                           \
01565   (((__GROUP__) == LL_ADC_GROUP_REGULAR)                                                                  \
01566     ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)                        \
01567       :                                                                                                   \
01568       ((__GROUP__) == LL_ADC_GROUP_INJECTED)                                                              \
01569        ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)                    \
01570          :                                                                                                \
01571          (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  \
01572   )
01573 
01574 /**
01575   * @brief  Helper macro to get the ADC analog watchdog threshold high
01576   *         or low from raw value with both thresholds concatenated.
01577   * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
01578   *         Example, to get analog watchdog threshold high from the register raw value:
01579   *           __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
01580   * @param  __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
01581   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
01582   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
01583   * @param  __AWD_THRESHOLDS__ For AWD1: 0x000...0xFFF, for AWD2, AWD3: 0x00...0xFF
01584   * @retval 0x00000000...0xFFFFFFFF
01585   */
01586 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__)       \
01587   (((__AWD_THRESHOLDS__) >> POSITION_VAL((__AWD_THRESHOLD_TYPE__))) & LL_ADC_AWD_THRESHOLD_LOW)
01588 
01589 /**
01590   * @brief  Helper macro to set the ADC calibration value with both single ended
01591   *         and differential modes calibration factors concatenated.
01592   * @note   To be used with function @ref LL_ADC_SetCalibrationFactor().
01593   *         Example, to set calibration factors single ended to 0x55
01594   *         and differential ended to 0x2A:
01595   *           LL_ADC_SetCalibrationFactor(
01596   *             ADC1,
01597   *             __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
01598   * @param  __CALIB_FACTOR_SINGLE_ENDED__ 0x00...0x7F
01599   * @param  __CALIB_FACTOR_DIFFERENTIAL__ 0x00...0x7F
01600   * @retval 0x00000000...0xFFFFFFFF
01601   */
01602 #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__)        \
01603   (((__CALIB_FACTOR_DIFFERENTIAL__) << POSITION_VAL(ADC_CALFACT_CALFACT_D)) | (__CALIB_FACTOR_SINGLE_ENDED__))
01604 
01605 #if defined(ADC2)
01606 /**
01607   * @brief  Helper macro to get the ADC multimode conversion data of ADC master
01608   *         or ADC slave from raw value with both ADC conversion data concatenated.
01609   * @note   This macro is intended to be used when multimode transfer by DMA
01610   *         is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
01611   *         In this case the transferred data need to processed with this macro
01612   *         to separate the conversion data of ADC master and ADC slave.
01613   * @param  __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
01614   *         @arg @ref LL_ADC_MULTI_MASTER
01615   *         @arg @ref LL_ADC_MULTI_SLAVE
01616   * @param  __ADC_MULTI_CONV_DATA__ 0x000...0xFFF
01617   * @retval 0x000...0xFFF
01618   */
01619 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__)  \
01620   (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
01621 #endif
01622 
01623 /**
01624   * @brief  Helper macro to select the ADC common instance
01625   *         to which is belonging the selected ADC instance.
01626   * @note   ADC common register instance can be used for:
01627   *          * Set parameters common to several ADC instances
01628   *          * Multimode (for devices with several ADC instances)
01629   *         Refer to functions having argument "ADCxy_COMMON" as parameter.
01630   * @param  __ADCx__ ADC instance
01631   * @retval ADC common register instance
01632   */
01633 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
01634 #define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
01635   (ADC123_COMMON)
01636 #elif defined(ADC1) && defined(ADC2)
01637 #define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
01638   (ADC12_COMMON)
01639 #else
01640 #define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
01641   (ADC1_COMMON)
01642 #endif
01643 
01644 /**
01645   * @brief  Helper macro to check if all ADC instances sharing the same
01646   *         ADC common instance are disabled.
01647   * @note   This check is required by functions with setting conditioned to
01648   *         ADC state:
01649   *         All ADC instances of the ADC common group must be disabled.
01650   *         Refer to functions having argument "ADCxy_COMMON" as parameter.
01651   * @retval 0: All ADC instances sharing the same ADC common instance
01652   *            are disabled.
01653   *         1: At least one ADC instance sharing the same ADC common instance
01654   *            is enabled
01655   */
01656 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
01657 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE()                              \
01658   (LL_ADC_IsEnabled(ADC1) |                                                    \
01659    LL_ADC_IsEnabled(ADC2) |                                                    \
01660    LL_ADC_IsEnabled(ADC3)  )
01661 #elif defined(ADC1) && defined(ADC2)
01662 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE()                              \
01663   (LL_ADC_IsEnabled(ADC1) |                                                    \
01664    LL_ADC_IsEnabled(ADC2)  )
01665 #else
01666 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE()                              \
01667   LL_ADC_IsEnabled(ADC1)
01668 #endif
01669 
01670 /**
01671   * @brief  Helper macro to define the ADC conversion data full-scale digital
01672   *         value corresponding to the selected ADC resolution.
01673   * @note   ADC conversion data full-scale corresponds to voltage range 
01674   *         determined by analog voltage references Vref+ and Vref-,
01675   *         refer to reference manual)
01676   * @param  __RESOLUTION__ This parameter can be one of the following values:
01677   *         @arg @ref LL_ADC_RESOLUTION_12B
01678   *         @arg @ref LL_ADC_RESOLUTION_10B
01679   *         @arg @ref LL_ADC_RESOLUTION_8B
01680   *         @arg @ref LL_ADC_RESOLUTION_6B
01681   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
01682   */
01683 #define __LL_ADC_DIGITAL_SCALE(__RESOLUTION__)                                 \
01684   (((uint32_t)0xFFF) >> ((__RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1 )))
01685 
01686 /**
01687   * @brief  Helper macro to calculate the voltage (unit: mVolt)
01688   *         corresponding to a ADC conversion data (unit: digital value).
01689   * @note   ADC measurement data must correspond to a resolution of 12bits
01690   *         (full scale digital value 4095). If not the case, the data must be
01691   *         preliminarily rescaled to an equivalent resolution of 12 bits.
01692   * @note   Analog reference voltage (Vref+) must be either known from
01693   *         user board environment or can be calculated using ADC measurement
01694   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
01695   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
01696   * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
01697   *                       (unit: digital value).
01698   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
01699   */
01700 #define __LL_ADC_CALC_DATA_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__)       \
01701   ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) / __LL_ADC_DIGITAL_SCALE(LL_ADC_RESOLUTION_12B))
01702 
01703 /**
01704   * @brief  Helper macro to calculate analog reference voltage (Vref+)
01705   *         (unit: mVolt) from ADC conversion data of internal voltage
01706   *         reference VrefInt.
01707   *         Computation is using VrefInt calibration value
01708   *         stored in system memory for each device during production.
01709   * @note   This voltage depends on user board environment: voltage level
01710   *         connected to pin Vref+.
01711   *         On devices with small package, the pin Vref+ is not present
01712   *         and internally bonded to pin Vdda.
01713   * @note   ADC measurement data must correspond to a resolution of 12bits
01714   *         (full scale digital value 4095). If not the case, the data must be
01715   *         preliminarily rescaled to an equivalent resolution of 12 bits.
01716   * @param  __VREFINT_ADC_DATA__: ADC conversion data (resolution 12 bits)
01717   *         of internal voltage reference VrefInt (unit: digital value).
01718   * @retval Analog reference voltage (unit: mV)
01719   */
01720 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__)                 \
01721   (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) / (__VREFINT_ADC_DATA__))
01722 
01723 /**
01724   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
01725   *         from ADC conversion data of internal temperature sensor.
01726   *         Computation is using temperature sensor calibration values
01727   *         stored in system memory for each device during production.
01728   * @note   Calculation formula:
01729   *           Temperature = ((TS_ADC_DATA - TS_CAL1)
01730   *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))
01731   *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
01732   *           with TS_ADC_DATA = temperature sensor raw data measured by ADC
01733   *                Avg_Slope = (TS_CAL2 - TS_CAL1)
01734   *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)
01735   *                TS_CAL1   = equivalent TS_ADC_DATA at temperature
01736   *                            TEMP_DEGC_CAL1 (calibrated in factory)
01737   *                TS_CAL2   = equivalent TS_ADC_DATA at temperature
01738   *                            TEMP_DEGC_CAL2 (calibrated in factory)
01739   *         Caution: Calculation relevancy under reserve that calibration
01740   *                  parameters are correct (address and data).
01741   *                  To calculate temperature using temperature sensor
01742   *                  datasheet typical values (generic values less, therefore
01743   *                  less accurate than calibrated values),
01744   *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
01745   * @note   As calculation input, the analog reference voltage (Vref+) must be
01746   *         defined as it impacts the ADC LSB equivalent voltage.
01747   * @note   Analog reference voltage (Vref+) must be either known from
01748   *         user board environment or can be calculated using ADC measurement
01749   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
01750   * @note   ADC measurement data must correspond to a resolution of 12bits
01751   *         (full scale digital value 4095). If not the case, the data must be
01752   *         preliminarily rescaled to an equivalent resolution of 12 bits.
01753   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
01754   * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data (resolution 12 bits)
01755   *         of internal temperature sensor (unit: digital value).
01756   * @retval Temperature (unit: degree Celsius)
01757   */
01758 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__) \
01759   (((( ((int32_t)(((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))           \
01760                   / TEMPSENSOR_CAL_VREFANALOG)                                     \
01761         - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \
01762      ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \
01763     ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
01764    ) + TEMPSENSOR_CAL1_TEMP                                                        \
01765   )
01766 
01767 /**
01768   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
01769   *         from ADC conversion data of internal temperature sensor.
01770   *         Computation is using temperature sensor typical values
01771   *         (refer to device datasheet).
01772   * @note   Calculation formula:
01773   *           Temperature = (TS_ADC_DATA * conv_uV - TS_TYP_CAL1_VOLT)
01774   *                         / Avg_Slope + CAL1_TEMP
01775   *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC
01776   *                                   (unit: digital value)
01777   *                Avg_Slope        = temperature sensor slope
01778   *                                   (unit: uV/Degree Celsius)
01779   *                TS_TYP_CAL1_VOLT = temperature sensor digital value at
01780   *                                   temperature CAL1_TEMP (unit: mV)
01781   *         Caution: Calculation relevancy under reserve the temperature sensor
01782   *                  of the current device has characteristics in line with
01783   *                  datasheet typical values.
01784   *                  If temperature sensor calibration values are available on
01785   *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
01786   *                  temperature calculation will be more accurate using
01787   *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().
01788   * @note   As calculation input, the analog reference voltage (Vref+) must be
01789   *         defined as it impacts the ADC LSB equivalent voltage.
01790   * @note   Analog reference voltage (Vref+) must be either known from
01791   *         user board environment or can be calculated using ADC measurement
01792   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
01793   * @note   ADC measurement data must correspond to a resolution of 12bits
01794   *         (full scale digital value 4095). If not the case, the data must be
01795   *         preliminarily rescaled to an equivalent resolution of 12 bits.
01796   * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
01797   *                                       On STM32L4, refer to device datasheet parameter "Avg_Slope".
01798   * @param  __TEMPSENSOR_TYP_CAL1_V__     Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
01799   *                                       On STM32L4, refer to device datasheet parameter "V30".
01800   * @param  __TEMPSENSOR_CAL1_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding(unit: mV)
01801   * @param  __TEMPSENSOR_CAL_VREFANALOG__ Analog voltage reference (Vref+) voltage (unit: mV)
01802   * @param  __VREFANALOG_VOLTAGE__        Analog reference voltage at which temperature sensor voltage (see parameter above) is corresponding(unit: mV)
01803   * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data (resolution 12 bits) of internal
01804   *                                       temperature sensor (unit: digital value).
01805   * @retval Temperature (unit: degree Celsius)
01806   */
01807 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
01808                                              __TEMPSENSOR_TYP_CAL1_V__,\
01809                                              __TEMPSENSOR_CAL1_TEMP__,\
01810                                              __TEMPSENSOR_CAL_VREFANALOG__,\
01811                                              __VREFANALOG_VOLTAGE__,\
01812                                              __TEMPSENSOR_ADC_DATA__)          \
01813   ((( ((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \
01814                   / __LL_ADC_DIGITAL_SCALE(LL_ADC_RESOLUTION_12B))             \
01815                  * 1000)                                                       \
01816        -                                                                       \
01817        (int32_t)(((__TEMPSENSOR_TYP_CAL1_V__))                                 \
01818                  * 1000)                                                       \
01819       )                                                                        \
01820     ) / (__TEMPSENSOR_TYP_AVGSLOPE__)                                          \
01821    ) + (__TEMPSENSOR_CAL1_TEMP__)                                              \
01822   )
01823 
01824 /**
01825   * @}
01826   */
01827 
01828 /**
01829   * @}
01830   */
01831 
01832 
01833 /* Exported functions --------------------------------------------------------*/
01834 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
01835   * @{
01836   */
01837 
01838 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
01839   * @{
01840   */
01841 /* Note: LL ADC functions to set DMA transfer are located into sections of    */
01842 /*       configuration of ADC instance, groups and multimode (if available):  */
01843 /*       @ref LL_ADC_REG_SetDMATransfer(), ...                                */
01844 
01845 /**
01846   * @brief  Function to help to configure DMA transfer from ADC: retrieve the
01847   *         ADC register address from ADC instance and a list of ADC registers
01848   *         intended to be used (most commonly) with DMA transfer.
01849   *         These ADC registers are data registers:
01850   *         when ADC conversion data is available in ADC data registers,
01851   *         ADC generates a DMA transfer request.
01852   * @note   This macro is intended to be used with LL DMA driver, refer to 
01853   *         function "LL_DMA_ConfigAddresses()".
01854   *         Example:
01855   *           LL_DMA_ConfigAddresses(DMA1,
01856   *                                  LL_DMA_CHANNEL_1,
01857   *                                  LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
01858   *                                  (uint32_t)&< array or variable >,
01859   *                                  LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
01860   * @note   For devices with several ADC: in multimode, some devices
01861   *         use a different data register outside of ADC instance scope
01862   *         (common data register). This macro manages this register difference,
01863   *         only ADC instance has to be set as parameter.
01864   * @rmtoll DR       RDATA          LL_ADC_DMA_GetRegAddr\n
01865   *         CDR      RDATA_MST      LL_ADC_DMA_GetRegAddr\n
01866   *         CDR      RDATA_SLV      LL_ADC_DMA_GetRegAddr
01867   * @param  ADCx ADC instance
01868   * @param  Register This parameter can be one of the following values:
01869   *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
01870   *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
01871   *         (1) Available on devices with several ADC instances.
01872   * @retval ADC register address
01873   */
01874 #if defined(ADC2)
01875 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
01876 {
01877   register uint32_t data_reg_addr = 0;
01878   
01879   if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
01880   {
01881     /* Retrieve address of register DR */
01882     data_reg_addr = (uint32_t)&(ADCx->DR);
01883   }
01884   else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
01885   {
01886     /* Retrieve address of register CDR */
01887     data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
01888   }
01889   
01890   return data_reg_addr;
01891 }
01892 #else
01893 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
01894 {
01895   /* Retrieve address of register DR */
01896   return (uint32_t)&(ADCx->DR);
01897 }
01898 #endif
01899 
01900 /**
01901   * @}
01902   */
01903 
01904 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC
01905   * @{
01906   */
01907 
01908 /**
01909   * @brief  Set parameter common to several ADC: Clock source and prescaler.
01910   * @note   On this STM32 family, if ADC group injected is used, some
01911   *         clock ratio constraints between ADC clock and AHB clock
01912   *         must be respected.
01913   *         Refer to reference manual.
01914   * @note   On this STM32 family, setting of this feature is conditioned to
01915   *         ADC state:
01916   *         All ADC instances of the ADC common group must be disabled.
01917   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
01918   *         ADC instance or by using helper macro helper macro
01919   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
01920   * @rmtoll CCR      CKMODE         LL_ADC_SetCommonClock\n
01921   *         CCR      PRESC          LL_ADC_SetCommonClock
01922   * @param  ADCxy_COMMON ADC common instance
01923   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
01924   * @param  ClockSource This parameter can be one of the following values:
01925   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
01926   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
01927   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
01928   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
01929   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
01930   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
01931   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
01932   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
01933   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
01934   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
01935   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
01936   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
01937   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
01938   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
01939   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
01940   * @retval None
01941   */
01942 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ClockSource)
01943 {
01944   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, ClockSource);
01945 }
01946 
01947 /**
01948   * @brief  Get parameter common to several ADC: Clock source and prescaler.
01949   * @rmtoll CCR      CKMODE         LL_ADC_GetCommonClock\n
01950   *         CCR      PRESC          LL_ADC_GetCommonClock
01951   * @param  ADCxy_COMMON ADC common instance
01952   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
01953   * @retval Returned value can be one of the following values:
01954   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
01955   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
01956   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
01957   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
01958   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
01959   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
01960   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
01961   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
01962   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
01963   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
01964   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
01965   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
01966   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
01967   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
01968   *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
01969   */
01970 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
01971 {
01972   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
01973 }
01974 
01975 /**
01976   * @brief  Set parameter common to several ADC: measurement path to internal
01977   *         channels (VrefInt, temperature sensor, ...).
01978   *         One or several values can be selected.
01979   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
01980   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
01981   * @note   On this STM32 family, setting of this feature is conditioned to
01982   *         ADC state:
01983   *         All ADC instances of the ADC common group must be disabled.
01984   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
01985   *         ADC instance or by using helper macro helper macro
01986   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
01987   * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalCh\n
01988   *         CCR      TSEN           LL_ADC_SetCommonPathInternalCh\n
01989   *         CCR      VBATEN         LL_ADC_SetCommonPathInternalCh
01990   * @param  ADCxy_COMMON ADC common instance
01991   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
01992   * @param  PathInternal This parameter can be a combination of the following values:
01993   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
01994   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
01995   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
01996   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
01997   * @retval None
01998   */
01999 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
02000 {
02001   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
02002 }
02003 
02004 /**
02005   * @brief  Get parameter common to several ADC: measurement path to internal
02006   *         channels (VrefInt, temperature sensor, ...).
02007   *         One or several values can be selected.
02008   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
02009   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
02010   * @rmtoll CCR      VREFEN         LL_ADC_GetCommonPathInternalCh\n
02011   *         CCR      TSEN           LL_ADC_GetCommonPathInternalCh\n
02012   *         CCR      VBATEN         LL_ADC_GetCommonPathInternalCh
02013   * @param  ADCxy_COMMON ADC common instance
02014   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
02015   * @retval Returned value can be a combination of the following values:
02016   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
02017   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
02018   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
02019   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
02020   */
02021 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
02022 {
02023   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
02024 }
02025 
02026 /**
02027   * @}
02028   */
02029 
02030 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
02031   * @{
02032   */
02033 
02034 /**
02035   * @brief  Set ADC calibration factor in the mode single-ended
02036   *         or differential (for devices with differential mode available).
02037   *         This function is intended to set calibration parameters
02038   *         without performing a new calibration using
02039   *         @ref LL_ADC_StartCalibration().
02040   * @note   In case of setting calibration factors of both modes single ended
02041   *         and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
02042   *         both calibration factors must be concatenated.
02043   *         To perform this processing, use helper macro
02044   *         @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
02045   * @note   On this STM32 family, setting of this feature is conditioned to
02046   *         ADC state:
02047   *         ADC must be enabled, without calibration on going, without conversion
02048   *         on going on group regular.
02049   * @rmtoll CALFACT  CALFACT_S      LL_ADC_SetCalibrationFactor\n
02050   *         CALFACT  CALFACT_D      LL_ADC_SetCalibrationFactor
02051   * @param  ADCx ADC instance
02052   * @param  SingleDiff This parameter can be one of the following values:
02053   *         @arg @ref LL_ADC_SINGLE_ENDED
02054   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
02055   *         @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
02056   * @param  CalibrationFactor 0x00...0x7F
02057   * @retval None
02058   */
02059 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
02060 {
02061   MODIFY_REG(ADCx->CALFACT,
02062              SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
02063              CalibrationFactor << POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK));
02064 }
02065 
02066 /**
02067   * @brief  Get ADC calibration factor in the mode single-ended
02068   *         or differential (for devices with differential mode available).
02069   *         Calibration factors are set by hardware after performing a
02070   *         calibration  using function @ref LL_ADC_StartCalibration().
02071   * @rmtoll CALFACT  CALFACT_S      LL_ADC_GetCalibrationFactor\n
02072   *         CALFACT  CALFACT_D      LL_ADC_GetCalibrationFactor
02073   * @param  ADCx ADC instance
02074   * @param  SingleDiff This parameter can be one of the following values:
02075   *         @arg @ref LL_ADC_SINGLE_ENDED
02076   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
02077   * @retval 0x00...0x7F
02078   */
02079 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
02080 {
02081   /* Retrieve bits with position in register depending on parameter           */
02082   /* "SingleDiff".                                                            */
02083   /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because      */
02084   /* containing other bits reserved for other purpose.                        */
02085   return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK));
02086 }
02087 
02088 /**
02089   * @brief  Set ADC data resolution.
02090   *         Refer to reference manual for alignments formats versus ADC resolutions.
02091   * @note   On this STM32 family, setting of this feature is conditioned to
02092   *         ADC state:
02093   *         ADC must be disabled or enabled without conversion on going
02094   *         on either groups regular or injected.
02095   * @rmtoll CFGR     RES            LL_ADC_SetResolution
02096   * @param  ADCx ADC instance
02097   * @param  Resolution This parameter can be one of the following values:
02098   *         @arg @ref LL_ADC_RESOLUTION_12B
02099   *         @arg @ref LL_ADC_RESOLUTION_10B
02100   *         @arg @ref LL_ADC_RESOLUTION_8B
02101   *         @arg @ref LL_ADC_RESOLUTION_6B
02102   * @retval None
02103   */
02104 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
02105 {
02106   MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
02107 }
02108 
02109 /**
02110   * @brief  Get ADC data resolution.
02111   *         Refer to reference manual for alignments formats versus ADC resolutions.
02112   * @rmtoll CFGR     RES            LL_ADC_GetResolution
02113   * @param  ADCx ADC instance
02114   * @retval Returned value can be one of the following values:
02115   *         @arg @ref LL_ADC_RESOLUTION_12B
02116   *         @arg @ref LL_ADC_RESOLUTION_10B
02117   *         @arg @ref LL_ADC_RESOLUTION_8B
02118   *         @arg @ref LL_ADC_RESOLUTION_6B
02119   */
02120 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
02121 {
02122   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
02123 }
02124 
02125 /**
02126   * @brief  Set ADC conversion data alignment.
02127   *         Refer to reference manual for alignments formats 
02128   *         dependencies to ADC resolutions.
02129   * @note   On this STM32 family, setting of this feature is conditioned to
02130   *         ADC state:
02131   *         ADC must be disabled or enabled without conversion on going
02132   *         on either groups regular or injected.
02133   * @rmtoll CFGR     ALIGN          LL_ADC_SetDataAlignment
02134   * @param  ADCx ADC instance
02135   * @param  DataAlignment This parameter can be one of the following values:
02136   *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
02137   *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
02138   * @retval None
02139   */
02140 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
02141 {
02142   MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
02143 }
02144 
02145 /**
02146   * @brief  Get ADC conversion data alignment.
02147   *         Refer to reference manual for alignments formats 
02148   *         dependencies to ADC resolutions.
02149   * @rmtoll CFGR     ALIGN          LL_ADC_GetDataAlignment
02150   * @param  ADCx ADC instance
02151   * @retval Returned value can be one of the following values:
02152   *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
02153   *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
02154   */
02155 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
02156 {
02157   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
02158 }
02159 
02160 /**
02161   * @brief  Set ADC low power mode:
02162   *          * ADC low power mode "auto wait": Dynamic low power mode, 
02163   *            ADC conversions occurrences are limited to the minimum necessary
02164   *            in order to reduce power consumption.
02165   *            New ADC conversion starts only when the previous
02166   *            unitary conversion data (for ADC group regular)
02167   *            or previous sequence conversions data (for ADC group injected)
02168   *            has been retrieved by user software.
02169   *            In the meantime, ADC remains idle: does not performs any 
02170   *            other conversion.
02171   *            This mode allows to automatically adapt the ADC conversions
02172   *            trigs to the speed of the software that reads the data. 
02173   *            Moreover, this avoids risk of overrun for low frequency
02174   *            applications.
02175   *            How to use this low power mode:
02176   *             * Do not use with interruption or DMA since these modes
02177   *               have to clear immediately the EOC flag to free the
02178   *               IRQ vector sequencer.
02179   *             * Do use with polling: 1. Start conversion, 
02180   *               2. Later on, when conversion data is needed: poll for end of
02181   *               conversion  to ensure that conversion is completed and
02182   *               retrieve ADC conversion data. This will trig another
02183   *               ADC conversion start.
02184   *          * ADC low power mode "auto power-off" (feature available on 
02185   *            this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
02186   *            the ADC automatically powers-off after a conversion and 
02187   *            automatically wakes-up when a new conversion is triggered 
02188   *            (with startup time between trigger and start of sampling).
02189   *            This feature can be combined with low power mode "auto wait".
02190   * @note   With ADC low power mode "auto wait", the ADC conversion data read 
02191   *         is corresponding to previous ADC conversion start, independently 
02192   *         of delay during which ADC was idle.
02193   *         Therefore, the ADC conversion data may be outdated: does not
02194   *         correspond to the current voltage level on the selected
02195   *         ADC channel.
02196   * @note   On this STM32 family, setting of this feature is conditioned to
02197   *         ADC state:
02198   *         ADC must be disabled or enabled without conversion on going
02199   *         on either groups regular or injected.
02200   * @rmtoll CFGR     AUTDLY         LL_ADC_SetLowPowerMode
02201   * @param  ADCx ADC instance
02202   * @param  LowPowerMode This parameter can be one of the following values:
02203   *         @arg @ref LL_ADC_LP_MODE_NONE
02204   *         @arg @ref LL_ADC_LP_AUTOWAIT
02205   * @retval None
02206   */
02207 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
02208 {
02209   MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
02210 }
02211 
02212 /**
02213   * @brief  Get ADC low power mode:
02214   *          * ADC low power mode "auto wait": Dynamic low power mode, 
02215   *            ADC conversions occurrences are limited to the minimum necessary
02216   *            in order to reduce power consumption.
02217   *            New ADC conversion starts only when the previous
02218   *            unitary conversion data (for ADC group regular)
02219   *            or previous sequence conversions data (for ADC group injected)
02220   *            has been retrieved by user software.
02221   *            In the meantime, ADC remains idle: does not performs any 
02222   *            other conversion.
02223   *            This mode allows to automatically adapt the ADC conversions
02224   *            trigs to the speed of the software that reads the data. 
02225   *            Moreover, this avoids risk of overrun for low frequency
02226   *            applications.
02227   *            How to use this low power mode:
02228   *             * Do not use with interruption or DMA since these modes
02229   *               have to clear immediately the EOC flag to free the
02230   *               IRQ vector sequencer.
02231   *             * Do use with polling: 1. Start conversion, 
02232   *               2. Later on, when conversion data is needed: poll for end of
02233   *               conversion  to ensure that conversion is completed and
02234   *               retrieve ADC conversion data. This will trig another
02235   *               ADC conversion start.
02236   *          * ADC low power mode "auto power-off" (feature available on 
02237   *            this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
02238   *            the ADC automatically powers-off after a conversion and 
02239   *            automatically wakes-up when a new conversion is triggered 
02240   *            (with startup time between trigger and start of sampling).
02241   *            This feature can be combined with low power mode "auto wait".
02242   * @note   With ADC low power mode "auto wait", the ADC conversion data read 
02243   *         is corresponding to previous ADC conversion start, independently 
02244   *         of delay during which ADC was idle.
02245   *         Therefore, the ADC conversion data may be outdated: does not
02246   *         correspond to the current voltage level on the selected
02247   *         ADC channel.
02248   * @rmtoll CFGR     AUTDLY         LL_ADC_GetLowPowerMode
02249   * @param  ADCx ADC instance
02250   * @retval Returned value can be one of the following values:
02251   *         @arg @ref LL_ADC_LP_MODE_NONE
02252   *         @arg @ref LL_ADC_LP_AUTOWAIT
02253   */
02254 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
02255 {
02256   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
02257 }
02258 
02259 /**
02260   * @brief  Set ADC selected offset number 1, 2, 3 or 4:
02261   *          * ADC channel to which the offset programmed will be applied
02262   *            (independently of channel mapped on ADC group regular
02263   *            or group injected)
02264   *          * Offset level (offset to be subtracted from the raw
02265   *            converted data).
02266   *         Caution: Offset format is dependent to ADC resolution:
02267   *         offset has to be left-aligned on bit 11, the LSB (right bits)
02268   *         are set to 0.
02269   * @note   This function enables the offset, by default. It can be forced
02270   *         to disable state using function LL_ADC_SetOffsetState().
02271   * @note   If a channel is mapped on several offsets numbers, only the offset
02272   *         with the lowest value is considered for the subtraction.
02273   * @note   On this STM32 family, setting of this feature is conditioned to
02274   *         ADC state:
02275   *         ADC must be disabled or enabled without conversion on going
02276   *         on either groups regular or injected.
02277   * @note   On STM32L4, some fast channels are available: fast analog inputs
02278   *         coming from GPIO pads (ADC_IN1..5).
02279   * @rmtoll OFR1     OFFSET1_CH     LL_ADC_SetOffset\n
02280   *         OFR1     OFFSET1        LL_ADC_SetOffset\n
02281   *         OFR1     OFFSET1_EN     LL_ADC_SetOffset\n
02282   *         OFR2     OFFSET2_CH     LL_ADC_SetOffset\n
02283   *         OFR2     OFFSET2        LL_ADC_SetOffset\n
02284   *         OFR2     OFFSET2_EN     LL_ADC_SetOffset\n
02285   *         OFR3     OFFSET3_CH     LL_ADC_SetOffset\n
02286   *         OFR3     OFFSET3        LL_ADC_SetOffset\n
02287   *         OFR3     OFFSET3_EN     LL_ADC_SetOffset\n
02288   *         OFR4     OFFSET4_CH     LL_ADC_SetOffset\n
02289   *         OFR4     OFFSET4        LL_ADC_SetOffset\n
02290   *         OFR4     OFFSET4_EN     LL_ADC_SetOffset
02291   * @param  ADCx ADC instance
02292   * @param  Offsety This parameter can be one of the following values:
02293   *         @arg @ref LL_ADC_OFFSET_1
02294   *         @arg @ref LL_ADC_OFFSET_2
02295   *         @arg @ref LL_ADC_OFFSET_3
02296   *         @arg @ref LL_ADC_OFFSET_4
02297   * @param  Channel This parameter can be one of the following values:
02298   *         @arg @ref LL_ADC_CHANNEL_0
02299   *         @arg @ref LL_ADC_CHANNEL_1           (5)
02300   *         @arg @ref LL_ADC_CHANNEL_2           (5)
02301   *         @arg @ref LL_ADC_CHANNEL_3           (5)
02302   *         @arg @ref LL_ADC_CHANNEL_4           (5)
02303   *         @arg @ref LL_ADC_CHANNEL_5           (5)
02304   *         @arg @ref LL_ADC_CHANNEL_6
02305   *         @arg @ref LL_ADC_CHANNEL_7
02306   *         @arg @ref LL_ADC_CHANNEL_8
02307   *         @arg @ref LL_ADC_CHANNEL_9
02308   *         @arg @ref LL_ADC_CHANNEL_10
02309   *         @arg @ref LL_ADC_CHANNEL_11
02310   *         @arg @ref LL_ADC_CHANNEL_12
02311   *         @arg @ref LL_ADC_CHANNEL_13
02312   *         @arg @ref LL_ADC_CHANNEL_14
02313   *         @arg @ref LL_ADC_CHANNEL_15
02314   *         @arg @ref LL_ADC_CHANNEL_16
02315   *         @arg @ref LL_ADC_CHANNEL_17
02316   *         @arg @ref LL_ADC_CHANNEL_18
02317   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
02318   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
02319   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
02320   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
02321   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
02322   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
02323   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
02324   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.
02325   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.
02326   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.
02327   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
02328   *         (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
02329   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
02330   * @param  OffsetLevel 0x000...0xFFF
02331   * @retval None
02332   */
02333 __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef* ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
02334 {
02335   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
02336   
02337   MODIFY_REG(*preg,
02338              ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
02339              ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
02340 }
02341 
02342 /**
02343   * @brief  Get ADC selected offset number 1, 2, 3 or 4:
02344   *          * Channel to which the offset programmed will be applied
02345   *            (independently of channel mapped on ADC group regular
02346   *            or group injected)
02347   * @note   Usage of the returned channel number:
02348   *          - To reinject this channel into another function LL_ADC_xxx:
02349   *            the returned channel number is only partly formatted on definition
02350   *            of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
02351   *            with literals LL_ADC_CHANNEL_x, then the selected
02352   *            literal LL_ADC_CHANNEL_x can be used as parameter for another
02353   *            function.
02354   *          - To get the channel number in decimal format:
02355   *            process the returned value with the helper macro
02356   *            @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
02357   * @note   On STM32L4, some fast channels are available: fast analog inputs
02358   *         coming from GPIO pads (ADC_IN1..5).
02359   * @rmtoll OFR1     OFFSET1_CH     LL_ADC_GetOffsetChannel\n
02360   *         OFR2     OFFSET2_CH     LL_ADC_GetOffsetChannel\n
02361   *         OFR3     OFFSET3_CH     LL_ADC_GetOffsetChannel\n
02362   *         OFR4     OFFSET4_CH     LL_ADC_GetOffsetChannel
02363   * @param  ADCx ADC instance
02364   * @param  Offsety This parameter can be one of the following values:
02365   *         @arg @ref LL_ADC_OFFSET_1
02366   *         @arg @ref LL_ADC_OFFSET_2
02367   *         @arg @ref LL_ADC_OFFSET_3
02368   *         @arg @ref LL_ADC_OFFSET_4
02369   * @retval Returned value can be one of the following values:
02370   *         @arg @ref LL_ADC_CHANNEL_0
02371   *         @arg @ref LL_ADC_CHANNEL_1           (5)
02372   *         @arg @ref LL_ADC_CHANNEL_2           (5)
02373   *         @arg @ref LL_ADC_CHANNEL_3           (5)
02374   *         @arg @ref LL_ADC_CHANNEL_4           (5)
02375   *         @arg @ref LL_ADC_CHANNEL_5           (5)
02376   *         @arg @ref LL_ADC_CHANNEL_6
02377   *         @arg @ref LL_ADC_CHANNEL_7
02378   *         @arg @ref LL_ADC_CHANNEL_8
02379   *         @arg @ref LL_ADC_CHANNEL_9
02380   *         @arg @ref LL_ADC_CHANNEL_10
02381   *         @arg @ref LL_ADC_CHANNEL_11
02382   *         @arg @ref LL_ADC_CHANNEL_12
02383   *         @arg @ref LL_ADC_CHANNEL_13
02384   *         @arg @ref LL_ADC_CHANNEL_14
02385   *         @arg @ref LL_ADC_CHANNEL_15
02386   *         @arg @ref LL_ADC_CHANNEL_16
02387   *         @arg @ref LL_ADC_CHANNEL_17
02388   *         @arg @ref LL_ADC_CHANNEL_18
02389   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
02390   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
02391   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
02392   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
02393   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
02394   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
02395   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
02396   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.
02397   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.
02398   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.
02399   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
02400   *         (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
02401   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
02402   *         (1, 2, 3, 4) For ADC channel read back from ADC register,
02403   *                      comparison with internal channel parameter to be done
02404   *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
02405   */
02406 __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
02407 {
02408   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
02409   
02410   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
02411 }
02412 
02413 /**
02414   * @brief  Get ADC instance selected offset number 1, 2, 3 or 4:
02415   *          * Offset level (offset to be subtracted from the raw
02416   *            converted data).
02417   *          Caution: Offset format is dependent to ADC resolution:
02418   *          offset has to be left-aligned on bit 11, the LSB (right bits)
02419   *          are set to 0.
02420   * @rmtoll OFR1     OFFSET1        LL_ADC_GetOffsetLevel\n
02421   *         OFR2     OFFSET2        LL_ADC_GetOffsetLevel\n
02422   *         OFR3     OFFSET3        LL_ADC_GetOffsetLevel\n
02423   *         OFR4     OFFSET4        LL_ADC_GetOffsetLevel
02424   * @param  ADCx ADC instance
02425   * @param  Offsety This parameter can be one of the following values:
02426   *         @arg @ref LL_ADC_OFFSET_1
02427   *         @arg @ref LL_ADC_OFFSET_2
02428   *         @arg @ref LL_ADC_OFFSET_3
02429   *         @arg @ref LL_ADC_OFFSET_4
02430   * @retval 0x000...0xFFF
02431   */
02432 __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
02433 {
02434   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
02435   
02436   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
02437 }
02438 
02439 /**
02440   * @brief  Set ADC instance selected offset number 1, 2, 3 or 4:
02441   *          * Force offset disable (or enable) without modifying offset channel
02442   *            or value.
02443   * @note   This function should be needed only in case of offset to be
02444   *         enabled-disabled dynamically, and should not be needed in other cases:
02445   *         function LL_ADC_SetOffset() automatically enables the offset.
02446   * @note   On this STM32 family, setting of this feature is conditioned to
02447   *         ADC state:
02448   *         ADC must be disabled or enabled without conversion on going
02449   *         on either groups regular or injected.
02450   * @rmtoll OFR1     OFFSET1_EN     LL_ADC_SetOffsetState\n
02451   *         OFR2     OFFSET2_EN     LL_ADC_SetOffsetState\n
02452   *         OFR3     OFFSET3_EN     LL_ADC_SetOffsetState\n
02453   *         OFR4     OFFSET4_EN     LL_ADC_SetOffsetState
02454   * @param  ADCx ADC instance
02455   * @param  Offsety This parameter can be one of the following values:
02456   *         @arg @ref LL_ADC_OFFSET_1
02457   *         @arg @ref LL_ADC_OFFSET_2
02458   *         @arg @ref LL_ADC_OFFSET_3
02459   *         @arg @ref LL_ADC_OFFSET_4
02460   * @param  OffsetState This parameter can be one of the following values:
02461   *         @arg @ref LL_ADC_OFFSET_DISABLE
02462   *         @arg @ref LL_ADC_OFFSET_ENABLE
02463   * @retval None
02464   */
02465 __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
02466 {
02467   register uint32_t *preg = (uint32_t *)((uint32_t)
02468                             ((uint32_t)(&ADCx->OFR1) + (Offsety*4)));
02469   
02470   MODIFY_REG(*preg,
02471              ADC_OFR1_OFFSET1_EN,
02472              OffsetState);
02473 }
02474 
02475 /**
02476   * @brief  Get ADC instance selected offset number 1, 2, 3 or 4:
02477   *          * Get offset state disabled or enabled.
02478   * @rmtoll OFR1     OFFSET1_EN     LL_ADC_GetOffsetState\n
02479   *         OFR2     OFFSET2_EN     LL_ADC_GetOffsetState\n
02480   *         OFR3     OFFSET3_EN     LL_ADC_GetOffsetState\n
02481   *         OFR4     OFFSET4_EN     LL_ADC_GetOffsetState
02482   * @param  ADCx ADC instance
02483   * @param  Offsety This parameter can be one of the following values:
02484   *         @arg @ref LL_ADC_OFFSET_1
02485   *         @arg @ref LL_ADC_OFFSET_2
02486   *         @arg @ref LL_ADC_OFFSET_3
02487   *         @arg @ref LL_ADC_OFFSET_4
02488   * @retval Returned value can be one of the following values:
02489   *         @arg @ref LL_ADC_OFFSET_DISABLE
02490   *         @arg @ref LL_ADC_OFFSET_ENABLE
02491   */
02492 __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)
02493 {
02494   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
02495   
02496   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
02497 }
02498 
02499 /**
02500   * @}
02501   */
02502 
02503 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
02504   * @{
02505   */
02506 
02507 /**
02508   * @brief  Set ADC group regular conversion trigger source:
02509   *         internal (SW start) or external from timer or external interrupt.
02510   * @note   Setting trigger source to external trigger also set trigger polarity
02511   *         to rising edge 
02512   *         (default setting for compatibility with some ADC on other
02513   *         STM32 families having this setting set by HW default value).
02514   *         In case of need to modify trigger edge, use
02515   *         function @ref LL_ADC_REG_SetTrigEdge().
02516   * @note   On this STM32 family, setting of this feature is conditioned to
02517   *         ADC state:
02518   *         ADC must be disabled or enabled without conversion on going
02519   *         on group regular.
02520   * @rmtoll CFGR     EXTSEL         LL_ADC_REG_SetTrigSource\n
02521   *         CFGR     EXTEN          LL_ADC_REG_SetTrigSource
02522   * @param  ADCx ADC instance
02523   * @param  TriggerSource This parameter can be one of the following values:
02524   *         @arg @ref LL_ADC_REG_TRIG_SW_START
02525   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
02526   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
02527   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CC1
02528   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CC2
02529   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CC3
02530   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
02531   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CC2
02532   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
02533   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CC4
02534   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
02535   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CC4
02536   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
02537   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
02538   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
02539   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
02540   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
02541   * @retval None
02542   */
02543 __STATIC_INLINE void LL_ADC_REG_SetTrigSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
02544 {
02545   MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
02546 }
02547 
02548 /**
02549   * @brief  Get ADC group regular conversion trigger source:
02550   *         internal (SW start) or external from timer or external interrupt.
02551   * @note   To determine whether group regular trigger source is
02552   *         internal (SW start) or external, without detail
02553   *         of which peripheral is selected as external trigger,
02554   *         (equivalent to 
02555   *         " if(LL_ADC_REG_GetTrigSource(ADC1) == LL_ADC_REG_TRIG_SW_START) ")
02556   *         use function @ref LL_ADC_REG_IsTrigSourceSWStart.
02557   * @rmtoll CFGR     EXTSEL         LL_ADC_REG_GetTrigSource\n
02558   *         CFGR     EXTEN          LL_ADC_REG_GetTrigSource
02559   * @param  ADCx ADC instance
02560   * @retval Returned value can be one of the following values:
02561   *         @arg @ref LL_ADC_REG_TRIG_SW_START
02562   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
02563   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
02564   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CC1
02565   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CC2
02566   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CC3
02567   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
02568   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CC2
02569   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
02570   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CC4
02571   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
02572   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CC4
02573   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
02574   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
02575   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
02576   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
02577   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
02578   */
02579 __STATIC_INLINE uint32_t LL_ADC_REG_GetTrigSource(ADC_TypeDef *ADCx)
02580 {
02581   register uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
02582   
02583   /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
02584   /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}.                            */
02585   register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2));
02586   
02587   /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL         */
02588   /* to match with triggers literals definition.                              */
02589   return ((TriggerSource
02590            & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)
02591           | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)
02592          );
02593 }
02594 
02595 /**
02596   * @brief  Get ADC group regular conversion trigger source:
02597   *         (0: trigger source external trigger, 1: trigger source SW start).
02598   * @note   In case of group regular trigger source set to external trigger,
02599   *         to determine which peripheral is selected as external trigger,
02600   *         use function @ref LL_ADC_REG_GetTrigSource().
02601   * @rmtoll CFGR     EXTEN          LL_ADC_REG_IsTrigSourceSWStart
02602   * @param  ADCx ADC instance
02603   * @retval State of bit (1 or 0).
02604   */
02605 __STATIC_INLINE uint32_t LL_ADC_REG_IsTrigSourceSWStart(ADC_TypeDef *ADCx)
02606 {
02607   return (READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SW_START & ADC_CFGR_EXTEN));
02608 }
02609 
02610 /**
02611   * @brief  Set ADC group regular conversion trigger polarity.
02612   *         Applicable only for trigger source set to external trigger.
02613   * @note   On this STM32 family, setting of this feature is conditioned to
02614   *         ADC state:
02615   *         ADC must be disabled or enabled without conversion on going
02616   *         on group regular.
02617   * @rmtoll CFGR     EXTEN          LL_ADC_REG_SetTrigEdge
02618   * @param  ADCx ADC instance
02619   * @param  ExternalTriggerEdge This parameter can be one of the following values:
02620   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
02621   *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
02622   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
02623   * @retval None
02624   */
02625 __STATIC_INLINE void LL_ADC_REG_SetTrigEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
02626 {
02627   MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
02628 }
02629 
02630 /**
02631   * @brief  Get ADC group regular conversion trigger polarity.
02632   *         Applicable only for trigger source set to external trigger.
02633   * @rmtoll CFGR     EXTEN          LL_ADC_REG_GetTrigEdge
02634   * @param  ADCx ADC instance
02635   * @retval Returned value can be one of the following values:
02636   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
02637   *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
02638   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
02639   */
02640 __STATIC_INLINE uint32_t LL_ADC_REG_GetTrigEdge(ADC_TypeDef *ADCx)
02641 {
02642   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
02643 }
02644 
02645 /**
02646   * @brief  Set ADC continuous conversion mode on ADC group regular:
02647   *         whether ADC conversions are performed:
02648   *          * single mode: one conversion per trigger
02649   *          * continuous mode: after the first trigger, following
02650   *            conversions launched successively automatically.
02651   * @note   It is not possible to enable both ADC continuous mode
02652   *         and ADC group regular discontinuous mode.
02653   * @note   On this STM32 family, setting of this feature is conditioned to
02654   *         ADC state:
02655   *         ADC must be disabled or enabled without conversion on going
02656   *         on group regular.
02657   * @rmtoll CFGR     CONT           LL_ADC_REG_SetContinuousMode
02658   * @param  ADCx ADC instance
02659   * @param  Continuous This parameter can be one of the following values:
02660   *         @arg @ref LL_ADC_REG_CONV_SINGLE
02661   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
02662   * @retval None
02663   */
02664 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
02665 {
02666   MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
02667 }
02668 
02669 /**
02670   * @brief  Get ADC continuous conversion mode on ADC group regular:
02671   *         whether ADC conversions are performed:
02672   *          * single mode: one conversion per trigger
02673   *          * continuous mode: after the first trigger, following
02674   *            conversions launched successively automatically.
02675   * @rmtoll CFGR     CONT           LL_ADC_REG_GetContinuousMode
02676   * @param  ADCx ADC instance
02677   * @retval Returned value can be one of the following values:
02678   *         @arg @ref LL_ADC_REG_CONV_SINGLE
02679   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
02680   */
02681 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
02682 {
02683   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
02684 }
02685 
02686 /**
02687   * @brief  Set ADC group regular conversion data transfer: no transfer or transfer by DMA.
02688   *         If transfer by DMA selected, specifies the DMA requests
02689   *         mode:
02690   *          * Limited mode (One shot mode): DMA transfer requests are stopped
02691   *            when number of DMA data transfers (number of
02692   *            ADC conversions) is reached.
02693   *            This ADC mode is intended to be used with DMA mode non-circular.
02694   *          * Unlimited mode: DMA transfer requests are unlimited,
02695   *            whatever number of DMA data transfers (number of
02696   *            ADC conversions).
02697   *            This ADC mode is intended to be used with DMA mode circular.
02698   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
02699   *         mode non-circular:
02700   *         when DMA transfers size will be reached, DMA will stop transfers of
02701   *         ADC conversions data ADC will raise an overrun error
02702   *        (overrun flag and interruption if enabled).
02703   * @note   For devices with several ADC instances: ADC multimode DMA
02704   *         settings are available using function @ref LL_ADC_SetMultiDMATransfer().
02705   * @note   To configure DMA source address (peripheral address),
02706   *         use function @ref LL_ADC_DMA_GetRegAddr().
02707   * @note   On this STM32 family, setting of this feature is conditioned to
02708   *         ADC state:
02709   *         ADC must be disabled or enabled without conversion on going
02710   *         on either groups regular or injected.
02711   * @rmtoll CFGR     DMAEN          LL_ADC_REG_SetDMATransfer\n
02712   *         CFGR     DMACFG         LL_ADC_REG_SetDMATransfer
02713   * @param  ADCx ADC instance
02714   * @param  DMATransfer This parameter can be one of the following values:
02715   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
02716   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
02717   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
02718   * @retval None
02719   */
02720 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
02721 {
02722   MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
02723 }
02724 
02725 /**
02726   * @brief  Get ADC group regular conversion data transfer: no transfer or transfer by DMA.
02727   *         If transfer by DMA selected, specifies the DMA requests
02728   *         mode:
02729   *          * Limited mode (One shot mode): DMA transfer requests are stopped
02730   *            when number of DMA data transfers (number of
02731   *            ADC conversions) is reached.
02732   *            This ADC mode is intended to be used with DMA mode non-circular.
02733   *          * Unlimited mode: DMA transfer requests are unlimited,
02734   *            whatever number of DMA data transfers (number of
02735   *            ADC conversions).
02736   *            This ADC mode is intended to be used with DMA mode circular.
02737   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
02738   *         mode non-circular:
02739   *         when DMA transfers size will be reached, DMA will stop transfers of
02740   *         ADC conversions data ADC will raise an overrun error
02741   *         (overrun flag and interruption if enabled).
02742   * @note   For devices with several ADC instances: ADC multimode DMA
02743   *         settings are available using function @ref LL_ADC_GetMultiDMATransfer().
02744   * @note   To configure DMA source address (peripheral address),
02745   *         use function @ref LL_ADC_DMA_GetRegAddr().
02746   * @rmtoll CFGR     DMAEN          LL_ADC_REG_GetDMATransfer\n
02747   *         CFGR     DMACFG         LL_ADC_REG_GetDMATransfer
02748   * @param  ADCx ADC instance
02749   * @retval Returned value can be one of the following values:
02750   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
02751   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
02752   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
02753   */
02754 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
02755 {
02756   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
02757 }
02758 
02759 /**
02760   * @brief  Set ADC group regular behaviour in case of overrun:
02761   *         data preserved or overwritten.
02762   * @note   Compatibility with devices without feature overrun:
02763   *         other devices without this feature have a behaviour
02764   *         equivalent to data overwritten.
02765   *         The default setting of overrun is data preserved.
02766   *         Therefore, for compatibility with all devices, parameter
02767   *         overrun should be set to data overwritten.
02768   * @note   On this STM32 family, setting of this feature is conditioned to
02769   *         ADC state:
02770   *         ADC must be disabled or enabled without conversion on going
02771   *         on group regular.
02772   * @rmtoll CFGR     OVRMOD         LL_ADC_REG_SetOverrun
02773   * @param  ADCx ADC instance
02774   * @param  Overrun This parameter can be one of the following values:
02775   *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
02776   *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
02777   * @retval None
02778   */
02779 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
02780 {
02781   MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
02782 }
02783 
02784 /**
02785   * @brief  Get ADC group regular behaviour in case of overrun:
02786   *         data preserved or overwritten.
02787   * @rmtoll CFGR     OVRMOD         LL_ADC_REG_GetOverrun
02788   * @param  ADCx ADC instance
02789   * @retval Returned value can be one of the following values:
02790   *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
02791   *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
02792   */
02793 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
02794 {
02795   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
02796 }
02797 
02798 /**
02799   * @brief  Set ADC group regular sequencer length and scan direction.
02800   *          * For devices with sequencer fully configurable
02801   *            (function "LL_ADC_REG_SetSequencerRanks()" available):
02802   *            sequencer length and each rank affectation to a channel 
02803   *            are configurable.
02804   *            This function performs:
02805   *            - Sequence length: Set number of ranks in the scan sequence.
02806   *            - Sequence direction: Unless specified in parameters, sequencer
02807   *              scan direction is forward (from rank 1 to rank n).
02808   *            Sequencer ranks are selected using
02809   *            function "LL_ADC_REG_SetSequencerRanks()".
02810   *          * For devices with sequencer not fully configurable
02811   *            (function "LL_ADC_REG_SetSequencerChannels()" available):
02812   *            sequencer length and each rank affectation to a channel 
02813   *            are defined by channel number.
02814   *            This function performs:
02815   *            - Sequence length: Number of ranks in the scan sequence is
02816   *              defined by number of channels set in the sequence,
02817   *              rank of each channel is fixed by channel HW number.
02818   *              (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
02819   *            - Sequence direction: Unless specified in parameters, sequencer
02820   *              scan direction is forward (from lowest channel number to
02821   *              highest channel number).
02822   *            Sequencer ranks are selected using
02823   *            function "LL_ADC_REG_SetSequencerChannels()".
02824   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
02825   *         ADC conversion on only 1 channel.
02826   * @note   On this STM32 family, setting of this feature is conditioned to
02827   *         ADC state:
02828   *         ADC must be disabled or enabled without conversion on going
02829   *         on group regular.
02830   * @rmtoll SQR1     L              LL_ADC_REG_SetSequencerLength
02831   * @param  ADCx ADC instance
02832   * @param  SequencerNbRanks This parameter can be one of the following values:
02833   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
02834   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
02835   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
02836   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
02837   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
02838   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
02839   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
02840   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
02841   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
02842   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
02843   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
02844   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
02845   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
02846   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
02847   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
02848   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
02849   * @retval None
02850   */
02851 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
02852 {
02853   MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
02854 }
02855 
02856 /**
02857   * @brief  Get ADC group regular sequencer length and scan direction.
02858   *          * For devices with sequencer fully configurable
02859   *            (function "LL_ADC_REG_SetSequencerRanks()" available):
02860   *            sequencer length and each rank affectation to a channel 
02861   *            are configurable.
02862   *            This function performs:
02863   *            - Sequence length: Set number of ranks in the scan sequence.
02864   *            - Sequence direction: Unless specified in parameters, sequencer
02865   *              scan direction is forward (from rank 1 to rank n).
02866   *            Sequencer ranks are selected using
02867   *            function "LL_ADC_REG_SetSequencerRanks()".
02868   *          * For devices with sequencer not fully configurable
02869   *            (function "LL_ADC_REG_SetSequencerChannels()" available):
02870   *            sequencer length and each rank affectation to a channel 
02871   *            are defined by channel number.
02872   *            This function performs:
02873   *            - Sequence length: Number of ranks in the scan sequence is
02874   *              defined by number of channels set in the sequence,
02875   *              rank of each channel is fixed by channel HW number.
02876   *              (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
02877   *            - Sequence direction: Unless specified in parameters, sequencer
02878   *              scan direction is forward (from lowest channel number to
02879   *              highest channel number).
02880   *            Sequencer ranks are selected using
02881   *            function "LL_ADC_REG_SetSequencerChannels()".
02882   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
02883   *         ADC conversion on only 1 channel.
02884   * @rmtoll SQR1     L              LL_ADC_REG_GetSequencerLength
02885   * @param  ADCx ADC instance
02886   * @retval Returned value can be one of the following values:
02887   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
02888   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
02889   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
02890   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
02891   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
02892   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
02893   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
02894   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
02895   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
02896   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
02897   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
02898   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
02899   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
02900   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
02901   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
02902   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
02903   */
02904 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
02905 {
02906   return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
02907 }
02908 
02909 /**
02910   * @brief  Set ADC group regular sequencer discontinuous mode:
02911   *         sequence subdivided and scan conversions interrupted every selected
02912   *         number of ranks.
02913   * @note   It is not possible to enable both ADC continuous mode
02914   *         and ADC group regular discontinuous mode.
02915   * @note   It is not possible to enable both ADC auto-injected mode
02916   *         and ADC group regular discontinuous mode.
02917   * @note   On this STM32 family, setting of this feature is conditioned to
02918   *         ADC state:
02919   *         ADC must be disabled or enabled without conversion on going
02920   *         on group regular.
02921   * @rmtoll CFGR     DISCEN         LL_ADC_REG_SetSequencerDiscont\n
02922   *         CFGR     DISCNUM        LL_ADC_REG_SetSequencerDiscont
02923   * @param  ADCx ADC instance
02924   * @param  SeqDiscont This parameter can be one of the following values:
02925   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
02926   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
02927   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
02928   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
02929   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
02930   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
02931   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
02932   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
02933   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
02934   * @retval None
02935   */
02936 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
02937 {
02938   MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
02939 }
02940 
02941 /**
02942   * @brief  Get ADC group regular sequencer discontinuous mode:
02943   *         sequence subdivided and scan conversions interrupted every selected
02944   *         number of ranks.
02945   * @rmtoll CFGR     DISCEN         LL_ADC_REG_GetSequencerDiscont\n
02946   *         CFGR     DISCNUM        LL_ADC_REG_GetSequencerDiscont
02947   * @param  ADCx ADC instance
02948   * @retval Returned value can be one of the following values:
02949   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
02950   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
02951   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
02952   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
02953   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
02954   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
02955   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
02956   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
02957   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
02958   */
02959 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
02960 {
02961   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
02962 }
02963 
02964 /**
02965   * @brief  Set ADC group regular sequence: channel on the selected
02966   *         scan sequence rank.
02967   *         This function performs:
02968   *          - Channels ordering into each rank of scan sequence:
02969   *            whatever channel can be placed into whatever rank.
02970   * @note   On this STM32 family, ADC group regular sequencer is
02971   *         fully configurable: sequencer length and each rank
02972   *         affectation to a channel are configurable.
02973   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
02974   * @note   Depending on devices and packages, some channels may not be available.
02975   *         Refer to device datasheet for channels availability.
02976   * @note   On this STM32 family, to measure internal channels (VrefInt,
02977   *         TempSensor, ...), measurement paths to internal channels must be
02978   *         enabled separately.
02979   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
02980   * @note   On this STM32 family, setting of this feature is conditioned to
02981   *         ADC state:
02982   *         ADC must be disabled or enabled without conversion on going
02983   *         on group regular.
02984   * @rmtoll SQR1     SQ1            LL_ADC_REG_SetSequencerRanks\n
02985   *         SQR1     SQ2            LL_ADC_REG_SetSequencerRanks\n
02986   *         SQR1     SQ3            LL_ADC_REG_SetSequencerRanks\n
02987   *         SQR1     SQ4            LL_ADC_REG_SetSequencerRanks\n
02988   *         SQR2     SQ5            LL_ADC_REG_SetSequencerRanks\n
02989   *         SQR2     SQ6            LL_ADC_REG_SetSequencerRanks\n
02990   *         SQR2     SQ7            LL_ADC_REG_SetSequencerRanks\n
02991   *         SQR2     SQ8            LL_ADC_REG_SetSequencerRanks\n
02992   *         SQR2     SQ9            LL_ADC_REG_SetSequencerRanks\n
02993   *         SQR3     SQ10           LL_ADC_REG_SetSequencerRanks\n
02994   *         SQR3     SQ11           LL_ADC_REG_SetSequencerRanks\n
02995   *         SQR3     SQ12           LL_ADC_REG_SetSequencerRanks\n
02996   *         SQR3     SQ13           LL_ADC_REG_SetSequencerRanks\n
02997   *         SQR3     SQ14           LL_ADC_REG_SetSequencerRanks\n
02998   *         SQR4     SQ15           LL_ADC_REG_SetSequencerRanks\n
02999   *         SQR4     SQ16           LL_ADC_REG_SetSequencerRanks
03000   * @param  ADCx ADC instance
03001   * @param  Rank This parameter can be one of the following values:
03002   *         @arg @ref LL_ADC_REG_RANK_1
03003   *         @arg @ref LL_ADC_REG_RANK_2
03004   *         @arg @ref LL_ADC_REG_RANK_3
03005   *         @arg @ref LL_ADC_REG_RANK_4
03006   *         @arg @ref LL_ADC_REG_RANK_5
03007   *         @arg @ref LL_ADC_REG_RANK_6
03008   *         @arg @ref LL_ADC_REG_RANK_7
03009   *         @arg @ref LL_ADC_REG_RANK_8
03010   *         @arg @ref LL_ADC_REG_RANK_9
03011   *         @arg @ref LL_ADC_REG_RANK_10
03012   *         @arg @ref LL_ADC_REG_RANK_11
03013   *         @arg @ref LL_ADC_REG_RANK_12
03014   *         @arg @ref LL_ADC_REG_RANK_13
03015   *         @arg @ref LL_ADC_REG_RANK_14
03016   *         @arg @ref LL_ADC_REG_RANK_15
03017   *         @arg @ref LL_ADC_REG_RANK_16
03018   * @param  Channel This parameter can be one of the following values:
03019   *         @arg @ref LL_ADC_CHANNEL_0
03020   *         @arg @ref LL_ADC_CHANNEL_1           (5)
03021   *         @arg @ref LL_ADC_CHANNEL_2           (5)
03022   *         @arg @ref LL_ADC_CHANNEL_3           (5)
03023   *         @arg @ref LL_ADC_CHANNEL_4           (5)
03024   *         @arg @ref LL_ADC_CHANNEL_5           (5)
03025   *         @arg @ref LL_ADC_CHANNEL_6
03026   *         @arg @ref LL_ADC_CHANNEL_7
03027   *         @arg @ref LL_ADC_CHANNEL_8
03028   *         @arg @ref LL_ADC_CHANNEL_9
03029   *         @arg @ref LL_ADC_CHANNEL_10
03030   *         @arg @ref LL_ADC_CHANNEL_11
03031   *         @arg @ref LL_ADC_CHANNEL_12
03032   *         @arg @ref LL_ADC_CHANNEL_13
03033   *         @arg @ref LL_ADC_CHANNEL_14
03034   *         @arg @ref LL_ADC_CHANNEL_15
03035   *         @arg @ref LL_ADC_CHANNEL_16
03036   *         @arg @ref LL_ADC_CHANNEL_17
03037   *         @arg @ref LL_ADC_CHANNEL_18
03038   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
03039   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
03040   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
03041   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
03042   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
03043   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
03044   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
03045   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.
03046   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.
03047   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.
03048   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
03049   *         (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
03050   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
03051   * @retval None
03052   */
03053 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
03054 {
03055   /* Set bits with content of parameter "Channel" with bits position          */
03056   /* in register and register position depending on parameter "Rank".         */
03057   /* Parameters "Rank" and "Channel" are used with masks because containing   */
03058   /* other bits reserved for other purpose.                                   */
03059   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
03060   
03061   MODIFY_REG(*preg,
03062              ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
03063              (Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) - (Rank & ADC_REG_RANK_ID_SQRX_MASK)));
03064 }
03065 
03066 /**
03067   * @brief  Get ADC group regular sequence: channel on the selected
03068   *         scan sequence rank.
03069   * @note   On this STM32 family, ADC group regular sequencer is
03070   *         fully configurable: sequencer length and each rank
03071   *         affectation to a channel are configurable.
03072   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
03073   * @note   Depending on devices and packages, some channels may not be available.
03074   *         Refer to device datasheet for channels availability.
03075   * @note   Usage of the returned channel number:
03076   *          - To reinject this channel into another function LL_ADC_xxx:
03077   *            the returned channel number is only partly formatted on definition
03078   *            of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
03079   *            with literals LL_ADC_CHANNEL_x, then the selected
03080   *            literal LL_ADC_CHANNEL_x can be used as parameter for another
03081   *            function.
03082   *          - To get the channel number in decimal format:
03083   *            process the returned value with the helper macro
03084   *            @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
03085   * @rmtoll SQR1     SQ1            LL_ADC_REG_GetSequencerRanks\n
03086   *         SQR1     SQ2            LL_ADC_REG_GetSequencerRanks\n
03087   *         SQR1     SQ3            LL_ADC_REG_GetSequencerRanks\n
03088   *         SQR1     SQ4            LL_ADC_REG_GetSequencerRanks\n
03089   *         SQR2     SQ5            LL_ADC_REG_GetSequencerRanks\n
03090   *         SQR2     SQ6            LL_ADC_REG_GetSequencerRanks\n
03091   *         SQR2     SQ7            LL_ADC_REG_GetSequencerRanks\n
03092   *         SQR2     SQ8            LL_ADC_REG_GetSequencerRanks\n
03093   *         SQR2     SQ9            LL_ADC_REG_GetSequencerRanks\n
03094   *         SQR3     SQ10           LL_ADC_REG_GetSequencerRanks\n
03095   *         SQR3     SQ11           LL_ADC_REG_GetSequencerRanks\n
03096   *         SQR3     SQ12           LL_ADC_REG_GetSequencerRanks\n
03097   *         SQR3     SQ13           LL_ADC_REG_GetSequencerRanks\n
03098   *         SQR3     SQ14           LL_ADC_REG_GetSequencerRanks\n
03099   *         SQR4     SQ15           LL_ADC_REG_GetSequencerRanks\n
03100   *         SQR4     SQ16           LL_ADC_REG_GetSequencerRanks
03101   * @param  ADCx ADC instance
03102   * @param  Rank This parameter can be one of the following values:
03103   *         @arg @ref LL_ADC_REG_RANK_1
03104   *         @arg @ref LL_ADC_REG_RANK_2
03105   *         @arg @ref LL_ADC_REG_RANK_3
03106   *         @arg @ref LL_ADC_REG_RANK_4
03107   *         @arg @ref LL_ADC_REG_RANK_5
03108   *         @arg @ref LL_ADC_REG_RANK_6
03109   *         @arg @ref LL_ADC_REG_RANK_7
03110   *         @arg @ref LL_ADC_REG_RANK_8
03111   *         @arg @ref LL_ADC_REG_RANK_9
03112   *         @arg @ref LL_ADC_REG_RANK_10
03113   *         @arg @ref LL_ADC_REG_RANK_11
03114   *         @arg @ref LL_ADC_REG_RANK_12
03115   *         @arg @ref LL_ADC_REG_RANK_13
03116   *         @arg @ref LL_ADC_REG_RANK_14
03117   *         @arg @ref LL_ADC_REG_RANK_15
03118   *         @arg @ref LL_ADC_REG_RANK_16
03119   * @retval Returned value can be one of the following values:
03120   *         @arg @ref LL_ADC_CHANNEL_0
03121   *         @arg @ref LL_ADC_CHANNEL_1           (5)
03122   *         @arg @ref LL_ADC_CHANNEL_2           (5)
03123   *         @arg @ref LL_ADC_CHANNEL_3           (5)
03124   *         @arg @ref LL_ADC_CHANNEL_4           (5)
03125   *         @arg @ref LL_ADC_CHANNEL_5           (5)
03126   *         @arg @ref LL_ADC_CHANNEL_6
03127   *         @arg @ref LL_ADC_CHANNEL_7
03128   *         @arg @ref LL_ADC_CHANNEL_8
03129   *         @arg @ref LL_ADC_CHANNEL_9
03130   *         @arg @ref LL_ADC_CHANNEL_10
03131   *         @arg @ref LL_ADC_CHANNEL_11
03132   *         @arg @ref LL_ADC_CHANNEL_12
03133   *         @arg @ref LL_ADC_CHANNEL_13
03134   *         @arg @ref LL_ADC_CHANNEL_14
03135   *         @arg @ref LL_ADC_CHANNEL_15
03136   *         @arg @ref LL_ADC_CHANNEL_16
03137   *         @arg @ref LL_ADC_CHANNEL_17
03138   *         @arg @ref LL_ADC_CHANNEL_18
03139   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
03140   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
03141   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
03142   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
03143   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
03144   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
03145   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
03146   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.
03147   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.
03148   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.
03149   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
03150   *         (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
03151   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
03152   *         (1, 2, 3, 4) For ADC channel read back from ADC register,
03153   *                      comparison with internal channel parameter to be done
03154   *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
03155   */
03156 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
03157 {
03158   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
03159   
03160   return (uint32_t) (READ_BIT(*preg,
03161                               ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
03162                      << (POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) - (Rank & ADC_REG_RANK_ID_SQRX_MASK))
03163                     );
03164 }
03165 
03166 /**
03167   * @}
03168   */
03169 
03170 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
03171   * @{
03172   */
03173 
03174 /**
03175   * @brief  Set ADC group injected conversion trigger source:
03176   *         internal (SW start) or external from timer or external interrupt.
03177   * @note   Setting trigger source to external trigger also set trigger polarity
03178   *         to rising edge 
03179   *         (default setting for compatibility with some ADC on other
03180   *         STM32 families having this setting set by HW default value).
03181   *         In case of need to modify trigger edge, use
03182   *         function @ref LL_ADC_INJ_SetTrigEdge().
03183   * @note   On this STM32 family, setting of this feature is conditioned to
03184   *         ADC state:
03185   *         ADC must not be disabled. Can be enabled with or without conversion
03186   *         on going on either groups regular or injected.
03187   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_SetTrigSource\n
03188   *         JSQR     JEXTEN         LL_ADC_INJ_SetTrigSource
03189   * @param  ADCx ADC instance
03190   * @param  TriggerSource This parameter can be one of the following values:
03191   *         @arg @ref LL_ADC_INJ_TRIG_SW_START
03192   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
03193   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
03194   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CC4
03195   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
03196   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CC1
03197   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
03198   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CC1
03199   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CC3
03200   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CC4
03201   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
03202   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
03203   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CC4
03204   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
03205   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
03206   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
03207   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
03208   * @retval None
03209   */
03210 __STATIC_INLINE void LL_ADC_INJ_SetTrigSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
03211 {
03212   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
03213 }
03214 
03215 /**
03216   * @brief  Get ADC group injected conversion trigger source:
03217   *         internal (SW start) or external from timer or external interrupt.
03218   * @note   To determine whether group injected trigger source is
03219   *         internal (SW start) or external, without detail
03220   *         of which peripheral is selected as external trigger,
03221   *         (equivalent to 
03222   *         " if(LL_ADC_INJ_GetTrigSource(ADC1) == LL_ADC_INJ_TRIG_SW_START) ")
03223   *         use function @ref LL_ADC_INJ_IsTrigSourceSWStart.
03224   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_GetTrigSource\n
03225   *         JSQR     JEXTEN         LL_ADC_INJ_GetTrigSource
03226   * @param  ADCx ADC instance
03227   * @retval Returned value can be one of the following values:
03228   *         @arg @ref LL_ADC_INJ_TRIG_SW_START
03229   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
03230   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
03231   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CC4
03232   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
03233   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CC1
03234   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
03235   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CC1
03236   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CC3
03237   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CC4
03238   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
03239   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
03240   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CC4
03241   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
03242   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
03243   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
03244   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
03245   */
03246 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigSource(ADC_TypeDef *ADCx)
03247 {
03248   register uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
03249   
03250   /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
03251   /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}.                           */
03252   register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2));
03253   
03254   /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL       */
03255   /* to match with triggers literals definition.                              */
03256   return ((TriggerSource
03257            & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)
03258           | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)
03259          );
03260 }
03261 
03262 /**
03263   * @brief  Get ADC group injected conversion trigger source:
03264   *         (0: trigger source external trigger, 1: trigger source SW start).
03265   * @note   In case of group injected trigger source set to external trigger,
03266   *         to determine which peripheral is selected as external trigger,
03267   *         use function @ref LL_ADC_INJ_GetTrigSource.
03268   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_IsTrigSourceSWStart
03269   * @param  ADCx ADC instance
03270   * @retval State of bit (1 or 0).
03271   */
03272 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTrigSourceSWStart(ADC_TypeDef *ADCx)
03273 {
03274   return (READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SW_START & ADC_JSQR_JEXTEN));
03275 }
03276 
03277 /**
03278   * @brief  Set ADC group injected conversion trigger polarity.
03279   *         Applicable only for trigger source set to external trigger.
03280   * @note   On this STM32 family, setting of this feature is conditioned to
03281   *         ADC state:
03282   *         ADC must not be disabled. Can be enabled with or without conversion
03283   *         on going on either groups regular or injected.
03284   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_SetTrigEdge
03285   * @param  ADCx ADC instance
03286   * @param  ExternalTriggerEdge This parameter can be one of the following values:
03287   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
03288   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
03289   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
03290   * @retval None
03291   */
03292 __STATIC_INLINE void LL_ADC_INJ_SetTrigEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
03293 {
03294   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
03295 }
03296 
03297 /**
03298   * @brief  Get ADC group injected conversion trigger polarity.
03299   *         Applicable only for trigger source set to external trigger.
03300   * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_GetTrigEdge
03301   * @param  ADCx ADC instance
03302   * @retval Returned value can be one of the following values:
03303   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
03304   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
03305   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
03306   */
03307 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigEdge(ADC_TypeDef *ADCx)
03308 {
03309   return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
03310 }
03311 
03312 /**
03313   * @brief  Set ADC group injected conversion trigger:
03314   *         independent or from ADC group regular.
03315   * @note   It is not possible to enable both ADC auto-injected mode
03316   *         and ADC group injected discontinuous mode.
03317   * @note   On this STM32 family, setting of this feature is conditioned to
03318   *         ADC state:
03319   *         ADC must be disabled or enabled without conversion on going
03320   *         on either groups regular or injected.
03321   * @rmtoll CFGR     JAUTO          LL_ADC_INJ_SetTrigAuto
03322   * @param  ADCx ADC instance
03323   * @param  InjTrigAuto This parameter can be one of the following values:
03324   *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
03325   *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
03326   * @retval None
03327   */
03328 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t InjTrigAuto)
03329 {
03330   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, InjTrigAuto);
03331 }
03332 
03333 /**
03334   * @brief  Get ADC group injected conversion trigger:
03335   *         independent or from ADC group regular.
03336   * @rmtoll CFGR     JAUTO          LL_ADC_INJ_GetTrigAuto
03337   * @param  ADCx ADC instance
03338   * @retval Returned value can be one of the following values:
03339   *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
03340   *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
03341   */
03342 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
03343 {
03344   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
03345 }
03346 
03347 /**
03348   * @brief  Set ADC group injected contexts queue mode.
03349   *         A context is a setting of injected group sequencer:
03350   *          * injected group trigger
03351   *          * sequencer length
03352   *          * sequencer ranks
03353   *         If contexts queue is disabled:
03354   *          * only 1 sequence can be configured
03355   *            and is active perpetually.
03356   *         If contexts queue is enabled:
03357   *          * up to 2 contexts can be queued
03358   *            and are checked in and out as a FIFO stack (first-in, first-out).
03359   *          * If a new context is set when queues is full, error is triggered
03360   *            by interruption "Injected Queue Overflow".
03361   *          * Two behaviours are possible when all contexts have been processed:
03362   *            the contexts queue can maintain the last context active perpetually
03363   *            or can be empty and injected group triggers are disabled.
03364   *          * Triggers can be only external (not internal SW start)
03365   *          * Caution: The sequence must be fully configured in one time
03366   *            (one write of register JSQR makes a check-in of a new context
03367   *            into the queue).
03368   *            Therefore functions to set separately injected trigger and
03369   *            sequencer channels cannot be used, register JSQR must be set
03370   *            using function @ref LL_ADC_INJ_ConfigQueueContext().
03371   * @note   This parameter can be modified only when no conversion is on going
03372   *         on either groups regular or injected.
03373   * @note   A modification of the context mode (bit JQDIS) causes the contexts
03374   *         queue to be flushed and the register JSQR is cleared.
03375   * @note   On this STM32 family, setting of this feature is conditioned to
03376   *         ADC state:
03377   *         ADC must be disabled or enabled without conversion on going
03378   *         on either groups regular or injected.
03379   * @rmtoll CFGR     JQM            LL_ADC_INJ_SetQueueMode\n
03380   *         CFGR     JQDIS          LL_ADC_INJ_SetQueueMode
03381   * @param  ADCx ADC instance
03382   * @param  QueueMode This parameter can be one of the following values:
03383   *         @arg @ref LL_ADC_INJ_QUEUE_DISABLE
03384   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
03385   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
03386   * @retval None
03387   */
03388 __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
03389 {
03390   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
03391 }
03392 
03393 /**
03394   * @brief  Get ADC group injected context queue mode.
03395   * @rmtoll CFGR     JQM            LL_ADC_INJ_GetQueueMode\n
03396   *         CFGR     JQDIS          LL_ADC_INJ_GetQueueMode
03397   * @param  ADCx ADC instance
03398   * @retval Returned value can be one of the following values:
03399   *         @arg @ref LL_ADC_INJ_QUEUE_DISABLE
03400   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
03401   *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
03402   */
03403 __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
03404 {
03405   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
03406 }
03407 
03408 /**
03409   * @brief  Set ADC group injected sequencer length and scan direction.
03410   *            * Sequence length: Set number of ranks in the sequence.
03411   *            * Sequence direction: Unless specified in parameters, sequencer
03412   *              scan direction is forward (from rank 1 to rank n).
03413   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
03414   *         ADC conversion on only 1 channel.
03415   * @note   On this STM32 family, setting of this feature is conditioned to
03416   *         ADC state:
03417   *         ADC must not be disabled. Can be enabled with or without conversion
03418   *         on going on either groups regular or injected.
03419   * @rmtoll JSQR     JL             LL_ADC_INJ_SetSequencerLength
03420   * @param  ADCx ADC instance
03421   * @param  SequencerNbRanks This parameter can be one of the following values:
03422   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
03423   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
03424   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
03425   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
03426   * @retval None
03427   */
03428 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
03429 {
03430   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
03431 }
03432 
03433 /**
03434   * @brief  Get ADC group injected sequencer length and scan direction.
03435   *          * Sequence length: Set number of ranks in the sequence.
03436   *          * Sequence direction: Unless specified in parameters, sequencer
03437   *            scan direction is forward (from rank 1 to rank n).
03438   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
03439   *         ADC conversion on only 1 channel.
03440   * @rmtoll JSQR     JL             LL_ADC_INJ_GetSequencerLength
03441   * @param  ADCx ADC instance
03442   * @retval Returned value can be one of the following values:
03443   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
03444   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
03445   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
03446   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
03447   */
03448 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
03449 {
03450   return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
03451 }
03452 
03453 /**
03454   * @brief  Set ADC group injected sequencer discontinuous mode:
03455   *         sequence subdivided and scan conversions interrupted every selected
03456   *         number of ranks.
03457   * @note   It is not possible to enable both ADC auto-injected mode
03458   *         and ADC group injected discontinuous mode.
03459   * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_SetSequencerDiscont
03460   * @param  ADCx ADC instance
03461   * @param  SeqDiscont This parameter can be one of the following values:
03462   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
03463   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
03464   * @retval None
03465   */
03466 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
03467 {
03468   MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
03469 }
03470 
03471 /**
03472   * @brief  Get ADC group injected sequencer discontinuous mode:
03473   *         sequence subdivided and scan conversions interrupted every selected
03474   *         number of ranks.
03475   * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_GetSequencerDiscont
03476   * @param  ADCx ADC instance
03477   * @retval Returned value can be one of the following values:
03478   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
03479   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
03480   */
03481 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
03482 {
03483   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
03484 }
03485 
03486 /**
03487   * @brief  Set ADC group injected sequence: channel on the selected
03488   *         sequence rank.
03489   * @note   Depending on devices and packages, some channels may not be available.
03490   *         Refer to device datasheet for channels availability.
03491   * @note   On this STM32 family, to measure internal channels (VrefInt,
03492   *         TempSensor, ...), measurement paths to internal channels must be
03493   *         enabled separately.
03494   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
03495   * @note   On this STM32 family, some fast channels are available: fast analog inputs
03496   *         coming from GPIO pads (ADC_IN1..5).
03497   * @note   On this STM32 family, setting of this feature is conditioned to
03498   *         ADC state:
03499   *         ADC must not be disabled. Can be enabled with or without conversion
03500   *         on going on either groups regular or injected.
03501   * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\n
03502   *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\n
03503   *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\n
03504   *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks
03505   * @param  ADCx ADC instance
03506   * @param  Rank This parameter can be one of the following values:
03507   *         @arg @ref LL_ADC_INJ_RANK_1
03508   *         @arg @ref LL_ADC_INJ_RANK_2
03509   *         @arg @ref LL_ADC_INJ_RANK_3
03510   *         @arg @ref LL_ADC_INJ_RANK_4
03511   * @param  Channel This parameter can be one of the following values:
03512   *         @arg @ref LL_ADC_CHANNEL_0
03513   *         @arg @ref LL_ADC_CHANNEL_1           (5)
03514   *         @arg @ref LL_ADC_CHANNEL_2           (5)
03515   *         @arg @ref LL_ADC_CHANNEL_3           (5)
03516   *         @arg @ref LL_ADC_CHANNEL_4           (5)
03517   *         @arg @ref LL_ADC_CHANNEL_5           (5)
03518   *         @arg @ref LL_ADC_CHANNEL_6
03519   *         @arg @ref LL_ADC_CHANNEL_7
03520   *         @arg @ref LL_ADC_CHANNEL_8
03521   *         @arg @ref LL_ADC_CHANNEL_9
03522   *         @arg @ref LL_ADC_CHANNEL_10
03523   *         @arg @ref LL_ADC_CHANNEL_11
03524   *         @arg @ref LL_ADC_CHANNEL_12
03525   *         @arg @ref LL_ADC_CHANNEL_13
03526   *         @arg @ref LL_ADC_CHANNEL_14
03527   *         @arg @ref LL_ADC_CHANNEL_15
03528   *         @arg @ref LL_ADC_CHANNEL_16
03529   *         @arg @ref LL_ADC_CHANNEL_17
03530   *         @arg @ref LL_ADC_CHANNEL_18
03531   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
03532   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
03533   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
03534   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
03535   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
03536   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
03537   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
03538   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.
03539   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.
03540   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.
03541   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
03542   *         (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
03543   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
03544   * @retval None
03545   */
03546 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
03547 {
03548   /* Set bits with content of parameter "Channel" with bits position          */
03549   /* in register depending on parameter "Rank".                               */
03550   /* Parameters "Rank" and "Channel" are used with masks because containing   */
03551   /* other bits reserved for other purpose.                                   */
03552   MODIFY_REG(ADCx->JSQR,
03553              ADC_CHANNEL_ID_NUMBER_MASK >> (POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)),
03554              (Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)));
03555 }
03556 
03557 /**
03558   * @brief  Get ADC group injected sequence: channel on the selected
03559   *         sequence rank.
03560   * @note   Depending on devices and packages, some channels may not be available.
03561   *         Refer to device datasheet for channels availability.
03562   * @note   Usage of the returned channel number:
03563   *          - To reinject this channel into another function LL_ADC_xxx:
03564   *            the returned channel number is only partly formatted on definition
03565   *            of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
03566   *            with literals LL_ADC_CHANNEL_x, then the selected
03567   *            literal LL_ADC_CHANNEL_x can be used as parameter for another
03568   *            function.
03569   *          - To get the channel number in decimal format:
03570   *            process the returned value with the helper macro
03571   *            @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
03572   * @rmtoll JSQR     JSQ1           LL_ADC_INJ_GetSequencerRanks\n
03573   *         JSQR     JSQ2           LL_ADC_INJ_GetSequencerRanks\n
03574   *         JSQR     JSQ3           LL_ADC_INJ_GetSequencerRanks\n
03575   *         JSQR     JSQ4           LL_ADC_INJ_GetSequencerRanks
03576   * @param  ADCx ADC instance
03577   * @param  Rank This parameter can be one of the following values:
03578   *         @arg @ref LL_ADC_INJ_RANK_1
03579   *         @arg @ref LL_ADC_INJ_RANK_2
03580   *         @arg @ref LL_ADC_INJ_RANK_3
03581   *         @arg @ref LL_ADC_INJ_RANK_4
03582   * @retval Returned value can be one of the following values:
03583   *         @arg @ref LL_ADC_CHANNEL_0
03584   *         @arg @ref LL_ADC_CHANNEL_1           (5)
03585   *         @arg @ref LL_ADC_CHANNEL_2           (5)
03586   *         @arg @ref LL_ADC_CHANNEL_3           (5)
03587   *         @arg @ref LL_ADC_CHANNEL_4           (5)
03588   *         @arg @ref LL_ADC_CHANNEL_5           (5)
03589   *         @arg @ref LL_ADC_CHANNEL_6
03590   *         @arg @ref LL_ADC_CHANNEL_7
03591   *         @arg @ref LL_ADC_CHANNEL_8
03592   *         @arg @ref LL_ADC_CHANNEL_9
03593   *         @arg @ref LL_ADC_CHANNEL_10
03594   *         @arg @ref LL_ADC_CHANNEL_11
03595   *         @arg @ref LL_ADC_CHANNEL_12
03596   *         @arg @ref LL_ADC_CHANNEL_13
03597   *         @arg @ref LL_ADC_CHANNEL_14
03598   *         @arg @ref LL_ADC_CHANNEL_15
03599   *         @arg @ref LL_ADC_CHANNEL_16
03600   *         @arg @ref LL_ADC_CHANNEL_17
03601   *         @arg @ref LL_ADC_CHANNEL_18
03602   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
03603   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
03604   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
03605   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
03606   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
03607   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
03608   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
03609   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.
03610   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.
03611   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.
03612   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
03613   *         (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
03614   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
03615   *         (1, 2, 3, 4) For ADC channel read back from ADC register,
03616   *                      comparison with internal channel parameter to be done
03617   *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
03618   */
03619 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
03620 {
03621   return (uint32_t)(READ_BIT(ADCx->JSQR,
03622                              ADC_CHANNEL_ID_NUMBER_MASK >> (POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)))
03623                     << (POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) - (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
03624                    );
03625 }
03626 
03627 /**
03628   * @brief  Set one context on ADC group injected that will be checked in
03629   *         contexts queue.
03630   *         A context is a setting of injected group sequencer:
03631   *          * injected group trigger
03632   *          * sequencer length
03633   *          * sequencer ranks
03634   *         This function is intended to be used when contexts queue is enabled,
03635   *         because the sequence must be fully configured in one time
03636   *         (functions to set separately injected trigger and sequencer channels
03637   *         cannot be used):
03638   *         Refer to function @ref LL_ADC_INJ_SetQueueMode().
03639   * @note   In the contexts queue, only the active context can be read.
03640   *         The parameters of this function can be read using functions:
03641   *          - @ref LL_ADC_INJ_GetTrigSource()
03642   *          - @ref LL_ADC_INJ_GetTrigEdge()
03643   *          - @ref LL_ADC_INJ_GetSequencerRanks()
03644   * @note   On this STM32 family, to measure internal channels (VrefInt,
03645   *         TempSensor, ...), measurement paths to internal channels must be
03646   *         enabled separately.
03647   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
03648   * @note   On this STM32 family, some fast channels are available: fast analog inputs
03649   *         coming from GPIO pads (ADC_IN1..5).
03650   * @note   On this STM32 family, setting of this feature is conditioned to
03651   *         ADC state:
03652   *         ADC must not be disabled. Can be enabled with or without conversion
03653   *         on going on either groups regular or injected.
03654   * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_ConfigQueueContext\n
03655   *         JSQR     JEXTEN         LL_ADC_INJ_ConfigQueueContext\n
03656   *         JSQR     JL             LL_ADC_INJ_ConfigQueueContext\n
03657   *         JSQR     JSQ1           LL_ADC_INJ_ConfigQueueContext\n
03658   *         JSQR     JSQ2           LL_ADC_INJ_ConfigQueueContext\n
03659   *         JSQR     JSQ3           LL_ADC_INJ_ConfigQueueContext\n
03660   *         JSQR     JSQ4           LL_ADC_INJ_ConfigQueueContext
03661   * @param  ADCx ADC instance
03662   * @param  TriggerSource This parameter can be one of the following values:
03663   *         @arg @ref LL_ADC_INJ_TRIG_SW_START
03664   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
03665   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CC4
03666   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
03667   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CC1
03668   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CC4
03669   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
03670   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
03671   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CC4
03672   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
03673   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
03674   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
03675   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CC3
03676   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
03677   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CC1
03678   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
03679   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
03680   * @param  ExternalTriggerEdge This parameter can be one of the following values:
03681   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
03682   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
03683   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
03684   * @param  SequencerNbRanks This parameter can be one of the following values:
03685   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
03686   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
03687   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
03688   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
03689   * @param  Rank1_Channel This parameter can be one of the following values:
03690   *         @arg @ref LL_ADC_CHANNEL_0
03691   *         @arg @ref LL_ADC_CHANNEL_1           (5)
03692   *         @arg @ref LL_ADC_CHANNEL_2           (5)
03693   *         @arg @ref LL_ADC_CHANNEL_3           (5)
03694   *         @arg @ref LL_ADC_CHANNEL_4           (5)
03695   *         @arg @ref LL_ADC_CHANNEL_5           (5)
03696   *         @arg @ref LL_ADC_CHANNEL_6
03697   *         @arg @ref LL_ADC_CHANNEL_7
03698   *         @arg @ref LL_ADC_CHANNEL_8
03699   *         @arg @ref LL_ADC_CHANNEL_9
03700   *         @arg @ref LL_ADC_CHANNEL_10
03701   *         @arg @ref LL_ADC_CHANNEL_11
03702   *         @arg @ref LL_ADC_CHANNEL_12
03703   *         @arg @ref LL_ADC_CHANNEL_13
03704   *         @arg @ref LL_ADC_CHANNEL_14
03705   *         @arg @ref LL_ADC_CHANNEL_15
03706   *         @arg @ref LL_ADC_CHANNEL_16
03707   *         @arg @ref LL_ADC_CHANNEL_17
03708   *         @arg @ref LL_ADC_CHANNEL_18
03709   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
03710   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
03711   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
03712   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
03713   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
03714   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
03715   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
03716   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.
03717   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.
03718   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.
03719   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
03720   *         (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
03721   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
03722   * @param  Rank2_Channel This parameter can be one of the following values:
03723   *         @arg @ref LL_ADC_CHANNEL_0
03724   *         @arg @ref LL_ADC_CHANNEL_1           (5)
03725   *         @arg @ref LL_ADC_CHANNEL_2           (5)
03726   *         @arg @ref LL_ADC_CHANNEL_3           (5)
03727   *         @arg @ref LL_ADC_CHANNEL_4           (5)
03728   *         @arg @ref LL_ADC_CHANNEL_5           (5)
03729   *         @arg @ref LL_ADC_CHANNEL_6
03730   *         @arg @ref LL_ADC_CHANNEL_7
03731   *         @arg @ref LL_ADC_CHANNEL_8
03732   *         @arg @ref LL_ADC_CHANNEL_9
03733   *         @arg @ref LL_ADC_CHANNEL_10
03734   *         @arg @ref LL_ADC_CHANNEL_11
03735   *         @arg @ref LL_ADC_CHANNEL_12
03736   *         @arg @ref LL_ADC_CHANNEL_13
03737   *         @arg @ref LL_ADC_CHANNEL_14
03738   *         @arg @ref LL_ADC_CHANNEL_15
03739   *         @arg @ref LL_ADC_CHANNEL_16
03740   *         @arg @ref LL_ADC_CHANNEL_17
03741   *         @arg @ref LL_ADC_CHANNEL_18
03742   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
03743   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
03744   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
03745   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
03746   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
03747   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
03748   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
03749   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.
03750   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.
03751   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.
03752   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
03753   *         (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
03754   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
03755   * @param  Rank3_Channel This parameter can be one of the following values:
03756   *         @arg @ref LL_ADC_CHANNEL_0
03757   *         @arg @ref LL_ADC_CHANNEL_1           (5)
03758   *         @arg @ref LL_ADC_CHANNEL_2           (5)
03759   *         @arg @ref LL_ADC_CHANNEL_3           (5)
03760   *         @arg @ref LL_ADC_CHANNEL_4           (5)
03761   *         @arg @ref LL_ADC_CHANNEL_5           (5)
03762   *         @arg @ref LL_ADC_CHANNEL_6
03763   *         @arg @ref LL_ADC_CHANNEL_7
03764   *         @arg @ref LL_ADC_CHANNEL_8
03765   *         @arg @ref LL_ADC_CHANNEL_9
03766   *         @arg @ref LL_ADC_CHANNEL_10
03767   *         @arg @ref LL_ADC_CHANNEL_11
03768   *         @arg @ref LL_ADC_CHANNEL_12
03769   *         @arg @ref LL_ADC_CHANNEL_13
03770   *         @arg @ref LL_ADC_CHANNEL_14
03771   *         @arg @ref LL_ADC_CHANNEL_15
03772   *         @arg @ref LL_ADC_CHANNEL_16
03773   *         @arg @ref LL_ADC_CHANNEL_17
03774   *         @arg @ref LL_ADC_CHANNEL_18
03775   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
03776   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
03777   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
03778   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
03779   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
03780   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
03781   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
03782   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.
03783   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.
03784   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.
03785   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
03786   *         (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
03787   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
03788   * @param  Rank4_Channel This parameter can be one of the following values:
03789   *         @arg @ref LL_ADC_CHANNEL_0
03790   *         @arg @ref LL_ADC_CHANNEL_1           (5)
03791   *         @arg @ref LL_ADC_CHANNEL_2           (5)
03792   *         @arg @ref LL_ADC_CHANNEL_3           (5)
03793   *         @arg @ref LL_ADC_CHANNEL_4           (5)
03794   *         @arg @ref LL_ADC_CHANNEL_5           (5)
03795   *         @arg @ref LL_ADC_CHANNEL_6
03796   *         @arg @ref LL_ADC_CHANNEL_7
03797   *         @arg @ref LL_ADC_CHANNEL_8
03798   *         @arg @ref LL_ADC_CHANNEL_9
03799   *         @arg @ref LL_ADC_CHANNEL_10
03800   *         @arg @ref LL_ADC_CHANNEL_11
03801   *         @arg @ref LL_ADC_CHANNEL_12
03802   *         @arg @ref LL_ADC_CHANNEL_13
03803   *         @arg @ref LL_ADC_CHANNEL_14
03804   *         @arg @ref LL_ADC_CHANNEL_15
03805   *         @arg @ref LL_ADC_CHANNEL_16
03806   *         @arg @ref LL_ADC_CHANNEL_17
03807   *         @arg @ref LL_ADC_CHANNEL_18
03808   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
03809   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
03810   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
03811   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
03812   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
03813   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
03814   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
03815   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.
03816   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.
03817   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.
03818   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
03819   *         (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
03820   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
03821   * @retval None
03822   */
03823 __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
03824                                                    uint32_t TriggerSource,
03825                                                    uint32_t ExternalTriggerEdge,
03826                                                    uint32_t SequencerNbRanks,
03827                                                    uint32_t Rank1_Channel,
03828                                                    uint32_t Rank2_Channel,
03829                                                    uint32_t Rank3_Channel,
03830                                                    uint32_t Rank4_Channel)
03831 {
03832   /* Set bits with content of parameter "Rankx_Channel" with bits position    */
03833   /* in register depending on literal "LL_ADC_INJ_RANK_x".                    */
03834   /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks   */
03835   /* because containing other bits reserved for other purpose.                */
03836   MODIFY_REG(ADCx->JSQR           ,
03837              ADC_JSQR_JEXTSEL |
03838              ADC_JSQR_JEXTEN  |
03839              ADC_JSQR_JSQ4    |
03840              ADC_JSQR_JSQ3    |
03841              ADC_JSQR_JSQ2    |
03842              ADC_JSQR_JSQ1    |
03843              ADC_JSQR_JL          ,
03844              TriggerSource       |
03845              ExternalTriggerEdge |
03846              ((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) - (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK))) |
03847              ((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) - (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK))) |
03848              ((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) - (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK))) |
03849              ((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) - (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK))) |
03850              SequencerNbRanks
03851             );
03852 }
03853 
03854 /**
03855   * @}
03856   */
03857 
03858 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
03859   * @{
03860   */
03861 
03862 /**
03863   * @brief  Set sampling time of the selected ADC channel.
03864   *         Unit: ADC clock cycles.
03865   *         On this device, sampling time is on channel scope: independently
03866   *         of channel mapped on ADC group regular or injected.
03867   * @note   In case of internal channel (VrefInt, TempSensor, ...) to be
03868   *         converted:
03869   *         sampling time constraints must be respected (sampling time can be
03870   *         adjusted in function of ADC clock frequency and sampling time
03871   *         setting).
03872   *         Refer to device datasheet for timings values (parameters TS_vrefint,
03873   *         TS_temp, ...).
03874   * @note   Conversion time is the addition of sampling time and processing time.
03875   *         On this STM32 family, ADC processing time is:
03876   *          - 12.5 ADC clock cycles at ADC resolution 12 bits
03877   *          - 10.5 ADC clock cycles at ADC resolution 10 bits
03878   *          - 8.5 ADC clock cycles at ADC resolution 8 bits
03879   *          - 6.5 ADC clock cycles at ADC resolution 6 bits
03880   * @note   On this STM32 family, setting of this feature is conditioned to
03881   *         ADC state:
03882   *         ADC must be disabled or enabled without conversion on going
03883   *         on either groups regular or injected.
03884   * @rmtoll SMPR1    SMP0           LL_ADC_SetChannelSamplingTime\n
03885   *         SMPR1    SMP1           LL_ADC_SetChannelSamplingTime\n
03886   *         SMPR1    SMP2           LL_ADC_SetChannelSamplingTime\n
03887   *         SMPR1    SMP3           LL_ADC_SetChannelSamplingTime\n
03888   *         SMPR1    SMP4           LL_ADC_SetChannelSamplingTime\n
03889   *         SMPR1    SMP5           LL_ADC_SetChannelSamplingTime\n
03890   *         SMPR1    SMP6           LL_ADC_SetChannelSamplingTime\n
03891   *         SMPR1    SMP7           LL_ADC_SetChannelSamplingTime\n
03892   *         SMPR1    SMP8           LL_ADC_SetChannelSamplingTime\n
03893   *         SMPR1    SMP9           LL_ADC_SetChannelSamplingTime\n
03894   *         SMPR2    SMP10          LL_ADC_SetChannelSamplingTime\n
03895   *         SMPR2    SMP11          LL_ADC_SetChannelSamplingTime\n
03896   *         SMPR2    SMP12          LL_ADC_SetChannelSamplingTime\n
03897   *         SMPR2    SMP13          LL_ADC_SetChannelSamplingTime\n
03898   *         SMPR2    SMP14          LL_ADC_SetChannelSamplingTime\n
03899   *         SMPR2    SMP15          LL_ADC_SetChannelSamplingTime\n
03900   *         SMPR2    SMP16          LL_ADC_SetChannelSamplingTime\n
03901   *         SMPR2    SMP17          LL_ADC_SetChannelSamplingTime\n
03902   *         SMPR2    SMP18          LL_ADC_SetChannelSamplingTime
03903   * @param  ADCx ADC instance
03904   * @param  Channel This parameter can be one of the following values:
03905   *         @arg @ref LL_ADC_CHANNEL_0
03906   *         @arg @ref LL_ADC_CHANNEL_1           (5)
03907   *         @arg @ref LL_ADC_CHANNEL_2           (5)
03908   *         @arg @ref LL_ADC_CHANNEL_3           (5)
03909   *         @arg @ref LL_ADC_CHANNEL_4           (5)
03910   *         @arg @ref LL_ADC_CHANNEL_5           (5)
03911   *         @arg @ref LL_ADC_CHANNEL_6
03912   *         @arg @ref LL_ADC_CHANNEL_7
03913   *         @arg @ref LL_ADC_CHANNEL_8
03914   *         @arg @ref LL_ADC_CHANNEL_9
03915   *         @arg @ref LL_ADC_CHANNEL_10
03916   *         @arg @ref LL_ADC_CHANNEL_11
03917   *         @arg @ref LL_ADC_CHANNEL_12
03918   *         @arg @ref LL_ADC_CHANNEL_13
03919   *         @arg @ref LL_ADC_CHANNEL_14
03920   *         @arg @ref LL_ADC_CHANNEL_15
03921   *         @arg @ref LL_ADC_CHANNEL_16
03922   *         @arg @ref LL_ADC_CHANNEL_17
03923   *         @arg @ref LL_ADC_CHANNEL_18
03924   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
03925   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
03926   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
03927   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
03928   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
03929   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
03930   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
03931   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.
03932   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.
03933   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.
03934   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
03935   *         (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
03936   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
03937   * @param  SamplingTime This parameter can be one of the following values:
03938   *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
03939   *         @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
03940   *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
03941   *         @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
03942   *         @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
03943   *         @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
03944   *         @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
03945   *         @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
03946   * @retval None
03947   */
03948 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
03949 {
03950   /* Set bits with content of parameter "SamplingTime" with bits position     */
03951   /* in register and register position depending on parameter "Channel".      */
03952   /* Parameter "Channel" is used with masks because containing                */
03953   /* other bits reserved for other purpose.                                   */
03954   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
03955     
03956   MODIFY_REG(*preg,
03957              ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
03958              SamplingTime   << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
03959 }
03960 
03961 /**
03962   * @brief  Get sampling time of the selected ADC channel. 
03963   *         Unit: ADC clock cycles.
03964   *         On this device, sampling time is on channel scope: independently
03965   *         of channel mapped on ADC group regular or injected.
03966   * @note   Conversion time is the addition of sampling time and processing time.
03967   *         On this STM32 family, ADC processing time is:
03968   *          - 12.5 ADC clock cycles at ADC resolution 12 bits
03969   *          - 10.5 ADC clock cycles at ADC resolution 10 bits
03970   *          - 8.5 ADC clock cycles at ADC resolution 8 bits
03971   *          - 6.5 ADC clock cycles at ADC resolution 6 bits
03972   * @rmtoll SMPR1    SMP0           LL_ADC_GetChannelSamplingTime\n
03973   *         SMPR1    SMP1           LL_ADC_GetChannelSamplingTime\n
03974   *         SMPR1    SMP2           LL_ADC_GetChannelSamplingTime\n
03975   *         SMPR1    SMP3           LL_ADC_GetChannelSamplingTime\n
03976   *         SMPR1    SMP4           LL_ADC_GetChannelSamplingTime\n
03977   *         SMPR1    SMP5           LL_ADC_GetChannelSamplingTime\n
03978   *         SMPR1    SMP6           LL_ADC_GetChannelSamplingTime\n
03979   *         SMPR1    SMP7           LL_ADC_GetChannelSamplingTime\n
03980   *         SMPR1    SMP8           LL_ADC_GetChannelSamplingTime\n
03981   *         SMPR1    SMP9           LL_ADC_GetChannelSamplingTime\n
03982   *         SMPR2    SMP10          LL_ADC_GetChannelSamplingTime\n
03983   *         SMPR2    SMP11          LL_ADC_GetChannelSamplingTime\n
03984   *         SMPR2    SMP12          LL_ADC_GetChannelSamplingTime\n
03985   *         SMPR2    SMP13          LL_ADC_GetChannelSamplingTime\n
03986   *         SMPR2    SMP14          LL_ADC_GetChannelSamplingTime\n
03987   *         SMPR2    SMP15          LL_ADC_GetChannelSamplingTime\n
03988   *         SMPR2    SMP16          LL_ADC_GetChannelSamplingTime\n
03989   *         SMPR2    SMP17          LL_ADC_GetChannelSamplingTime\n
03990   *         SMPR2    SMP18          LL_ADC_GetChannelSamplingTime
03991   * @param  ADCx ADC instance
03992   * @param  Channel This parameter can be one of the following values:
03993   *         @arg @ref LL_ADC_CHANNEL_0
03994   *         @arg @ref LL_ADC_CHANNEL_1           (5)
03995   *         @arg @ref LL_ADC_CHANNEL_2           (5)
03996   *         @arg @ref LL_ADC_CHANNEL_3           (5)
03997   *         @arg @ref LL_ADC_CHANNEL_4           (5)
03998   *         @arg @ref LL_ADC_CHANNEL_5           (5)
03999   *         @arg @ref LL_ADC_CHANNEL_6
04000   *         @arg @ref LL_ADC_CHANNEL_7
04001   *         @arg @ref LL_ADC_CHANNEL_8
04002   *         @arg @ref LL_ADC_CHANNEL_9
04003   *         @arg @ref LL_ADC_CHANNEL_10
04004   *         @arg @ref LL_ADC_CHANNEL_11
04005   *         @arg @ref LL_ADC_CHANNEL_12
04006   *         @arg @ref LL_ADC_CHANNEL_13
04007   *         @arg @ref LL_ADC_CHANNEL_14
04008   *         @arg @ref LL_ADC_CHANNEL_15
04009   *         @arg @ref LL_ADC_CHANNEL_16
04010   *         @arg @ref LL_ADC_CHANNEL_17
04011   *         @arg @ref LL_ADC_CHANNEL_18
04012   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
04013   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)
04014   *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)
04015   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
04016   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
04017   *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)
04018   *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)
04019   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.
04020   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.
04021   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.
04022   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
04023   *         (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
04024   *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
04025   * @retval Returned value can be one of the following values:
04026   *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
04027   *         @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
04028   *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
04029   *         @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
04030   *         @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
04031   *         @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
04032   *         @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
04033   *         @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
04034   */
04035 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
04036 {
04037   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
04038   
04039   return (uint32_t)(READ_BIT(*preg,
04040                              ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
04041                     >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
04042                    );
04043 }
04044 
04045 /**
04046   * @brief  Set mode single-ended or differential input of the selected
04047   *         ADC channel.
04048   *         Channel ending is on channel scope: independently of channel mapped
04049   *         on ADC group regular or injected.
04050   *         In differential mode: Differential measurement is carried out
04051   *         between the selected channel 'i' (positive input) and
04052   *         channel 'i+1' (negative input). Only channel 'i' has to be
04053   *         configured, channel 'i+1' is configured automatically.
04054   * @note   Refer to Reference Manual to ensure the selected channel is available
04055   *         in differential mode.
04056   *         For example, internal channels (VrefInt, TempSensor, ...) are
04057   *         not available in differential mode.
04058   * @note   When configuring a channel 'i' in differential mode,
04059   *         the channel 'i+1' is not usable separately.
04060   * @note   On STM32L4, channels 15, 16, 17, 18 of ADC1, ADC2, ADC3 (if available)
04061   *         are internally fixed to single-ended inputs configuration.
04062   * @note   On this STM32 family, setting of this feature is conditioned to
04063   *         ADC state:
04064   *         ADC must be ADC disabled.
04065   * @note   One or several values can be selected.
04066   *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
04067   * @rmtoll DIFSEL   DIFSEL         LL_ADC_GetChannelSamplingTime
04068   * @param  ADCx ADC instance
04069   * @param  Channel This parameter can be one of the following values:
04070   *         @arg @ref LL_ADC_CHANNEL_1
04071   *         @arg @ref LL_ADC_CHANNEL_2
04072   *         @arg @ref LL_ADC_CHANNEL_3
04073   *         @arg @ref LL_ADC_CHANNEL_4
04074   *         @arg @ref LL_ADC_CHANNEL_5
04075   *         @arg @ref LL_ADC_CHANNEL_6
04076   *         @arg @ref LL_ADC_CHANNEL_7
04077   *         @arg @ref LL_ADC_CHANNEL_8
04078   *         @arg @ref LL_ADC_CHANNEL_9
04079   *         @arg @ref LL_ADC_CHANNEL_10
04080   *         @arg @ref LL_ADC_CHANNEL_11
04081   *         @arg @ref LL_ADC_CHANNEL_12
04082   *         @arg @ref LL_ADC_CHANNEL_13
04083   *         @arg @ref LL_ADC_CHANNEL_14
04084   * @param  SingleDiff This parameter can be a combination of the following values:
04085   *         @arg @ref LL_ADC_SINGLE_ENDED
04086   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
04087   * @retval None
04088   */
04089 __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
04090 {
04091   /* Bits of channels in single or differential mode are set only for         */
04092   /* differential mode (for single mode, mask of bits allowed to be set is    */
04093   /* shifted out of range of bits of channels in single or differential mode. */
04094   MODIFY_REG(ADCx->DIFSEL,
04095              Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
04096              (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL << (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
04097 }
04098 
04099 /**
04100   * @brief  Get mode single-ended or differential input of the selected
04101   *         ADC channel.
04102   * @note   When configuring a channel 'i' in differential mode,
04103   *         the channel 'i+1' is not usable separately.
04104   *         Therefore, to ensure a channel is configured in single-ended mode,
04105   *         the configuration of channel itself and the channel 'i-1' must be
04106   *         read back (to ensure that the selected channel channel has not been
04107   *         configured in differential mode by the previous channel).
04108   * @note   Refer to Reference Manual to ensure the selected channel is available
04109   *         in differential mode.
04110   *         For example, internal channels (VrefInt, TempSensor, ...) are
04111   *         not available in differential mode.
04112   * @note   When configuring a channel 'i' in differential mode,
04113   *         the channel 'i+1' is not usable separately.
04114   * @note   On STM32L4, channels 15, 16, 17, 18 of ADC1, ADC2, ADC3 (if available)
04115   *         are internally fixed to single-ended inputs configuration.
04116   * @note   One or several values can be selected. In this case, the value
04117   *         returned is null if all channels are in single ended-mode.
04118   *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
04119   * @rmtoll DIFSEL   DIFSEL         LL_ADC_GetChannelSamplingTime
04120   * @param  ADCx ADC instance
04121   * @param  Channel This parameter can be a combination of the following values:
04122   *         @arg @ref LL_ADC_CHANNEL_0
04123   *         @arg @ref LL_ADC_CHANNEL_1
04124   *         @arg @ref LL_ADC_CHANNEL_2
04125   *         @arg @ref LL_ADC_CHANNEL_3
04126   *         @arg @ref LL_ADC_CHANNEL_4
04127   *         @arg @ref LL_ADC_CHANNEL_5
04128   *         @arg @ref LL_ADC_CHANNEL_6
04129   *         @arg @ref LL_ADC_CHANNEL_7
04130   *         @arg @ref LL_ADC_CHANNEL_8
04131   *         @arg @ref LL_ADC_CHANNEL_9
04132   *         @arg @ref LL_ADC_CHANNEL_10
04133   *         @arg @ref LL_ADC_CHANNEL_11
04134   *         @arg @ref LL_ADC_CHANNEL_12
04135   *         @arg @ref LL_ADC_CHANNEL_13
04136   *         @arg @ref LL_ADC_CHANNEL_14
04137   * @retval 0: channel in single-ended mode, else: channel in differential mode
04138   */
04139 __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
04140 {
04141   return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
04142 }
04143 
04144 /**
04145   * @}
04146   */
04147 
04148 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
04149   * @{
04150   */
04151 
04152 /**
04153   * @brief  Set ADC analog watchdog monitored channels:
04154   *         a single channel, multiple channels or all channels,
04155   *         on ADC groups regular and-or injected.
04156   * @note   Once monitored channels are selected, analog watchdog
04157   *         is enabled.
04158   * @note   In case of need to define a single channel to monitor
04159   *         with analog watchdog from sequencer channel definition,
04160   *         use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
04161   * @note   On this STM32 family, there are 2 kinds of analog watchdog
04162   *         instance:
04163   *          - AWD standard (instance AWD1):
04164   *            - channels monitored: can monitor 1 channel or all channels.
04165   *            - groups monitored: ADC groups regular and-or injected.
04166   *            - resolution: resolution is not limited (corresponds to
04167   *              ADC resolution configured).
04168   *          - AWD flexible (instances AWD2, AWD3):
04169   *            - channels monitored: flexible on channels monitored, selection is
04170   *              channel wise, from from 1 to all channels.
04171   *              Specificity of this analog watchdog: Multiple channels can
04172   *              be selected. For example:
04173   *              (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
04174   *            - groups monitored: not selection possible (monitoring on both
04175   *              groups regular and injected).
04176   *              Channels selected are monitored on regular and injected groups:
04177   *              LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
04178   *              LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
04179   *            - resolution: resolution is limited to 8 bits: if ADC resolution is
04180   *              12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
04181   *              the 2 LSB are ignored.
04182   * @note   On this STM32 family, setting of this feature is conditioned to
04183   *         ADC state:
04184   *         ADC must be disabled or enabled without conversion on going
04185   *         on either groups regular or injected.
04186   * @rmtoll CFGR     AWD1CH         LL_ADC_SetAnalogWDMonitChannels\n
04187   *         CFGR     AWD1SGL        LL_ADC_SetAnalogWDMonitChannels\n
04188   *         CFGR     AWD1EN         LL_ADC_SetAnalogWDMonitChannels\n
04189   *         CFGR     JAWD1EN        LL_ADC_SetAnalogWDMonitChannels\n
04190   *         AWD2CR   AWD2CH         LL_ADC_SetAnalogWDMonitChannels\n
04191   *         AWD3CR   AWD3CH         LL_ADC_SetAnalogWDMonitChannels
04192   * @param  ADCx ADC instance
04193   * @param  AWDy This parameter can be one of the following values:
04194   *         @arg @ref LL_ADC_AWD1
04195   *         @arg @ref LL_ADC_AWD2
04196   *         @arg @ref LL_ADC_AWD3
04197   * @param  AWDChannelGroup This parameter can be one of the following values:
04198   *         @arg @ref LL_ADC_AWD_DISABLE
04199   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
04200   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
04201   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
04202   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
04203   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
04204   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
04205   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
04206   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
04207   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
04208   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
04209   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
04210   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
04211   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
04212   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
04213   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
04214   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
04215   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
04216   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
04217   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
04218   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
04219   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
04220   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
04221   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
04222   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
04223   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
04224   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
04225   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
04226   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
04227   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
04228   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
04229   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
04230   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
04231   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
04232   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
04233   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
04234   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
04235   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
04236   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
04237   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
04238   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
04239   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
04240   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
04241   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
04242   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
04243   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
04244   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
04245   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
04246   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
04247   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
04248   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
04249   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
04250   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
04251   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
04252   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
04253   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
04254   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
04255   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
04256   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
04257   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
04258   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
04259   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)(1)
04260   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)(1)
04261   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ         (1)
04262   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (0)(4)
04263   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (4)(4)
04264   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ      (4)
04265   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(4)
04266   *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(4)
04267   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (4)
04268   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG     (0)(2)
04269   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ     (0)(2)
04270   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ    (2)
04271   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG     (0)(2)
04272   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ     (0)(2)
04273   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ    (2)
04274   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG     (0)(3)
04275   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ     (0)(3)
04276   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ    (3)
04277   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG     (0)(3)
04278   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ     (0)(3)
04279   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ    (3)
04280   *         (0) On STM32L4, parameter available only on analog watchdog number: AWD1.
04281   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.
04282   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.
04283   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.
04284   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
04285   * @retval None
04286   */
04287 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
04288 {
04289   /* Set bits with content of parameter "AWDChannelGroup" with bits position  */
04290   /* in register and register position depending on parameter "AWDy".         */
04291   /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because      */
04292   /* containing other bits reserved for other purpose.                        */
04293   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK)
04294                                                              + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
04295   
04296   MODIFY_REG(*preg,
04297              (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
04298              AWDChannelGroup & AWDy);
04299 }
04300 
04301 /**
04302   * @brief  Get ADC analog watchdog monitored channel.
04303   * @note   Usage of the returned channel number:
04304   *          - To reinject this channel into another function LL_ADC_xxx:
04305   *            the returned channel number is only partly formatted on definition
04306   *            of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
04307   *            with literals LL_ADC_CHANNEL_x, then the selected
04308   *            literal LL_ADC_CHANNEL_x can be used as parameter for another
04309   *            function.
04310   *          - To get the channel number in decimal format:
04311   *            process the returned value with the helper macro
04312   *            @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
04313   *            Applicable only when the analog watchdog is set to monitor
04314   *            one channel.
04315   * @note   On this STM32 family, there are 2 kinds of analog watchdog
04316   *         instance:
04317   *          - AWD standard (instance AWD1):
04318   *            - channels monitored: can monitor 1 channel or all channels.
04319   *            - groups monitored: ADC groups regular and-or injected.
04320   *            - resolution: resolution is not limited (corresponds to
04321   *              ADC resolution configured).
04322   *          - AWD flexible (instances AWD2, AWD3):
04323   *            - channels monitored: flexible on channels monitored, selection is
04324   *              channel wise, from from 1 to all channels.
04325   *              Specificity of this analog watchdog: Multiple channels can
04326   *              be selected. For example:
04327   *              (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
04328   *            - groups monitored: not selection possible (monitoring on both
04329   *              groups regular and injected).
04330   *              Channels selected are monitored on regular and injected groups:
04331   *              LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
04332   *              LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
04333   *            - resolution: resolution is limited to 8 bits: if ADC resolution is
04334   *              12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
04335   *              the 2 LSB are ignored.
04336   * @note   On this STM32 family, setting of this feature is conditioned to
04337   *         ADC state:
04338   *         ADC must be disabled or enabled without conversion on going
04339   *         on either groups regular or injected.
04340   * @rmtoll CFGR     AWD1CH         LL_ADC_GetAnalogWDMonitChannels\n
04341   *         CFGR     AWD1SGL        LL_ADC_GetAnalogWDMonitChannels\n
04342   *         CFGR     AWD1EN         LL_ADC_GetAnalogWDMonitChannels\n
04343   *         CFGR     JAWD1EN        LL_ADC_GetAnalogWDMonitChannels\n
04344   *         AWD2CR   AWD2CH         LL_ADC_GetAnalogWDMonitChannels\n
04345   *         AWD3CR   AWD3CH         LL_ADC_GetAnalogWDMonitChannels
04346   * @param  ADCx ADC instance
04347   * @param  AWDy This parameter can be one of the following values:
04348   *         @arg @ref LL_ADC_AWD1
04349   *         @arg @ref LL_ADC_AWD2
04350   *         @arg @ref LL_ADC_AWD3
04351   * @retval Returned value can be one of the following values:
04352   *         @arg @ref LL_ADC_AWD_DISABLE
04353   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
04354   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
04355   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
04356   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
04357   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
04358   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
04359   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
04360   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
04361   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
04362   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
04363   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
04364   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
04365   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
04366   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
04367   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
04368   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
04369   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
04370   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
04371   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
04372   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
04373   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
04374   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
04375   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
04376   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
04377   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
04378   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
04379   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
04380   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
04381   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
04382   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
04383   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
04384   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
04385   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
04386   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
04387   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
04388   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
04389   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
04390   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
04391   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
04392   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
04393   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
04394   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
04395   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
04396   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
04397   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
04398   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
04399   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
04400   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
04401   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
04402   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
04403   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
04404   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
04405   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
04406   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
04407   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
04408   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
04409   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
04410   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
04411   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
04412   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
04413   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)(1)
04414   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)(1)
04415   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ         (1)
04416   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (0)(4)
04417   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (4)(4)
04418   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ      (4)
04419   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(4)
04420   *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(4)
04421   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (4)
04422   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG     (0)(2)
04423   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ     (0)(2)
04424   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ    (2)
04425   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG     (0)(2)
04426   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ     (0)(2)
04427   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ    (2)
04428   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG     (0)(3)
04429   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ     (0)(3)
04430   *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ    (3)
04431   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG     (0)(3)
04432   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ     (0)(3)
04433   *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ    (3)
04434   *         (0) On STM32L4, parameter available only on analog watchdog number: AWD1.
04435   *         (1) On STM32L4, parameter available only on ADC instance: ADC1.
04436   *         (2) On STM32L4, parameter available only on ADC instance: ADC2.
04437   *         (3) On STM32L4, parameter available only on ADC instance: ADC3.
04438   *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
04439   */
04440 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
04441 {
04442   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK)
04443                                                              + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
04444   
04445   return (uint32_t)(READ_BIT(*preg,
04446                              AWDy)
04447                    );
04448 }
04449 
04450 /**
04451   * @brief  Set ADC analog watchdog thresholds value of both thresholds
04452   *         high and low.
04453   * @note   If value of only one threshold high or low must be set,
04454   *         use function @ref LL_ADC_SetAnalogWDThresholds().
04455   * @note   On this STM32 family, there are 2 kinds of analog watchdog
04456   *         instance:
04457   *          - AWD standard (instance AWD1):
04458   *            - channels monitored: can monitor 1 channel or all channels.
04459   *            - groups monitored: ADC groups regular and-or injected.
04460   *            - resolution: resolution is not limited (corresponds to
04461   *              ADC resolution configured).
04462   *          - AWD flexible (instances AWD2, AWD3):
04463   *            - channels monitored: flexible on channels monitored, selection is
04464   *              channel wise, from from 1 to all channels.
04465   *              Specificity of this analog watchdog: Multiple channels can
04466   *              be selected. For example:
04467   *              (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
04468   *            - groups monitored: not selection possible (monitoring on both
04469   *              groups regular and injected).
04470   *              Channels selected are monitored on regular and injected groups:
04471   *              LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
04472   *              LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
04473   *            - resolution: resolution is limited to 8 bits: if ADC resolution is
04474   *              12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
04475   *              the 2 LSB are ignored.
04476   * @note   On this STM32 family, setting of this feature is conditioned to
04477   *         ADC state:
04478   *         ADC must be disabled or enabled without conversion on going
04479   *         on either groups regular or injected.
04480   * @rmtoll TR1      HT1            LL_ADC_ConfigAnalogWDThresholds\n
04481   *         TR2      HT2            LL_ADC_ConfigAnalogWDThresholds\n
04482   *         TR3      HT3            LL_ADC_ConfigAnalogWDThresholds\n
04483   *         TR1      LT1            LL_ADC_ConfigAnalogWDThresholds\n
04484   *         TR2      LT2            LL_ADC_ConfigAnalogWDThresholds\n
04485   *         TR3      LT3            LL_ADC_ConfigAnalogWDThresholds
04486   * @param  ADCx ADC instance
04487   * @param  AWDy This parameter can be one of the following values:
04488   *         @arg @ref LL_ADC_AWD1
04489   *         @arg @ref LL_ADC_AWD2
04490   *         @arg @ref LL_ADC_AWD3
04491   * @param  AWDThresholdHighValue For AWD1: 0x000...0xFFF, for AWD2, AWD3: 0x00...0xFF
04492   * @param  AWDThresholdLowValue For AWD1: 0x000...0xFFF, for AWD2, AWD3: 0x00...0xFF
04493   * @retval None
04494   */
04495 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef* ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
04496 {
04497   /* Set bits with content of parameter "AWDThresholdxxxValue" with bits      */
04498   /* position in register and register position depending on parameter        */
04499   /* "AWDy".                                                                  */
04500   /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
04501   /* containing other bits reserved for other purpose.                        */
04502   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
04503   
04504   MODIFY_REG(*preg,
04505              ADC_TR1_HT1 | ADC_TR1_LT1,
04506              (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
04507 }
04508 
04509 /**
04510   * @brief  Set ADC analog watchdog threshold value of threshold
04511   *         high or low.
04512   * @note   If values of both thresholds high or low must be set,
04513   *         use function @ref LL_ADC_ConfigAnalogWDThresholds().
04514   * @note   On this STM32 family, there are 2 kinds of analog watchdog
04515   *         instance:
04516   *          - AWD standard (instance AWD1):
04517   *            - channels monitored: can monitor 1 channel or all channels.
04518   *            - groups monitored: ADC groups regular and-or injected.
04519   *            - resolution: resolution is not limited (corresponds to
04520   *              ADC resolution configured).
04521   *          - AWD flexible (instances AWD2, AWD3):
04522   *            - channels monitored: flexible on channels monitored, selection is
04523   *              channel wise, from from 1 to all channels.
04524   *              Specificity of this analog watchdog: Multiple channels can
04525   *              be selected. For example:
04526   *              (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
04527   *            - groups monitored: not selection possible (monitoring on both
04528   *              groups regular and injected).
04529   *              Channels selected are monitored on regular and injected groups:
04530   *              LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
04531   *              LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
04532   *            - resolution: resolution is limited to 8 bits: if ADC resolution is
04533   *              12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
04534   *              the 2 LSB are ignored.
04535   * @note   On this STM32 family, setting of this feature is conditioned to
04536   *         ADC state:
04537   *         ADC must be disabled or enabled without conversion on going
04538   *         on either groups regular or injected.
04539   * @rmtoll TR1      HT1            LL_ADC_SetAnalogWDThresholds\n
04540   *         TR2      HT2            LL_ADC_SetAnalogWDThresholds\n
04541   *         TR3      HT3            LL_ADC_SetAnalogWDThresholds\n
04542   *         TR1      LT1            LL_ADC_SetAnalogWDThresholds\n
04543   *         TR2      LT2            LL_ADC_SetAnalogWDThresholds\n
04544   *         TR3      LT3            LL_ADC_SetAnalogWDThresholds
04545   * @param  ADCx ADC instance
04546   * @param  AWDy This parameter can be one of the following values:
04547   *         @arg @ref LL_ADC_AWD1
04548   *         @arg @ref LL_ADC_AWD2
04549   *         @arg @ref LL_ADC_AWD3
04550   * @param  AWDThresholdsHighLow This parameter can be one of the following values:
04551   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
04552   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
04553   * @param  AWDThresholdValue: For AWD1: 0x000...0xFFF, for AWD2, AWD3: 0x00...0xFF          
04554   * @retval None
04555   */
04556 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef* ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
04557 {
04558   /* Set bits with content of parameter "AWDThresholdValue" with bits         */
04559   /* position in register and register position depending on parameters       */
04560   /* "AWDThresholdsHighLow" and "AWDy".                                       */
04561   /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because    */
04562   /* containing other bits reserved for other purpose.                        */
04563   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
04564   
04565   MODIFY_REG(*preg,
04566              AWDThresholdsHighLow,
04567              AWDThresholdValue << POSITION_VAL(AWDThresholdsHighLow));
04568 }
04569 
04570 /**
04571   * @brief  Get ADC analog watchdog threshold value of threshold high,
04572   *         threshold low or raw data with ADC thresholds high and low concatenated.
04573   * @note   If raw data with raw data with ADC thresholds high and low is retrieved,
04574   *         the data of each threshold high or low can still be isolated
04575   *         using helper macro:
04576   *         @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
04577   * @rmtoll TR1      HT1            LL_ADC_GetAnalogWDThresholds\n
04578   *         TR2      HT2            LL_ADC_GetAnalogWDThresholds\n
04579   *         TR3      HT3            LL_ADC_GetAnalogWDThresholds\n
04580   *         TR1      LT1            LL_ADC_GetAnalogWDThresholds\n
04581   *         TR2      LT2            LL_ADC_GetAnalogWDThresholds\n
04582   *         TR3      LT3            LL_ADC_GetAnalogWDThresholds
04583   * @param  ADCx ADC instance
04584   * @param  AWDy This parameter can be one of the following values:
04585   *         @arg @ref LL_ADC_AWD1
04586   *         @arg @ref LL_ADC_AWD2
04587   *         @arg @ref LL_ADC_AWD3
04588   * @param  AWDThresholdsHighLow This parameter can be one of the following values:
04589   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
04590   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
04591   *         @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
04592   * @retval For AWD1: 0x000...0xFFF, for AWD2, AWD3: 0x00...0xFF
04593 */
04594 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
04595 {
04596   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
04597   
04598   return (uint32_t)(READ_BIT(*preg,
04599                              (AWDThresholdsHighLow | ADC_TR1_LT1))
04600                     >> POSITION_VAL(AWDThresholdsHighLow)
04601                    );
04602 }
04603 
04604 /**
04605   * @}
04606   */
04607 
04608 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
04609   * @{
04610   */
04611 
04612 /**
04613   * @brief  Set ADC oversampling scope: ADC groups regular and-or injected
04614   *         (availability of ADC group injected depends on devices).
04615   *         If both groups regular and injected are selected,
04616   *         specify behaviour of ADC group injected interrupting
04617   *         group regular: when ADC group injected is triggered,
04618   *         the oversampling on ADC group regular is either
04619   *         temporary stopped and continued, or resumed from start
04620   *         (oversampler buffer reset).
04621   * @note   On this STM32 family, setting of this feature is conditioned to
04622   *         ADC state:
04623   *         ADC must be disabled or enabled without conversion on going
04624   *         on either groups regular or injected.
04625   * @rmtoll CFGR2    ROVSE          LL_ADC_SetOverSamplingScope\n
04626   *         CFGR2    JOVSE          LL_ADC_SetOverSamplingScope\n
04627   *         CFGR2    ROVSM          LL_ADC_SetOverSamplingScope
04628   * @param  ADCx ADC instance
04629   * @param  OvsScope This parameter can be one of the following values:
04630   *         @arg @ref LL_ADC_OVS_DISABLE
04631   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
04632   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
04633   *         @arg @ref LL_ADC_OVS_GRP_INJECTED
04634   *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
04635   * @retval None
04636   */
04637 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
04638 {
04639   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
04640 }
04641 
04642 /**
04643   * @brief  Get ADC oversampling scope: ADC groups regular and-or injected
04644   *         (availability of ADC group injected depends on devices).
04645   *         If both groups regular and injected are selected,
04646   *         specify behaviour of ADC group injected interrupting
04647   *         group regular: when ADC group injected is triggered,
04648   *         the oversampling on ADC group regular is either
04649   *         temporary stopped and continued, or resumed from start
04650   *         (oversampler buffer reset).
04651   * @rmtoll CFGR2    ROVSE          LL_ADC_GetOverSamplingScope\n
04652   *         CFGR2    JOVSE          LL_ADC_GetOverSamplingScope\n
04653   *         CFGR2    ROVSM          LL_ADC_GetOverSamplingScope
04654   * @param  ADCx ADC instance
04655   * @retval Returned value can be one of the following values:
04656   *         @arg @ref LL_ADC_OVS_DISABLE
04657   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
04658   *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
04659   *         @arg @ref LL_ADC_OVS_GRP_INJECTED
04660   *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
04661   */
04662 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
04663 {
04664   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
04665 }
04666 
04667 /**
04668   * @brief  Set ADC oversampling discontinuous mode (triggered mode)
04669   *         on the selected ADC group: number of oversampled conversions
04670   *         are done either in:
04671   *          * continuous mode (all conversions of oversampling ratio
04672   *            are done from 1 trigger)
04673   *          * discontinuous mode (each conversion of oversampling ratio
04674   *            needs a trigger).
04675   * @note   On this STM32 family, setting of this feature is conditioned to
04676   *         ADC state:
04677   *         ADC must be disabled or enabled without conversion on going
04678   *         on group regular.
04679   * @note   On STM32L4, oversampling discontinuous mode (triggered mode)
04680   *         can be used only when oversampling is set on group regular only
04681   *         and in resumed mode.
04682   * @rmtoll CFGR2    TROVS          LL_ADC_SetOverSamplingDiscont
04683   * @param  ADCx ADC instance
04684   * @param  OverSamplingDiscont This parameter can be one of the following values:
04685   *         @arg @ref LL_ADC_OVS_REG_CONT
04686   *         @arg @ref LL_ADC_OVS_REG_DISCONT
04687   * @retval None
04688   */
04689 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
04690 {
04691   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
04692 }
04693 
04694 /**
04695   * @brief  Get ADC oversampling discontinuous mode (triggered mode)
04696   *         on the selected ADC group: number of oversampled conversions
04697   *         are done either in:
04698   *          * continuous mode (all conversions of oversampling ratio
04699   *            are done from 1 trigger)
04700   *          * discontinuous mode (each conversion of oversampling ratio
04701   *            needs a trigger).
04702   * @rmtoll CFGR2    TROVS          LL_ADC_GetOverSamplingDiscont
04703   * @param  ADCx ADC instance
04704   * @retval Returned value can be one of the following values:
04705   *         @arg @ref LL_ADC_OVS_REG_CONT
04706   *         @arg @ref LL_ADC_OVS_REG_DISCONT
04707   */
04708 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
04709 {
04710   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
04711 }
04712 
04713 /**
04714   * @brief  Set ADC oversampling (impacting both ADC groups regular and injected)
04715   *         parameters:
04716   *          * ratio
04717   *          * shift
04718   * @note   On this STM32 family, setting of this feature is conditioned to
04719   *         ADC state:
04720   *         ADC must be disabled or enabled without conversion on going
04721   *         on either groups regular or injected.
04722   * @rmtoll CFGR2    OVSS           LL_ADC_ConfigOverSamplingRatioShift\n
04723   *         CFGR2    OVSR           LL_ADC_ConfigOverSamplingRatioShift
04724   * @param  ADCx ADC instance
04725   * @param  Ratio This parameter can be one of the following values:
04726   *         @arg @ref LL_ADC_OVS_RATIO_2
04727   *         @arg @ref LL_ADC_OVS_RATIO_4
04728   *         @arg @ref LL_ADC_OVS_RATIO_8
04729   *         @arg @ref LL_ADC_OVS_RATIO_16
04730   *         @arg @ref LL_ADC_OVS_RATIO_32
04731   *         @arg @ref LL_ADC_OVS_RATIO_64
04732   *         @arg @ref LL_ADC_OVS_RATIO_128
04733   *         @arg @ref LL_ADC_OVS_RATIO_256
04734   * @param  Shift This parameter can be one of the following values:
04735   *         @arg @ref LL_ADC_OVS_DATA_SHIFT_NONE
04736   *         @arg @ref LL_ADC_OVS_DATA_SHIFT_1
04737   *         @arg @ref LL_ADC_OVS_DATA_SHIFT_2
04738   *         @arg @ref LL_ADC_OVS_DATA_SHIFT_3
04739   *         @arg @ref LL_ADC_OVS_DATA_SHIFT_4
04740   *         @arg @ref LL_ADC_OVS_DATA_SHIFT_5
04741   *         @arg @ref LL_ADC_OVS_DATA_SHIFT_6
04742   *         @arg @ref LL_ADC_OVS_DATA_SHIFT_7
04743   *         @arg @ref LL_ADC_OVS_DATA_SHIFT_8
04744   * @retval None
04745   */
04746 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
04747 {
04748   MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
04749 }
04750 
04751 /**
04752   * @brief  Get ADC oversampling (impacting both ADC groups regular and injected)
04753   *         parameters:
04754   *          * ratio
04755   * @rmtoll CFGR2    OVSR           LL_ADC_GetOverSamplingRatio
04756   * @param  ADCx ADC instance
04757   * @retval Ratio This parameter can be one of the following values:
04758   *         @arg @ref LL_ADC_OVS_RATIO_2
04759   *         @arg @ref LL_ADC_OVS_RATIO_4
04760   *         @arg @ref LL_ADC_OVS_RATIO_8
04761   *         @arg @ref LL_ADC_OVS_RATIO_16
04762   *         @arg @ref LL_ADC_OVS_RATIO_32
04763   *         @arg @ref LL_ADC_OVS_RATIO_64
04764   *         @arg @ref LL_ADC_OVS_RATIO_128
04765   *         @arg @ref LL_ADC_OVS_RATIO_256
04766 */
04767 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
04768 {
04769   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
04770 }
04771 
04772 /**
04773   * @brief  Get ADC oversampling (impacting both ADC groups regular and injected)
04774   *         parameters:
04775   *          * shift
04776   * @rmtoll CFGR2    OVSS           LL_ADC_GetOverSamplingShift
04777   * @param  ADCx ADC instance
04778   * @retval Shift This parameter can be one of the following values:
04779   *         @arg @ref LL_ADC_OVS_DATA_SHIFT_NONE
04780   *         @arg @ref LL_ADC_OVS_DATA_SHIFT_1
04781   *         @arg @ref LL_ADC_OVS_DATA_SHIFT_2
04782   *         @arg @ref LL_ADC_OVS_DATA_SHIFT_3
04783   *         @arg @ref LL_ADC_OVS_DATA_SHIFT_4
04784   *         @arg @ref LL_ADC_OVS_DATA_SHIFT_5
04785   *         @arg @ref LL_ADC_OVS_DATA_SHIFT_6
04786   *         @arg @ref LL_ADC_OVS_DATA_SHIFT_7
04787   *         @arg @ref LL_ADC_OVS_DATA_SHIFT_8
04788 */
04789 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
04790 {
04791   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
04792 }
04793 
04794 /**
04795   * @}
04796   */
04797 
04798 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
04799   * @{
04800   */
04801 
04802 #if defined(ADC2)
04803 /**
04804   * @brief  Set ADC multimode configuration to operate in independent mode
04805   *         or multimode (for devices with several ADC instances).
04806   *         If multimode configuration: the selected ADC instance is
04807   *         either master or slave depending on hardware.
04808   *         Refer to reference manual.
04809   * @note   On this STM32 family, setting of this feature is conditioned to
04810   *         ADC state:
04811   *         All ADC instances of the ADC common group must be disabled.
04812   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
04813   *         ADC instance or by using helper macro
04814   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
04815   * @rmtoll CCR      DUAL           LL_ADC_SetMultimode
04816   * @param  ADCxy_COMMON ADC common instance
04817   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
04818   * @param  Multimode This parameter can be one of the following values:
04819   *         @arg @ref LL_ADC_MULTI_INDEPENDENT
04820   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
04821   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
04822   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
04823   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
04824   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
04825   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
04826   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
04827   * @retval None
04828   */
04829 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
04830 {
04831   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
04832 }
04833 
04834 /**
04835   * @brief  Get ADC multimode configuration to operate in independent mode
04836   *         or multimode (for devices with several ADC instances).
04837   *         If multimode configuration: the selected ADC instance is
04838   *         either master or slave depending on hardware.
04839   *         Refer to reference manual.
04840   * @rmtoll CCR      DUAL           LL_ADC_GetMultimode
04841   * @param  ADCxy_COMMON ADC common instance
04842   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
04843   * @retval Returned value can be one of the following values:
04844   *         @arg @ref LL_ADC_MULTI_INDEPENDENT
04845   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
04846   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
04847   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
04848   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
04849   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
04850   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
04851   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
04852   */
04853 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
04854 {
04855   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
04856 }
04857 
04858 /**
04859   * @brief  Set ADC multimode conversion data transfer: no transfer
04860   *         or transfer by DMA.
04861   *         If ADC multimode transfer by DMA is not selected:
04862   *         each ADC uses its own DMA channel, with its individual
04863   *         DMA transfer settings.
04864   *         If ADC multimode transfer by DMA is selected:
04865   *         One DMA channel is used for both ADC (DMA of ADC master)
04866   *         Specifies the DMA requests mode:
04867   *          * Limited mode (One shot mode): DMA transfer requests are stopped
04868   *            when number of DMA data transfers (number of
04869   *            ADC conversions) is reached.
04870   *            This ADC mode is intended to be used with DMA mode non-circular.
04871   *          * Unlimited mode: DMA transfer requests are unlimited,
04872   *            whatever number of DMA data transfers (number of
04873   *            ADC conversions).
04874   *            This ADC mode is intended to be used with DMA mode circular.
04875   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
04876   *         mode non-circular:
04877   *         when DMA transfers size will be reached, DMA will stop transfers of
04878   *         ADC conversions data ADC will raise an overrun error
04879   *         (overrun flag and interruption if enabled).
04880   * @note   How to retrieve multimode conversion data:
04881   *         Whatever multimode transfer by DMA setting: using function
04882   *         @ref LL_ADC_REG_ReadMultiConversionData32().
04883   *         If ADC multimode transfer by DMA is selected: conversion data
04884   *         is a raw data with ADC master and slave concatenated.
04885   *         A macro is available to get the conversion data of
04886   *         ADC master or ADC slave: see helper macro
04887   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
04888   * @note   On this STM32 family, setting of this feature is conditioned to
04889   *         ADC state:
04890   *         All ADC instances of the ADC common group must be disabled
04891   *         or enabled without conversion on going on group regular.
04892   * @rmtoll CCR      MDMA           LL_ADC_SetMultiDMATransfer\n
04893   *         CCR      DMACFG         LL_ADC_SetMultiDMATransfer
04894   * @param  ADCxy_COMMON ADC common instance
04895   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
04896   * @param  DMATransfer This parameter can be one of the following values:
04897   *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
04898   *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
04899   *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
04900   *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
04901   *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
04902   * @retval None
04903   */
04904 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t DMATransfer)
04905 {
04906   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, DMATransfer);
04907 }
04908 
04909 /**
04910   * @brief  Get ADC multimode conversion data transfer: no transfer
04911   *         or transfer by DMA.
04912   *         If ADC multimode transfer by DMA is not selected:
04913   *         each ADC uses its own DMA channel, with its individual
04914   *         DMA transfer settings.
04915   *         If ADC multimode transfer by DMA is selected:
04916   *         One DMA channel is used for both ADC (DMA of ADC master)
04917   *         Specifies the DMA requests mode:
04918   *          * Limited mode (One shot mode): DMA transfer requests are stopped
04919   *            when number of DMA data transfers (number of
04920   *            ADC conversions) is reached.
04921   *            This ADC mode is intended to be used with DMA mode non-circular.
04922   *          * Unlimited mode: DMA transfer requests are unlimited,
04923   *            whatever number of DMA data transfers (number of
04924   *            ADC conversions).
04925   *            This ADC mode is intended to be used with DMA mode circular.
04926   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
04927   *         mode non-circular:
04928   *         when DMA transfers size will be reached, DMA will stop transfers of
04929   *         ADC conversions data ADC will raise an overrun error
04930   *         (overrun flag and interruption if enabled).
04931   * @note   How to retrieve multimode conversion data:
04932   *         Whatever multimode transfer by DMA setting: using function
04933   *         @ref LL_ADC_REG_ReadMultiConversionData32().
04934   *         If ADC multimode transfer by DMA is selected: conversion data
04935   *         is a raw data with ADC master and slave concatenated.
04936   *         A macro is available to get the conversion data of
04937   *         ADC master or ADC slave: see helper macro
04938   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
04939   * @rmtoll CCR      MDMA           LL_ADC_GetMultiDMATransfer\n
04940   *         CCR      DMACFG         LL_ADC_GetMultiDMATransfer
04941   * @param  ADCxy_COMMON ADC common instance
04942   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
04943   * @retval Returned value can be one of the following values:
04944   *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
04945   *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
04946   *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
04947   *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
04948   *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
04949   */
04950 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
04951 {
04952   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
04953 }
04954 
04955 /**
04956   * @brief  Set ADC multimode delay between 2 sampling phases.
04957   * @note   The sampling delay range depends on ADC resolution:
04958   *          - ADC resolution 12 bits can have maximum delay of 12 cycles.
04959   *          - ADC resolution 10 bits can have maximum delay of 10 cycles.
04960   *          - ADC resolution  8 bits can have maximum delay of  8 cycles.
04961   *          - ADC resolution  6 bits can have maximum delay of  6 cycles.
04962   * @note   On this STM32 family, setting of this feature is conditioned to
04963   *         ADC state:
04964   *         All ADC instances of the ADC common group must be disabled.
04965   *         This check can be done with function @ref LL_ADC_IsEnabled() for each
04966   *         ADC instance or by using helper macro helper macro
04967   *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
04968   * @rmtoll CCR      DELAY          LL_ADC_SetMultiTwoSamplingDelay
04969   * @param  ADCxy_COMMON ADC common instance
04970   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
04971   * @param  TwoSamplingDelay This parameter can be one of the following values:
04972   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
04973   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
04974   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
04975   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
04976   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
04977   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (1)
04978   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (1)
04979   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (2)
04980   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (2)
04981   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
04982   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
04983   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
04984   *         (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.
04985   *         (2) Parameter available only if ADC resolution is 12 or 10 bits.
04986   *         (3) Parameter available only if ADC resolution is 12 bits.
04987   * @retval None
04988   */
04989 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t TwoSamplingDelay)
04990 {
04991   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, TwoSamplingDelay);
04992 }
04993 
04994 /**
04995   * @brief  Get ADC multimode delay between 2 sampling phases.
04996   * @rmtoll CCR      DELAY          LL_ADC_GetMultiTwoSamplingDelay
04997   * @param  ADCxy_COMMON ADC common instance
04998   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
04999   * @retval Returned value can be one of the following values:
05000   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
05001   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
05002   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
05003   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
05004   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
05005   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (1)
05006   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (1)
05007   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (2)
05008   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (2)
05009   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
05010   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
05011   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
05012   *         (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.
05013   *         (2) Parameter available only if ADC resolution is 12 or 10 bits.
05014   *         (3) Parameter available only if ADC resolution is 12 bits.
05015   */
05016 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
05017 {
05018   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
05019 }
05020 #endif /* ADC2 */
05021 
05022 /**
05023   * @}
05024   */
05025 
05026 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
05027   * @{
05028   */
05029 
05030 /**
05031   * @brief  Put ADC instance in deep power down state.
05032   * @note   In case of ADC calibration necessary: When ADC is in deep-power-down
05033   *         state, the internal analog calibration is lost. After exiting from
05034   *         deep power down, calibration must be relaunched or calibration factor
05035   *         (preliminarily saved) must be set back into calibration register.
05036   * @note   On this STM32 family, setting of this feature is conditioned to
05037   *         ADC state:
05038   *         ADC must be ADC disabled.
05039   * @rmtoll CR       DEEPPWD        LL_ADC_EnableDeepPowerDown
05040   * @param  ADCx ADC instance
05041   * @retval None
05042   */
05043 __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
05044 {
05045   /* Note: Write register with some additional bits forced to state reset     */
05046   /*       instead of modifying only the selected bit for this function,      */
05047   /*       to not interfere with bits with HW property "rs".                  */
05048   MODIFY_REG(ADCx->CR,
05049              ADC_CR_BITS_PROPERTY_RS,
05050              ADC_CR_DEEPPWD);
05051 }
05052 
05053 /**
05054   * @brief  Disable ADC deep power down mode.
05055   * @note   In case of ADC calibration necessary: When ADC is in deep-power-down
05056   *         state, the internal analog calibration is lost. After exiting from
05057   *         deep power down, calibration must be relaunched or calibration factor
05058   *         (preliminarily saved) must be set back into calibration register.
05059   * @note   On this STM32 family, setting of this feature is conditioned to
05060   *         ADC state:
05061   *         ADC must be ADC disabled.
05062   * @rmtoll CR       DEEPPWD        LL_ADC_DisableDeepPowerDown
05063   * @param  ADCx ADC instance
05064   * @retval None
05065   */
05066 __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
05067 {
05068   /* Note: Write register with some additional bits forced to state reset     */
05069   /*       instead of modifying only the selected bit for this function,      */
05070   /*       to not interfere with bits with HW property "rs".                  */
05071   CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
05072 }
05073 
05074 /**
05075   * @brief  Get the selected ADC instance deep power down state.
05076   *         (0: deep power down is disabled, 1: deep power down is enabled)
05077   * @rmtoll CR       DEEPPWD        LL_ADC_IsDeepPowerDownEnabled
05078   * @param  ADCx ADC instance
05079   * @retval State of bit (1 or 0).
05080   */
05081 __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
05082 {
05083   return (READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD));
05084 }
05085 
05086 /**
05087   * @brief  Enable ADC instance internal voltage regulator.
05088   * @note   On this STM32 family, after ADC internal voltage regulator enable,
05089   *         a delay for ADC internal voltage regulator stabilization
05090   *         is required before performing a ADC calibration or ADC enable.
05091   *         Refer to device datasheet, parameter tADCVREG_STUP.
05092   * @note   On this STM32 family, setting of this feature is conditioned to
05093   *         ADC state:
05094   *         ADC must be ADC disabled.
05095   * @rmtoll CR       ADVREGEN       LL_ADC_EnableInternalRegulator
05096   * @param  ADCx ADC instance
05097   * @retval None
05098   */
05099 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
05100 {
05101   /* Note: Write register with some additional bits forced to state reset     */
05102   /*       instead of modifying only the selected bit for this function,      */
05103   /*       to not interfere with bits with HW property "rs".                  */
05104   MODIFY_REG(ADCx->CR,
05105              ADC_CR_BITS_PROPERTY_RS,
05106              ADC_CR_ADVREGEN);
05107 }
05108 
05109 /**
05110   * @brief  Disable ADC internal voltage regulator.
05111   * @note   On this STM32 family, setting of this feature is conditioned to
05112   *         ADC state:
05113   *         ADC must be ADC disabled.
05114   * @rmtoll CR       ADVREGEN       LL_ADC_DisableInternalRegulator
05115   * @param  ADCx ADC instance
05116   * @retval None
05117   */
05118 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
05119 {
05120   CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
05121 }
05122 
05123 /**
05124   * @brief  Get the selected ADC instance internal voltage regulator state.
05125   *         (0: internal regulator is disabled, 1: internal regulator is
05126   *         enabled).
05127   * @rmtoll CR       ADVREGEN       LL_ADC_IsInternalRegulatorEnabled
05128   * @param  ADCx ADC instance
05129   * @retval State of bit (1 or 0).
05130   */
05131 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
05132 {
05133   return (READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN));
05134 }
05135 
05136 /**
05137   * @brief  Enable the selected ADC instance.
05138   * @note   On this STM32 family, after ADC enable, a delay for 
05139   *         ADC internal analog stabilization is required before performing a
05140   *         ADC conversion start.
05141   *         Refer to device datasheet, parameter tSTAB.
05142   * @note   On this STM32 family, flag LL_ADC_ISR_ADRDY is raised when the ADC
05143   *         is enabled and when conversion clock (not core clock) is active.
05144   * @note   On this STM32 family, setting of this feature is conditioned to
05145   *         ADC state:
05146   *         ADC must be ADC disabled and ADC internal voltage regulator enabled.
05147   * @rmtoll CR       ADEN           LL_ADC_Enable
05148   * @param  ADCx ADC instance
05149   * @retval None
05150   */
05151 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
05152 {
05153   /* Note: Write register with some additional bits forced to state reset     */
05154   /*       instead of modifying only the selected bit for this function,      */
05155   /*       to not interfere with bits with HW property "rs".                  */
05156   MODIFY_REG(ADCx->CR,
05157              ADC_CR_BITS_PROPERTY_RS,
05158              ADC_CR_ADEN);
05159 }
05160 
05161 /**
05162   * @brief  Disable the selected ADC instance.
05163   * @note   On this STM32 family, setting of this feature is conditioned to
05164   *         ADC state:
05165   *         ADC must be not disabled. Must be enabled without conversion on going
05166   *         on either groups regular or injected.
05167   * @rmtoll CR       ADDIS          LL_ADC_Disable
05168   * @param  ADCx ADC instance
05169   * @retval None
05170   */
05171 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
05172 {
05173   /* Note: Write register with some additional bits forced to state reset     */
05174   /*       instead of modifying only the selected bit for this function,      */
05175   /*       to not interfere with bits with HW property "rs".                  */
05176   MODIFY_REG(ADCx->CR,
05177              ADC_CR_BITS_PROPERTY_RS,
05178              ADC_CR_ADDIS);
05179 }
05180 
05181 /**
05182   * @brief  Get the selected ADC instance enable state.
05183   *         (0: ADC is disabled, 1: ADC is enabled).
05184   * @note   On this STM32 family, flag LL_ADC_ISR_ADRDY is raised when the ADC
05185   *         is enabled and when conversion clock (not core clock) is active.
05186   * @rmtoll CR       ADEN           LL_ADC_IsEnabled
05187   * @param  ADCx ADC instance
05188   * @retval State of bit (1 or 0).
05189   */
05190 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
05191 {
05192   return (READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN));
05193 }
05194 
05195 /**
05196   * @brief  Get the selected ADC instance disable state.
05197   *         (0: no ADC disable command on going)
05198   * @rmtoll CR       ADDIS          LL_ADC_IsDisableOngoing
05199   * @param  ADCx ADC instance
05200   * @retval State of bit (1 or 0).
05201   */
05202 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
05203 {
05204   return (READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS));
05205 }
05206 
05207 /**
05208   * @brief  Start ADC calibration in the mode single-ended
05209   *         or differential (for devices with differential mode available).
05210   * @note   On this STM32 family, a delay of 4 ADC clock cycles is required
05211   *         between ADC end of calibration and ADC enable.
05212   * @note   On this STM32 family, setting of this feature is conditioned to
05213   *         ADC state:
05214   *         ADC must be ADC disabled.
05215   * @rmtoll CR       ADCAL          LL_ADC_StartCalibration\n
05216   *         CR       ADCALDIF       LL_ADC_StartCalibration
05217   * @param  ADCx ADC instance
05218   * @param  SingleDiff This parameter can be one of the following values:
05219   *         @arg @ref LL_ADC_SINGLE_ENDED
05220   *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
05221   * @retval None
05222   */
05223 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
05224 {
05225   /* Note: Write register with some additional bits forced to state reset     */
05226   /*       instead of modifying only the selected bit for this function,      */
05227   /*       to not interfere with bits with HW property "rs".                  */
05228   MODIFY_REG(ADCx->CR,
05229              ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
05230              ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
05231 }
05232 
05233 /**
05234   * @brief  Get ADC calibration state.
05235   *         (0: calibration complete, 1: calibration in progress)
05236   * @rmtoll CR       ADCAL          LL_ADC_IsCalibrationOnGoing
05237   * @param  ADCx ADC instance
05238   * @retval State of bit (1 or 0).
05239   */
05240 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
05241 {
05242   return (READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL));
05243 }
05244 
05245 /**
05246   * @}
05247   */
05248 
05249 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
05250   * @{
05251   */
05252 
05253 /**
05254   * @brief  Start ADC group regular conversion.
05255   * @note   On this STM32 family, this function is relevant for both 
05256   *         internal trigger (SW start) and external trigger:
05257   *          - If ADC trigger has been set to software start, ADC conversion
05258   *            starts immediately.
05259   *          - If ADC trigger has been set to external trigger, ADC conversion
05260   *            will start at next trigger event (on the selected trigger edge)
05261   *            following the ADC start conversion command.
05262   * @note   On this STM32 family, setting of this feature is conditioned to
05263   *         ADC state:
05264   *         ADC must be enabled without conversion on going on group regular,
05265   *         without conversion stop command on going on group regular.
05266   * @rmtoll CR       ADSTART        LL_ADC_REG_StartConversion
05267   * @param  ADCx ADC instance
05268   * @retval None
05269   */
05270 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
05271 {
05272   /* Note: Write register with some additional bits forced to state reset     */
05273   /*       instead of modifying only the selected bit for this function,      */
05274   /*       to not interfere with bits with HW property "rs".                  */
05275   MODIFY_REG(ADCx->CR,
05276              ADC_CR_BITS_PROPERTY_RS,
05277              ADC_CR_ADSTART);
05278 }
05279 
05280 /**
05281   * @brief  Stop ADC group regular conversion.
05282   * @note   On this STM32 family, setting of this feature is conditioned to
05283   *         ADC state:
05284   *         ADC must be enabled with conversion on going on group regular,
05285   *         without ADC disable command on going.
05286   * @rmtoll CR       ADSTP          LL_ADC_REG_StopConversion
05287   * @param  ADCx ADC instance
05288   * @retval None
05289   */
05290 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
05291 {
05292   /* Note: Write register with some additional bits forced to state reset     */
05293   /*       instead of modifying only the selected bit for this function,      */
05294   /*       to not interfere with bits with HW property "rs".                  */
05295   MODIFY_REG(ADCx->CR,
05296              ADC_CR_BITS_PROPERTY_RS,
05297              ADC_CR_ADSTP);
05298 }
05299 
05300 /**
05301   * @brief  Get ADC group regular conversion state.
05302   *         (0: no conversion is on going on ADC group regular)
05303   * @rmtoll CR       ADSTART        LL_ADC_REG_IsConversionOngoing
05304   * @param  ADCx ADC instance
05305   * @retval State of bit (1 or 0).
05306   */
05307 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
05308 {
05309   return (READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART));
05310 }
05311 
05312 /**
05313   * @brief  Get ADC group regular command of conversion stop state
05314   *         (0: no command of conversion stop is on going on ADC group regular).
05315   * @rmtoll CR       ADSTP          LL_ADC_REG_IsStopConversionOngoing
05316   * @param  ADCx ADC instance
05317   * @retval State of bit (1 or 0).
05318   */
05319 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
05320 {
05321   return (READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP));
05322 }
05323 
05324 /**
05325   * @brief  Get ADC group regular conversion data, range fit for
05326   *         all ADC configurations: all ADC resolutions and
05327   *         all oversampling increased data width (for devices
05328   *         with feature oversampling).
05329   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData32
05330   * @param  ADCx ADC instance
05331   * @retval 0x00000000...0xFFFFFFFF
05332   */
05333 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
05334 {
05335   return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
05336 }
05337 
05338 /**
05339   * @brief  Get ADC group regular conversion data, range fit for
05340   *         ADC resolution 12 bits.
05341   * @note   For devices with feature oversampling: Oversampling
05342   *         can increase data width, function for extended range
05343   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
05344   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData12
05345   * @param  ADCx ADC instance
05346   * @retval 0x000...0xFFF
05347   */
05348 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
05349 {
05350   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
05351 }
05352 
05353 /**
05354   * @brief  Get ADC group regular conversion data, range fit for
05355   *         ADC resolution 10 bits.
05356   * @note   For devices with feature oversampling: Oversampling
05357   *         can increase data width, function for extended range
05358   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
05359   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData10
05360   * @param  ADCx ADC instance
05361   * @retval 0x000...0x3FF
05362   */
05363 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
05364 {
05365   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
05366 }
05367 
05368 /**
05369   * @brief  Get ADC group regular conversion data, range fit for
05370   *         ADC resolution 8 bits.
05371   * @note   For devices with feature oversampling: Oversampling
05372   *         can increase data width, function for extended range
05373   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
05374   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData8
05375   * @param  ADCx ADC instance
05376   * @retval 0x00...0xFF
05377   */
05378 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
05379 {
05380   return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
05381 }
05382 
05383 /**
05384   * @brief  Get ADC group regular conversion data, range fit for
05385   *         ADC resolution 6 bits.
05386   * @note   For devices with feature oversampling: Oversampling
05387   *         can increase data width, function for extended range
05388   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
05389   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData6
05390   * @param  ADCx ADC instance
05391   * @retval 0x00...0x3F
05392   */
05393 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
05394 {
05395   return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
05396 }
05397 
05398 #if defined(ADC2)
05399 /**
05400   * @brief  Get ADC multimode conversion data of ADC master, ADC slave
05401   *         or raw data with ADC master and slave concatenated.
05402   * @note   If raw data with ADC master and slave concatenated is retrieved,
05403   *         a macro is available to get the conversion data of
05404   *         ADC master or ADC slave: see helper macro
05405   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
05406   *         (however this macro is mainly intended for multimode
05407   *         transfer by DMA, because this function can do the same
05408   *         by getting multimode conversion data of ADC master or ADC slave
05409   *         separately).
05410   * @rmtoll CDR      RDATA_MST      LL_ADC_REG_ReadMultiConversionData32\n
05411   *         CDR      RDATA_SLV      LL_ADC_REG_ReadMultiConversionData32
05412   * @param  ADCxy_COMMON ADC common instance
05413   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
05414   * @param  ConvData This parameter can be one of the following values:
05415   *         @arg @ref LL_ADC_MULTI_MASTER
05416   *         @arg @ref LL_ADC_MULTI_SLAVE
05417   *         @arg @ref LL_ADC_MULTI_MASTER_SLAVE
05418   * @retval 0x00000000...0xFFFFFFFF
05419   */
05420 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConvData)
05421 {
05422   return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
05423                              (ConvData | ADC_CDR_RDATA_SLV))
05424                     >> POSITION_VAL(ConvData)
05425                    );
05426 }
05427 #endif /* ADC2 */
05428 
05429 /**
05430   * @}
05431   */
05432 
05433 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
05434   * @{
05435   */
05436 
05437 /**
05438   * @brief  Start ADC group injected conversion.
05439   * @note   On this STM32 family, this function is relevant for both 
05440   *         internal trigger (SW start) and external trigger:
05441   *          - If ADC trigger has been set to software start, ADC conversion
05442   *            starts immediately.
05443   *          - If ADC trigger has been set to external trigger, ADC conversion
05444   *            will start at next trigger event (on the selected trigger edge)
05445   *            following the ADC start conversion command.
05446   * @note   On this STM32 family, setting of this feature is conditioned to
05447   *         ADC state:
05448   *         ADC must be enabled without conversion on going on group injected,
05449   *         without conversion stop command on going on group injected.
05450   * @rmtoll CR       JADSTART       LL_ADC_INJ_StartConversion
05451   * @param  ADCx ADC instance
05452   * @retval None
05453   */
05454 __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
05455 {
05456   /* Note: Write register with some additional bits forced to state reset     */
05457   /*       instead of modifying only the selected bit for this function,      */
05458   /*       to not interfere with bits with HW property "rs".                  */
05459   MODIFY_REG(ADCx->CR,
05460              ADC_CR_BITS_PROPERTY_RS,
05461              ADC_CR_JADSTART);
05462 }
05463 
05464 /**
05465   * @brief  Stop ADC group injected conversion.
05466   * @note   On this STM32 family, setting of this feature is conditioned to
05467   *         ADC state:
05468   *         ADC must be enabled with conversion on going on group injected,
05469   *         without ADC disable command on going.
05470   * @rmtoll CR       JADSTP         LL_ADC_INJ_StopConversion
05471   * @param  ADCx ADC instance
05472   * @retval None
05473   */
05474 __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
05475 {
05476   /* Note: Write register with some additional bits forced to state reset     */
05477   /*       instead of modifying only the selected bit for this function,      */
05478   /*       to not interfere with bits with HW property "rs".                  */
05479   MODIFY_REG(ADCx->CR,
05480              ADC_CR_BITS_PROPERTY_RS,
05481              ADC_CR_JADSTP);
05482 }
05483 
05484 /**
05485   * @brief  Get ADC group injected conversion state.
05486   *         (0: no conversion is on going on ADC group injected)
05487   * @rmtoll CR       JADSTART       LL_ADC_INJ_IsConversionOngoing
05488   * @param  ADCx ADC instance
05489   * @retval State of bit (1 or 0).
05490   */
05491 __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
05492 {
05493   return (READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART));
05494 }
05495 
05496 /**
05497   * @brief  Get ADC group injected command of conversion stop state
05498   *         (0: no command of conversion stop is on going on ADC group injected).
05499   * @rmtoll CR       JADSTP         LL_ADC_INJ_IsStopConversionOngoing
05500   * @param  ADCx ADC instance
05501   * @retval State of bit (1 or 0).
05502   */
05503 __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
05504 {
05505   return (READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP));
05506 }
05507 
05508 /**
05509   * @brief  Get ADC group regular conversion data, range fit for
05510   *         all ADC configurations: all ADC resolutions and
05511   *         all oversampling increased data width (for devices
05512   *         with feature oversampling).
05513   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData32\n
05514   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData32\n
05515   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData32\n
05516   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData32
05517   * @param  ADCx ADC instance
05518   * @param  Rank This parameter can be one of the following values:
05519   *         @arg @ref LL_ADC_INJ_RANK_1
05520   *         @arg @ref LL_ADC_INJ_RANK_2
05521   *         @arg @ref LL_ADC_INJ_RANK_3
05522   *         @arg @ref LL_ADC_INJ_RANK_4
05523   * @retval 0x00000000...0xFFFFFFFF
05524   */
05525 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
05526 {
05527   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
05528   
05529   return (uint32_t)(READ_BIT(*preg,
05530                              ADC_JDR1_JDATA)
05531                    );
05532 }
05533 
05534 /**
05535   * @brief  Get ADC group injected conversion data, range fit for
05536   *         ADC resolution 12 bits.
05537   * @note   For devices with feature oversampling: Oversampling
05538   *         can increase data width, function for extended range
05539   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
05540   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData12\n
05541   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData12\n
05542   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData12\n
05543   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData12
05544   * @param  ADCx ADC instance
05545   * @param  Rank This parameter can be one of the following values:
05546   *         @arg @ref LL_ADC_INJ_RANK_1
05547   *         @arg @ref LL_ADC_INJ_RANK_2
05548   *         @arg @ref LL_ADC_INJ_RANK_3
05549   *         @arg @ref LL_ADC_INJ_RANK_4
05550   * @retval 0x000...0xFFF
05551   */
05552 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
05553 {
05554   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
05555   
05556   return (uint16_t)(READ_BIT(*preg,
05557                              ADC_JDR1_JDATA)
05558                    );
05559 }
05560 
05561 /**
05562   * @brief  Get ADC group injected conversion data, range fit for
05563   *         ADC resolution 10 bits.
05564   * @note   For devices with feature oversampling: Oversampling
05565   *         can increase data width, function for extended range
05566   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
05567   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData10\n
05568   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData10\n
05569   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData10\n
05570   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData10
05571   * @param  ADCx ADC instance
05572   * @param  Rank This parameter can be one of the following values:
05573   *         @arg @ref LL_ADC_INJ_RANK_1
05574   *         @arg @ref LL_ADC_INJ_RANK_2
05575   *         @arg @ref LL_ADC_INJ_RANK_3
05576   *         @arg @ref LL_ADC_INJ_RANK_4
05577   * @retval 0x000...0x3FF
05578   */
05579 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
05580 {
05581   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
05582   
05583   return (uint16_t)(READ_BIT(*preg,
05584                              ADC_JDR1_JDATA)
05585                    );
05586 }
05587 
05588 /**
05589   * @brief  Get ADC group injected conversion data, range fit for
05590   *         ADC resolution 8 bits.
05591   * @note   For devices with feature oversampling: Oversampling
05592   *         can increase data width, function for extended range
05593   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
05594   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData8\n
05595   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData8\n
05596   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData8\n
05597   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData8
05598   * @param  ADCx ADC instance
05599   * @param  Rank This parameter can be one of the following values:
05600   *         @arg @ref LL_ADC_INJ_RANK_1
05601   *         @arg @ref LL_ADC_INJ_RANK_2
05602   *         @arg @ref LL_ADC_INJ_RANK_3
05603   *         @arg @ref LL_ADC_INJ_RANK_4
05604   * @retval 0x00...0xFF
05605   */
05606 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
05607 {
05608   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
05609   
05610   return (uint8_t)(READ_BIT(*preg,
05611                             ADC_JDR1_JDATA)
05612                   );
05613 }
05614 
05615 /**
05616   * @brief  Get ADC group injected conversion data, range fit for
05617   *         ADC resolution 6 bits.
05618   * @note   For devices with feature oversampling: Oversampling
05619   *         can increase data width, function for extended range
05620   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
05621   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData6\n
05622   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData6\n
05623   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData6\n
05624   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData6
05625   * @param  ADCx ADC instance
05626   * @param  Rank This parameter can be one of the following values:
05627   *         @arg @ref LL_ADC_INJ_RANK_1
05628   *         @arg @ref LL_ADC_INJ_RANK_2
05629   *         @arg @ref LL_ADC_INJ_RANK_3
05630   *         @arg @ref LL_ADC_INJ_RANK_4
05631   * @retval 0x00...0x3F
05632   */
05633 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
05634 {
05635   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
05636   
05637   return (uint8_t)(READ_BIT(*preg,
05638                             ADC_JDR1_JDATA)
05639                   );
05640 }
05641 
05642 /**
05643   * @}
05644   */
05645 
05646 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
05647   * @{
05648   */
05649 
05650 /**
05651   * @brief  Get flag ADC ready.
05652   * @rmtoll ISR      ADRDY          LL_ADC_IsActiveFlag_ADRDY
05653   * @param  ADCx ADC instance
05654   * @retval State of bit (1 or 0).
05655   */
05656 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
05657 {
05658   return (READ_BIT(ADCx->ISR, ADC_ISR_ADRDY) == (ADC_ISR_ADRDY));
05659 }
05660 
05661 /**
05662   * @brief  Get flag ADC group regular end of unitary conversion.
05663   * @rmtoll ISR      EOC            LL_ADC_IsActiveFlag_EOC
05664   * @param  ADCx ADC instance
05665   * @retval State of bit (1 or 0).
05666   */
05667 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
05668 {
05669   return (READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC));
05670 }
05671 
05672 /**
05673   * @brief  Get flag ADC group regular end of sequence conversions.
05674   * @rmtoll ISR      EOS            LL_ADC_IsActiveFlag_EOS
05675   * @param  ADCx ADC instance
05676   * @retval State of bit (1 or 0).
05677   */
05678 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
05679 {
05680   return (READ_BIT(ADCx->ISR, ADC_ISR_EOS) == (ADC_ISR_EOS));
05681 }
05682 
05683 /**
05684   * @brief  Get flag ADC group regular overrun.
05685   * @rmtoll ISR      OVR            LL_ADC_IsActiveFlag_OVR
05686   * @param  ADCx ADC instance
05687   * @retval State of bit (1 or 0).
05688   */
05689 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
05690 {
05691   return (READ_BIT(ADCx->ISR, ADC_ISR_OVR) == (ADC_ISR_OVR));
05692 }
05693 
05694 /**
05695   * @brief  Get flag ADC group regular end of sampling phase.
05696   * @rmtoll ISR      EOSMP          LL_ADC_IsActiveFlag_EOSMP
05697   * @param  ADCx ADC instance
05698   * @retval State of bit (1 or 0).
05699   */
05700 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
05701 {
05702   return (READ_BIT(ADCx->ISR, ADC_ISR_EOSMP) == (ADC_ISR_EOSMP));
05703 }
05704 
05705 /**
05706   * @brief  Get flag ADC group injected end of unitary conversion.
05707   * @rmtoll ISR      JEOC           LL_ADC_IsActiveFlag_JEOC
05708   * @param  ADCx ADC instance
05709   * @retval State of bit (1 or 0).
05710   */
05711 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
05712 {
05713   return (READ_BIT(ADCx->ISR, ADC_ISR_JEOC) == (ADC_ISR_JEOC));
05714 }
05715 
05716 /**
05717   * @brief  Get flag ADC group injected end of sequence conversions.
05718   * @rmtoll ISR      JEOS           LL_ADC_IsActiveFlag_JEOS
05719   * @param  ADCx ADC instance
05720   * @retval State of bit (1 or 0).
05721   */
05722 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
05723 {
05724   return (READ_BIT(ADCx->ISR, ADC_ISR_JEOS) == (ADC_ISR_JEOS));
05725 }
05726 
05727 /**
05728   * @brief  Get flag ADC group injected contexts queue overflow.
05729   * @rmtoll ISR      JQOVF          LL_ADC_IsActiveFlag_JQOVF
05730   * @param  ADCx ADC instance
05731   * @retval State of bit (1 or 0).
05732   */
05733 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
05734 {
05735   return (READ_BIT(ADCx->ISR, ADC_ISR_JQOVF) == (ADC_ISR_JQOVF));
05736 }
05737 
05738 /**
05739   * @brief  Get flag ADC analog watchdog 1 flag
05740   * @rmtoll ISR      AWD1           LL_ADC_IsActiveFlag_AWD1
05741   * @param  ADCx ADC instance
05742   * @retval State of bit (1 or 0).
05743   */
05744 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
05745 {
05746   return (READ_BIT(ADCx->ISR, ADC_ISR_AWD1) == (ADC_ISR_AWD1));
05747 }
05748 
05749 /**
05750   * @brief  Get flag ADC analog watchdog 2.
05751   * @rmtoll ISR      AWD2           LL_ADC_IsActiveFlag_AWD2
05752   * @param  ADCx ADC instance
05753   * @retval State of bit (1 or 0).
05754   */
05755 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
05756 {
05757   return (READ_BIT(ADCx->ISR, ADC_ISR_AWD2) == (ADC_ISR_AWD2));
05758 }
05759 
05760 /**
05761   * @brief  Get flag ADC analog watchdog 3.
05762   * @rmtoll ISR      AWD3           LL_ADC_IsActiveFlag_AWD3
05763   * @param  ADCx ADC instance
05764   * @retval State of bit (1 or 0).
05765   */
05766 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
05767 {
05768   return (READ_BIT(ADCx->ISR, ADC_ISR_AWD3) == (ADC_ISR_AWD3));
05769 }
05770 
05771 /**
05772   * @brief  Clear flag ADC ready.
05773   * @rmtoll ISR      ADRDY          LL_ADC_ClearFlag_ADRDY
05774   * @param  ADCx ADC instance
05775   * @retval None
05776   */
05777 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
05778 {
05779   WRITE_REG(ADCx->ISR, ADC_ISR_ADRDY);
05780 }
05781 
05782 /**
05783   * @brief  Clear flag ADC group regular end of unitary conversion.
05784   * @rmtoll ISR      EOC            LL_ADC_ClearFlag_EOC
05785   * @param  ADCx ADC instance
05786   * @retval None
05787   */
05788 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
05789 {
05790   WRITE_REG(ADCx->ISR, ADC_ISR_EOC);
05791 }
05792 
05793 /**
05794   * @brief  Clear flag ADC group regular end of sequence conversions.
05795   * @rmtoll ISR      EOS            LL_ADC_ClearFlag_EOS
05796   * @param  ADCx ADC instance
05797   * @retval None
05798   */
05799 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
05800 {
05801   WRITE_REG(ADCx->ISR, ADC_ISR_EOS);
05802 }
05803 
05804 /**
05805   * @brief  Clear flag ADC group regular overrun.
05806   * @rmtoll ISR      OVR            LL_ADC_ClearFlag_OVR
05807   * @param  ADCx ADC instance
05808   * @retval None
05809   */
05810 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
05811 {
05812   WRITE_REG(ADCx->ISR, ADC_ISR_OVR);
05813 }
05814 
05815 /**
05816   * @brief  Clear flag ADC group regular end of sampling phase.
05817   * @rmtoll ISR      EOSMP          LL_ADC_ClearFlag_EOSMP
05818   * @param  ADCx ADC instance
05819   * @retval None
05820   */
05821 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
05822 {
05823   WRITE_REG(ADCx->ISR, ADC_ISR_EOSMP);
05824 }
05825 
05826 /**
05827   * @brief  Clear flag ADC group injected end of unitary conversion.
05828   * @rmtoll ISR      JEOC           LL_ADC_ClearFlag_JEOC
05829   * @param  ADCx ADC instance
05830   * @retval None
05831   */
05832 __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
05833 {
05834   WRITE_REG(ADCx->ISR, ADC_ISR_JEOC);
05835 }
05836 
05837 /**
05838   * @brief  Clear flag ADC group injected end of sequence conversions.
05839   * @rmtoll ISR      JEOS           LL_ADC_ClearFlag_JEOS
05840   * @param  ADCx ADC instance
05841   * @retval None
05842   */
05843 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
05844 {
05845   WRITE_REG(ADCx->ISR, ADC_ISR_JEOS);
05846 }
05847 
05848 /**
05849   * @brief  Clear flag ADC group injected contexts queue overflow.
05850   * @rmtoll ISR      JQOVF          LL_ADC_ClearFlag_JQOVF
05851   * @param  ADCx ADC instance
05852   * @retval None
05853   */
05854 __STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
05855 {
05856   WRITE_REG(ADCx->ISR, ADC_ISR_JQOVF);
05857 }
05858 
05859 /**
05860   * @brief  Clear flag ADC analog watchdog 1.
05861   * @rmtoll ISR      AWD1           LL_ADC_ClearFlag_AWD1
05862   * @param  ADCx ADC instance
05863   * @retval None
05864   */
05865 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
05866 {
05867   WRITE_REG(ADCx->ISR, ADC_ISR_AWD1);
05868 }
05869 
05870 /**
05871   * @brief  Clear flag ADC analog watchdog 2.
05872   * @rmtoll ISR      AWD2           LL_ADC_ClearFlag_AWD2
05873   * @param  ADCx ADC instance
05874   * @retval None
05875   */
05876 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
05877 {
05878   WRITE_REG(ADCx->ISR, ADC_ISR_AWD2);
05879 }
05880 
05881 /**
05882   * @brief  Clear flag ADC analog watchdog 3.
05883   * @rmtoll ISR      AWD3           LL_ADC_ClearFlag_AWD3
05884   * @param  ADCx ADC instance
05885   * @retval None
05886   */
05887 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
05888 {
05889   WRITE_REG(ADCx->ISR, ADC_ISR_AWD3);
05890 }
05891 
05892 #if defined(ADC2)
05893 /**
05894   * @brief  Get flag multimode ADC ready of the ADC master.
05895   * @rmtoll CSR      ADRDY_MST      LL_ADC_IsActiveFlag_MST_ADRDY
05896   * @param  ADCxy_COMMON ADC common instance
05897   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
05898   * @retval State of bit (1 or 0).
05899   */
05900 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
05901 {
05902   return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_ADRDY_MST) == (ADC_CSR_ADRDY_MST));
05903 }
05904 
05905 /**
05906   * @brief  Get flag multimode ADC ready of the ADC slave.
05907   * @rmtoll CSR      ADRDY_SLV      LL_ADC_IsActiveFlag_SLV_ADRDY
05908   * @param  ADCxy_COMMON ADC common instance
05909   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
05910   * @retval State of bit (1 or 0).
05911   */
05912 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
05913 {
05914   return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_ADRDY_SLV) == (ADC_CSR_ADRDY_SLV));
05915 }
05916 
05917 /**
05918   * @brief  Get flag multimode ADC group regular end of unitary conversion of the ADC master.
05919   * @rmtoll CSR      EOC_MST        LL_ADC_IsActiveFlag_MST_EOC
05920   * @param  ADCxy_COMMON ADC common instance
05921   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
05922   * @retval State of bit (1 or 0).
05923   */
05924 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
05925 {
05926   return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_EOC_SLV) == (ADC_CSR_EOC_SLV));
05927 }
05928 
05929 /**
05930   * @brief  Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
05931   * @rmtoll CSR      EOC_SLV        LL_ADC_IsActiveFlag_SLV_EOC
05932   * @param  ADCxy_COMMON ADC common instance
05933   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
05934   * @retval State of bit (1 or 0).
05935   */
05936 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
05937 {
05938   return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_EOC_SLV) == (ADC_CSR_EOC_SLV));
05939 }
05940 
05941 /**
05942   * @brief  Get flag multimode ADC group regular end of sequence conversions of the ADC master.
05943   * @rmtoll CSR      EOS_MST        LL_ADC_IsActiveFlag_MST_EOS
05944   * @param  ADCxy_COMMON ADC common instance
05945   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
05946   * @retval State of bit (1 or 0).
05947   */
05948 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
05949 {
05950   return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_EOS_MST) == (ADC_CSR_EOS_MST));
05951 }
05952 
05953 /**
05954   * @brief  Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
05955   * @rmtoll CSR      EOS_SLV        LL_ADC_IsActiveFlag_SLV_EOS
05956   * @param  ADCxy_COMMON ADC common instance
05957   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
05958   * @retval State of bit (1 or 0).
05959   */
05960 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
05961 {
05962   return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_EOS_SLV) == (ADC_CSR_EOS_SLV));
05963 }
05964 
05965 /**
05966   * @brief  Get flag multimode ADC group regular overrun of the ADC master.
05967   * @rmtoll CSR      OVR_MST        LL_ADC_IsActiveFlag_MST_OVR
05968   * @param  ADCxy_COMMON ADC common instance
05969   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
05970   * @retval State of bit (1 or 0).
05971   */
05972 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
05973 {
05974   return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_OVR_MST) == (ADC_CSR_OVR_MST));
05975 }
05976 
05977 /**
05978   * @brief  Get flag multimode ADC group regular overrun of the ADC slave.
05979   * @rmtoll CSR      OVR_SLV        LL_ADC_IsActiveFlag_SLV_OVR
05980   * @param  ADCxy_COMMON ADC common instance
05981   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
05982   * @retval State of bit (1 or 0).
05983   */
05984 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
05985 {
05986   return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_OVR_SLV) == (ADC_CSR_OVR_SLV));
05987 }
05988 
05989 /**
05990   * @brief  Get flag multimode ADC group regular end of sampling of the ADC master.
05991   * @rmtoll CSR      EOSMP_MST      LL_ADC_IsActiveFlag_MST_EOSMP
05992   * @param  ADCxy_COMMON ADC common instance
05993   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
05994   * @retval State of bit (1 or 0).
05995   */
05996 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
05997 {
05998   return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_EOSMP_MST) == (ADC_CSR_EOSMP_MST));
05999 }
06000 
06001 /**
06002   * @brief  Get flag multimode ADC group regular end of sampling of the ADC slave.
06003   * @rmtoll CSR      EOSMP_SLV      LL_ADC_IsActiveFlag_SLV_EOSMP
06004   * @param  ADCxy_COMMON ADC common instance
06005   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06006   * @retval State of bit (1 or 0).
06007   */
06008 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
06009 {
06010   return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_EOSMP_SLV) == (ADC_CSR_EOSMP_SLV));
06011 }
06012 
06013 /**
06014   * @brief  Get flag multimode ADC group injected end of unitary conversion of the ADC master.
06015   * @rmtoll CSR      JEOC_MST       LL_ADC_IsActiveFlag_MST_JEOC
06016   * @param  ADCxy_COMMON ADC common instance
06017   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06018   * @retval State of bit (1 or 0).
06019   */
06020 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
06021 {
06022   return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC_MST) == (ADC_CSR_JEOC_MST));
06023 }
06024 
06025 /**
06026   * @brief  Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
06027   * @rmtoll CSR      JEOC_SLV       LL_ADC_IsActiveFlag_SLV_JEOC
06028   * @param  ADCxy_COMMON ADC common instance
06029   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06030   * @retval State of bit (1 or 0).
06031   */
06032 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
06033 {
06034   return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC_SLV) == (ADC_CSR_JEOC_SLV));
06035 }
06036 
06037 /**
06038   * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC master.
06039   * @rmtoll CSR      JEOS_MST       LL_ADC_IsActiveFlag_MST_JEOS
06040   * @param  ADCxy_COMMON ADC common instance
06041   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06042   * @retval State of bit (1 or 0).
06043   */
06044 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
06045 {
06046   return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOS_MST) == (ADC_CSR_JEOS_MST));
06047 }
06048 
06049 /**
06050   * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
06051   * @rmtoll CSR      JEOS_SLV       LL_ADC_IsActiveFlag_SLV_JEOS
06052   * @param  ADCxy_COMMON ADC common instance
06053   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06054   * @retval State of bit (1 or 0).
06055   */
06056 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
06057 {
06058   return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOS_SLV) == (ADC_CSR_JEOS_SLV));
06059 }
06060 
06061 /**
06062   * @brief  Get flag multimode ADC group injected context queue overflow of the ADC master.
06063   * @rmtoll CSR      JQOVF_MST      LL_ADC_IsActiveFlag_MST_JQOVF
06064   * @param  ADCxy_COMMON ADC common instance
06065   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06066   * @retval State of bit (1 or 0).
06067   */
06068 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
06069 {
06070   return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JQOVF_MST) == (ADC_CSR_JQOVF_MST));
06071 }
06072 
06073 /**
06074   * @brief  Get flag multimode ADC group injected context queue overflow of the ADC slave.
06075   * @rmtoll CSR      JQOVF_SLV      LL_ADC_IsActiveFlag_SLV_JQOVF
06076   * @param  ADCxy_COMMON ADC common instance
06077   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06078   * @retval State of bit (1 or 0).
06079   */
06080 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
06081 {
06082   return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JQOVF_SLV) == (ADC_CSR_JQOVF_SLV));
06083 }
06084 
06085 /**
06086   * @brief  Get flag multimode ADC analog watchdog 1 of the ADC master.
06087   * @rmtoll CSR      AWD1_MST       LL_ADC_IsActiveFlag_MST_AWD1
06088   * @param  ADCxy_COMMON ADC common instance
06089   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06090   * @retval State of bit (1 or 0).
06091   */
06092 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
06093 {
06094   return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_AWD1_MST) == (ADC_CSR_AWD1_MST));
06095 }
06096 
06097 /**
06098   * @brief  Get flag multimode analog watchdog 1 of the ADC slave.
06099   * @rmtoll CSR      AWD1_SLV       LL_ADC_IsActiveFlag_SLV_AWD1
06100   * @param  ADCxy_COMMON ADC common instance
06101   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06102   * @retval State of bit (1 or 0).
06103   */
06104 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
06105 {
06106   return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_AWD1_SLV) == (ADC_CSR_AWD1_SLV));
06107 }
06108 
06109 /**
06110   * @brief  Get flag multimode ADC analog watchdog 2 of the ADC master.
06111   * @rmtoll CSR      AWD2_MST       LL_ADC_IsActiveFlag_MST_AWD2
06112   * @param  ADCxy_COMMON ADC common instance
06113   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06114   * @retval State of bit (1 or 0).
06115   */
06116 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
06117 {
06118   return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_AWD2_MST) == (ADC_CSR_AWD2_MST));
06119 }
06120 
06121 /**
06122   * @brief  Get flag multimode ADC analog watchdog 2 of the ADC slave.
06123   * @rmtoll CSR      AWD2_SLV       LL_ADC_IsActiveFlag_SLV_AWD2
06124   * @param  ADCxy_COMMON ADC common instance
06125   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06126   * @retval State of bit (1 or 0).
06127   */
06128 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
06129 {
06130   return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_AWD2_SLV) == (ADC_CSR_AWD2_SLV));
06131 }
06132 
06133 /**
06134   * @brief  Get flag multimode ADC analog watchdog 3 of the ADC master.
06135   * @rmtoll CSR      AWD3_MST       LL_ADC_IsActiveFlag_MST_AWD3
06136   * @param  ADCxy_COMMON ADC common instance
06137   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06138   * @retval State of bit (1 or 0).
06139   */
06140 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
06141 {
06142   return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_AWD3_MST) == (ADC_CSR_AWD3_MST));
06143 }
06144 
06145 /**
06146   * @brief  Get flag multimode ADC analog watchdog 3 of the ADC slave.
06147   * @rmtoll CSR      AWD3_SLV       LL_ADC_IsActiveFlag_SLV_AWD3
06148   * @param  ADCxy_COMMON ADC common instance
06149   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
06150   * @retval State of bit (1 or 0).
06151   */
06152 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
06153 {
06154   return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_AWD3_SLV) == (ADC_CSR_AWD3_SLV));
06155 }
06156 #endif /* ADC2 */
06157 
06158 /**
06159   * @}
06160   */
06161 
06162 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
06163   * @{
06164   */
06165 
06166 /**
06167   * @brief  Enable ADC ready.
06168   * @rmtoll IER      ADRDYIE        LL_ADC_EnableIT_ADRDY
06169   * @param  ADCx ADC instance
06170   * @retval None
06171   */
06172 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
06173 {
06174   SET_BIT(ADCx->IER, ADC_IER_ADRDY);
06175 }
06176 
06177 /**
06178   * @brief  Enable interruption ADC group regular end of unitary conversion.
06179   * @rmtoll IER      EOCIE          LL_ADC_EnableIT_EOC
06180   * @param  ADCx ADC instance
06181   * @retval None
06182   */
06183 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
06184 {
06185   SET_BIT(ADCx->IER, ADC_IER_EOC);
06186 }
06187 
06188 /**
06189   * @brief  Enable interruption ADC group regular end of sequence conversions.
06190   * @rmtoll IER      EOSIE          LL_ADC_EnableIT_EOS
06191   * @param  ADCx ADC instance
06192   * @retval None
06193   */
06194 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
06195 {
06196   SET_BIT(ADCx->IER, ADC_IER_EOS);
06197 }
06198 
06199 /**
06200   * @brief  Enable ADC group regular interruption overrun.
06201   * @rmtoll IER      OVRIE          LL_ADC_EnableIT_OVR
06202   * @param  ADCx ADC instance
06203   * @retval None
06204   */
06205 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
06206 {
06207   SET_BIT(ADCx->IER, ADC_IER_OVR);
06208 }
06209 
06210 /**
06211   * @brief  Enable interruption ADC group regular end of sampling.
06212   * @rmtoll IER      EOSMPIE        LL_ADC_EnableIT_EOSMP
06213   * @param  ADCx ADC instance
06214   * @retval None
06215   */
06216 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
06217 {
06218   SET_BIT(ADCx->IER, ADC_IER_EOSMP);
06219 }
06220 
06221 /**
06222   * @brief  Enable interruption ADC group injected end of unitary conversion.
06223   * @rmtoll IER      JEOCIE         LL_ADC_EnableIT_JEOC
06224   * @param  ADCx ADC instance
06225   * @retval None
06226   */
06227 __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
06228 {
06229   SET_BIT(ADCx->IER, ADC_IER_JEOC);
06230 }
06231 
06232 /**
06233   * @brief  Enable interruption ADC group injected end of sequence conversions.
06234   * @rmtoll IER      JEOSIE         LL_ADC_EnableIT_JEOS
06235   * @param  ADCx ADC instance
06236   * @retval None
06237   */
06238 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
06239 {
06240   SET_BIT(ADCx->IER, ADC_IER_JEOS);
06241 }
06242 
06243 /**
06244   * @brief  Enable interruption ADC group injected context queue overflow.
06245   * @rmtoll IER      JQOVFIE        LL_ADC_EnableIT_JQOVF
06246   * @param  ADCx ADC instance
06247   * @retval None
06248   */
06249 __STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
06250 {
06251   SET_BIT(ADCx->IER, ADC_IER_JQOVF);
06252 }
06253 
06254 /**
06255   * @brief  Enable interruption ADC analog watchdog 1.
06256   * @rmtoll IER      AWD1IE         LL_ADC_EnableIT_AWD1
06257   * @param  ADCx ADC instance
06258   * @retval None
06259   */
06260 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
06261 {
06262   SET_BIT(ADCx->IER, ADC_IER_AWD1);
06263 }
06264 
06265 /**
06266   * @brief  Enable interruption ADC analog watchdog 2.
06267   * @rmtoll IER      AWD2IE         LL_ADC_EnableIT_AWD2
06268   * @param  ADCx ADC instance
06269   * @retval None
06270   */
06271 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
06272 {
06273   SET_BIT(ADCx->IER, ADC_IER_AWD2);
06274 }
06275 
06276 /**
06277   * @brief  Enable interruption ADC analog watchdog 3.
06278   * @rmtoll IER      AWD3IE         LL_ADC_EnableIT_AWD3
06279   * @param  ADCx ADC instance
06280   * @retval None
06281   */
06282 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
06283 {
06284   SET_BIT(ADCx->IER, ADC_IER_AWD3);
06285 }
06286 
06287 /**
06288   * @brief  Disable interruption ADC ready.
06289   * @rmtoll IER      ADRDYIE        LL_ADC_DisableIT_ADRDY
06290   * @param  ADCx ADC instance
06291   * @retval None
06292   */
06293 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
06294 {
06295   CLEAR_BIT(ADCx->IER, ADC_IER_ADRDY);
06296 }
06297 
06298 /**
06299   * @brief  Disable interruption ADC group regular end of unitary conversion.
06300   * @rmtoll IER      EOCIE          LL_ADC_DisableIT_EOC
06301   * @param  ADCx ADC instance
06302   * @retval None
06303   */
06304 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
06305 {
06306   CLEAR_BIT(ADCx->IER, ADC_IER_EOC);
06307 }
06308 
06309 /**
06310   * @brief  Disable interruption ADC group regular end of sequence conversions.
06311   * @rmtoll IER      EOSIE          LL_ADC_DisableIT_EOS
06312   * @param  ADCx ADC instance
06313   * @retval None
06314   */
06315 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
06316 {
06317   CLEAR_BIT(ADCx->IER, ADC_IER_EOS);
06318 }
06319 
06320 /**
06321   * @brief  Disable interruption ADC group regular overrun.
06322   * @rmtoll IER      OVRIE          LL_ADC_DisableIT_OVR
06323   * @param  ADCx ADC instance
06324   * @retval None
06325   */
06326 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
06327 {
06328   CLEAR_BIT(ADCx->IER, ADC_IER_OVR);
06329 }
06330 
06331 /**
06332   * @brief  Disable interruption ADC group regular end of sampling.
06333   * @rmtoll IER      EOSMPIE        LL_ADC_DisableIT_EOSMP
06334   * @param  ADCx ADC instance
06335   * @retval None
06336   */
06337 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
06338 {
06339   CLEAR_BIT(ADCx->IER, ADC_IER_EOSMP);
06340 }
06341 
06342 /**
06343   * @brief  Disable interruption ADC group regular end of unitary conversion.
06344   * @rmtoll IER      JEOCIE         LL_ADC_DisableIT_JEOC
06345   * @param  ADCx ADC instance
06346   * @retval None
06347   */
06348 __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
06349 {
06350   CLEAR_BIT(ADCx->IER, ADC_IER_JEOC);
06351 }
06352 
06353 /**
06354   * @brief  Disable interruption ADC group injected end of sequence conversions.
06355   * @rmtoll IER      JEOSIE         LL_ADC_DisableIT_JEOS
06356   * @param  ADCx ADC instance
06357   * @retval None
06358   */
06359 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
06360 {
06361   CLEAR_BIT(ADCx->IER, ADC_IER_JEOS);
06362 }
06363 
06364 /**
06365   * @brief  Disable interruption ADC group injected context queue overflow.
06366   * @rmtoll IER      JQOVFIE        LL_ADC_DisableIT_JQOVF
06367   * @param  ADCx ADC instance
06368   * @retval None
06369   */
06370 __STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
06371 {
06372   CLEAR_BIT(ADCx->IER, ADC_IER_JQOVF);
06373 }
06374 
06375 /**
06376   * @brief  Disable interruption ADC analog watchdog 1.
06377   * @rmtoll IER      AWD1IE         LL_ADC_DisableIT_AWD1
06378   * @param  ADCx ADC instance
06379   * @retval None
06380   */
06381 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
06382 {
06383   CLEAR_BIT(ADCx->IER, ADC_IER_AWD1);
06384 }
06385 
06386 /**
06387   * @brief  Disable interruption ADC analog watchdog 2.
06388   * @rmtoll IER      AWD2IE         LL_ADC_DisableIT_AWD2
06389   * @param  ADCx ADC instance
06390   * @retval None
06391   */
06392 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
06393 {
06394   CLEAR_BIT(ADCx->IER, ADC_IER_AWD2);
06395 }
06396 
06397 /**
06398   * @brief  Disable interruption ADC analog watchdog 3.
06399   * @rmtoll IER      AWD3IE         LL_ADC_DisableIT_AWD3
06400   * @param  ADCx ADC instance
06401   * @retval None
06402   */
06403 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
06404 {
06405   CLEAR_BIT(ADCx->IER, ADC_IER_AWD3);
06406 }
06407 
06408 /**
06409   * @brief  Get state of interruption ADC ready.
06410   *         (0: interrupt disabled, 1: interrupt enabled)
06411   * @rmtoll IER      ADRDYIE        LL_ADC_IsEnabledIT_ADRDY
06412   * @param  ADCx ADC instance
06413   * @retval State of bit (1 or 0).
06414   */
06415 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
06416 {
06417   return (READ_BIT(ADCx->IER, ADC_IER_ADRDY) == (ADC_IER_ADRDY));
06418 }
06419 
06420 /**
06421   * @brief  Get state of interruption ADC group regular end of unitary conversion.
06422   *         (0: interrupt disabled, 1: interrupt enabled)
06423   * @rmtoll IER      EOCIE          LL_ADC_IsEnabledIT_EOC
06424   * @param  ADCx ADC instance
06425   * @retval State of bit (1 or 0).
06426   */
06427 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
06428 {
06429   return (READ_BIT(ADCx->IER, ADC_IER_EOC) == (ADC_IER_EOC));
06430 }
06431 
06432 /**
06433   * @brief  Get state of interruption ADC group regular end of sequence conversions.
06434   *         (0: interrupt disabled, 1: interrupt enabled)
06435   * @rmtoll IER      EOSIE          LL_ADC_IsEnabledIT_EOS
06436   * @param  ADCx ADC instance
06437   * @retval State of bit (1 or 0).
06438   */
06439 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
06440 {
06441   return (READ_BIT(ADCx->IER, ADC_IER_EOS) == (ADC_IER_EOS));
06442 }
06443 
06444 /**
06445   * @brief  Get state of interruption ADC group regular overrun.
06446   *         (0: interrupt disabled, 1: interrupt enabled)
06447   * @rmtoll IER      OVRIE          LL_ADC_IsEnabledIT_OVR
06448   * @param  ADCx ADC instance
06449   * @retval State of bit (1 or 0).
06450   */
06451 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
06452 {
06453   return (READ_BIT(ADCx->IER, ADC_IER_OVR) == (ADC_IER_OVR));
06454 }
06455 
06456 /**
06457   * @brief  Get state of interruption ADC group regular end of sampling.
06458   *         (0: interrupt disabled, 1: interrupt enabled)
06459   * @rmtoll IER      EOSMPIE        LL_ADC_IsEnabledIT_EOSMP
06460   * @param  ADCx ADC instance
06461   * @retval State of bit (1 or 0).
06462   */
06463 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
06464 {
06465   return (READ_BIT(ADCx->IER, ADC_IER_EOSMP) == (ADC_IER_EOSMP));
06466 }
06467 
06468 /**
06469   * @brief  Get state of interruption ADC group injected end of unitary conversion.
06470   *         (0: interrupt disabled, 1: interrupt enabled)
06471   * @rmtoll IER      JEOCIE         LL_ADC_IsEnabledIT_JEOC
06472   * @param  ADCx ADC instance
06473   * @retval State of bit (1 or 0).
06474   */
06475 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)
06476 {
06477   return (READ_BIT(ADCx->IER, ADC_IER_JEOC) == (ADC_IER_JEOC));
06478 }
06479 
06480 /**
06481   * @brief  Get state of interruption ADC group injected end of sequence conversions.
06482   *         (0: interrupt disabled, 1: interrupt enabled)
06483   * @rmtoll IER      JEOSIE         LL_ADC_IsEnabledIT_JEOS
06484   * @param  ADCx ADC instance
06485   * @retval State of bit (1 or 0).
06486   */
06487 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
06488 {
06489   return (READ_BIT(ADCx->IER, ADC_IER_JEOS) == (ADC_IER_JEOS));
06490 }
06491 
06492 /**
06493   * @brief  Get state of interruption ADC group injected context queue overflow interrupt state
06494   *         (0: interrupt disabled, 1: interrupt enabled)
06495   * @rmtoll IER      JQOVFIE        LL_ADC_IsEnabledIT_JQOVF
06496   * @param  ADCx ADC instance
06497   * @retval State of bit (1 or 0).
06498   */
06499 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)
06500 {
06501   return (READ_BIT(ADCx->IER, ADC_IER_JQOVF) == (ADC_IER_JQOVF));
06502 }
06503 
06504 /**
06505   * @brief  Get state of interruption ADC analog watchdog 1.
06506   *         (0: interrupt disabled, 1: interrupt enabled)
06507   * @rmtoll IER      AWD1IE         LL_ADC_IsEnabledIT_AWD1
06508   * @param  ADCx ADC instance
06509   * @retval State of bit (1 or 0).
06510   */
06511 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
06512 {
06513   return (READ_BIT(ADCx->IER, ADC_IER_AWD1) == (ADC_IER_AWD1));
06514 }
06515 
06516 /**
06517   * @brief  Get state of interruption Get ADC analog watchdog 2.
06518   *         (0: interrupt disabled, 1: interrupt enabled)
06519   * @rmtoll IER      AWD2IE         LL_ADC_IsEnabledIT_AWD2
06520   * @param  ADCx ADC instance
06521   * @retval State of bit (1 or 0).
06522   */
06523 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
06524 {
06525   return (READ_BIT(ADCx->IER, ADC_IER_AWD2) == (ADC_IER_AWD2));
06526 }
06527 
06528 /**
06529   * @brief  Get state of interruption Get ADC analog watchdog 3.
06530   *         (0: interrupt disabled, 1: interrupt enabled)
06531   * @rmtoll IER      AWD3IE         LL_ADC_IsEnabledIT_AWD3
06532   * @param  ADCx ADC instance
06533   * @retval State of bit (1 or 0).
06534   */
06535 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
06536 {
06537   return (READ_BIT(ADCx->IER, ADC_IER_AWD3) == (ADC_IER_AWD3));
06538 }
06539 
06540 /**
06541   * @}
06542   */
06543 
06544 
06545 /**
06546   * @}
06547   */
06548 
06549 /**
06550   * @}
06551   */
06552 
06553 #endif /* ADC1 || ADC2 || ADC3 */
06554 
06555 /**
06556   * @}
06557   */
06558 
06559 #ifdef __cplusplus
06560 }
06561 #endif
06562 
06563 #endif /* __STM32L4xx_LL_ADC_H */
06564 
06565 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
06566