Eric Lewiston
Hal Drivers for L4
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stm32l4xx_hal_qspi.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_qspi.h 00004 * @author MCD Application Team 00005 * @version V1.1.0 00006 * @date 16-September-2015 00007 * @brief Header file of QSPI HAL module. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> 00012 * 00013 * Redistribution and use in source and binary forms, with or without modification, 00014 * are permitted provided that the following conditions are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright notice, 00018 * this list of conditions and the following disclaimer in the documentation 00019 * and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00021 * may be used to endorse or promote products derived from this software 00022 * without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00027 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00028 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00029 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00030 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00031 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00032 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00033 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 00038 /* Define to prevent recursive inclusion -------------------------------------*/ 00039 #ifndef __STM32L4xx_HAL_QSPI_H 00040 #define __STM32L4xx_HAL_QSPI_H 00041 00042 #ifdef __cplusplus 00043 extern "C" { 00044 #endif 00045 00046 /* Includes ------------------------------------------------------------------*/ 00047 #include "stm32l4xx_hal_def.h" 00048 00049 /** @addtogroup STM32L4xx_HAL_Driver 00050 * @{ 00051 */ 00052 00053 /** @addtogroup QSPI 00054 * @{ 00055 */ 00056 00057 /* Exported types ------------------------------------------------------------*/ 00058 /** @defgroup QSPI_Exported_Types QSPI Exported Types 00059 * @{ 00060 */ 00061 00062 /** 00063 * @brief QSPI Init structure definition 00064 */ 00065 typedef struct 00066 { 00067 uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock. 00068 This parameter can be a number between 0 and 255 */ 00069 uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode) 00070 This parameter can be a value between 1 and 16 */ 00071 uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to 00072 take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode) 00073 This parameter can be a value of @ref QSPI_SampleShifting */ 00074 uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits 00075 required to address the flash memory. The flash capacity can be up to 4GB 00076 (addressed using 32 bits) in indirect mode, but the addressable space in 00077 memory-mapped mode is limited to 256MB 00078 This parameter can be a number between 0 and 31 */ 00079 uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number 00080 of clock cycles which the chip select must remain high between commands. 00081 This parameter can be a value of @ref QSPI_ChipSelectHighTime */ 00082 uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands. 00083 This parameter can be a value of @ref QSPI_ClockMode */ 00084 }QSPI_InitTypeDef; 00085 00086 /** 00087 * @brief HAL QSPI State structures definition 00088 */ 00089 typedef enum 00090 { 00091 HAL_QSPI_STATE_RESET = 0x00, /*!< Peripheral not initialized */ 00092 HAL_QSPI_STATE_READY = 0x01, /*!< Peripheral initialized and ready for use */ 00093 HAL_QSPI_STATE_BUSY = 0x02, /*!< Peripheral in indirect mode and busy */ 00094 HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12, /*!< Peripheral in indirect mode with transmission ongoing */ 00095 HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22, /*!< Peripheral in indirect mode with reception ongoing */ 00096 HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42, /*!< Peripheral in auto polling mode ongoing */ 00097 HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82, /*!< Peripheral in memory mapped mode ongoing */ 00098 HAL_QSPI_STATE_ERROR = 0x04 /*!< Peripheral in error */ 00099 }HAL_QSPI_StateTypeDef; 00100 00101 /** 00102 * @brief QSPI Handle Structure definition 00103 */ 00104 typedef struct 00105 { 00106 QUADSPI_TypeDef *Instance; /* QSPI registers base address */ 00107 QSPI_InitTypeDef Init; /* QSPI communication parameters */ 00108 uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */ 00109 __IO uint16_t TxXferSize; /* QSPI Tx Transfer size */ 00110 __IO uint16_t TxXferCount; /* QSPI Tx Transfer Counter */ 00111 uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */ 00112 __IO uint16_t RxXferSize; /* QSPI Rx Transfer size */ 00113 __IO uint16_t RxXferCount; /* QSPI Rx Transfer Counter */ 00114 DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */ 00115 __IO HAL_LockTypeDef Lock; /* Locking object */ 00116 __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */ 00117 __IO uint32_t ErrorCode; /* QSPI Error code */ 00118 uint32_t Timeout; /* Timeout for the QSPI memory access */ 00119 }QSPI_HandleTypeDef; 00120 00121 /** 00122 * @brief QSPI Command structure definition 00123 */ 00124 typedef struct 00125 { 00126 uint32_t Instruction; /* Specifies the Instruction to be sent 00127 This parameter can be a value (8-bit) between 0x00 and 0xFF */ 00128 uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize) 00129 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ 00130 uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize) 00131 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ 00132 uint32_t AddressSize; /* Specifies the Address Size 00133 This parameter can be a value of @ref QSPI_AddressSize */ 00134 uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size 00135 This parameter can be a value of @ref QSPI_AlternateBytesSize */ 00136 uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles. 00137 This parameter can be a number between 0 and 31 */ 00138 uint32_t InstructionMode; /* Specifies the Instruction Mode 00139 This parameter can be a value of @ref QSPI_InstructionMode */ 00140 uint32_t AddressMode; /* Specifies the Address Mode 00141 This parameter can be a value of @ref QSPI_AddressMode */ 00142 uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode 00143 This parameter can be a value of @ref QSPI_AlternateBytesMode */ 00144 uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases) 00145 This parameter can be a value of @ref QSPI_DataMode */ 00146 uint32_t NbData; /* Specifies the number of data to transfer. 00147 This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length 00148 until end of memory)*/ 00149 uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase 00150 This parameter can be a value of @ref QSPI_DdrMode */ 00151 uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of 00152 system clock in DDR mode. Not available on STM32L4x6 devices but in future devices. 00153 This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */ 00154 uint32_t SIOOMode; /* Specifies the send instruction only once mode 00155 This parameter can be a value of @ref QSPI_SIOOMode */ 00156 }QSPI_CommandTypeDef; 00157 00158 /** 00159 * @brief QSPI Auto Polling mode configuration structure definition 00160 */ 00161 typedef struct 00162 { 00163 uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. 00164 This parameter can be any value between 0 and 0xFFFFFFFF */ 00165 uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. 00166 This parameter can be any value between 0 and 0xFFFFFFFF */ 00167 uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. 00168 This parameter can be any value between 0 and 0xFFFF */ 00169 uint32_t StatusBytesSize; /* Specifies the size of the status bytes received. 00170 This parameter can be any value between 1 and 4 */ 00171 uint32_t MatchMode; /* Specifies the method used for determining a match. 00172 This parameter can be a value of @ref QSPI_MatchMode */ 00173 uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match. 00174 This parameter can be a value of @ref QSPI_AutomaticStop */ 00175 }QSPI_AutoPollingTypeDef; 00176 00177 /** 00178 * @brief QSPI Memory Mapped mode configuration structure definition 00179 */ 00180 typedef struct 00181 { 00182 uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. 00183 This parameter can be any value between 0 and 0xFFFF */ 00184 uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. 00185 This parameter can be a value of @ref QSPI_TimeOutActivation */ 00186 }QSPI_MemoryMappedTypeDef; 00187 00188 /** 00189 * @} 00190 */ 00191 00192 /* Exported constants --------------------------------------------------------*/ 00193 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants 00194 * @{ 00195 */ 00196 00197 /** @defgroup QSPI_ErrorCode QSPI Error Code 00198 * @{ 00199 */ 00200 #define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ 00201 #define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */ 00202 #define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002) /*!< Transfer error */ 00203 #define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004) /*!< DMA transfer error */ 00204 /** 00205 * @} 00206 */ 00207 00208 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting 00209 * @{ 00210 */ 00211 #define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000) /*!<No clock cycle shift to sample data*/ 00212 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/ 00213 /** 00214 * @} 00215 */ 00216 00217 /** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time 00218 * @{ 00219 */ 00220 #define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000) /*!<nCS stay high for at least 1 clock cycle between commands*/ 00221 #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/ 00222 #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/ 00223 #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/ 00224 #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/ 00225 #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/ 00226 #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/ 00227 #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/ 00228 /** 00229 * @} 00230 */ 00231 00232 /** @defgroup QSPI_ClockMode QSPI Clock Mode 00233 * @{ 00234 */ 00235 #define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000) /*!<Clk stays low while nCS is released*/ 00236 #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/ 00237 /** 00238 * @} 00239 */ 00240 00241 /** @defgroup QSPI_AddressSize QSPI Address Size 00242 * @{ 00243 */ 00244 #define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000) /*!<8-bit address*/ 00245 #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/ 00246 #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/ 00247 #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/ 00248 /** 00249 * @} 00250 */ 00251 00252 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size 00253 * @{ 00254 */ 00255 #define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000) /*!<8-bit alternate bytes*/ 00256 #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/ 00257 #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/ 00258 #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/ 00259 /** 00260 * @} 00261 */ 00262 00263 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode 00264 * @{ 00265 */ 00266 #define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000) /*!<No instruction*/ 00267 #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/ 00268 #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/ 00269 #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/ 00270 /** 00271 * @} 00272 */ 00273 00274 /** @defgroup QSPI_AddressMode QSPI Address Mode 00275 * @{ 00276 */ 00277 #define QSPI_ADDRESS_NONE ((uint32_t)0x00000000) /*!<No address*/ 00278 #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/ 00279 #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/ 00280 #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/ 00281 /** 00282 * @} 00283 */ 00284 00285 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode 00286 * @{ 00287 */ 00288 #define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000) /*!<No alternate bytes*/ 00289 #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/ 00290 #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/ 00291 #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/ 00292 /** 00293 * @} 00294 */ 00295 00296 /** @defgroup QSPI_DataMode QSPI Data Mode 00297 * @{ 00298 */ 00299 #define QSPI_DATA_NONE ((uint32_t)0X00000000) /*!<No data*/ 00300 #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/ 00301 #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/ 00302 #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/ 00303 /** 00304 * @} 00305 */ 00306 00307 /** @defgroup QSPI_DdrMode QSPI DDR Mode 00308 * @{ 00309 */ 00310 #define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000) /*!<Double data rate mode disabled*/ 00311 #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/ 00312 /** 00313 * @} 00314 */ 00315 00316 /** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay 00317 * @{ 00318 */ 00319 #define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000) /*!<Delay the data output using analog delay in DDR mode*/ 00320 /** 00321 * @} 00322 */ 00323 00324 /** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode 00325 * @{ 00326 */ 00327 #define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000) /*!<Send instruction on every transaction*/ 00328 #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/ 00329 /** 00330 * @} 00331 */ 00332 00333 /** @defgroup QSPI_MatchMode QSPI Match Mode 00334 * @{ 00335 */ 00336 #define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000) /*!<AND match mode between unmasked bits*/ 00337 #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/ 00338 /** 00339 * @} 00340 */ 00341 00342 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop 00343 * @{ 00344 */ 00345 #define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000) /*!<AutoPolling stops only with abort or QSPI disabling*/ 00346 #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/ 00347 /** 00348 * @} 00349 */ 00350 00351 /** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation 00352 * @{ 00353 */ 00354 #define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000) /*!<Timeout counter disabled, nCS remains active*/ 00355 #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/ 00356 /** 00357 * @} 00358 */ 00359 00360 /** @defgroup QSPI_Flags QSPI Flags 00361 * @{ 00362 */ 00363 #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/ 00364 #define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/ 00365 #define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/ 00366 #define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/ 00367 #define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/ 00368 #define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/ 00369 /** 00370 * @} 00371 */ 00372 00373 /** @defgroup QSPI_Interrupts QSPI Interrupts 00374 * @{ 00375 */ 00376 #define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/ 00377 #define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/ 00378 #define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/ 00379 #define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/ 00380 #define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/ 00381 /** 00382 * @} 00383 */ 00384 00385 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition 00386 * @brief QSPI Timeout definition 00387 * @{ 00388 */ 00389 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */ 00390 /** 00391 * @} 00392 */ 00393 00394 /** 00395 * @} 00396 */ 00397 00398 /* Exported macros -----------------------------------------------------------*/ 00399 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros 00400 * @{ 00401 */ 00402 /** @brief Reset QSPI handle state. 00403 * @param __HANDLE__: QSPI handle. 00404 * @retval None 00405 */ 00406 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) 00407 00408 /** @brief Enable the QSPI peripheral. 00409 * @param __HANDLE__: specifies the QSPI Handle. 00410 * @retval None 00411 */ 00412 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) 00413 00414 /** @brief Disable the QSPI peripheral. 00415 * @param __HANDLE__: specifies the QSPI Handle. 00416 * @retval None 00417 */ 00418 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) 00419 00420 /** @brief Enable the specified QSPI interrupt. 00421 * @param __HANDLE__: specifies the QSPI Handle. 00422 * @param __INTERRUPT__: specifies the QSPI interrupt source to enable. 00423 * This parameter can be one of the following values: 00424 * @arg QSPI_IT_TO: QSPI Timeout interrupt 00425 * @arg QSPI_IT_SM: QSPI Status match interrupt 00426 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 00427 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 00428 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 00429 * @retval None 00430 */ 00431 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 00432 00433 00434 /** @brief Disable the specified QSPI interrupt. 00435 * @param __HANDLE__: specifies the QSPI Handle. 00436 * @param __INTERRUPT__: specifies the QSPI interrupt source to disable. 00437 * This parameter can be one of the following values: 00438 * @arg QSPI_IT_TO: QSPI Timeout interrupt 00439 * @arg QSPI_IT_SM: QSPI Status match interrupt 00440 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 00441 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 00442 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 00443 * @retval None 00444 */ 00445 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 00446 00447 /** @brief Check whether the specified QSPI interrupt source is enabled or not. 00448 * @param __HANDLE__: specifies the QSPI Handle. 00449 * @param __INTERRUPT__: specifies the QSPI interrupt source to check. 00450 * This parameter can be one of the following values: 00451 * @arg QSPI_IT_TO: QSPI Timeout interrupt 00452 * @arg QSPI_IT_SM: QSPI Status match interrupt 00453 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 00454 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 00455 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 00456 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 00457 */ 00458 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) 00459 00460 /** 00461 * @brief Check whether the selected QSPI flag is set or not. 00462 * @param __HANDLE__: specifies the QSPI Handle. 00463 * @param __FLAG__: specifies the QSPI flag to check. 00464 * This parameter can be one of the following values: 00465 * @arg QSPI_FLAG_BUSY: QSPI Busy flag 00466 * @arg QSPI_FLAG_TO: QSPI Timeout flag 00467 * @arg QSPI_FLAG_SM: QSPI Status match flag 00468 * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag 00469 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag 00470 * @arg QSPI_FLAG_TE: QSPI Transfer error flag 00471 * @retval None 00472 */ 00473 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0) 00474 00475 /** @brief Clears the specified QSPI's flag status. 00476 * @param __HANDLE__: specifies the QSPI Handle. 00477 * @param __FLAG__: specifies the QSPI clear register flag that needs to be set 00478 * This parameter can be one of the following values: 00479 * @arg QSPI_FLAG_TO: QSPI Timeout flag 00480 * @arg QSPI_FLAG_SM: QSPI Status match flag 00481 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag 00482 * @arg QSPI_FLAG_TE: QSPI Transfer error flag 00483 * @retval None 00484 */ 00485 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) 00486 /** 00487 * @} 00488 */ 00489 00490 /* Exported functions --------------------------------------------------------*/ 00491 /** @addtogroup QSPI_Exported_Functions 00492 * @{ 00493 */ 00494 /* Initialization/de-initialization functions ********************************/ 00495 HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi); 00496 HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi); 00497 void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi); 00498 void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi); 00499 00500 /* IO operation functions *****************************************************/ 00501 /* QSPI IRQ handler method */ 00502 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi); 00503 00504 /* QSPI indirect mode */ 00505 HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout); 00506 HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); 00507 HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); 00508 HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd); 00509 HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 00510 HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 00511 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 00512 HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 00513 00514 /* QSPI status flag polling mode */ 00515 HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); 00516 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg); 00517 00518 /* QSPI memory-mapped mode */ 00519 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg); 00520 00521 /* Callback functions in non-blocking modes ***********************************/ 00522 void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi); 00523 void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi); 00524 00525 /* QSPI indirect mode */ 00526 void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi); 00527 void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi); 00528 void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi); 00529 void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); 00530 void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); 00531 00532 /* QSPI status flag polling mode */ 00533 void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi); 00534 00535 /* QSPI memory-mapped mode */ 00536 void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi); 00537 00538 /* Peripheral Control and State functions ************************************/ 00539 HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi); 00540 uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi); 00541 HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi); 00542 void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout); 00543 /** 00544 * @} 00545 */ 00546 /* End of exported functions -------------------------------------------------*/ 00547 00548 /* Private macros ------------------------------------------------------------*/ 00549 /** @defgroup QSPI_Private_Macros QSPI Private Macros 00550 * @{ 00551 */ 00552 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF) 00553 00554 #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 16)) 00555 00556 #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \ 00557 ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) 00558 00559 #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31)) 00560 00561 #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \ 00562 ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \ 00563 ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \ 00564 ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \ 00565 ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \ 00566 ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \ 00567 ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \ 00568 ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE)) 00569 00570 #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ 00571 ((CLKMODE) == QSPI_CLOCK_MODE_3)) 00572 00573 #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF) 00574 00575 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \ 00576 ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \ 00577 ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \ 00578 ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS)) 00579 00580 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \ 00581 ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \ 00582 ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \ 00583 ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) 00584 00585 #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31) 00586 00587 #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ 00588 ((MODE) == QSPI_INSTRUCTION_1_LINE) || \ 00589 ((MODE) == QSPI_INSTRUCTION_2_LINES) || \ 00590 ((MODE) == QSPI_INSTRUCTION_4_LINES)) 00591 00592 #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \ 00593 ((MODE) == QSPI_ADDRESS_1_LINE) || \ 00594 ((MODE) == QSPI_ADDRESS_2_LINES) || \ 00595 ((MODE) == QSPI_ADDRESS_4_LINES)) 00596 00597 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \ 00598 ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \ 00599 ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \ 00600 ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES)) 00601 00602 #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \ 00603 ((MODE) == QSPI_DATA_1_LINE) || \ 00604 ((MODE) == QSPI_DATA_2_LINES) || \ 00605 ((MODE) == QSPI_DATA_4_LINES)) 00606 00607 #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ 00608 ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) 00609 00610 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY)) 00611 00612 #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \ 00613 ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) 00614 00615 #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) 00616 00617 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4)) 00618 00619 #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ 00620 ((MODE) == QSPI_MATCH_MODE_OR)) 00621 00622 #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \ 00623 ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) 00624 00625 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \ 00626 ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) 00627 00628 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF) 00629 /** 00630 * @} 00631 */ 00632 /* End of private macros -----------------------------------------------------*/ 00633 00634 /** 00635 * @} 00636 */ 00637 00638 /** 00639 * @} 00640 */ 00641 00642 #ifdef __cplusplus 00643 } 00644 #endif 00645 00646 #endif /* __STM32L4xx_HAL_QSPI_H */ 00647 00648 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 00649
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