Hal Drivers for L4
Dependents: BSP OneHopeOnePrayer FINAL_AUDIO_RECORD AudioDemo
Fork of STM32L4xx_HAL_Driver by
stm32l4xx_hal_pwr_ex.c
00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_pwr_ex.c 00004 * @author MCD Application Team 00005 * @version V1.1.0 00006 * @date 16-September-2015 00007 * @brief Extended PWR HAL module driver. 00008 * This file provides firmware functions to manage the following 00009 * functionalities of the Power Controller (PWR) peripheral: 00010 * + Extended Initialization and de-initialization functions 00011 * + Extended Peripheral Control functions 00012 * 00013 ****************************************************************************** 00014 * @attention 00015 * 00016 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> 00017 * 00018 * Redistribution and use in source and binary forms, with or without modification, 00019 * are permitted provided that the following conditions are met: 00020 * 1. Redistributions of source code must retain the above copyright notice, 00021 * this list of conditions and the following disclaimer. 00022 * 2. Redistributions in binary form must reproduce the above copyright notice, 00023 * this list of conditions and the following disclaimer in the documentation 00024 * and/or other materials provided with the distribution. 00025 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00026 * may be used to endorse or promote products derived from this software 00027 * without specific prior written permission. 00028 * 00029 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00030 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00031 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00032 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00033 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00034 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00035 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00036 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00037 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00038 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00039 * 00040 ****************************************************************************** 00041 */ 00042 00043 /* Includes ------------------------------------------------------------------*/ 00044 #include "stm32l4xx_hal.h" 00045 00046 /** @addtogroup STM32L4xx_HAL_Driver 00047 * @{ 00048 */ 00049 00050 /** @defgroup PWREx PWREx 00051 * @brief PWR Extended HAL module driver 00052 * @{ 00053 */ 00054 00055 #ifdef HAL_PWR_MODULE_ENABLED 00056 00057 /* Private typedef -----------------------------------------------------------*/ 00058 /* Private define ------------------------------------------------------------*/ 00059 #define PWR_PORTH_AVAILABLE_PINS (PWR_GPIO_BIT_0|PWR_GPIO_BIT_1) 00060 00061 00062 /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines 00063 * @{ 00064 */ 00065 00066 /** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask 00067 * @{ 00068 */ 00069 #define PVM_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVM threshold crossing */ 00070 #define PVM_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVM threshold crossing */ 00071 #define PVM_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVM trigger */ 00072 #define PVM_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVM trigger */ 00073 /** 00074 * @} 00075 */ 00076 00077 /** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value 00078 * @{ 00079 */ 00080 #define PWR_FLAG_SETTING_DELAY_US 50 /*!< Time out value for REGLPF and VOSF flags setting */ 00081 /** 00082 * @} 00083 */ 00084 00085 00086 00087 /** 00088 * @} 00089 */ 00090 00091 00092 00093 /* Private macro -------------------------------------------------------------*/ 00094 /* Private variables ---------------------------------------------------------*/ 00095 /* Private function prototypes -----------------------------------------------*/ 00096 /* Exported functions --------------------------------------------------------*/ 00097 00098 /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions 00099 * @{ 00100 */ 00101 00102 /** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions 00103 * @brief Extended Peripheral Control functions 00104 * 00105 @verbatim 00106 =============================================================================== 00107 ##### Extended Peripheral Initialization and de-initialization functions ##### 00108 =============================================================================== 00109 [..] 00110 00111 @endverbatim 00112 * @{ 00113 */ 00114 00115 00116 /** 00117 * @brief Return Voltage Scaling Range. 00118 * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2) 00119 */ 00120 uint32_t HAL_PWREx_GetVoltageRange(void) 00121 { 00122 return (PWR->CR1 & PWR_CR1_VOS); 00123 } 00124 00125 00126 00127 /** 00128 * @brief Configure the main internal regulator output voltage. 00129 * @param VoltageScaling: specifies the regulator output voltage to achieve 00130 * a tradeoff between performance and power consumption. 00131 * This parameter can be one of the following values: 00132 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, 00133 * typical output voltage at 1.2 V, 00134 * system frequency up to 80 MHz. 00135 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode, 00136 * typical output voltage at 1.0 V, 00137 * system frequency up to 26 MHz. 00138 * @note When moving from Range 1 to Range 2, the system frequency must be decreased to 00139 * a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API. 00140 * When moving from Range 2 to Range 1, the system frequency can be increased to 00141 * a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API. 00142 * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be 00143 * cleared before returning the status. If the flag is not cleared within 00144 * 50 microseconds, HAL_TIMEOUT status is reported. 00145 * @retval HAL Status 00146 */ 00147 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) 00148 { 00149 uint32_t wait_loop_index = 0; 00150 00151 assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); 00152 00153 /* If Set Range 1 */ 00154 if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) 00155 { 00156 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1) 00157 { 00158 /* Set Range 1 */ 00159 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); 00160 00161 /* Wait until VOSF is cleared */ 00162 wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); 00163 while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) 00164 { 00165 wait_loop_index--; 00166 } 00167 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) 00168 { 00169 return HAL_TIMEOUT; 00170 } 00171 } 00172 } 00173 else 00174 { 00175 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2) 00176 { 00177 /* Set Range 2 */ 00178 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2); 00179 /* No need to wait for VOSF to be cleared for this transition */ 00180 } 00181 } 00182 00183 return HAL_OK; 00184 } 00185 00186 00187 /** 00188 * @brief Enable battery charging. 00189 * When VDD is present, charge the external battery on VBAT thru an internal resistor. 00190 * @param ResistorSelection: specifies the resistor impedance. 00191 * This parameter can be one of the following values: 00192 * @arg PWR_BATTERY_CHARGING_RESISTOR_5: 5 kOhms resistor 00193 * @arg PWR_BATTERY_CHARGING_RESISTOR_1_5: 1.5 kOhms resistor 00194 * @retval None 00195 */ 00196 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection) 00197 { 00198 assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection)); 00199 00200 /* Specify resistor selection */ 00201 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection); 00202 00203 /* Enable battery charging */ 00204 SET_BIT(PWR->CR4, PWR_CR4_VBE); 00205 } 00206 00207 00208 /** 00209 * @brief Disable battery charging. 00210 * @retval None 00211 */ 00212 void HAL_PWREx_DisableBatteryCharging(void) 00213 { 00214 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); 00215 } 00216 00217 00218 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00219 /** 00220 * @brief Enable VDDUSB supply. 00221 * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present. 00222 * @retval None 00223 */ 00224 void HAL_PWREx_EnableVddUSB(void) 00225 { 00226 SET_BIT(PWR->CR2, PWR_CR2_USV); 00227 } 00228 00229 00230 /** 00231 * @brief Disable VDDUSB supply. 00232 * @retval None 00233 */ 00234 void HAL_PWREx_DisableVddUSB(void) 00235 { 00236 CLEAR_BIT(PWR->CR2, PWR_CR2_USV); 00237 } 00238 #endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 00239 00240 /** 00241 * @brief Enable VDDIO2 supply. 00242 * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present. 00243 * @retval None 00244 */ 00245 void HAL_PWREx_EnableVddIO2(void) 00246 { 00247 SET_BIT(PWR->CR2, PWR_CR2_IOSV); 00248 } 00249 00250 00251 /** 00252 * @brief Disable VDDIO2 supply. 00253 * @retval None 00254 */ 00255 void HAL_PWREx_DisableVddIO2(void) 00256 { 00257 CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV); 00258 } 00259 00260 00261 /** 00262 * @brief Enable Internal Wake-up Line. 00263 * @retval None 00264 */ 00265 void HAL_PWREx_EnableInternalWakeUpLine(void) 00266 { 00267 SET_BIT(PWR->CR3, PWR_CR3_EIWF); 00268 } 00269 00270 00271 /** 00272 * @brief Disable Internal Wake-up Line. 00273 * @retval None 00274 */ 00275 void HAL_PWREx_DisableInternalWakeUpLine(void) 00276 { 00277 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF); 00278 } 00279 00280 00281 00282 /** 00283 * @brief Enable GPIO pull-up state in Standby and Shutdown modes. 00284 * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in 00285 * pull-up state in Standby and Shutdown modes. 00286 * @note This state is effective in Standby and Shutdown modes only if APC bit 00287 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. 00288 * @note The configuration is lost when exiting the Shutdown mode due to the 00289 * power-on reset, maintained when exiting the Standby mode. 00290 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding 00291 * PDy bit of PWR_PDCRx register is cleared unless it is reserved. 00292 * @note Even if a PUy bit to set is reserved, the other PUy bits entered as input 00293 * parameter at the same time are set. 00294 * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H 00295 * to select the GPIO peripheral. 00296 * @param GPIONumber: Specify the I/O pins numbers. 00297 * This parameter can be one of the following values: 00298 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less 00299 * I/O pins are available) or the logical OR of several of them to set 00300 * several bits for a given port in a single API call. 00301 * @retval HAL Status 00302 */ 00303 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) 00304 { 00305 assert_param(IS_PWR_GPIO(GPIO)); 00306 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); 00307 00308 switch (GPIO) 00309 { 00310 case PWR_GPIO_A: 00311 SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14)))); 00312 CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15)))); 00313 break; 00314 case PWR_GPIO_B: 00315 SET_BIT(PWR->PUCRB, GPIONumber); 00316 CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4)))); 00317 break; 00318 case PWR_GPIO_C: 00319 SET_BIT(PWR->PUCRC, GPIONumber); 00320 CLEAR_BIT(PWR->PDCRC, GPIONumber); 00321 break; 00322 case PWR_GPIO_D: 00323 SET_BIT(PWR->PUCRD, GPIONumber); 00324 CLEAR_BIT(PWR->PDCRD, GPIONumber); 00325 break; 00326 case PWR_GPIO_E: 00327 SET_BIT(PWR->PUCRE, GPIONumber); 00328 CLEAR_BIT(PWR->PDCRE, GPIONumber); 00329 break; 00330 case PWR_GPIO_F: 00331 SET_BIT(PWR->PUCRF, GPIONumber); 00332 CLEAR_BIT(PWR->PDCRF, GPIONumber); 00333 break; 00334 case PWR_GPIO_G: 00335 SET_BIT(PWR->PUCRG, GPIONumber); 00336 CLEAR_BIT(PWR->PDCRG, GPIONumber); 00337 break; 00338 case PWR_GPIO_H: 00339 SET_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); 00340 CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); 00341 break; 00342 default: 00343 return HAL_ERROR; 00344 } 00345 00346 return HAL_OK; 00347 } 00348 00349 00350 /** 00351 * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes. 00352 * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O 00353 * in pull-up state in Standby and Shutdown modes. 00354 * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input 00355 * parameter at the same time are reset. 00356 * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H 00357 * to select the GPIO peripheral. 00358 * @param GPIONumber: Specify the I/O pins numbers. 00359 * This parameter can be one of the following values: 00360 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less 00361 * I/O pins are available) or the logical OR of several of them to reset 00362 * several bits for a given port in a single API call. 00363 * @retval HAL Status 00364 */ 00365 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) 00366 { 00367 assert_param(IS_PWR_GPIO(GPIO)); 00368 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); 00369 00370 switch (GPIO) 00371 { 00372 case PWR_GPIO_A: 00373 CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14)))); 00374 break; 00375 case PWR_GPIO_B: 00376 CLEAR_BIT(PWR->PUCRB, GPIONumber); 00377 break; 00378 case PWR_GPIO_C: 00379 CLEAR_BIT(PWR->PUCRC, GPIONumber); 00380 break; 00381 case PWR_GPIO_D: 00382 CLEAR_BIT(PWR->PUCRD, GPIONumber); 00383 break; 00384 case PWR_GPIO_E: 00385 CLEAR_BIT(PWR->PUCRE, GPIONumber); 00386 break; 00387 case PWR_GPIO_F: 00388 CLEAR_BIT(PWR->PUCRF, GPIONumber); 00389 break; 00390 case PWR_GPIO_G: 00391 CLEAR_BIT(PWR->PUCRG, GPIONumber); 00392 break; 00393 case PWR_GPIO_H: 00394 CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); 00395 break; 00396 default: 00397 return HAL_ERROR; 00398 } 00399 00400 return HAL_OK; 00401 } 00402 00403 00404 00405 /** 00406 * @brief Enable GPIO pull-down state in Standby and Shutdown modes. 00407 * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in 00408 * pull-down state in Standby and Shutdown modes. 00409 * @note This state is effective in Standby and Shutdown modes only if APC bit 00410 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. 00411 * @note The configuration is lost when exiting the Shutdown mode due to the 00412 * power-on reset, maintained when exiting the Standby mode. 00413 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding 00414 * PUy bit of PWR_PUCRx register is cleared unless it is reserved. 00415 * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input 00416 * parameter at the same time are set. 00417 * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H 00418 * to select the GPIO peripheral. 00419 * @param GPIONumber: Specify the I/O pins numbers. 00420 * This parameter can be one of the following values: 00421 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less 00422 * I/O pins are available) or the logical OR of several of them to set 00423 * several bits for a given port in a single API call. 00424 * @retval HAL Status 00425 */ 00426 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) 00427 { 00428 assert_param(IS_PWR_GPIO(GPIO)); 00429 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); 00430 00431 switch (GPIO) 00432 { 00433 case PWR_GPIO_A: 00434 SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15)))); 00435 CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14)))); 00436 break; 00437 case PWR_GPIO_B: 00438 SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4)))); 00439 CLEAR_BIT(PWR->PUCRB, GPIONumber); 00440 break; 00441 case PWR_GPIO_C: 00442 SET_BIT(PWR->PDCRC, GPIONumber); 00443 CLEAR_BIT(PWR->PUCRC, GPIONumber); 00444 break; 00445 case PWR_GPIO_D: 00446 SET_BIT(PWR->PDCRD, GPIONumber); 00447 CLEAR_BIT(PWR->PUCRD, GPIONumber); 00448 break; 00449 case PWR_GPIO_E: 00450 SET_BIT(PWR->PDCRE, GPIONumber); 00451 CLEAR_BIT(PWR->PUCRE, GPIONumber); 00452 break; 00453 case PWR_GPIO_F: 00454 SET_BIT(PWR->PDCRF, GPIONumber); 00455 CLEAR_BIT(PWR->PUCRF, GPIONumber); 00456 break; 00457 case PWR_GPIO_G: 00458 SET_BIT(PWR->PDCRG, GPIONumber); 00459 CLEAR_BIT(PWR->PUCRG, GPIONumber); 00460 break; 00461 case PWR_GPIO_H: 00462 SET_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); 00463 CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); 00464 break; 00465 default: 00466 return HAL_ERROR; 00467 } 00468 00469 return HAL_OK; 00470 } 00471 00472 00473 /** 00474 * @brief Disable GPIO pull-down state in Standby and Shutdown modes. 00475 * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O 00476 * in pull-down state in Standby and Shutdown modes. 00477 * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input 00478 * parameter at the same time are reset. 00479 * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H 00480 * to select the GPIO peripheral. 00481 * @param GPIONumber: Specify the I/O pins numbers. 00482 * This parameter can be one of the following values: 00483 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less 00484 * I/O pins are available) or the logical OR of several of them to reset 00485 * several bits for a given port in a single API call. 00486 * @retval HAL Status 00487 */ 00488 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) 00489 { 00490 assert_param(IS_PWR_GPIO(GPIO)); 00491 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); 00492 00493 switch (GPIO) 00494 { 00495 case PWR_GPIO_A: 00496 CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15)))); 00497 break; 00498 case PWR_GPIO_B: 00499 CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4)))); 00500 break; 00501 case PWR_GPIO_C: 00502 CLEAR_BIT(PWR->PDCRC, GPIONumber); 00503 break; 00504 case PWR_GPIO_D: 00505 CLEAR_BIT(PWR->PDCRD, GPIONumber); 00506 break; 00507 case PWR_GPIO_E: 00508 CLEAR_BIT(PWR->PDCRE, GPIONumber); 00509 break; 00510 case PWR_GPIO_F: 00511 CLEAR_BIT(PWR->PDCRF, GPIONumber); 00512 break; 00513 case PWR_GPIO_G: 00514 CLEAR_BIT(PWR->PDCRG, GPIONumber); 00515 break; 00516 case PWR_GPIO_H: 00517 CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); 00518 break; 00519 default: 00520 return HAL_ERROR; 00521 } 00522 00523 return HAL_OK; 00524 } 00525 00526 00527 00528 /** 00529 * @brief Enable pull-up and pull-down configuration. 00530 * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in 00531 * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes. 00532 * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding 00533 * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher). 00534 * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there 00535 * is no conflict when setting PUy or PDy bit. 00536 * @retval None 00537 */ 00538 void HAL_PWREx_EnablePullUpPullDownConfig(void) 00539 { 00540 SET_BIT(PWR->CR3, PWR_CR3_APC); 00541 } 00542 00543 00544 /** 00545 * @brief Disable pull-up and pull-down configuration. 00546 * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in 00547 * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes. 00548 * @retval None 00549 */ 00550 void HAL_PWREx_DisablePullUpPullDownConfig(void) 00551 { 00552 CLEAR_BIT(PWR->CR3, PWR_CR3_APC); 00553 } 00554 00555 00556 00557 /** 00558 * @brief Enable SRAM2 content retention in Standby mode. 00559 * @note When RRS bit is set, SRAM2 is powered by the low-power regulator in 00560 * Standby mode and its content is kept. 00561 * @retval None 00562 */ 00563 void HAL_PWREx_EnableSRAM2ContentRetention(void) 00564 { 00565 SET_BIT(PWR->CR3, PWR_CR3_RRS); 00566 } 00567 00568 00569 /** 00570 * @brief Disable SRAM2 content retention in Standby mode. 00571 * @note When RRS bit is reset, SRAM2 is powered off in Standby mode 00572 * and its content is lost. 00573 * @retval None 00574 */ 00575 void HAL_PWREx_DisableSRAM2ContentRetention(void) 00576 { 00577 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); 00578 } 00579 00580 00581 00582 00583 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00584 /** 00585 * @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V. 00586 * @retval None 00587 */ 00588 void HAL_PWREx_EnablePVM1(void) 00589 { 00590 SET_BIT(PWR->CR2, PWR_PVM_1); 00591 } 00592 00593 /** 00594 * @brief Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V. 00595 * @retval None 00596 */ 00597 void HAL_PWREx_DisablePVM1(void) 00598 { 00599 CLEAR_BIT(PWR->CR2, PWR_PVM_1); 00600 } 00601 #endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 00602 00603 /** 00604 * @brief Enable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V. 00605 * @retval None 00606 */ 00607 void HAL_PWREx_EnablePVM2(void) 00608 { 00609 SET_BIT(PWR->CR2, PWR_PVM_2); 00610 } 00611 00612 /** 00613 * @brief Disable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V. 00614 * @retval None 00615 */ 00616 void HAL_PWREx_DisablePVM2(void) 00617 { 00618 CLEAR_BIT(PWR->CR2, PWR_PVM_2); 00619 } 00620 00621 00622 /** 00623 * @brief Enable the Power Voltage Monitoring 3: VDDA versus 1.62V. 00624 * @retval None 00625 */ 00626 void HAL_PWREx_EnablePVM3(void) 00627 { 00628 SET_BIT(PWR->CR2, PWR_PVM_3); 00629 } 00630 00631 /** 00632 * @brief Disable the Power Voltage Monitoring 3: VDDA versus 1.62V. 00633 * @retval None 00634 */ 00635 void HAL_PWREx_DisablePVM3(void) 00636 { 00637 CLEAR_BIT(PWR->CR2, PWR_PVM_3); 00638 } 00639 00640 00641 /** 00642 * @brief Enable the Power Voltage Monitoring 4: VDDA versus 2.2V. 00643 * @retval None 00644 */ 00645 void HAL_PWREx_EnablePVM4(void) 00646 { 00647 SET_BIT(PWR->CR2, PWR_PVM_4); 00648 } 00649 00650 /** 00651 * @brief Disable the Power Voltage Monitoring 4: VDDA versus 2.2V. 00652 * @retval None 00653 */ 00654 void HAL_PWREx_DisablePVM4(void) 00655 { 00656 CLEAR_BIT(PWR->CR2, PWR_PVM_4); 00657 } 00658 00659 00660 00661 00662 /** 00663 * @brief Configure the Peripheral Voltage Monitoring (PVM). 00664 * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the 00665 * PVM configuration information. 00666 * @note The API configures a single PVM according to the information contained 00667 * in the input structure. To configure several PVMs, the API must be singly 00668 * called for each PVM used. 00669 * @note Refer to the electrical characteristics of your device datasheet for 00670 * more details about the voltage thresholds corresponding to each 00671 * detection level and to each monitored supply. 00672 * @retval HAL status 00673 */ 00674 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) 00675 { 00676 /* Check the parameters */ 00677 assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType)); 00678 assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode)); 00679 00680 00681 /* Configure EXTI 35 to 38 interrupts if so required: 00682 scan thru PVMType to detect which PVMx is set and 00683 configure the corresponding EXTI line accordingly. */ 00684 switch (sConfigPVM->PVMType) 00685 { 00686 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00687 case PWR_PVM_1: 00688 /* Clear any previous config. Keep it clear if no event or IT mode is selected */ 00689 __HAL_PWR_PVM1_EXTI_DISABLE_EVENT(); 00690 __HAL_PWR_PVM1_EXTI_DISABLE_IT(); 00691 __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); 00692 __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); 00693 00694 /* Configure interrupt mode */ 00695 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) 00696 { 00697 __HAL_PWR_PVM1_EXTI_ENABLE_IT(); 00698 } 00699 00700 /* Configure event mode */ 00701 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) 00702 { 00703 __HAL_PWR_PVM1_EXTI_ENABLE_EVENT(); 00704 } 00705 00706 /* Configure the edge */ 00707 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) 00708 { 00709 __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); 00710 } 00711 00712 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) 00713 { 00714 __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); 00715 } 00716 break; 00717 #endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 00718 00719 case PWR_PVM_2: 00720 /* Clear any previous config. Keep it clear if no event or IT mode is selected */ 00721 __HAL_PWR_PVM2_EXTI_DISABLE_EVENT(); 00722 __HAL_PWR_PVM2_EXTI_DISABLE_IT(); 00723 __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); 00724 __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); 00725 00726 /* Configure interrupt mode */ 00727 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) 00728 { 00729 __HAL_PWR_PVM2_EXTI_ENABLE_IT(); 00730 } 00731 00732 /* Configure event mode */ 00733 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) 00734 { 00735 __HAL_PWR_PVM2_EXTI_ENABLE_EVENT(); 00736 } 00737 00738 /* Configure the edge */ 00739 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) 00740 { 00741 __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); 00742 } 00743 00744 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) 00745 { 00746 __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); 00747 } 00748 break; 00749 00750 case PWR_PVM_3: 00751 /* Clear any previous config. Keep it clear if no event or IT mode is selected */ 00752 __HAL_PWR_PVM3_EXTI_DISABLE_EVENT(); 00753 __HAL_PWR_PVM3_EXTI_DISABLE_IT(); 00754 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); 00755 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); 00756 00757 /* Configure interrupt mode */ 00758 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) 00759 { 00760 __HAL_PWR_PVM3_EXTI_ENABLE_IT(); 00761 } 00762 00763 /* Configure event mode */ 00764 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) 00765 { 00766 __HAL_PWR_PVM3_EXTI_ENABLE_EVENT(); 00767 } 00768 00769 /* Configure the edge */ 00770 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) 00771 { 00772 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); 00773 } 00774 00775 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) 00776 { 00777 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); 00778 } 00779 break; 00780 00781 case PWR_PVM_4: 00782 /* Clear any previous config. Keep it clear if no event or IT mode is selected */ 00783 __HAL_PWR_PVM4_EXTI_DISABLE_EVENT(); 00784 __HAL_PWR_PVM4_EXTI_DISABLE_IT(); 00785 __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); 00786 __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); 00787 00788 /* Configure interrupt mode */ 00789 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) 00790 { 00791 __HAL_PWR_PVM4_EXTI_ENABLE_IT(); 00792 } 00793 00794 /* Configure event mode */ 00795 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) 00796 { 00797 __HAL_PWR_PVM4_EXTI_ENABLE_EVENT(); 00798 } 00799 00800 /* Configure the edge */ 00801 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) 00802 { 00803 __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); 00804 } 00805 00806 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) 00807 { 00808 __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); 00809 } 00810 break; 00811 00812 default: 00813 return HAL_ERROR; 00814 00815 } 00816 00817 00818 return HAL_OK; 00819 } 00820 00821 00822 00823 /** 00824 * @brief Enter Low-power Run mode 00825 * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode. 00826 * @note When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the 00827 * Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register. 00828 * Additionally, the clock frequency must be reduced below 2 MHz. 00829 * Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must 00830 * be done before calling HAL_PWREx_EnableLowPowerRunMode() API. 00831 * @retval None 00832 */ 00833 void HAL_PWREx_EnableLowPowerRunMode(void) 00834 { 00835 /* Set Regulator parameter */ 00836 SET_BIT(PWR->CR1, PWR_CR1_LPR); 00837 } 00838 00839 00840 /** 00841 * @brief Exit Low-power Run mode. 00842 * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that 00843 * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode 00844 * returns HAL_TIMEOUT status). The system clock frequency can then be 00845 * increased above 2 MHz. 00846 * @retval HAL Status 00847 */ 00848 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) 00849 { 00850 uint32_t wait_loop_index = 0; 00851 00852 /* Clear LPR bit */ 00853 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); 00854 00855 /* Wait until REGLPF is reset */ 00856 wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); 00857 while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))) 00858 { 00859 wait_loop_index--; 00860 } 00861 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) 00862 { 00863 return HAL_TIMEOUT; 00864 } 00865 00866 return HAL_OK; 00867 } 00868 00869 00870 /** 00871 * @brief Enter Stop 1 mode. 00872 * @note In Stop 1 mode, all I/O pins keep the same state as in Run mode. 00873 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, 00874 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability 00875 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI 00876 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated 00877 * only to the peripheral requesting it. 00878 * SRAM1, SRAM2 and register contents are preserved. 00879 * The BOR is available. 00880 * The voltage regulator can be configured either in normal or low-power mode. 00881 * @note When exiting Stop 1 mode by issuing an interrupt or a wakeup event, 00882 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register 00883 * is set; the MSI oscillator is selected if STOPWUCK is cleared. 00884 * @note When the voltage regulator operates in low power mode, an additional 00885 * startup delay is incurred when waking up from Stop 1 mode. 00886 * By keeping the internal regulator ON during Stop 1 mode, the consumption 00887 * is higher although the startup time is reduced. 00888 * @param Regulator: Specifies the regulator state in Stop 1 mode. 00889 * This parameter can be one of the following values: 00890 * @arg PWR_MAINREGULATOR_ON: Stop 1 mode with regulator ON 00891 * @arg PWR_LOWPOWERREGULATOR_ON: Stop 1 mode with low power regulator ON 00892 * This parameter has no effect when entering stop mode 2. 00893 * @param STOPEntry: specifies if Stop mode in entered with WFI or WFE instruction. 00894 * This parameter can be one of the following values: 00895 * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction 00896 * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction 00897 * @retval None 00898 */ 00899 void HAL_PWREx_EnterSTOP1Mode(uint32_t Regulator, uint8_t STOPEntry) 00900 { 00901 /* Check the parameters */ 00902 assert_param(IS_PWR_REGULATOR(Regulator)); 00903 assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); 00904 00905 if (Regulator == PWR_MAINREGULATOR_ON) 00906 { 00907 /* Stop 1 mode with Main Regulator */ 00908 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1MR); 00909 } 00910 else 00911 { 00912 /* Stop 1 mode with Low-Power Regulator */ 00913 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1LPR); 00914 } 00915 00916 /* Set SLEEPDEEP bit of Cortex System Control Register */ 00917 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 00918 00919 /* Select Stop mode entry --------------------------------------------------*/ 00920 if(STOPEntry == PWR_STOPENTRY_WFI) 00921 { 00922 /* Request Wait For Interrupt */ 00923 __WFI(); 00924 } 00925 else 00926 { 00927 /* Request Wait For Event */ 00928 __SEV(); 00929 __WFE(); 00930 __WFE(); 00931 } 00932 00933 /* Reset SLEEPDEEP bit of Cortex System Control Register */ 00934 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 00935 } 00936 00937 00938 /** 00939 * @brief Enter Stop 2 mode. 00940 * @note In Stop 2 mode, all I/O pins keep the same state as in Run mode. 00941 * @note All clocks in the VCORE domain are stopped, the PLL, the MSI, 00942 * the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability 00943 * (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after 00944 * receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only 00945 * to the peripheral requesting it. 00946 * SRAM1, SRAM2 and register contents are preserved. 00947 * The BOR is available. 00948 * The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode. 00949 * Otherwise, Stop 1 mode is entered. 00950 * @note When exiting Stop 2 mode by issuing an interrupt or a wakeup event, 00951 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register 00952 * is set; the MSI oscillator is selected if STOPWUCK is cleared. 00953 * @param STOPEntry: specifies if Stop mode in entered with WFI or WFE instruction. 00954 * This parameter can be one of the following values: 00955 * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction 00956 * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction 00957 * @retval None 00958 */ 00959 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry) 00960 { 00961 /* Check the parameter */ 00962 assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); 00963 00964 /* Set Stop mode 2 */ 00965 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP2); 00966 00967 00968 /* Set SLEEPDEEP bit of Cortex System Control Register */ 00969 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 00970 00971 /* Select Stop mode entry --------------------------------------------------*/ 00972 if(STOPEntry == PWR_STOPENTRY_WFI) 00973 { 00974 /* Request Wait For Interrupt */ 00975 __WFI(); 00976 } 00977 else 00978 { 00979 /* Request Wait For Event */ 00980 __SEV(); 00981 __WFE(); 00982 __WFE(); 00983 } 00984 00985 /* Reset SLEEPDEEP bit of Cortex System Control Register */ 00986 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 00987 } 00988 00989 00990 00991 00992 00993 /** 00994 * @brief Enter Shutdown mode. 00995 * @note In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched 00996 * off. The voltage regulator is disabled and Vcore domain is powered off. 00997 * SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain. 00998 * The BOR is not available. 00999 * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state. 01000 * @retval None 01001 */ 01002 void HAL_PWREx_EnterSHUTDOWNMode(void) 01003 { 01004 01005 /* Set Shutdown mode */ 01006 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN); 01007 01008 /* Set SLEEPDEEP bit of Cortex System Control Register */ 01009 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 01010 01011 /* This option is used to ensure that store operations are completed */ 01012 #if defined ( __CC_ARM) 01013 __force_stores(); 01014 #endif 01015 /* Request Wait For Interrupt */ 01016 __WFI(); 01017 } 01018 01019 01020 01021 01022 /** 01023 * @brief This function handles the PWR PVD/PVMx interrupt request. 01024 * @note This API should be called under the PVD_PVM_IRQHandler(). 01025 * @retval None 01026 */ 01027 void HAL_PWREx_PVD_PVM_IRQHandler(void) 01028 { 01029 /* Check PWR exti flag */ 01030 if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) 01031 { 01032 /* PWR PVD interrupt user callback */ 01033 HAL_PWR_PVDCallback(); 01034 01035 /* Clear PVD exti pending bit */ 01036 __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); 01037 } 01038 /* Next, successively check PVMx exti flags */ 01039 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 01040 if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != RESET) 01041 { 01042 /* PWR PVM1 interrupt user callback */ 01043 HAL_PWREx_PVM1Callback(); 01044 01045 /* Clear PVM1 exti pending bit */ 01046 __HAL_PWR_PVM1_EXTI_CLEAR_FLAG(); 01047 } 01048 #endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 01049 if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != RESET) 01050 { 01051 /* PWR PVM2 interrupt user callback */ 01052 HAL_PWREx_PVM2Callback(); 01053 01054 /* Clear PVM2 exti pending bit */ 01055 __HAL_PWR_PVM2_EXTI_CLEAR_FLAG(); 01056 } 01057 if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != RESET) 01058 { 01059 /* PWR PVM3 interrupt user callback */ 01060 HAL_PWREx_PVM3Callback(); 01061 01062 /* Clear PVM3 exti pending bit */ 01063 __HAL_PWR_PVM3_EXTI_CLEAR_FLAG(); 01064 } 01065 if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != RESET) 01066 { 01067 /* PWR PVM4 interrupt user callback */ 01068 HAL_PWREx_PVM4Callback(); 01069 01070 /* Clear PVM4 exti pending bit */ 01071 __HAL_PWR_PVM4_EXTI_CLEAR_FLAG(); 01072 } 01073 } 01074 01075 01076 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 01077 /** 01078 * @brief PWR PVM1 interrupt callback 01079 * @retval None 01080 */ 01081 __weak void HAL_PWREx_PVM1Callback(void) 01082 { 01083 /* NOTE : This function should not be modified; when the callback is needed, 01084 HAL_PWREx_PVM1Callback() API can be implemented in the user file 01085 */ 01086 } 01087 #endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 01088 01089 /** 01090 * @brief PWR PVM2 interrupt callback 01091 * @retval None 01092 */ 01093 __weak void HAL_PWREx_PVM2Callback(void) 01094 { 01095 /* NOTE : This function should not be modified; when the callback is needed, 01096 HAL_PWREx_PVM2Callback() API can be implemented in the user file 01097 */ 01098 } 01099 01100 /** 01101 * @brief PWR PVM3 interrupt callback 01102 * @retval None 01103 */ 01104 __weak void HAL_PWREx_PVM3Callback(void) 01105 { 01106 /* NOTE : This function should not be modified; when the callback is needed, 01107 HAL_PWREx_PVM3Callback() API can be implemented in the user file 01108 */ 01109 } 01110 01111 /** 01112 * @brief PWR PVM4 interrupt callback 01113 * @retval None 01114 */ 01115 __weak void HAL_PWREx_PVM4Callback(void) 01116 { 01117 /* NOTE : This function should not be modified; when the callback is needed, 01118 HAL_PWREx_PVM4Callback() API can be implemented in the user file 01119 */ 01120 } 01121 01122 01123 /** 01124 * @} 01125 */ 01126 01127 /** 01128 * @} 01129 */ 01130 01131 #endif /* HAL_PWR_MODULE_ENABLED */ 01132 /** 01133 * @} 01134 */ 01135 01136 /** 01137 * @} 01138 */ 01139 01140 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 01141
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