Hal Drivers for L4
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stm32l4xx_hal.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal.h 00004 * @author MCD Application Team 00005 * @version V1.1.0 00006 * @date 16-September-2015 00007 * @brief This file contains all the functions prototypes for the HAL 00008 * module driver. 00009 ****************************************************************************** 00010 * @attention 00011 * 00012 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> 00013 * 00014 * Redistribution and use in source and binary forms, with or without modification, 00015 * are permitted provided that the following conditions are met: 00016 * 1. Redistributions of source code must retain the above copyright notice, 00017 * this list of conditions and the following disclaimer. 00018 * 2. Redistributions in binary form must reproduce the above copyright notice, 00019 * this list of conditions and the following disclaimer in the documentation 00020 * and/or other materials provided with the distribution. 00021 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00022 * may be used to endorse or promote products derived from this software 00023 * without specific prior written permission. 00024 * 00025 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00026 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00027 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00028 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00029 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00030 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00031 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00032 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00033 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00034 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00035 * 00036 ****************************************************************************** 00037 */ 00038 00039 /* Define to prevent recursive inclusion -------------------------------------*/ 00040 #ifndef __STM32L4xx_HAL_H 00041 #define __STM32L4xx_HAL_H 00042 00043 #ifdef __cplusplus 00044 extern "C" { 00045 #endif 00046 00047 /* Includes ------------------------------------------------------------------*/ 00048 #include "stm32l4xx_hal_conf.h" 00049 00050 /** @addtogroup STM32L4xx_HAL_Driver 00051 * @{ 00052 */ 00053 00054 /** @addtogroup HAL 00055 * @{ 00056 */ 00057 00058 /* Exported types ------------------------------------------------------------*/ 00059 /* Exported constants --------------------------------------------------------*/ 00060 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants 00061 * @{ 00062 */ 00063 00064 /** @defgroup SYSCFG_BootMode Boot Mode 00065 * @{ 00066 */ 00067 #define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000) 00068 #define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 00069 #define SYSCFG_BOOT_FMC SYSCFG_MEMRMP_MEM_MODE_1 00070 #define SYSCFG_BOOT_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) 00071 #define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) 00072 00073 /** 00074 * @} 00075 */ 00076 00077 /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts 00078 * @{ 00079 */ 00080 #define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ 00081 #define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ 00082 #define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ 00083 #define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ 00084 #define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ 00085 #define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ 00086 00087 /** 00088 * @} 00089 */ 00090 00091 /** @defgroup SYSCFG_SRAM2WRP SRAM2 Write protection 00092 * @{ 00093 */ 00094 #define SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */ 00095 #define SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */ 00096 #define SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */ 00097 #define SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */ 00098 #define SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */ 00099 #define SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */ 00100 #define SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */ 00101 #define SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */ 00102 #define SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */ 00103 #define SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */ 00104 #define SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */ 00105 #define SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */ 00106 #define SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */ 00107 #define SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */ 00108 #define SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */ 00109 #define SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */ 00110 #define SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */ 00111 #define SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */ 00112 #define SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */ 00113 #define SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */ 00114 #define SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */ 00115 #define SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */ 00116 #define SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */ 00117 #define SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */ 00118 #define SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */ 00119 #define SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */ 00120 #define SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */ 00121 #define SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */ 00122 #define SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */ 00123 #define SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */ 00124 #define SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */ 00125 #define SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */ 00126 00127 /** 00128 * @} 00129 */ 00130 00131 /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale 00132 * @{ 00133 */ 00134 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ 00135 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */ 00136 00137 /** 00138 * @} 00139 */ 00140 00141 /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance 00142 * @{ 00143 */ 00144 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ 00145 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ 00146 00147 /** 00148 * @} 00149 */ 00150 00151 /** @defgroup SYSCFG_flags_definition Flags 00152 * @{ 00153 */ 00154 00155 #define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */ 00156 #define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY /*!< SRAM2 busy by erase operation */ 00157 00158 /** 00159 * @} 00160 */ 00161 00162 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO 00163 * @{ 00164 */ 00165 00166 /** @brief Fast-mode Plus driving capability on a specific GPIO 00167 */ 00168 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ 00169 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ 00170 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ 00171 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ 00172 00173 /** 00174 * @} 00175 */ 00176 00177 /** 00178 * @} 00179 */ 00180 00181 /* Exported macros -----------------------------------------------------------*/ 00182 00183 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros 00184 * @{ 00185 */ 00186 00187 /** @brief Freeze/Unfreeze Peripherals in Debug mode 00188 */ 00189 #if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP) 00190 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 00191 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 00192 #endif 00193 00194 #if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP) 00195 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 00196 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 00197 #endif 00198 00199 #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) 00200 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 00201 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 00202 #endif 00203 00204 #if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP) 00205 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 00206 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 00207 #endif 00208 00209 #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP) 00210 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 00211 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 00212 #endif 00213 00214 #if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP) 00215 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 00216 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 00217 #endif 00218 00219 #if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP) 00220 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) 00221 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) 00222 #endif 00223 00224 #if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP) 00225 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 00226 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 00227 #endif 00228 00229 #if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP) 00230 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 00231 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 00232 #endif 00233 00234 #if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP) 00235 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 00236 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 00237 #endif 00238 00239 #if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP) 00240 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 00241 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 00242 #endif 00243 00244 #if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP) 00245 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) 00246 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) 00247 #endif 00248 00249 #if defined(DBGMCU_APB1FZR1_DBG_CAN_STOP) 00250 #define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP) 00251 #define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP) 00252 #endif 00253 00254 #if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) 00255 #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) 00256 #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) 00257 #endif 00258 00259 #if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 00260 #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 00261 #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 00262 #endif 00263 00264 #if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP) 00265 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) 00266 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) 00267 #endif 00268 00269 #if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP) 00270 #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) 00271 #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) 00272 #endif 00273 00274 #if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP) 00275 #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) 00276 #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) 00277 #endif 00278 00279 #if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP) 00280 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) 00281 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) 00282 #endif 00283 00284 #if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP) 00285 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) 00286 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) 00287 #endif 00288 00289 /** 00290 * @} 00291 */ 00292 00293 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros 00294 * @{ 00295 */ 00296 00297 /** @brief Main Flash memory mapped at 0x00000000. 00298 */ 00299 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) 00300 00301 /** @brief System Flash memory mapped at 0x00000000. 00302 */ 00303 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0) 00304 00305 /** @brief Embedded SRAM mapped at 0x00000000. 00306 */ 00307 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0)) 00308 00309 /** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000. 00310 */ 00311 #define __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1) 00312 00313 /** @brief QUADSPI mapped at 0x00000000. 00314 */ 00315 #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1)) 00316 00317 /** 00318 * @brief Return the boot mode as configured by user. 00319 * @retval The boot mode as configured by user. The returned value can be one 00320 * of the following values: 00321 * @arg SYSCFG_BOOT_MAINFLASH 00322 * @arg SYSCFG_BOOT_SYSTEMFLASH 00323 * @arg SYSCFG_BOOT_FMC 00324 * @arg SYSCFG_BOOT_SRAM 00325 * @arg SYSCFG_BOOT_QUADSPI 00326 */ 00327 #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) 00328 00329 /** @brief SRAM2 page write protection enable macro 00330 * @param __SRAM2WRP__: This parameter can be a value of @ref SYSCFG_SRAM2WRP 00331 * @note write protection can only be disabled by a system reset 00332 */ 00333 #define __HAL_SYSCFG_SRAM2_WRP_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ 00334 SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\ 00335 }while(0) 00336 00337 /** @brief SRAM2 page write protection unlock prior to erase 00338 * @note Writing a wrong key reactivates the write protection 00339 */ 00340 #define __HAL_SYSCFG_SRAM2_WRP_UNLOCK() do {SYSCFG->SKR = 0xCA;\ 00341 SYSCFG->SKR = 0x53;\ 00342 }while(0) 00343 00344 /** @brief SRAM2 erase 00345 * @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase 00346 */ 00347 #define __HAL_SYSCFG_SRAM2_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER) 00348 00349 /** @brief Floating Point Unit interrupt enable/disable macros 00350 * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts 00351 */ 00352 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 00353 SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ 00354 }while(0) 00355 00356 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 00357 CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ 00358 }while(0) 00359 00360 /** @brief SYSCFG Break ECC lock. 00361 * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. 00362 * @note The selected configuration is locked and can be unlocked only by system reset. 00363 */ 00364 #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL) 00365 00366 /** @brief SYSCFG Break Cortex-M4 Lockup lock. 00367 * Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input. 00368 * @note The selected configuration is locked and can be unlocked only by system reset. 00369 */ 00370 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) 00371 00372 /** @brief SYSCFG Break PVD lock. 00373 * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register. 00374 * @note The selected configuration is locked and can be unlocked only by system reset. 00375 */ 00376 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL) 00377 00378 /** @brief SYSCFG Break SRAM2 parity lock. 00379 * Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input. 00380 * @note The selected configuration is locked and can be unlocked by system reset. 00381 */ 00382 #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL) 00383 00384 /** @brief Check SYSCFG flag is set or not. 00385 * @param __FLAG__: specifies the flag to check. 00386 * This parameter can be one of the following values: 00387 * @arg SYSCFG_FLAG_SRAM2_PE: SRAM2 Parity Error Flag 00388 * @arg SYSCFG_FLAG_SRAM2_BUSY: SRAM2 Erase Ongoing 00389 * @retval The new state of __FLAG__ (TRUE or FALSE). 00390 */ 00391 #define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0) ? 1 : 0) 00392 00393 /** @brief Set the SPF bit to clear the SRAM Parity Error Flag. 00394 */ 00395 #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) 00396 00397 /** @brief Fast-mode Plus driving capability enable/disable macros 00398 * @param __FASTMODEPLUS__: This parameter can be a value of : 00399 * @arg SYSCFG_FASTMODEPLUS_PB6: Fast-mode Plus driving capability activation on PB6 00400 * @arg SYSCFG_FASTMODEPLUS_PB7: Fast-mode Plus driving capability activation on PB7 00401 * @arg SYSCFG_FASTMODEPLUS_PB8: Fast-mode Plus driving capability activation on PB8 00402 * @arg SYSCFG_FASTMODEPLUS_PB9: Fast-mode Plus driving capability activation on PB9 00403 */ 00404 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 00405 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 00406 }while(0) 00407 00408 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 00409 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 00410 }while(0) 00411 00412 /** 00413 * @} 00414 */ 00415 00416 /* Private macros ------------------------------------------------------------*/ 00417 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros 00418 * @{ 00419 */ 00420 00421 #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \ 00422 (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \ 00423 (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \ 00424 (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \ 00425 (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \ 00426 (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) 00427 00428 #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \ 00429 ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ 00430 ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \ 00431 ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) 00432 00433 #define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= 0xFFFFFFFF)) 00434 00435 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ 00436 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1)) 00437 00438 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ 00439 ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) 00440 00441 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) 00442 00443 00444 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 00445 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 00446 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ 00447 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) 00448 00449 /** 00450 * @} 00451 */ 00452 00453 /* Exported functions --------------------------------------------------------*/ 00454 00455 /** @addtogroup HAL_Exported_Functions 00456 * @{ 00457 */ 00458 00459 /** @addtogroup HAL_Exported_Functions_Group1 00460 * @{ 00461 */ 00462 00463 /* Initialization and de-initialization functions ******************************/ 00464 HAL_StatusTypeDef HAL_Init(void); 00465 HAL_StatusTypeDef HAL_DeInit(void); 00466 void HAL_MspInit(void); 00467 void HAL_MspDeInit(void); 00468 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); 00469 00470 /** 00471 * @} 00472 */ 00473 00474 /** @addtogroup HAL_Exported_Functions_Group2 00475 * @{ 00476 */ 00477 00478 /* Peripheral Control functions ************************************************/ 00479 void HAL_IncTick(void); 00480 void HAL_Delay(uint32_t Delay); 00481 uint32_t HAL_GetTick(void); 00482 void HAL_SuspendTick(void); 00483 void HAL_ResumeTick(void); 00484 uint32_t HAL_GetHalVersion(void); 00485 uint32_t HAL_GetREVID(void); 00486 uint32_t HAL_GetDEVID(void); 00487 00488 /** 00489 * @} 00490 */ 00491 00492 /** @addtogroup HAL_Exported_Functions_Group3 00493 * @{ 00494 */ 00495 00496 /* DBGMCU Peripheral Control functions *****************************************/ 00497 void HAL_DBGMCU_EnableDBGSleepMode(void); 00498 void HAL_DBGMCU_DisableDBGSleepMode(void); 00499 void HAL_DBGMCU_EnableDBGStopMode(void); 00500 void HAL_DBGMCU_DisableDBGStopMode(void); 00501 void HAL_DBGMCU_EnableDBGStandbyMode(void); 00502 void HAL_DBGMCU_DisableDBGStandbyMode(void); 00503 00504 /** 00505 * @} 00506 */ 00507 00508 /** @addtogroup HAL_Exported_Functions_Group4 00509 * @{ 00510 */ 00511 00512 /* SYSCFG Control functions ****************************************************/ 00513 void HAL_SYSCFG_SRAM2Erase(void); 00514 void HAL_SYSCFG_EnableMemorySwappingBank(void); 00515 void HAL_SYSCFG_DisableMemorySwappingBank(void); 00516 00517 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); 00518 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); 00519 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); 00520 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); 00521 void HAL_SYSCFG_DisableVREFBUF(void); 00522 00523 /** 00524 * @} 00525 */ 00526 00527 /** 00528 * @} 00529 */ 00530 00531 /** 00532 * @} 00533 */ 00534 00535 /** 00536 * @} 00537 */ 00538 00539 #ifdef __cplusplus 00540 } 00541 #endif 00542 00543 #endif /* __STM32L4xx_HAL_H */ 00544 00545 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 00546
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