Eric Lewiston
Hal Drivers for L4
Dependents: BSP OneHopeOnePrayer FINAL_AUDIO_RECORD AudioDemo
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stm32_hal_legacy.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32_hal_legacy.h 00004 * @author MCD Application Team 00005 * @version V1.1.0 00006 * @date 16-September-2015 00007 * @brief This file contains aliases definition for the STM32Cube HAL constants 00008 * macros and functions maintained for legacy purpose. 00009 ****************************************************************************** 00010 * @attention 00011 * 00012 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> 00013 * 00014 * Redistribution and use in source and binary forms, with or without modification, 00015 * are permitted provided that the following conditions are met: 00016 * 1. Redistributions of source code must retain the above copyright notice, 00017 * this list of conditions and the following disclaimer. 00018 * 2. Redistributions in binary form must reproduce the above copyright notice, 00019 * this list of conditions and the following disclaimer in the documentation 00020 * and/or other materials provided with the distribution. 00021 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00022 * may be used to endorse or promote products derived from this software 00023 * without specific prior written permission. 00024 * 00025 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00026 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00027 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00028 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00029 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00030 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00031 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00032 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00033 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00034 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00035 * 00036 ****************************************************************************** 00037 */ 00038 00039 /* Define to prevent recursive inclusion -------------------------------------*/ 00040 #ifndef __STM32_HAL_LEGACY 00041 #define __STM32_HAL_LEGACY 00042 00043 #ifdef __cplusplus 00044 extern "C" { 00045 #endif 00046 00047 /* Includes ------------------------------------------------------------------*/ 00048 /* Exported types ------------------------------------------------------------*/ 00049 /* Exported constants --------------------------------------------------------*/ 00050 00051 /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose 00052 * @{ 00053 */ 00054 #define AES_FLAG_RDERR CRYP_FLAG_RDERR 00055 #define AES_FLAG_WRERR CRYP_FLAG_WRERR 00056 #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF 00057 #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR 00058 #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR 00059 00060 /** 00061 * @} 00062 */ 00063 00064 /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose 00065 * @{ 00066 */ 00067 #define ADC_RESOLUTION12b ADC_RESOLUTION_12B 00068 #define ADC_RESOLUTION10b ADC_RESOLUTION_10B 00069 #define ADC_RESOLUTION8b ADC_RESOLUTION_8B 00070 #define ADC_RESOLUTION6b ADC_RESOLUTION_6B 00071 #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN 00072 #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED 00073 #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV 00074 #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV 00075 #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV 00076 #define REGULAR_GROUP ADC_REGULAR_GROUP 00077 #define INJECTED_GROUP ADC_INJECTED_GROUP 00078 #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP 00079 #define AWD_EVENT ADC_AWD_EVENT 00080 #define AWD1_EVENT ADC_AWD1_EVENT 00081 #define AWD2_EVENT ADC_AWD2_EVENT 00082 #define AWD3_EVENT ADC_AWD3_EVENT 00083 #define OVR_EVENT ADC_OVR_EVENT 00084 #define JQOVF_EVENT ADC_JQOVF_EVENT 00085 #define ALL_CHANNELS ADC_ALL_CHANNELS 00086 #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS 00087 #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS 00088 #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR 00089 #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT 00090 #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 00091 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 00092 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 00093 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 00094 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 00095 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO 00096 #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 00097 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO 00098 #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 00099 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO 00100 #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 00101 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 00102 #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE 00103 #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING 00104 #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING 00105 #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING 00106 00107 #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY 00108 #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY 00109 #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC 00110 #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC 00111 #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL 00112 #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL 00113 #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 00114 /** 00115 * @} 00116 */ 00117 00118 /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose 00119 * @{ 00120 */ 00121 00122 #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG 00123 00124 /** 00125 * @} 00126 */ 00127 00128 /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose 00129 * @{ 00130 */ 00131 00132 #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE 00133 #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE 00134 #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 00135 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 00136 #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 00137 #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 00138 #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 00139 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 00140 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 00141 #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR 00142 #if defined(STM32F373xC) || defined(STM32F378xx) 00143 #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 00144 #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR 00145 #endif /* STM32F373xC || STM32F378xx */ 00146 /** 00147 * @} 00148 */ 00149 00150 /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose 00151 * @{ 00152 */ 00153 00154 #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE 00155 #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE 00156 00157 /** 00158 * @} 00159 */ 00160 00161 /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose 00162 * @{ 00163 */ 00164 00165 #define DAC1_CHANNEL_1 DAC_CHANNEL_1 00166 #define DAC1_CHANNEL_2 DAC_CHANNEL_2 00167 #define DAC2_CHANNEL_1 DAC_CHANNEL_1 00168 #define DAC_WAVE_NONE ((uint32_t)0x00000000) 00169 #define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0) 00170 #define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) 00171 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE 00172 #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE 00173 #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE 00174 00175 /** 00176 * @} 00177 */ 00178 00179 /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose 00180 * @{ 00181 */ 00182 #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 00183 #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 00184 #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 00185 #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 00186 #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 00187 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 00188 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 00189 #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 00190 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 00191 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 00192 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 00193 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 00194 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 00195 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 00196 #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 00197 00198 #define IS_HAL_REMAPDMA IS_DMA_REMAP 00199 #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE 00200 #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE 00201 00202 00203 00204 /** 00205 * @} 00206 */ 00207 00208 /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose 00209 * @{ 00210 */ 00211 00212 #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE 00213 #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD 00214 #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD 00215 #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD 00216 #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS 00217 #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES 00218 #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES 00219 #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE 00220 #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE 00221 #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE 00222 #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE 00223 #define OBEX_PCROP OPTIONBYTE_PCROP 00224 #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG 00225 #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE 00226 #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE 00227 #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE 00228 #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD 00229 #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD 00230 #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE 00231 #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD 00232 #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD 00233 #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE 00234 #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD 00235 #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD 00236 #define PAGESIZE FLASH_PAGE_SIZE 00237 #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE 00238 #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD 00239 #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD 00240 #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 00241 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 00242 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 00243 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 00244 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST 00245 #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST 00246 #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA 00247 #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB 00248 #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA 00249 #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB 00250 #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE 00251 #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN 00252 #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE 00253 #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN 00254 #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE 00255 #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD 00256 #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG 00257 #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS 00258 #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP 00259 #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV 00260 #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR 00261 #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG 00262 #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION 00263 #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA 00264 #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE 00265 #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE 00266 #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS 00267 #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS 00268 #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST 00269 #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR 00270 #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO 00271 #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION 00272 #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS 00273 #define OB_WDG_SW OB_IWDG_SW 00274 #define OB_WDG_HW OB_IWDG_HW 00275 #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET 00276 #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET 00277 #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET 00278 #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET 00279 #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR 00280 #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 00281 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 00282 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 00283 /** 00284 * @} 00285 */ 00286 00287 /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose 00288 * @{ 00289 */ 00290 00291 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 00292 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 00293 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 00294 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 00295 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 00296 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 00297 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 00298 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 00299 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 00300 /** 00301 * @} 00302 */ 00303 00304 00305 /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose 00306 * @{ 00307 */ 00308 #if defined(STM32L4) || defined(STM32F7) 00309 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE 00310 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE 00311 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 00312 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 00313 #else 00314 #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE 00315 #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE 00316 #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 00317 #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 00318 #endif 00319 /** 00320 * @} 00321 */ 00322 00323 /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose 00324 * @{ 00325 */ 00326 00327 #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef 00328 #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef 00329 /** 00330 * @} 00331 */ 00332 00333 /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose 00334 * @{ 00335 */ 00336 #define GET_GPIO_SOURCE GPIO_GET_INDEX 00337 #define GET_GPIO_INDEX GPIO_GET_INDEX 00338 00339 #if defined(STM32F4) 00340 #define GPIO_AF12_SDMMC GPIO_AF12_SDIO 00341 #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO 00342 #endif 00343 00344 #if defined(STM32F7) 00345 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 00346 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 00347 #endif 00348 00349 #if defined(STM32L4) 00350 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 00351 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 00352 #endif 00353 00354 #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 00355 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 00356 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 00357 00358 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) 00359 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW 00360 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM 00361 #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH 00362 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH 00363 #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 */ 00364 00365 #if defined(STM32L1) 00366 #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW 00367 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM 00368 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH 00369 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH 00370 #endif /* STM32L1 */ 00371 00372 /** 00373 * @} 00374 */ 00375 00376 /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose 00377 * @{ 00378 */ 00379 #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED 00380 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 00381 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 00382 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 00383 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 00384 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 00385 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 00386 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 00387 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 00388 00389 #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER 00390 #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER 00391 #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD 00392 #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD 00393 #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER 00394 #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER 00395 #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE 00396 #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE 00397 /** 00398 * @} 00399 */ 00400 00401 /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose 00402 * @{ 00403 */ 00404 #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE 00405 #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE 00406 #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE 00407 #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE 00408 #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE 00409 #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE 00410 #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE 00411 #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE 00412 /** 00413 * @} 00414 */ 00415 00416 /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose 00417 * @{ 00418 */ 00419 #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE 00420 #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE 00421 00422 /** 00423 * @} 00424 */ 00425 00426 /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose 00427 * @{ 00428 */ 00429 #define KR_KEY_RELOAD IWDG_KEY_RELOAD 00430 #define KR_KEY_ENABLE IWDG_KEY_ENABLE 00431 #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE 00432 #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE 00433 /** 00434 * @} 00435 */ 00436 00437 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose 00438 * @{ 00439 */ 00440 00441 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 00442 #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS 00443 #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS 00444 #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS 00445 00446 #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING 00447 #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING 00448 #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING 00449 00450 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 00451 #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS 00452 #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS 00453 #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS 00454 00455 /* The following 3 definition have also been present in a temporary version of lptim.h */ 00456 /* They need to be renamed also to the right name, just in case */ 00457 #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS 00458 #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS 00459 #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS 00460 00461 /** 00462 * @} 00463 */ 00464 00465 /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose 00466 * @{ 00467 */ 00468 #define NAND_AddressTypedef NAND_AddressTypeDef 00469 00470 #define __ARRAY_ADDRESS ARRAY_ADDRESS 00471 #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE 00472 #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE 00473 #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE 00474 #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE 00475 /** 00476 * @} 00477 */ 00478 00479 /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose 00480 * @{ 00481 */ 00482 #define NOR_StatusTypedef HAL_NOR_StatusTypeDef 00483 #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS 00484 #define NOR_ONGOING HAL_NOR_STATUS_ONGOING 00485 #define NOR_ERROR HAL_NOR_STATUS_ERROR 00486 #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT 00487 00488 #define __NOR_WRITE NOR_WRITE 00489 #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT 00490 /** 00491 * @} 00492 */ 00493 00494 /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose 00495 * @{ 00496 */ 00497 00498 #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 00499 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 00500 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 00501 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 00502 00503 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 00504 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 00505 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 00506 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 00507 00508 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 00509 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 00510 00511 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 00512 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 00513 00514 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 00515 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 00516 00517 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 00518 00519 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO 00520 #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 00521 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 00522 00523 /** 00524 * @} 00525 */ 00526 00527 /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose 00528 * @{ 00529 */ 00530 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS 00531 /** 00532 * @} 00533 */ 00534 00535 /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose 00536 * @{ 00537 */ 00538 00539 /* Compact Flash-ATA registers description */ 00540 #define CF_DATA ATA_DATA 00541 #define CF_SECTOR_COUNT ATA_SECTOR_COUNT 00542 #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER 00543 #define CF_CYLINDER_LOW ATA_CYLINDER_LOW 00544 #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH 00545 #define CF_CARD_HEAD ATA_CARD_HEAD 00546 #define CF_STATUS_CMD ATA_STATUS_CMD 00547 #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE 00548 #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA 00549 00550 /* Compact Flash-ATA commands */ 00551 #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD 00552 #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD 00553 #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD 00554 #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD 00555 00556 #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef 00557 #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS 00558 #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING 00559 #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR 00560 #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT 00561 /** 00562 * @} 00563 */ 00564 00565 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose 00566 * @{ 00567 */ 00568 00569 #define FORMAT_BIN RTC_FORMAT_BIN 00570 #define FORMAT_BCD RTC_FORMAT_BCD 00571 00572 #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE 00573 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE 00574 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE 00575 #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 00576 #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 00577 00578 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 00579 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 00580 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE 00581 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE 00582 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 00583 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 00584 #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT 00585 #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT 00586 00587 #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT 00588 #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 00589 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 00590 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 00591 00592 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE 00593 #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 00594 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 00595 00596 #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT 00597 #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 00598 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 00599 00600 /** 00601 * @} 00602 */ 00603 00604 00605 /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose 00606 * @{ 00607 */ 00608 #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE 00609 #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE 00610 00611 #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE 00612 #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE 00613 #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE 00614 #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE 00615 00616 #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE 00617 #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE 00618 00619 #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE 00620 #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE 00621 /** 00622 * @} 00623 */ 00624 00625 00626 /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose 00627 * @{ 00628 */ 00629 #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE 00630 #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE 00631 #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE 00632 #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE 00633 #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE 00634 #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE 00635 #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE 00636 #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE 00637 #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE 00638 #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE 00639 #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN 00640 /** 00641 * @} 00642 */ 00643 00644 /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose 00645 * @{ 00646 */ 00647 #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE 00648 #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE 00649 00650 #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE 00651 #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE 00652 00653 #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE 00654 #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE 00655 00656 /** 00657 * @} 00658 */ 00659 00660 /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose 00661 * @{ 00662 */ 00663 #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK 00664 #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK 00665 00666 #define TIM_DMABase_CR1 TIM_DMABASE_CR1 00667 #define TIM_DMABase_CR2 TIM_DMABASE_CR2 00668 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR 00669 #define TIM_DMABase_DIER TIM_DMABASE_DIER 00670 #define TIM_DMABase_SR TIM_DMABASE_SR 00671 #define TIM_DMABase_EGR TIM_DMABASE_EGR 00672 #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 00673 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 00674 #define TIM_DMABase_CCER TIM_DMABASE_CCER 00675 #define TIM_DMABase_CNT TIM_DMABASE_CNT 00676 #define TIM_DMABase_PSC TIM_DMABASE_PSC 00677 #define TIM_DMABase_ARR TIM_DMABASE_ARR 00678 #define TIM_DMABase_RCR TIM_DMABASE_RCR 00679 #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 00680 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 00681 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 00682 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 00683 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR 00684 #define TIM_DMABase_DCR TIM_DMABASE_DCR 00685 #define TIM_DMABase_DMAR TIM_DMABASE_DMAR 00686 #define TIM_DMABase_OR1 TIM_DMABASE_OR1 00687 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 00688 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 00689 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 00690 #define TIM_DMABase_OR2 TIM_DMABASE_OR2 00691 #define TIM_DMABase_OR3 TIM_DMABASE_OR3 00692 #define TIM_DMABase_OR TIM_DMABASE_OR 00693 00694 #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE 00695 #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 00696 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 00697 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 00698 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 00699 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM 00700 #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER 00701 #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK 00702 #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 00703 00704 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER 00705 #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS 00706 #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS 00707 #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS 00708 #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS 00709 #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS 00710 #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS 00711 #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS 00712 #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS 00713 #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS 00714 #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS 00715 #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS 00716 #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS 00717 #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS 00718 #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS 00719 #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS 00720 #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS 00721 #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS 00722 00723 /** 00724 * @} 00725 */ 00726 00727 /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose 00728 * @{ 00729 */ 00730 #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING 00731 #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING 00732 /** 00733 * @} 00734 */ 00735 00736 /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose 00737 * @{ 00738 */ 00739 #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE 00740 #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE 00741 #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE 00742 #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE 00743 00744 #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE 00745 #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE 00746 00747 #define __DIV_SAMPLING16 UART_DIV_SAMPLING16 00748 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 00749 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 00750 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 00751 00752 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8 00753 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 00754 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 00755 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 00756 00757 #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE 00758 #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK 00759 00760 /** 00761 * @} 00762 */ 00763 00764 00765 /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose 00766 * @{ 00767 */ 00768 00769 #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE 00770 #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE 00771 00772 #define USARTNACK_ENABLED USART_NACK_ENABLE 00773 #define USARTNACK_DISABLED USART_NACK_DISABLE 00774 /** 00775 * @} 00776 */ 00777 00778 /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose 00779 * @{ 00780 */ 00781 #define CFR_BASE WWDG_CFR_BASE 00782 00783 /** 00784 * @} 00785 */ 00786 00787 /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose 00788 * @{ 00789 */ 00790 #define CAN_FilterFIFO0 CAN_FILTER_FIFO0 00791 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1 00792 #define CAN_IT_RQCP0 CAN_IT_TME 00793 #define CAN_IT_RQCP1 CAN_IT_TME 00794 #define CAN_IT_RQCP2 CAN_IT_TME 00795 #define INAK_TIMEOUT CAN_TIMEOUT_VALUE 00796 #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE 00797 #define CAN_TXSTATUS_FAILED ((uint8_t)0x00) 00798 #define CAN_TXSTATUS_OK ((uint8_t)0x01) 00799 #define CAN_TXSTATUS_PENDING ((uint8_t)0x02) 00800 00801 /** 00802 * @} 00803 */ 00804 00805 /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose 00806 * @{ 00807 */ 00808 00809 #define VLAN_TAG ETH_VLAN_TAG 00810 #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD 00811 #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD 00812 #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD 00813 #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK 00814 #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK 00815 #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK 00816 #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK 00817 00818 #define ETH_MMCCR ((uint32_t)0x00000100) 00819 #define ETH_MMCRIR ((uint32_t)0x00000104) 00820 #define ETH_MMCTIR ((uint32_t)0x00000108) 00821 #define ETH_MMCRIMR ((uint32_t)0x0000010C) 00822 #define ETH_MMCTIMR ((uint32_t)0x00000110) 00823 #define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) 00824 #define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) 00825 #define ETH_MMCTGFCR ((uint32_t)0x00000168) 00826 #define ETH_MMCRFCECR ((uint32_t)0x00000194) 00827 #define ETH_MMCRFAECR ((uint32_t)0x00000198) 00828 #define ETH_MMCRGUFCR ((uint32_t)0x000001C4) 00829 00830 /** 00831 * @} 00832 */ 00833 00834 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose 00835 * @{ 00836 */ 00837 00838 /** 00839 * @} 00840 */ 00841 00842 /* Exported functions --------------------------------------------------------*/ 00843 00844 /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose 00845 * @{ 00846 */ 00847 #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback 00848 /** 00849 * @} 00850 */ 00851 00852 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose 00853 * @{ 00854 */ 00855 #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef 00856 #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef 00857 #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish 00858 #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish 00859 #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish 00860 #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish 00861 00862 /*HASH Algorithm Selection*/ 00863 00864 #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 00865 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 00866 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 00867 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 00868 00869 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH 00870 #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC 00871 00872 #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY 00873 #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY 00874 /** 00875 * @} 00876 */ 00877 00878 /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose 00879 * @{ 00880 */ 00881 #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode 00882 #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode 00883 #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode 00884 #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode 00885 #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode 00886 #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode 00887 #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) 00888 #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect 00889 #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) 00890 #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) 00891 #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) 00892 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) 00893 /** 00894 * @} 00895 */ 00896 00897 /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose 00898 * @{ 00899 */ 00900 #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram 00901 #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown 00902 #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown 00903 #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock 00904 #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock 00905 #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase 00906 #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program 00907 00908 /** 00909 * @} 00910 */ 00911 00912 /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose 00913 * @{ 00914 */ 00915 #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter 00916 #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter 00917 00918 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) 00919 /** 00920 * @} 00921 */ 00922 00923 /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose 00924 * @{ 00925 */ 00926 #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD 00927 #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg 00928 #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown 00929 #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor 00930 #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg 00931 #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown 00932 #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor 00933 #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler 00934 #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD 00935 #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler 00936 #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback 00937 #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive 00938 #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive 00939 #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC 00940 #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC 00941 #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM 00942 00943 #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL 00944 #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING 00945 #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING 00946 #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING 00947 #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING 00948 #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING 00949 #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING 00950 00951 #define CR_OFFSET_BB PWR_CR_OFFSET_BB 00952 #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB 00953 00954 #define DBP_BitNumber DBP_BIT_NUMBER 00955 #define PVDE_BitNumber PVDE_BIT_NUMBER 00956 #define PMODE_BitNumber PMODE_BIT_NUMBER 00957 #define EWUP_BitNumber EWUP_BIT_NUMBER 00958 #define FPDS_BitNumber FPDS_BIT_NUMBER 00959 #define ODEN_BitNumber ODEN_BIT_NUMBER 00960 #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER 00961 #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER 00962 #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER 00963 #define BRE_BitNumber BRE_BIT_NUMBER 00964 00965 #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL 00966 00967 /** 00968 * @} 00969 */ 00970 00971 /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose 00972 * @{ 00973 */ 00974 #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT 00975 #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback 00976 #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback 00977 /** 00978 * @} 00979 */ 00980 00981 /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose 00982 * @{ 00983 */ 00984 #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo 00985 /** 00986 * @} 00987 */ 00988 00989 /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose 00990 * @{ 00991 */ 00992 #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt 00993 #define HAL_TIM_DMAError TIM_DMAError 00994 #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt 00995 #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt 00996 /** 00997 * @} 00998 */ 00999 01000 /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose 01001 * @{ 01002 */ 01003 #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback 01004 /** 01005 * @} 01006 */ 01007 01008 /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose 01009 * @{ 01010 */ 01011 #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback 01012 /** 01013 * @} 01014 */ 01015 01016 01017 /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose 01018 * @{ 01019 */ 01020 01021 /** 01022 * @} 01023 */ 01024 01025 /* Exported macros ------------------------------------------------------------*/ 01026 01027 /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose 01028 * @{ 01029 */ 01030 #define AES_IT_CC CRYP_IT_CC 01031 #define AES_IT_ERR CRYP_IT_ERR 01032 #define AES_FLAG_CCF CRYP_FLAG_CCF 01033 /** 01034 * @} 01035 */ 01036 01037 /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose 01038 * @{ 01039 */ 01040 #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE 01041 #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH 01042 #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH 01043 #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM 01044 #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC 01045 #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM 01046 #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC 01047 #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI 01048 #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK 01049 #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG 01050 #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG 01051 #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE 01052 #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE 01053 01054 #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY 01055 #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 01056 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS 01057 #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER 01058 #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER 01059 01060 /** 01061 * @} 01062 */ 01063 01064 01065 /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose 01066 * @{ 01067 */ 01068 #define __ADC_ENABLE __HAL_ADC_ENABLE 01069 #define __ADC_DISABLE __HAL_ADC_DISABLE 01070 #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS 01071 #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS 01072 #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE 01073 #define __ADC_IS_ENABLED ADC_IS_ENABLE 01074 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR 01075 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED 01076 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED 01077 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR 01078 #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED 01079 #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING 01080 #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE 01081 01082 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION 01083 #define __HAL_ADC_JSQR_RK ADC_JSQR_RK 01084 #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT 01085 #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR 01086 #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION 01087 #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE 01088 #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS 01089 #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS 01090 #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM 01091 #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT 01092 #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS 01093 #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN 01094 #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ 01095 #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET 01096 #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET 01097 #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL 01098 #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL 01099 #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET 01100 #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET 01101 #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD 01102 01103 #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION 01104 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION 01105 #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION 01106 #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER 01107 #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI 01108 #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE 01109 #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE 01110 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER 01111 #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER 01112 #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE 01113 01114 #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT 01115 #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT 01116 #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL 01117 #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM 01118 #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET 01119 #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE 01120 #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE 01121 #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER 01122 01123 #define __HAL_ADC_SQR1 ADC_SQR1 01124 #define __HAL_ADC_SMPR1 ADC_SMPR1 01125 #define __HAL_ADC_SMPR2 ADC_SMPR2 01126 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK 01127 #define __HAL_ADC_SQR2_RK ADC_SQR2_RK 01128 #define __HAL_ADC_SQR1_RK ADC_SQR1_RK 01129 #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS 01130 #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS 01131 #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV 01132 #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection 01133 #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq 01134 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION 01135 #define __HAL_ADC_JSQR ADC_JSQR 01136 01137 #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL 01138 #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS 01139 #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF 01140 #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT 01141 #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS 01142 #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN 01143 #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR 01144 #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ 01145 01146 /** 01147 * @} 01148 */ 01149 01150 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose 01151 * @{ 01152 */ 01153 #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT 01154 #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT 01155 #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT 01156 #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE 01157 01158 /** 01159 * @} 01160 */ 01161 01162 /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose 01163 * @{ 01164 */ 01165 #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 01166 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 01167 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 01168 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 01169 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 01170 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 01171 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 01172 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 01173 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 01174 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 01175 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 01176 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 01177 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 01178 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 01179 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 01180 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 01181 01182 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 01183 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 01184 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 01185 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 01186 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 01187 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 01188 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 01189 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 01190 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 01191 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 01192 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 01193 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 01194 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 01195 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 01196 01197 01198 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 01199 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 01200 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 01201 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 01202 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 01203 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 01204 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC 01205 #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC 01206 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG 01207 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG 01208 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG 01209 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG 01210 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT 01211 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT 01212 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT 01213 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT 01214 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT 01215 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT 01216 #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 01217 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 01218 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 01219 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 01220 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 01221 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 01222 01223 /** 01224 * @} 01225 */ 01226 01227 /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose 01228 * @{ 01229 */ 01230 #if defined(STM32F3) 01231 #define COMP_START __HAL_COMP_ENABLE 01232 #define COMP_STOP __HAL_COMP_DISABLE 01233 #define COMP_LOCK __HAL_COMP_LOCK 01234 01235 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 01236 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 01237 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 01238 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) 01239 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 01240 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 01241 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) 01242 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 01243 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 01244 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) 01245 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 01246 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 01247 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) 01248 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 01249 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 01250 __HAL_COMP_COMP6_EXTI_ENABLE_IT()) 01251 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 01252 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 01253 __HAL_COMP_COMP6_EXTI_DISABLE_IT()) 01254 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 01255 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 01256 __HAL_COMP_COMP6_EXTI_GET_FLAG()) 01257 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 01258 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 01259 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) 01260 # endif 01261 # if defined(STM32F302xE) || defined(STM32F302xC) 01262 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 01263 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 01264 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 01265 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) 01266 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 01267 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 01268 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 01269 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) 01270 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 01271 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 01272 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 01273 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) 01274 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 01275 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 01276 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 01277 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) 01278 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 01279 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 01280 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 01281 __HAL_COMP_COMP6_EXTI_ENABLE_IT()) 01282 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 01283 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 01284 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 01285 __HAL_COMP_COMP6_EXTI_DISABLE_IT()) 01286 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 01287 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 01288 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 01289 __HAL_COMP_COMP6_EXTI_GET_FLAG()) 01290 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 01291 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 01292 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 01293 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) 01294 # endif 01295 # if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) 01296 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 01297 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 01298 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ 01299 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 01300 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ 01301 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ 01302 __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) 01303 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 01304 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 01305 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ 01306 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 01307 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ 01308 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ 01309 __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) 01310 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 01311 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 01312 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ 01313 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 01314 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ 01315 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ 01316 __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) 01317 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 01318 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 01319 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ 01320 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 01321 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ 01322 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ 01323 __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) 01324 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 01325 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 01326 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ 01327 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 01328 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ 01329 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ 01330 __HAL_COMP_COMP7_EXTI_ENABLE_IT()) 01331 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 01332 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 01333 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ 01334 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 01335 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ 01336 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ 01337 __HAL_COMP_COMP7_EXTI_DISABLE_IT()) 01338 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 01339 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 01340 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ 01341 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 01342 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ 01343 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ 01344 __HAL_COMP_COMP7_EXTI_GET_FLAG()) 01345 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 01346 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 01347 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ 01348 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 01349 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ 01350 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ 01351 __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) 01352 # endif 01353 # if defined(STM32F373xC) ||defined(STM32F378xx) 01354 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 01355 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) 01356 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 01357 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) 01358 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 01359 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) 01360 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 01361 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) 01362 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 01363 __HAL_COMP_COMP2_EXTI_ENABLE_IT()) 01364 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 01365 __HAL_COMP_COMP2_EXTI_DISABLE_IT()) 01366 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 01367 __HAL_COMP_COMP2_EXTI_GET_FLAG()) 01368 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 01369 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) 01370 # endif 01371 #else 01372 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 01373 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) 01374 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 01375 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) 01376 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 01377 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) 01378 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 01379 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) 01380 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 01381 __HAL_COMP_COMP2_EXTI_ENABLE_IT()) 01382 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 01383 __HAL_COMP_COMP2_EXTI_DISABLE_IT()) 01384 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 01385 __HAL_COMP_COMP2_EXTI_GET_FLAG()) 01386 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 01387 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) 01388 #endif 01389 01390 #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE 01391 01392 /** 01393 * @} 01394 */ 01395 01396 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose 01397 * @{ 01398 */ 01399 01400 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ 01401 ((WAVE) == DAC_WAVE_NOISE)|| \ 01402 ((WAVE) == DAC_WAVE_TRIANGLE)) 01403 01404 /** 01405 * @} 01406 */ 01407 01408 /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose 01409 * @{ 01410 */ 01411 01412 #define IS_WRPAREA IS_OB_WRPAREA 01413 #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM 01414 #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM 01415 #define IS_TYPEERASE IS_FLASH_TYPEERASE 01416 #define IS_NBSECTORS IS_FLASH_NBSECTORS 01417 #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE 01418 01419 /** 01420 * @} 01421 */ 01422 01423 /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose 01424 * @{ 01425 */ 01426 01427 #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 01428 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START 01429 #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE 01430 #define __HAL_I2C_RISE_TIME I2C_RISE_TIME 01431 #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD 01432 #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST 01433 #define __HAL_I2C_SPEED I2C_SPEED 01434 #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE 01435 #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ 01436 #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS 01437 #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE 01438 #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ 01439 #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB 01440 #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB 01441 #define __HAL_I2C_FREQRANGE I2C_FREQRANGE 01442 /** 01443 * @} 01444 */ 01445 01446 /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose 01447 * @{ 01448 */ 01449 01450 #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE 01451 #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT 01452 01453 /** 01454 * @} 01455 */ 01456 01457 /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose 01458 * @{ 01459 */ 01460 01461 #define __IRDA_DISABLE __HAL_IRDA_DISABLE 01462 #define __IRDA_ENABLE __HAL_IRDA_ENABLE 01463 01464 #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE 01465 #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION 01466 #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE 01467 #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION 01468 01469 #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE 01470 01471 01472 /** 01473 * @} 01474 */ 01475 01476 01477 /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose 01478 * @{ 01479 */ 01480 #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS 01481 #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS 01482 /** 01483 * @} 01484 */ 01485 01486 01487 /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose 01488 * @{ 01489 */ 01490 01491 #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT 01492 #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT 01493 #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE 01494 01495 /** 01496 * @} 01497 */ 01498 01499 01500 /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose 01501 * @{ 01502 */ 01503 #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD 01504 #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX 01505 #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX 01506 #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX 01507 #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX 01508 #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L 01509 #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H 01510 #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM 01511 #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES 01512 #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX 01513 #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT 01514 #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION 01515 #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET 01516 01517 /** 01518 * @} 01519 */ 01520 01521 01522 /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose 01523 * @{ 01524 */ 01525 #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT 01526 #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT 01527 #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE 01528 #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 01529 #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE 01530 #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 01531 #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE 01532 #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE 01533 #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE 01534 #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE 01535 #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE 01536 #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE 01537 #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine 01538 #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine 01539 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig 01540 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig 01541 #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) 01542 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT 01543 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT 01544 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE 01545 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 01546 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE 01547 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 01548 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 01549 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 01550 #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) 01551 #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) 01552 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention 01553 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention 01554 #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 01555 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 01556 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE 01557 #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE 01558 #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB 01559 #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB 01560 01561 #if defined (STM32F4) 01562 #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() 01563 #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() 01564 #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() 01565 #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() 01566 #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() 01567 #else 01568 #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG 01569 #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT 01570 #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT 01571 #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT 01572 #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG 01573 #endif /* STM32F4 */ 01574 /** 01575 * @} 01576 */ 01577 01578 01579 /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose 01580 * @{ 01581 */ 01582 01583 #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI 01584 #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI 01585 01586 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback 01587 #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) 01588 01589 #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE 01590 #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE 01591 #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE 01592 #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE 01593 #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET 01594 #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET 01595 #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE 01596 #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE 01597 #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET 01598 #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET 01599 #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE 01600 #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE 01601 #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE 01602 #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE 01603 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET 01604 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET 01605 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE 01606 #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE 01607 #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET 01608 #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET 01609 #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE 01610 #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE 01611 #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE 01612 #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE 01613 #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET 01614 #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET 01615 #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE 01616 #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE 01617 #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE 01618 #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE 01619 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET 01620 #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET 01621 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE 01622 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE 01623 #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET 01624 #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET 01625 #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET 01626 #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET 01627 #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET 01628 #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET 01629 #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET 01630 #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET 01631 #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET 01632 #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET 01633 #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET 01634 #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET 01635 #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET 01636 #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET 01637 #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE 01638 #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE 01639 #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET 01640 #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET 01641 #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE 01642 #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE 01643 #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE 01644 #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE 01645 #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET 01646 #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET 01647 #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE 01648 #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE 01649 #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET 01650 #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET 01651 #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE 01652 #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE 01653 #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET 01654 #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET 01655 #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE 01656 #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE 01657 #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE 01658 #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE 01659 #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET 01660 #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET 01661 #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE 01662 #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE 01663 #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET 01664 #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET 01665 #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE 01666 #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE 01667 #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE 01668 #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE 01669 #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET 01670 #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET 01671 #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE 01672 #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE 01673 #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET 01674 #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET 01675 #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE 01676 #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE 01677 #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE 01678 #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE 01679 #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET 01680 #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET 01681 #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE 01682 #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE 01683 #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET 01684 #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET 01685 #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE 01686 #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE 01687 #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE 01688 #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE 01689 #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET 01690 #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET 01691 #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE 01692 #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE 01693 #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE 01694 #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE 01695 #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET 01696 #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET 01697 #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE 01698 #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE 01699 #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE 01700 #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE 01701 #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET 01702 #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET 01703 #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE 01704 #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE 01705 #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET 01706 #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET 01707 #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE 01708 #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE 01709 #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE 01710 #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE 01711 #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE 01712 #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE 01713 #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE 01714 #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE 01715 #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE 01716 #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE 01717 #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET 01718 #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET 01719 #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE 01720 #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE 01721 #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET 01722 #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET 01723 #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE 01724 #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE 01725 #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE 01726 #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE 01727 #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE 01728 #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE 01729 #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET 01730 #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET 01731 #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE 01732 #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE 01733 #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE 01734 #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE 01735 #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE 01736 #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE 01737 #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET 01738 #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET 01739 #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE 01740 #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE 01741 #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE 01742 #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE 01743 #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET 01744 #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET 01745 #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE 01746 #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE 01747 #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE 01748 #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE 01749 #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET 01750 #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET 01751 #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE 01752 #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE 01753 #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE 01754 #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE 01755 #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET 01756 #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET 01757 #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE 01758 #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE 01759 #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE 01760 #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE 01761 #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET 01762 #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET 01763 #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE 01764 #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE 01765 #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE 01766 #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE 01767 #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET 01768 #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET 01769 #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE 01770 #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE 01771 #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE 01772 #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE 01773 #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET 01774 #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET 01775 #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE 01776 #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE 01777 #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE 01778 #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE 01779 #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET 01780 #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET 01781 #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE 01782 #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE 01783 #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE 01784 #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE 01785 #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET 01786 #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET 01787 #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE 01788 #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE 01789 #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE 01790 #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE 01791 #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET 01792 #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET 01793 #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE 01794 #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE 01795 #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE 01796 #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE 01797 #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET 01798 #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET 01799 #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE 01800 #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE 01801 #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE 01802 #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE 01803 #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET 01804 #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET 01805 #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE 01806 #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE 01807 #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE 01808 #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE 01809 #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET 01810 #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET 01811 #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE 01812 #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE 01813 #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE 01814 #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE 01815 #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET 01816 #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET 01817 #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE 01818 #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE 01819 #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE 01820 #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE 01821 #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET 01822 #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET 01823 #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE 01824 #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE 01825 #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE 01826 #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE 01827 #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET 01828 #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET 01829 #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE 01830 #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE 01831 #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE 01832 #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE 01833 #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET 01834 #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET 01835 #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE 01836 #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE 01837 #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE 01838 #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE 01839 #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET 01840 #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET 01841 #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE 01842 #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE 01843 #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE 01844 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE 01845 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET 01846 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET 01847 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE 01848 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE 01849 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE 01850 #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE 01851 #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET 01852 #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET 01853 #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE 01854 #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE 01855 #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE 01856 #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE 01857 #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET 01858 #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET 01859 #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE 01860 #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE 01861 #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE 01862 #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE 01863 #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET 01864 #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET 01865 #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE 01866 #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE 01867 #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE 01868 #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE 01869 #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE 01870 #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE 01871 #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET 01872 #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET 01873 #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE 01874 #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE 01875 #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE 01876 #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE 01877 #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET 01878 #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET 01879 #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE 01880 #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE 01881 #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE 01882 #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE 01883 #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET 01884 #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET 01885 #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE 01886 #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE 01887 #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE 01888 #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE 01889 #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET 01890 #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET 01891 #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE 01892 #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE 01893 #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE 01894 #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE 01895 #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE 01896 #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE 01897 #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE 01898 #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE 01899 #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE 01900 #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE 01901 #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET 01902 #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET 01903 #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE 01904 #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE 01905 #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE 01906 #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE 01907 #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET 01908 #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET 01909 #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE 01910 #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE 01911 #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE 01912 #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE 01913 #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET 01914 #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET 01915 #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE 01916 #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE 01917 #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET 01918 #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET 01919 #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE 01920 #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE 01921 #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET 01922 #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET 01923 #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE 01924 #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE 01925 #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET 01926 #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET 01927 #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE 01928 #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE 01929 #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET 01930 #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET 01931 #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE 01932 #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE 01933 #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET 01934 #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET 01935 #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE 01936 #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE 01937 #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE 01938 #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE 01939 #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET 01940 #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET 01941 #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE 01942 #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE 01943 #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE 01944 #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE 01945 #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET 01946 #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET 01947 #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE 01948 #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE 01949 #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE 01950 #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE 01951 #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET 01952 #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET 01953 #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE 01954 #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE 01955 #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE 01956 #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE 01957 #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET 01958 #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET 01959 #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE 01960 #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE 01961 #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE 01962 #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE 01963 #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET 01964 #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET 01965 #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE 01966 #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE 01967 #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE 01968 #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE 01969 #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET 01970 #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET 01971 #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE 01972 #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE 01973 #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE 01974 #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE 01975 #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET 01976 #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET 01977 #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE 01978 #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE 01979 #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE 01980 #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE 01981 #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET 01982 #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET 01983 #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE 01984 #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE 01985 #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE 01986 #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE 01987 #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET 01988 #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET 01989 #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE 01990 #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE 01991 #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE 01992 #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE 01993 #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET 01994 #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET 01995 #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE 01996 #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE 01997 #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET 01998 #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET 01999 #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE 02000 #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE 02001 #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE 02002 #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE 02003 #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET 02004 #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET 02005 #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE 02006 #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE 02007 #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE 02008 #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE 02009 #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET 02010 #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET 02011 #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE 02012 #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE 02013 #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE 02014 #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE 02015 #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET 02016 #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET 02017 #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE 02018 #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE 02019 #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE 02020 #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE 02021 #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET 02022 #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET 02023 #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE 02024 #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE 02025 #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE 02026 #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE 02027 #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET 02028 #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET 02029 #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE 02030 #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE 02031 #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE 02032 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE 02033 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET 02034 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET 02035 #define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE 02036 #define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE 02037 #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE 02038 #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE 02039 #define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET 02040 #define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET 02041 #define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE 02042 #define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE 02043 #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE 02044 #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE 02045 #define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET 02046 #define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET 02047 #define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE 02048 #define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE 02049 #define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET 02050 #define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET 02051 #define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE 02052 #define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE 02053 #define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET 02054 #define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET 02055 #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE 02056 #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE 02057 #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET 02058 #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE 02059 #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE 02060 #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE 02061 #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE 02062 #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET 02063 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE 02064 #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE 02065 #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE 02066 #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE 02067 #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET 02068 #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET 02069 #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE 02070 #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE 02071 #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET 02072 #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET 02073 #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE 02074 #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE 02075 #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE 02076 #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE 02077 #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET 02078 #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET 02079 #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE 02080 #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE 02081 #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE 02082 #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE 02083 #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE 02084 #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE 02085 #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET 02086 #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET 02087 #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE 02088 #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE 02089 02090 #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET 02091 #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET 02092 #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE 02093 #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE 02094 #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE 02095 #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE 02096 #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE 02097 #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE 02098 #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE 02099 #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE 02100 #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE 02101 #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE 02102 #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE 02103 #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE 02104 #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE 02105 #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE 02106 #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE 02107 #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE 02108 #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE 02109 #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET 02110 #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET 02111 #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE 02112 #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE 02113 #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE 02114 #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE 02115 #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE 02116 #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET 02117 #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET 02118 #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE 02119 #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE 02120 #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE 02121 #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE 02122 #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET 02123 #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET 02124 #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE 02125 #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE 02126 #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE 02127 #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE 02128 #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET 02129 #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET 02130 #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE 02131 #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE 02132 #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE 02133 #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE 02134 #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE 02135 #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE 02136 #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE 02137 #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE 02138 #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE 02139 #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE 02140 #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE 02141 #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE 02142 #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE 02143 #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE 02144 #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE 02145 #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE 02146 #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE 02147 #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE 02148 #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE 02149 #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE 02150 #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE 02151 #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET 02152 #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET 02153 #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE 02154 #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE 02155 #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE 02156 #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE 02157 #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET 02158 #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET 02159 #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE 02160 #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE 02161 #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE 02162 #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE 02163 #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET 02164 #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET 02165 #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE 02166 #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE 02167 #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE 02168 #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE 02169 #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET 02170 #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET 02171 #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE 02172 #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE 02173 #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE 02174 #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE 02175 #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET 02176 #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE 02177 #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE 02178 #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE 02179 #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE 02180 #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE 02181 #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE 02182 #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET 02183 #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET 02184 #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE 02185 #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE 02186 #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE 02187 #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE 02188 #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET 02189 #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET 02190 #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE 02191 #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE 02192 #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE 02193 #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE 02194 #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET 02195 #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET 02196 #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE 02197 #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE 02198 #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE 02199 #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE 02200 #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET 02201 #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET 02202 #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE 02203 #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 02204 #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE 02205 #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE 02206 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED 02207 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED 02208 #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET 02209 #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET 02210 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE 02211 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 02212 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED 02213 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED 02214 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET 02215 #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE 02216 #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE 02217 #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE 02218 #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE 02219 #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE 02220 #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE 02221 #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE 02222 #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE 02223 #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE 02224 #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET 02225 #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET 02226 #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE 02227 #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE 02228 #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET 02229 #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET 02230 #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE 02231 #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE 02232 #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE 02233 #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE 02234 #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET 02235 #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET 02236 #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE 02237 #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE 02238 02239 /* alias define maintained for legacy */ 02240 #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET 02241 #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET 02242 02243 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE 02244 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE 02245 #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE 02246 #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE 02247 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE 02248 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE 02249 #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE 02250 #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE 02251 #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE 02252 #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE 02253 #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE 02254 #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE 02255 #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE 02256 #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE 02257 #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE 02258 #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE 02259 #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE 02260 #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE 02261 #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE 02262 #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE 02263 #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE 02264 #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE 02265 02266 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET 02267 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET 02268 #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET 02269 #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET 02270 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET 02271 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET 02272 #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET 02273 #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET 02274 #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET 02275 #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET 02276 #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET 02277 #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET 02278 #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET 02279 #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET 02280 #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET 02281 #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET 02282 #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET 02283 #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET 02284 #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET 02285 #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET 02286 #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET 02287 #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET 02288 02289 #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED 02290 #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED 02291 #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED 02292 #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED 02293 #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED 02294 #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED 02295 #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED 02296 #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED 02297 #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED 02298 #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED 02299 #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED 02300 #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED 02301 #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED 02302 #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED 02303 #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED 02304 #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED 02305 #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED 02306 #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED 02307 #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED 02308 #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED 02309 #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED 02310 #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED 02311 #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED 02312 #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED 02313 #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED 02314 #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED 02315 #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED 02316 #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED 02317 #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED 02318 #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED 02319 #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED 02320 #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED 02321 #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED 02322 #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED 02323 #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED 02324 #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED 02325 #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED 02326 #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED 02327 #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED 02328 #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED 02329 #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED 02330 #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED 02331 #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED 02332 #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED 02333 #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED 02334 #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED 02335 #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED 02336 #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED 02337 #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED 02338 #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED 02339 #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED 02340 #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED 02341 #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED 02342 #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED 02343 #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED 02344 #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED 02345 #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED 02346 #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED 02347 #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED 02348 #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED 02349 #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED 02350 #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED 02351 #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED 02352 #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED 02353 #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED 02354 #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED 02355 #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED 02356 #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED 02357 #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED 02358 #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED 02359 #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED 02360 #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED 02361 #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED 02362 #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED 02363 #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED 02364 #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED 02365 #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED 02366 #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED 02367 #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED 02368 #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED 02369 #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED 02370 #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED 02371 #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED 02372 #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED 02373 #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED 02374 #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED 02375 #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED 02376 #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED 02377 #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED 02378 #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED 02379 #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED 02380 #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED 02381 #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED 02382 #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED 02383 #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED 02384 #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED 02385 #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED 02386 #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED 02387 #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED 02388 #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED 02389 #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED 02390 #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED 02391 #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED 02392 #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED 02393 #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED 02394 #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED 02395 #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED 02396 #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED 02397 #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED 02398 #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED 02399 #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED 02400 #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED 02401 #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED 02402 #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED 02403 #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED 02404 #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED 02405 02406 #if defined(STM32F4) 02407 #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET 02408 #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET 02409 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE 02410 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE 02411 #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE 02412 #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE 02413 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED 02414 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED 02415 #define Sdmmc1ClockSelection SdioClockSelection 02416 #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO 02417 #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 02418 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK 02419 #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG 02420 #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE 02421 #endif 02422 02423 #if defined(STM32F7) || defined(STM32L4) 02424 #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET 02425 #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET 02426 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE 02427 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE 02428 #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE 02429 #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE 02430 #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED 02431 #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED 02432 #define SdioClockSelection Sdmmc1ClockSelection 02433 #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 02434 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG 02435 #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE 02436 #endif 02437 02438 #if defined(STM32F7) 02439 #define RCC_SDIOCLKSOURCE_CK48 RCC_SDMMC1CLKSOURCE_CLK48 02440 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK 02441 #endif 02442 02443 #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG 02444 #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG 02445 02446 #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE 02447 02448 #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE 02449 #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE 02450 #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK 02451 #define IS_RCC_HCLK_DIV IS_RCC_PCLK 02452 #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK 02453 02454 #define RCC_IT_HSI14 RCC_IT_HSI14RDY 02455 02456 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE 02457 #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG 02458 #define RCC_MCO_NODIV RCC_MCODIV_1 02459 #define RCC_MCO_DIV1 RCC_MCODIV_1 02460 #define RCC_MCO_DIV2 RCC_MCODIV_2 02461 #define RCC_MCO_DIV4 RCC_MCODIV_4 02462 #define RCC_MCO_DIV8 RCC_MCODIV_8 02463 #define RCC_MCO_DIV16 RCC_MCODIV_16 02464 #define RCC_MCO_DIV32 RCC_MCODIV_32 02465 #define RCC_MCO_DIV64 RCC_MCODIV_64 02466 #define RCC_MCO_DIV128 RCC_MCODIV_128 02467 #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK 02468 #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI 02469 #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE 02470 #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK 02471 #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI 02472 #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 02473 #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 02474 #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE 02475 #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK 02476 #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK 02477 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 02478 02479 #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK 02480 02481 #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 02482 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL 02483 #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI 02484 #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL 02485 #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL 02486 #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 02487 #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 02488 #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 02489 02490 #define HSION_BitNumber RCC_HSION_BIT_NUMBER 02491 #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER 02492 #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER 02493 #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER 02494 #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER 02495 #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER 02496 #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER 02497 #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER 02498 #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER 02499 #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER 02500 #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER 02501 #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER 02502 #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER 02503 #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER 02504 #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER 02505 #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER 02506 #define LSION_BitNumber RCC_LSION_BIT_NUMBER 02507 #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER 02508 #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER 02509 #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER 02510 #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER 02511 #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER 02512 #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER 02513 #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER 02514 #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER 02515 #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER 02516 #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS 02517 #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS 02518 #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS 02519 #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS 02520 #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE 02521 #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE 02522 02523 #define CR_HSION_BB RCC_CR_HSION_BB 02524 #define CR_CSSON_BB RCC_CR_CSSON_BB 02525 #define CR_PLLON_BB RCC_CR_PLLON_BB 02526 #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB 02527 #define CR_MSION_BB RCC_CR_MSION_BB 02528 #define CSR_LSION_BB RCC_CSR_LSION_BB 02529 #define CSR_LSEON_BB RCC_CSR_LSEON_BB 02530 #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB 02531 #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB 02532 #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB 02533 #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB 02534 #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB 02535 #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB 02536 #define CR_HSEON_BB RCC_CR_HSEON_BB 02537 #define CSR_RMVF_BB RCC_CSR_RMVF_BB 02538 #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB 02539 #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB 02540 02541 #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE 02542 #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE 02543 #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE 02544 #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE 02545 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE 02546 02547 #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT 02548 /** 02549 * @} 02550 */ 02551 02552 /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose 02553 * @{ 02554 */ 02555 #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) 02556 02557 /** 02558 * @} 02559 */ 02560 02561 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose 02562 * @{ 02563 */ 02564 02565 #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG 02566 #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT 02567 #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT 02568 02569 #if defined (STM32F1) 02570 #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() 02571 02572 #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() 02573 02574 #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() 02575 02576 #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() 02577 02578 #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() 02579 #else 02580 #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ 02581 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ 02582 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) 02583 #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ 02584 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ 02585 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) 02586 #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ 02587 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ 02588 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) 02589 #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ 02590 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ 02591 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) 02592 #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ 02593 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ 02594 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) 02595 #endif /* STM32F1 */ 02596 02597 #define IS_ALARM IS_RTC_ALARM 02598 #define IS_ALARM_MASK IS_RTC_ALARM_MASK 02599 #define IS_TAMPER IS_RTC_TAMPER 02600 #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE 02601 #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER 02602 #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT 02603 #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE 02604 #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION 02605 #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE 02606 #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ 02607 #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION 02608 #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER 02609 #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK 02610 #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER 02611 02612 #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE 02613 #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE 02614 02615 /** 02616 * @} 02617 */ 02618 02619 /** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose 02620 * @{ 02621 */ 02622 02623 #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE 02624 #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS 02625 02626 #if defined(STM32F4) 02627 #define SD_SDMMC_DISABLED SD_SDIO_DISABLED 02628 #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY 02629 #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED 02630 #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION 02631 #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND 02632 #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT 02633 #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED 02634 #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE 02635 #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE 02636 #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE 02637 #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL 02638 #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT 02639 #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT 02640 #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG 02641 #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG 02642 #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT 02643 #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT 02644 #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS 02645 #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT 02646 #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND 02647 /* alias CMSIS */ 02648 #define SDMMC1_IRQn SDIO_IRQn 02649 #define SDMMC1_IRQHandler SDIO_IRQHandler 02650 #endif 02651 02652 #if defined(STM32F7) || defined(STM32L4) 02653 #define SD_SDIO_DISABLED SD_SDMMC_DISABLED 02654 #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY 02655 #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED 02656 #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION 02657 #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND 02658 #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT 02659 #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED 02660 #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE 02661 #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE 02662 #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE 02663 #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE 02664 #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT 02665 #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT 02666 #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG 02667 #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG 02668 #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT 02669 #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT 02670 #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS 02671 #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT 02672 #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND 02673 /* alias CMSIS for compatibilities */ 02674 #define SDIO_IRQn SDMMC1_IRQn 02675 #define SDIO_IRQHandler SDMMC1_IRQHandler 02676 #endif 02677 /** 02678 * @} 02679 */ 02680 02681 /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose 02682 * @{ 02683 */ 02684 02685 #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT 02686 #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT 02687 #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE 02688 #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE 02689 #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE 02690 #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE 02691 02692 #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE 02693 #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE 02694 02695 #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE 02696 02697 /** 02698 * @} 02699 */ 02700 02701 /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose 02702 * @{ 02703 */ 02704 #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 02705 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 02706 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START 02707 #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH 02708 #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR 02709 #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE 02710 #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE 02711 #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED 02712 /** 02713 * @} 02714 */ 02715 02716 /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose 02717 * @{ 02718 */ 02719 02720 #define __HAL_SPI_1LINE_TX SPI_1LINE_TX 02721 #define __HAL_SPI_1LINE_RX SPI_1LINE_RX 02722 #define __HAL_SPI_RESET_CRC SPI_RESET_CRC 02723 02724 /** 02725 * @} 02726 */ 02727 02728 /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose 02729 * @{ 02730 */ 02731 02732 #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE 02733 #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION 02734 #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE 02735 #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION 02736 02737 #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD 02738 02739 #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE 02740 #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE 02741 02742 /** 02743 * @} 02744 */ 02745 02746 02747 /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose 02748 * @{ 02749 */ 02750 02751 #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT 02752 #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT 02753 #define __USART_ENABLE __HAL_USART_ENABLE 02754 #define __USART_DISABLE __HAL_USART_DISABLE 02755 02756 #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE 02757 #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE 02758 02759 /** 02760 * @} 02761 */ 02762 02763 /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose 02764 * @{ 02765 */ 02766 #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE 02767 02768 #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 02769 #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 02770 #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 02771 #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE 02772 02773 #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 02774 #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 02775 #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 02776 #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE 02777 02778 #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT 02779 #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT 02780 #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG 02781 #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG 02782 #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE 02783 #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE 02784 #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 02785 02786 #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT 02787 #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT 02788 #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG 02789 #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG 02790 #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE 02791 #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE 02792 #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 02793 #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT 02794 02795 #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT 02796 #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT 02797 #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG 02798 #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG 02799 #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE 02800 #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE 02801 #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 02802 #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT 02803 02804 #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup 02805 #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup 02806 02807 #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo 02808 #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo 02809 /** 02810 * @} 02811 */ 02812 02813 /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose 02814 * @{ 02815 */ 02816 #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE 02817 #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE 02818 02819 #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE 02820 #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT 02821 02822 #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE 02823 02824 #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN 02825 #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER 02826 #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER 02827 #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER 02828 #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD 02829 #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD 02830 #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION 02831 #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION 02832 #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER 02833 #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER 02834 #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE 02835 #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE 02836 02837 #define TIM_TS_ITR0 ((uint32_t)0x0000) 02838 #define TIM_TS_ITR1 ((uint32_t)0x0010) 02839 #define TIM_TS_ITR2 ((uint32_t)0x0020) 02840 #define TIM_TS_ITR3 ((uint32_t)0x0030) 02841 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ 02842 ((SELECTION) == TIM_TS_ITR1) || \ 02843 ((SELECTION) == TIM_TS_ITR2) || \ 02844 ((SELECTION) == TIM_TS_ITR3)) 02845 02846 #define TIM_CHANNEL_1 ((uint32_t)0x0000) 02847 #define TIM_CHANNEL_2 ((uint32_t)0x0004) 02848 #define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ 02849 ((CHANNEL) == TIM_CHANNEL_2)) 02850 02851 #define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000) 02852 #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE) 02853 02854 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \ 02855 ((STATE) == TIM_OUTPUTNSTATE_ENABLE)) 02856 02857 #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000) 02858 #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) 02859 02860 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \ 02861 ((STATE) == TIM_OUTPUTSTATE_ENABLE)) 02862 /** 02863 * @} 02864 */ 02865 02866 /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose 02867 * @{ 02868 */ 02869 02870 #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT 02871 #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT 02872 #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG 02873 #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG 02874 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER 02875 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER 02876 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER 02877 02878 #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE 02879 #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE 02880 #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE 02881 /** 02882 * @} 02883 */ 02884 02885 /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose 02886 * @{ 02887 */ 02888 #define __HAL_LTDC_LAYER LTDC_LAYER 02889 /** 02890 * @} 02891 */ 02892 02893 /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose 02894 * @{ 02895 */ 02896 #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE 02897 #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE 02898 #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE 02899 #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE 02900 #define SAI_STREOMODE SAI_STEREOMODE 02901 #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY 02902 #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL 02903 #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL 02904 #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL 02905 #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL 02906 #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL 02907 #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE 02908 02909 /** 02910 * @} 02911 */ 02912 02913 02914 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose 02915 * @{ 02916 */ 02917 02918 /** 02919 * @} 02920 */ 02921 02922 #ifdef __cplusplus 02923 } 02924 #endif 02925 02926 #endif /* ___STM32_HAL_LEGACY */ 02927 02928 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 02929 02930
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