Eric Lewiston / STM32L4xx_HAL_Driver

Hal Drivers for L4

Dependents:   BSP OneHopeOnePrayer FINAL_AUDIO_RECORD AudioDemo

Fork of STM32L4xx_HAL_Driver by Senior Design: Sound Monitor

Src/stm32l4xx_ll_fmc.c@0:80ee8f3b695e, 2015-11-02 (annotated)

Committer:
EricLew
Date:
Mon Nov 02 19:37:23 2015 +0000
Revision:
0:80ee8f3b695e
Errors are with definitions of LCD and QSPI functions. I believe all .h and .c files are  uploaded, but there may need to be certain functions called.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
EricLew 0:80ee8f3b695e 1 /**
EricLew 0:80ee8f3b695e 2 ******************************************************************************
EricLew 0:80ee8f3b695e 3 * @file stm32l4xx_ll_fmc.c
EricLew 0:80ee8f3b695e 4 * @author MCD Application Team
EricLew 0:80ee8f3b695e 5 * @version V1.1.0
EricLew 0:80ee8f3b695e 6 * @date 16-September-2015
EricLew 0:80ee8f3b695e 7 * @brief FMC Low Layer HAL module driver.
EricLew 0:80ee8f3b695e 8 * This file provides firmware functions to manage the following
EricLew 0:80ee8f3b695e 9 * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
EricLew 0:80ee8f3b695e 10 * + Initialization/de-initialization functions
EricLew 0:80ee8f3b695e 11 * + Peripheral Control functions
EricLew 0:80ee8f3b695e 12 * + Peripheral State functions
EricLew 0:80ee8f3b695e 13 *
EricLew 0:80ee8f3b695e 14 @verbatim
EricLew 0:80ee8f3b695e 15 ==============================================================================
EricLew 0:80ee8f3b695e 16 ##### FMC peripheral features #####
EricLew 0:80ee8f3b695e 17 ==============================================================================
EricLew 0:80ee8f3b695e 18 [..] The Flexible memory controller (FMC) includes following memory controllers:
EricLew 0:80ee8f3b695e 19 (+) The NOR/PSRAM memory controller
EricLew 0:80ee8f3b695e 20 (+) The NAND memory controller
EricLew 0:80ee8f3b695e 21
EricLew 0:80ee8f3b695e 22 [..] The FMC functional block makes the interface with synchronous and asynchronous static
EricLew 0:80ee8f3b695e 23 memories and 16-bit PC memory cards. Its main purposes are:
EricLew 0:80ee8f3b695e 24 (+) to translate AHB transactions into the appropriate external device protocol.
EricLew 0:80ee8f3b695e 25 (+) to meet the access time requirements of the external memory devices.
EricLew 0:80ee8f3b695e 26
EricLew 0:80ee8f3b695e 27 [..] All external memories share the addresses, data and control signals with the controller.
EricLew 0:80ee8f3b695e 28 Each external device is accessed by means of a unique Chip Select. The FMC performs
EricLew 0:80ee8f3b695e 29 only one access at a time to an external device.
EricLew 0:80ee8f3b695e 30 The main features of the FMC controller are the following:
EricLew 0:80ee8f3b695e 31 (+) Interface with static-memory mapped devices including:
EricLew 0:80ee8f3b695e 32 (++) Static random access memory (SRAM).
EricLew 0:80ee8f3b695e 33 (++) NOR Flash memory.
EricLew 0:80ee8f3b695e 34 (++) PSRAM (4 memory banks).
EricLew 0:80ee8f3b695e 35 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
EricLew 0:80ee8f3b695e 36 data
EricLew 0:80ee8f3b695e 37 (+) Independent Chip Select control for each memory bank
EricLew 0:80ee8f3b695e 38 (+) Independent configuration for each memory bank
EricLew 0:80ee8f3b695e 39
EricLew 0:80ee8f3b695e 40 @endverbatim
EricLew 0:80ee8f3b695e 41 ******************************************************************************
EricLew 0:80ee8f3b695e 42 * @attention
EricLew 0:80ee8f3b695e 43 *
EricLew 0:80ee8f3b695e 44 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
EricLew 0:80ee8f3b695e 45 *
EricLew 0:80ee8f3b695e 46 * Redistribution and use in source and binary forms, with or without modification,
EricLew 0:80ee8f3b695e 47 * are permitted provided that the following conditions are met:
EricLew 0:80ee8f3b695e 48 * 1. Redistributions of source code must retain the above copyright notice,
EricLew 0:80ee8f3b695e 49 * this list of conditions and the following disclaimer.
EricLew 0:80ee8f3b695e 50 * 2. Redistributions in binary form must reproduce the above copyright notice,
EricLew 0:80ee8f3b695e 51 * this list of conditions and the following disclaimer in the documentation
EricLew 0:80ee8f3b695e 52 * and/or other materials provided with the distribution.
EricLew 0:80ee8f3b695e 53 * 3. Neither the name of STMicroelectronics nor the names of its contributors
EricLew 0:80ee8f3b695e 54 * may be used to endorse or promote products derived from this software
EricLew 0:80ee8f3b695e 55 * without specific prior written permission.
EricLew 0:80ee8f3b695e 56 *
EricLew 0:80ee8f3b695e 57 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew 0:80ee8f3b695e 58 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew 0:80ee8f3b695e 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
EricLew 0:80ee8f3b695e 60 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
EricLew 0:80ee8f3b695e 61 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
EricLew 0:80ee8f3b695e 62 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
EricLew 0:80ee8f3b695e 63 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
EricLew 0:80ee8f3b695e 64 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
EricLew 0:80ee8f3b695e 65 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
EricLew 0:80ee8f3b695e 66 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
EricLew 0:80ee8f3b695e 67 *
EricLew 0:80ee8f3b695e 68 ******************************************************************************
EricLew 0:80ee8f3b695e 69 */
EricLew 0:80ee8f3b695e 70
EricLew 0:80ee8f3b695e 71 /* Includes ------------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 72 #include "stm32l4xx_hal.h"
EricLew 0:80ee8f3b695e 73
EricLew 0:80ee8f3b695e 74 /** @addtogroup STM32L4xx_HAL_Driver
EricLew 0:80ee8f3b695e 75 * @{
EricLew 0:80ee8f3b695e 76 */
EricLew 0:80ee8f3b695e 77
EricLew 0:80ee8f3b695e 78 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED)
EricLew 0:80ee8f3b695e 79
EricLew 0:80ee8f3b695e 80 /** @defgroup FMC_LL FMC Low Layer
EricLew 0:80ee8f3b695e 81 * @brief FMC driver modules
EricLew 0:80ee8f3b695e 82 * @{
EricLew 0:80ee8f3b695e 83 */
EricLew 0:80ee8f3b695e 84
EricLew 0:80ee8f3b695e 85 /* Private typedef -----------------------------------------------------------*/
EricLew 0:80ee8f3b695e 86 /* Private define ------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 87 /** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants
EricLew 0:80ee8f3b695e 88 * @{
EricLew 0:80ee8f3b695e 89 */
EricLew 0:80ee8f3b695e 90
EricLew 0:80ee8f3b695e 91 /* ----------------------- FMC registers bit mask --------------------------- */
EricLew 0:80ee8f3b695e 92 /* --- BCRx Register ---*/
EricLew 0:80ee8f3b695e 93 /* BCRx register clear mask */
EricLew 0:80ee8f3b695e 94 #define BCRx_CLEAR_MASK ((uint32_t)(FMC_BCRx_MBKEN | FMC_BCRx_MUXEN |\
EricLew 0:80ee8f3b695e 95 FMC_BCRx_MTYP | FMC_BCRx_MWID |\
EricLew 0:80ee8f3b695e 96 FMC_BCRx_FACCEN | FMC_BCRx_BURSTEN |\
EricLew 0:80ee8f3b695e 97 FMC_BCRx_WAITPOL | FMC_BCRx_WAITCFG |\
EricLew 0:80ee8f3b695e 98 FMC_BCRx_WREN | FMC_BCRx_WAITEN |\
EricLew 0:80ee8f3b695e 99 FMC_BCRx_EXTMOD | FMC_BCRx_ASYNCWAIT |\
EricLew 0:80ee8f3b695e 100 FMC_BCRx_CPSIZE | FMC_BCRx_CBURSTRW))
EricLew 0:80ee8f3b695e 101 /* --- BTRx Register ---*/
EricLew 0:80ee8f3b695e 102 /* BTRx register clear mask */
EricLew 0:80ee8f3b695e 103 #define BTRx_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\
EricLew 0:80ee8f3b695e 104 FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\
EricLew 0:80ee8f3b695e 105 FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\
EricLew 0:80ee8f3b695e 106 FMC_BTRx_ACCMOD))
EricLew 0:80ee8f3b695e 107
EricLew 0:80ee8f3b695e 108 /* --- BWTRx Register ---*/
EricLew 0:80ee8f3b695e 109 /* BWTRx register clear mask */
EricLew 0:80ee8f3b695e 110 #define BWTRx_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\
EricLew 0:80ee8f3b695e 111 FMC_BWTRx_DATAST | FMC_BWTRx_ACCMOD))
EricLew 0:80ee8f3b695e 112
EricLew 0:80ee8f3b695e 113 /* --- PCR Register ---*/
EricLew 0:80ee8f3b695e 114 /* PCR register clear mask */
EricLew 0:80ee8f3b695e 115 #define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN |\
EricLew 0:80ee8f3b695e 116 FMC_PCR_PTYP | FMC_PCR_PWID |\
EricLew 0:80ee8f3b695e 117 FMC_PCR_ECCEN | FMC_PCR_TCLR |\
EricLew 0:80ee8f3b695e 118 FMC_PCR_TAR | FMC_PCR_ECCPS))
EricLew 0:80ee8f3b695e 119
EricLew 0:80ee8f3b695e 120 /* --- SR Register ---*/
EricLew 0:80ee8f3b695e 121 /* SR register clear mask */
EricLew 0:80ee8f3b695e 122 #define SR_CLEAR_MASK ((uint32_t)(FMC_SR_FEMPT))
EricLew 0:80ee8f3b695e 123
EricLew 0:80ee8f3b695e 124 /* --- PMEM Register ---*/
EricLew 0:80ee8f3b695e 125 /* PMEM register clear mask */
EricLew 0:80ee8f3b695e 126 #define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM_MEMSET | FMC_PMEM_MEMWAIT |\
EricLew 0:80ee8f3b695e 127 FMC_PMEM_MEMHOLD | FMC_PMEM_MEMHIZ))
EricLew 0:80ee8f3b695e 128
EricLew 0:80ee8f3b695e 129 /* --- PATT Register ---*/
EricLew 0:80ee8f3b695e 130 /* PATT register clear mask */
EricLew 0:80ee8f3b695e 131 #define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET | FMC_PATT_ATTWAIT |\
EricLew 0:80ee8f3b695e 132 FMC_PATT_ATTHOLD | FMC_PATT_ATTHIZ))
EricLew 0:80ee8f3b695e 133 /**
EricLew 0:80ee8f3b695e 134 * @}
EricLew 0:80ee8f3b695e 135 */
EricLew 0:80ee8f3b695e 136
EricLew 0:80ee8f3b695e 137 /* Private macro -------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 138 /** @defgroup FMC_LL_Private_Macros FMC Low Layer Private Macros
EricLew 0:80ee8f3b695e 139 * @{
EricLew 0:80ee8f3b695e 140 */
EricLew 0:80ee8f3b695e 141
EricLew 0:80ee8f3b695e 142 /**
EricLew 0:80ee8f3b695e 143 * @}
EricLew 0:80ee8f3b695e 144 */
EricLew 0:80ee8f3b695e 145
EricLew 0:80ee8f3b695e 146 /* Private variables ---------------------------------------------------------*/
EricLew 0:80ee8f3b695e 147 /* Private function prototypes -----------------------------------------------*/
EricLew 0:80ee8f3b695e 148 /* Exported functions --------------------------------------------------------*/
EricLew 0:80ee8f3b695e 149
EricLew 0:80ee8f3b695e 150 /** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
EricLew 0:80ee8f3b695e 151 * @{
EricLew 0:80ee8f3b695e 152 */
EricLew 0:80ee8f3b695e 153
EricLew 0:80ee8f3b695e 154 /** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions
EricLew 0:80ee8f3b695e 155 * @brief NORSRAM Controller functions
EricLew 0:80ee8f3b695e 156 *
EricLew 0:80ee8f3b695e 157 @verbatim
EricLew 0:80ee8f3b695e 158 ==============================================================================
EricLew 0:80ee8f3b695e 159 ##### How to use NORSRAM device driver #####
EricLew 0:80ee8f3b695e 160 ==============================================================================
EricLew 0:80ee8f3b695e 161
EricLew 0:80ee8f3b695e 162 [..]
EricLew 0:80ee8f3b695e 163 This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
EricLew 0:80ee8f3b695e 164 to run the NORSRAM external devices.
EricLew 0:80ee8f3b695e 165
EricLew 0:80ee8f3b695e 166 (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
EricLew 0:80ee8f3b695e 167 (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
EricLew 0:80ee8f3b695e 168 (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
EricLew 0:80ee8f3b695e 169 (+) FMC NORSRAM bank extended timing configuration using the function
EricLew 0:80ee8f3b695e 170 FMC_NORSRAM_Extended_Timing_Init()
EricLew 0:80ee8f3b695e 171 (+) FMC NORSRAM bank enable/disable write operation using the functions
EricLew 0:80ee8f3b695e 172 FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
EricLew 0:80ee8f3b695e 173
EricLew 0:80ee8f3b695e 174
EricLew 0:80ee8f3b695e 175 @endverbatim
EricLew 0:80ee8f3b695e 176 * @{
EricLew 0:80ee8f3b695e 177 */
EricLew 0:80ee8f3b695e 178
EricLew 0:80ee8f3b695e 179 /** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
EricLew 0:80ee8f3b695e 180 * @brief Initialization and Configuration functions
EricLew 0:80ee8f3b695e 181 *
EricLew 0:80ee8f3b695e 182 @verbatim
EricLew 0:80ee8f3b695e 183 ==============================================================================
EricLew 0:80ee8f3b695e 184 ##### Initialization and de-initialization functions #####
EricLew 0:80ee8f3b695e 185 ==============================================================================
EricLew 0:80ee8f3b695e 186 [..]
EricLew 0:80ee8f3b695e 187 This section provides functions allowing to:
EricLew 0:80ee8f3b695e 188 (+) Initialize and configure the FMC NORSRAM interface
EricLew 0:80ee8f3b695e 189 (+) De-initialize the FMC NORSRAM interface
EricLew 0:80ee8f3b695e 190 (+) Configure the FMC clock and associated GPIOs
EricLew 0:80ee8f3b695e 191
EricLew 0:80ee8f3b695e 192 @endverbatim
EricLew 0:80ee8f3b695e 193 * @{
EricLew 0:80ee8f3b695e 194 */
EricLew 0:80ee8f3b695e 195
EricLew 0:80ee8f3b695e 196 /**
EricLew 0:80ee8f3b695e 197 * @brief Initialize the FMC_NORSRAM device according to the specified
EricLew 0:80ee8f3b695e 198 * control parameters in the FMC_NORSRAM_InitTypeDef
EricLew 0:80ee8f3b695e 199 * @param Device: Pointer to NORSRAM device instance
EricLew 0:80ee8f3b695e 200 * @param Init: Pointer to NORSRAM Initialization structure
EricLew 0:80ee8f3b695e 201 * @retval HAL status
EricLew 0:80ee8f3b695e 202 */
EricLew 0:80ee8f3b695e 203 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)
EricLew 0:80ee8f3b695e 204 {
EricLew 0:80ee8f3b695e 205 /* Check the parameters */
EricLew 0:80ee8f3b695e 206 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
EricLew 0:80ee8f3b695e 207 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
EricLew 0:80ee8f3b695e 208 assert_param(IS_FMC_MUX(Init->DataAddressMux));
EricLew 0:80ee8f3b695e 209 assert_param(IS_FMC_MEMORY(Init->MemoryType));
EricLew 0:80ee8f3b695e 210 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
EricLew 0:80ee8f3b695e 211 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
EricLew 0:80ee8f3b695e 212 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
EricLew 0:80ee8f3b695e 213 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
EricLew 0:80ee8f3b695e 214 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
EricLew 0:80ee8f3b695e 215 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
EricLew 0:80ee8f3b695e 216 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
EricLew 0:80ee8f3b695e 217 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
EricLew 0:80ee8f3b695e 218 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
EricLew 0:80ee8f3b695e 219 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
EricLew 0:80ee8f3b695e 220 assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
EricLew 0:80ee8f3b695e 221 assert_param(IS_FMC_PAGESIZE(Init->PageSize));
EricLew 0:80ee8f3b695e 222
EricLew 0:80ee8f3b695e 223 /* Set NORSRAM device control parameters */
EricLew 0:80ee8f3b695e 224 if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)
EricLew 0:80ee8f3b695e 225 {
EricLew 0:80ee8f3b695e 226 MODIFY_REG(Device->BTCR[Init->NSBank], BCRx_CLEAR_MASK, (uint32_t)(FMC_NORSRAM_FLASH_ACCESS_ENABLE |\
EricLew 0:80ee8f3b695e 227 Init->DataAddressMux |\
EricLew 0:80ee8f3b695e 228 Init->MemoryType |\
EricLew 0:80ee8f3b695e 229 Init->MemoryDataWidth |\
EricLew 0:80ee8f3b695e 230 Init->BurstAccessMode |\
EricLew 0:80ee8f3b695e 231 Init->WaitSignalPolarity |\
EricLew 0:80ee8f3b695e 232 Init->WaitSignalActive |\
EricLew 0:80ee8f3b695e 233 Init->WriteOperation |\
EricLew 0:80ee8f3b695e 234 Init->WaitSignal |\
EricLew 0:80ee8f3b695e 235 Init->ExtendedMode |\
EricLew 0:80ee8f3b695e 236 Init->AsynchronousWait |\
EricLew 0:80ee8f3b695e 237 Init->WriteBurst |\
EricLew 0:80ee8f3b695e 238 Init->ContinuousClock |\
EricLew 0:80ee8f3b695e 239 Init->WriteFifo |\
EricLew 0:80ee8f3b695e 240 Init->PageSize)
EricLew 0:80ee8f3b695e 241 );
EricLew 0:80ee8f3b695e 242 }
EricLew 0:80ee8f3b695e 243 else
EricLew 0:80ee8f3b695e 244 {
EricLew 0:80ee8f3b695e 245 MODIFY_REG(Device->BTCR[Init->NSBank], BCRx_CLEAR_MASK, (uint32_t)(FMC_NORSRAM_FLASH_ACCESS_DISABLE |\
EricLew 0:80ee8f3b695e 246 Init->DataAddressMux |\
EricLew 0:80ee8f3b695e 247 Init->MemoryType |\
EricLew 0:80ee8f3b695e 248 Init->MemoryDataWidth |\
EricLew 0:80ee8f3b695e 249 Init->BurstAccessMode |\
EricLew 0:80ee8f3b695e 250 Init->WaitSignalPolarity |\
EricLew 0:80ee8f3b695e 251 Init->WaitSignalActive |\
EricLew 0:80ee8f3b695e 252 Init->WriteOperation |\
EricLew 0:80ee8f3b695e 253 Init->WaitSignal |\
EricLew 0:80ee8f3b695e 254 Init->ExtendedMode |\
EricLew 0:80ee8f3b695e 255 Init->AsynchronousWait |\
EricLew 0:80ee8f3b695e 256 Init->WriteBurst |\
EricLew 0:80ee8f3b695e 257 Init->ContinuousClock |\
EricLew 0:80ee8f3b695e 258 Init->WriteFifo |\
EricLew 0:80ee8f3b695e 259 Init->PageSize)
EricLew 0:80ee8f3b695e 260 );
EricLew 0:80ee8f3b695e 261 }
EricLew 0:80ee8f3b695e 262
EricLew 0:80ee8f3b695e 263 /* Specific bits on bank1 register for bank2..4 */
EricLew 0:80ee8f3b695e 264 if(Init->NSBank != FMC_NORSRAM_BANK1)
EricLew 0:80ee8f3b695e 265 {
EricLew 0:80ee8f3b695e 266 /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */
EricLew 0:80ee8f3b695e 267 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));
EricLew 0:80ee8f3b695e 268
EricLew 0:80ee8f3b695e 269 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
EricLew 0:80ee8f3b695e 270 if(Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)
EricLew 0:80ee8f3b695e 271 {
EricLew 0:80ee8f3b695e 272 Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE;
EricLew 0:80ee8f3b695e 273 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCRx_BURSTEN | FMC_BCR1_CCLKEN, (uint32_t)(Init->BurstAccessMode |\
EricLew 0:80ee8f3b695e 274 Init->ContinuousClock));
EricLew 0:80ee8f3b695e 275 }
EricLew 0:80ee8f3b695e 276 }
EricLew 0:80ee8f3b695e 277
EricLew 0:80ee8f3b695e 278 return HAL_OK;
EricLew 0:80ee8f3b695e 279 }
EricLew 0:80ee8f3b695e 280
EricLew 0:80ee8f3b695e 281
EricLew 0:80ee8f3b695e 282 /**
EricLew 0:80ee8f3b695e 283 * @brief DeInitialize the FMC_NORSRAM peripheral
EricLew 0:80ee8f3b695e 284 * @param Device: Pointer to NORSRAM device instance
EricLew 0:80ee8f3b695e 285 * @param ExDevice: Pointer to NORSRAM extended mode device instance
EricLew 0:80ee8f3b695e 286 * @param Bank: NORSRAM bank number
EricLew 0:80ee8f3b695e 287 * @retval HAL status
EricLew 0:80ee8f3b695e 288 */
EricLew 0:80ee8f3b695e 289 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
EricLew 0:80ee8f3b695e 290 {
EricLew 0:80ee8f3b695e 291 /* Check the parameters */
EricLew 0:80ee8f3b695e 292 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
EricLew 0:80ee8f3b695e 293 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
EricLew 0:80ee8f3b695e 294 assert_param(IS_FMC_NORSRAM_BANK(Bank));
EricLew 0:80ee8f3b695e 295
EricLew 0:80ee8f3b695e 296 /* Disable the FMC_NORSRAM device */
EricLew 0:80ee8f3b695e 297 __FMC_NORSRAM_DISABLE(Device, Bank);
EricLew 0:80ee8f3b695e 298
EricLew 0:80ee8f3b695e 299 /* De-initialize the FMC_NORSRAM device */
EricLew 0:80ee8f3b695e 300 /* FMC_NORSRAM_BANK1 */
EricLew 0:80ee8f3b695e 301 if(Bank == FMC_NORSRAM_BANK1)
EricLew 0:80ee8f3b695e 302 {
EricLew 0:80ee8f3b695e 303 Device->BTCR[Bank] = 0x000030DB;
EricLew 0:80ee8f3b695e 304 }
EricLew 0:80ee8f3b695e 305 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
EricLew 0:80ee8f3b695e 306 else
EricLew 0:80ee8f3b695e 307 {
EricLew 0:80ee8f3b695e 308 Device->BTCR[Bank] = 0x000030D2;
EricLew 0:80ee8f3b695e 309 }
EricLew 0:80ee8f3b695e 310
EricLew 0:80ee8f3b695e 311 Device->BTCR[Bank + 1] = 0x0FFFFFFF;
EricLew 0:80ee8f3b695e 312 ExDevice->BWTR[Bank] = 0x0FFFFFFF;
EricLew 0:80ee8f3b695e 313
EricLew 0:80ee8f3b695e 314 return HAL_OK;
EricLew 0:80ee8f3b695e 315 }
EricLew 0:80ee8f3b695e 316
EricLew 0:80ee8f3b695e 317
EricLew 0:80ee8f3b695e 318 /**
EricLew 0:80ee8f3b695e 319 * @brief Initialize the FMC_NORSRAM Timing according to the specified
EricLew 0:80ee8f3b695e 320 * parameters in the FMC_NORSRAM_TimingTypeDef
EricLew 0:80ee8f3b695e 321 * @param Device: Pointer to NORSRAM device instance
EricLew 0:80ee8f3b695e 322 * @param Timing: Pointer to NORSRAM Timing structure
EricLew 0:80ee8f3b695e 323 * @param Bank: NORSRAM bank number
EricLew 0:80ee8f3b695e 324 * @retval HAL status
EricLew 0:80ee8f3b695e 325 */
EricLew 0:80ee8f3b695e 326 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
EricLew 0:80ee8f3b695e 327 {
EricLew 0:80ee8f3b695e 328 uint32_t tmpr = 0;
EricLew 0:80ee8f3b695e 329
EricLew 0:80ee8f3b695e 330 /* Check the parameters */
EricLew 0:80ee8f3b695e 331 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
EricLew 0:80ee8f3b695e 332 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
EricLew 0:80ee8f3b695e 333 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
EricLew 0:80ee8f3b695e 334 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
EricLew 0:80ee8f3b695e 335 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
EricLew 0:80ee8f3b695e 336 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
EricLew 0:80ee8f3b695e 337 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
EricLew 0:80ee8f3b695e 338 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
EricLew 0:80ee8f3b695e 339 assert_param(IS_FMC_NORSRAM_BANK(Bank));
EricLew 0:80ee8f3b695e 340
EricLew 0:80ee8f3b695e 341 /* Set FMC_NORSRAM device timing parameters */
EricLew 0:80ee8f3b695e 342 MODIFY_REG(Device->BTCR[Bank + 1], \
EricLew 0:80ee8f3b695e 343 BTRx_CLEAR_MASK, \
EricLew 0:80ee8f3b695e 344 (uint32_t)(Timing->AddressSetupTime |\
EricLew 0:80ee8f3b695e 345 ((Timing->AddressHoldTime) << POSITION_VAL(FMC_BTRx_ADDHLD)) |\
EricLew 0:80ee8f3b695e 346 ((Timing->DataSetupTime) << POSITION_VAL(FMC_BTRx_DATAST)) |\
EricLew 0:80ee8f3b695e 347 ((Timing->BusTurnAroundDuration) << POSITION_VAL(FMC_BTRx_BUSTURN)) |\
EricLew 0:80ee8f3b695e 348 (((Timing->CLKDivision)-1) << POSITION_VAL(FMC_BTRx_CLKDIV)) |\
EricLew 0:80ee8f3b695e 349 (((Timing->DataLatency)-2) << POSITION_VAL(FMC_BTRx_DATLAT)) |\
EricLew 0:80ee8f3b695e 350 (Timing->AccessMode)));
EricLew 0:80ee8f3b695e 351
EricLew 0:80ee8f3b695e 352 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
EricLew 0:80ee8f3b695e 353 if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
EricLew 0:80ee8f3b695e 354 {
EricLew 0:80ee8f3b695e 355 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << POSITION_VAL(FMC_BTRx_CLKDIV)));
EricLew 0:80ee8f3b695e 356 tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << POSITION_VAL(FMC_BTRx_CLKDIV));
EricLew 0:80ee8f3b695e 357 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1], FMC_BTRx_CLKDIV, tmpr);
EricLew 0:80ee8f3b695e 358 }
EricLew 0:80ee8f3b695e 359
EricLew 0:80ee8f3b695e 360 return HAL_OK;
EricLew 0:80ee8f3b695e 361 }
EricLew 0:80ee8f3b695e 362
EricLew 0:80ee8f3b695e 363 /**
EricLew 0:80ee8f3b695e 364 * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
EricLew 0:80ee8f3b695e 365 * parameters in the FMC_NORSRAM_TimingTypeDef
EricLew 0:80ee8f3b695e 366 * @param Device: Pointer to NORSRAM device instance
EricLew 0:80ee8f3b695e 367 * @param Timing: Pointer to NORSRAM Timing structure
EricLew 0:80ee8f3b695e 368 * @param Bank: NORSRAM bank number
EricLew 0:80ee8f3b695e 369 * @param ExtendedMode: FMC Extended Mode
EricLew 0:80ee8f3b695e 370 * This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 371 * @arg FMC_EXTENDED_MODE_DISABLE
EricLew 0:80ee8f3b695e 372 * @arg FMC_EXTENDED_MODE_ENABLE
EricLew 0:80ee8f3b695e 373 * @retval HAL status
EricLew 0:80ee8f3b695e 374 */
EricLew 0:80ee8f3b695e 375 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
EricLew 0:80ee8f3b695e 376 {
EricLew 0:80ee8f3b695e 377 /* Check the parameters */
EricLew 0:80ee8f3b695e 378 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
EricLew 0:80ee8f3b695e 379
EricLew 0:80ee8f3b695e 380 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
EricLew 0:80ee8f3b695e 381 if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
EricLew 0:80ee8f3b695e 382 {
EricLew 0:80ee8f3b695e 383 /* Check the parameters */
EricLew 0:80ee8f3b695e 384 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
EricLew 0:80ee8f3b695e 385 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
EricLew 0:80ee8f3b695e 386 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
EricLew 0:80ee8f3b695e 387 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
EricLew 0:80ee8f3b695e 388 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
EricLew 0:80ee8f3b695e 389 assert_param(IS_FMC_NORSRAM_BANK(Bank));
EricLew 0:80ee8f3b695e 390
EricLew 0:80ee8f3b695e 391 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
EricLew 0:80ee8f3b695e 392 MODIFY_REG(Device->BWTR[Bank], \
EricLew 0:80ee8f3b695e 393 BWTRx_CLEAR_MASK, \
EricLew 0:80ee8f3b695e 394 (uint32_t)(Timing->AddressSetupTime |\
EricLew 0:80ee8f3b695e 395 ((Timing->AddressHoldTime) << POSITION_VAL(FMC_BTRx_ADDHLD)) |\
EricLew 0:80ee8f3b695e 396 ((Timing->DataSetupTime) << POSITION_VAL(FMC_BTRx_DATAST)) |\
EricLew 0:80ee8f3b695e 397 (Timing->AccessMode)));
EricLew 0:80ee8f3b695e 398 }
EricLew 0:80ee8f3b695e 399 else
EricLew 0:80ee8f3b695e 400 {
EricLew 0:80ee8f3b695e 401 Device->BWTR[Bank] = 0x0FFFFFFF;
EricLew 0:80ee8f3b695e 402 }
EricLew 0:80ee8f3b695e 403
EricLew 0:80ee8f3b695e 404 return HAL_OK;
EricLew 0:80ee8f3b695e 405 }
EricLew 0:80ee8f3b695e 406
EricLew 0:80ee8f3b695e 407
EricLew 0:80ee8f3b695e 408 /**
EricLew 0:80ee8f3b695e 409 * @}
EricLew 0:80ee8f3b695e 410 */
EricLew 0:80ee8f3b695e 411
EricLew 0:80ee8f3b695e 412
EricLew 0:80ee8f3b695e 413 /** @defgroup FMC_NORSRAM_Exported_Functions_Group2 Peripheral Control functions
EricLew 0:80ee8f3b695e 414 * @brief management functions
EricLew 0:80ee8f3b695e 415 *
EricLew 0:80ee8f3b695e 416 @verbatim
EricLew 0:80ee8f3b695e 417 ==============================================================================
EricLew 0:80ee8f3b695e 418 ##### FMC_NORSRAM Control functions #####
EricLew 0:80ee8f3b695e 419 ==============================================================================
EricLew 0:80ee8f3b695e 420 [..]
EricLew 0:80ee8f3b695e 421 This subsection provides a set of functions allowing to control dynamically
EricLew 0:80ee8f3b695e 422 the FMC NORSRAM interface.
EricLew 0:80ee8f3b695e 423
EricLew 0:80ee8f3b695e 424 @endverbatim
EricLew 0:80ee8f3b695e 425 * @{
EricLew 0:80ee8f3b695e 426 */
EricLew 0:80ee8f3b695e 427
EricLew 0:80ee8f3b695e 428 /**
EricLew 0:80ee8f3b695e 429 * @brief Enables dynamically FMC_NORSRAM write operation.
EricLew 0:80ee8f3b695e 430 * @param Device: Pointer to NORSRAM device instance
EricLew 0:80ee8f3b695e 431 * @param Bank: NORSRAM bank number
EricLew 0:80ee8f3b695e 432 * @retval HAL status
EricLew 0:80ee8f3b695e 433 */
EricLew 0:80ee8f3b695e 434 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
EricLew 0:80ee8f3b695e 435 {
EricLew 0:80ee8f3b695e 436 /* Check the parameters */
EricLew 0:80ee8f3b695e 437 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
EricLew 0:80ee8f3b695e 438 assert_param(IS_FMC_NORSRAM_BANK(Bank));
EricLew 0:80ee8f3b695e 439
EricLew 0:80ee8f3b695e 440 /* Enable write operation */
EricLew 0:80ee8f3b695e 441 SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
EricLew 0:80ee8f3b695e 442
EricLew 0:80ee8f3b695e 443 return HAL_OK;
EricLew 0:80ee8f3b695e 444 }
EricLew 0:80ee8f3b695e 445
EricLew 0:80ee8f3b695e 446 /**
EricLew 0:80ee8f3b695e 447 * @brief Disables dynamically FMC_NORSRAM write operation.
EricLew 0:80ee8f3b695e 448 * @param Device: Pointer to NORSRAM device instance
EricLew 0:80ee8f3b695e 449 * @param Bank: NORSRAM bank number
EricLew 0:80ee8f3b695e 450 * @retval HAL status
EricLew 0:80ee8f3b695e 451 */
EricLew 0:80ee8f3b695e 452 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
EricLew 0:80ee8f3b695e 453 {
EricLew 0:80ee8f3b695e 454 /* Check the parameters */
EricLew 0:80ee8f3b695e 455 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
EricLew 0:80ee8f3b695e 456 assert_param(IS_FMC_NORSRAM_BANK(Bank));
EricLew 0:80ee8f3b695e 457
EricLew 0:80ee8f3b695e 458 /* Disable write operation */
EricLew 0:80ee8f3b695e 459 CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
EricLew 0:80ee8f3b695e 460
EricLew 0:80ee8f3b695e 461 return HAL_OK;
EricLew 0:80ee8f3b695e 462 }
EricLew 0:80ee8f3b695e 463
EricLew 0:80ee8f3b695e 464 /**
EricLew 0:80ee8f3b695e 465 * @}
EricLew 0:80ee8f3b695e 466 */
EricLew 0:80ee8f3b695e 467
EricLew 0:80ee8f3b695e 468 /**
EricLew 0:80ee8f3b695e 469 * @}
EricLew 0:80ee8f3b695e 470 */
EricLew 0:80ee8f3b695e 471
EricLew 0:80ee8f3b695e 472 /** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions
EricLew 0:80ee8f3b695e 473 * @brief NAND Controller functions
EricLew 0:80ee8f3b695e 474 *
EricLew 0:80ee8f3b695e 475 @verbatim
EricLew 0:80ee8f3b695e 476 ==============================================================================
EricLew 0:80ee8f3b695e 477 ##### How to use NAND device driver #####
EricLew 0:80ee8f3b695e 478 ==============================================================================
EricLew 0:80ee8f3b695e 479 [..]
EricLew 0:80ee8f3b695e 480 This driver contains a set of APIs to interface with the FMC NAND banks in order
EricLew 0:80ee8f3b695e 481 to run the NAND external devices.
EricLew 0:80ee8f3b695e 482
EricLew 0:80ee8f3b695e 483 (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
EricLew 0:80ee8f3b695e 484 (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
EricLew 0:80ee8f3b695e 485 (+) FMC NAND bank common space timing configuration using the function
EricLew 0:80ee8f3b695e 486 FMC_NAND_CommonSpace_Timing_Init()
EricLew 0:80ee8f3b695e 487 (+) FMC NAND bank attribute space timing configuration using the function
EricLew 0:80ee8f3b695e 488 FMC_NAND_AttributeSpace_Timing_Init()
EricLew 0:80ee8f3b695e 489 (+) FMC NAND bank enable/disable ECC correction feature using the functions
EricLew 0:80ee8f3b695e 490 FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
EricLew 0:80ee8f3b695e 491 (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
EricLew 0:80ee8f3b695e 492
EricLew 0:80ee8f3b695e 493 @endverbatim
EricLew 0:80ee8f3b695e 494 * @{
EricLew 0:80ee8f3b695e 495 */
EricLew 0:80ee8f3b695e 496
EricLew 0:80ee8f3b695e 497 /** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
EricLew 0:80ee8f3b695e 498 * @brief Initialization and Configuration functions
EricLew 0:80ee8f3b695e 499 *
EricLew 0:80ee8f3b695e 500 @verbatim
EricLew 0:80ee8f3b695e 501 ==============================================================================
EricLew 0:80ee8f3b695e 502 ##### Initialization and de-initialization functions #####
EricLew 0:80ee8f3b695e 503 ==============================================================================
EricLew 0:80ee8f3b695e 504 [..]
EricLew 0:80ee8f3b695e 505 This section provides functions allowing to:
EricLew 0:80ee8f3b695e 506 (+) Initialize and configure the FMC NAND interface
EricLew 0:80ee8f3b695e 507 (+) De-initialize the FMC NAND interface
EricLew 0:80ee8f3b695e 508 (+) Configure the FMC clock and associated GPIOs
EricLew 0:80ee8f3b695e 509
EricLew 0:80ee8f3b695e 510 @endverbatim
EricLew 0:80ee8f3b695e 511 * @{
EricLew 0:80ee8f3b695e 512 */
EricLew 0:80ee8f3b695e 513
EricLew 0:80ee8f3b695e 514 /**
EricLew 0:80ee8f3b695e 515 * @brief Initializes the FMC_NAND device according to the specified
EricLew 0:80ee8f3b695e 516 * control parameters in the FMC_NAND_HandleTypeDef
EricLew 0:80ee8f3b695e 517 * @param Device: Pointer to NAND device instance
EricLew 0:80ee8f3b695e 518 * @param Init: Pointer to NAND Initialization structure
EricLew 0:80ee8f3b695e 519 * @retval HAL status
EricLew 0:80ee8f3b695e 520 */
EricLew 0:80ee8f3b695e 521 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
EricLew 0:80ee8f3b695e 522 {
EricLew 0:80ee8f3b695e 523 /* Check the parameters */
EricLew 0:80ee8f3b695e 524 assert_param(IS_FMC_NAND_DEVICE(Device));
EricLew 0:80ee8f3b695e 525 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
EricLew 0:80ee8f3b695e 526 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
EricLew 0:80ee8f3b695e 527 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
EricLew 0:80ee8f3b695e 528 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
EricLew 0:80ee8f3b695e 529 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
EricLew 0:80ee8f3b695e 530 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
EricLew 0:80ee8f3b695e 531 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
EricLew 0:80ee8f3b695e 532
EricLew 0:80ee8f3b695e 533 /* Set NAND device control parameters */
EricLew 0:80ee8f3b695e 534 /* NAND bank 3 registers configuration */
EricLew 0:80ee8f3b695e 535 MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature |\
EricLew 0:80ee8f3b695e 536 FMC_PCR_MEMORY_TYPE_NAND |\
EricLew 0:80ee8f3b695e 537 Init->MemoryDataWidth |\
EricLew 0:80ee8f3b695e 538 Init->EccComputation |\
EricLew 0:80ee8f3b695e 539 Init->ECCPageSize |\
EricLew 0:80ee8f3b695e 540 ((Init->TCLRSetupTime) << POSITION_VAL(FMC_PCR_TCLR)) |\
EricLew 0:80ee8f3b695e 541 ((Init->TARSetupTime) << POSITION_VAL(FMC_PCR_TAR))));
EricLew 0:80ee8f3b695e 542
EricLew 0:80ee8f3b695e 543 return HAL_OK;
EricLew 0:80ee8f3b695e 544
EricLew 0:80ee8f3b695e 545 }
EricLew 0:80ee8f3b695e 546
EricLew 0:80ee8f3b695e 547 /**
EricLew 0:80ee8f3b695e 548 * @brief Initializes the FMC_NAND Common space Timing according to the specified
EricLew 0:80ee8f3b695e 549 * parameters in the FMC_NAND_PCC_TimingTypeDef
EricLew 0:80ee8f3b695e 550 * @param Device: Pointer to NAND device instance
EricLew 0:80ee8f3b695e 551 * @param Timing: Pointer to NAND timing structure
EricLew 0:80ee8f3b695e 552 * @param Bank: NAND bank number
EricLew 0:80ee8f3b695e 553 * @retval HAL status
EricLew 0:80ee8f3b695e 554 */
EricLew 0:80ee8f3b695e 555 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
EricLew 0:80ee8f3b695e 556 {
EricLew 0:80ee8f3b695e 557 /* Check the parameters */
EricLew 0:80ee8f3b695e 558 assert_param(IS_FMC_NAND_DEVICE(Device));
EricLew 0:80ee8f3b695e 559 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
EricLew 0:80ee8f3b695e 560 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
EricLew 0:80ee8f3b695e 561 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
EricLew 0:80ee8f3b695e 562 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
EricLew 0:80ee8f3b695e 563 assert_param(IS_FMC_NAND_BANK(Bank));
EricLew 0:80ee8f3b695e 564
EricLew 0:80ee8f3b695e 565 /* Set FMC_NAND device timing parameters */
EricLew 0:80ee8f3b695e 566 /* NAND bank 3 registers configuration */
EricLew 0:80ee8f3b695e 567 MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime |\
EricLew 0:80ee8f3b695e 568 ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PMEM_MEMWAIT)) |\
EricLew 0:80ee8f3b695e 569 ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PMEM_MEMHOLD)) |\
EricLew 0:80ee8f3b695e 570 ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PMEM_MEMHIZ))));
EricLew 0:80ee8f3b695e 571
EricLew 0:80ee8f3b695e 572 return HAL_OK;
EricLew 0:80ee8f3b695e 573 }
EricLew 0:80ee8f3b695e 574
EricLew 0:80ee8f3b695e 575 /**
EricLew 0:80ee8f3b695e 576 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
EricLew 0:80ee8f3b695e 577 * parameters in the FMC_NAND_PCC_TimingTypeDef
EricLew 0:80ee8f3b695e 578 * @param Device: Pointer to NAND device instance
EricLew 0:80ee8f3b695e 579 * @param Timing: Pointer to NAND timing structure
EricLew 0:80ee8f3b695e 580 * @param Bank: NAND bank number
EricLew 0:80ee8f3b695e 581 * @retval HAL status
EricLew 0:80ee8f3b695e 582 */
EricLew 0:80ee8f3b695e 583 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
EricLew 0:80ee8f3b695e 584 {
EricLew 0:80ee8f3b695e 585 /* Check the parameters */
EricLew 0:80ee8f3b695e 586 assert_param(IS_FMC_NAND_DEVICE(Device));
EricLew 0:80ee8f3b695e 587 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
EricLew 0:80ee8f3b695e 588 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
EricLew 0:80ee8f3b695e 589 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
EricLew 0:80ee8f3b695e 590 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
EricLew 0:80ee8f3b695e 591 assert_param(IS_FMC_NAND_BANK(Bank));
EricLew 0:80ee8f3b695e 592
EricLew 0:80ee8f3b695e 593 /* Set FMC_NAND device timing parameters */
EricLew 0:80ee8f3b695e 594 /* NAND bank 3 registers configuration */
EricLew 0:80ee8f3b695e 595 MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime |\
EricLew 0:80ee8f3b695e 596 ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PMEM_MEMWAIT)) |\
EricLew 0:80ee8f3b695e 597 ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PMEM_MEMHOLD)) |\
EricLew 0:80ee8f3b695e 598 ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PMEM_MEMHIZ))));
EricLew 0:80ee8f3b695e 599
EricLew 0:80ee8f3b695e 600 return HAL_OK;
EricLew 0:80ee8f3b695e 601 }
EricLew 0:80ee8f3b695e 602
EricLew 0:80ee8f3b695e 603
EricLew 0:80ee8f3b695e 604 /**
EricLew 0:80ee8f3b695e 605 * @brief DeInitialize the FMC_NAND device
EricLew 0:80ee8f3b695e 606 * @param Device: Pointer to NAND device instance
EricLew 0:80ee8f3b695e 607 * @param Bank: NAND bank number
EricLew 0:80ee8f3b695e 608 * @retval HAL status
EricLew 0:80ee8f3b695e 609 */
EricLew 0:80ee8f3b695e 610 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
EricLew 0:80ee8f3b695e 611 {
EricLew 0:80ee8f3b695e 612 /* Check the parameters */
EricLew 0:80ee8f3b695e 613 assert_param(IS_FMC_NAND_DEVICE(Device));
EricLew 0:80ee8f3b695e 614 assert_param(IS_FMC_NAND_BANK(Bank));
EricLew 0:80ee8f3b695e 615
EricLew 0:80ee8f3b695e 616 /* Disable the NAND Bank */
EricLew 0:80ee8f3b695e 617 __FMC_NAND_DISABLE(Device, Bank);
EricLew 0:80ee8f3b695e 618
EricLew 0:80ee8f3b695e 619 /* Set the FMC_NAND_BANK registers to their reset values */
EricLew 0:80ee8f3b695e 620 WRITE_REG(Device->PCR, 0x00000018);
EricLew 0:80ee8f3b695e 621 WRITE_REG(Device->SR, 0x00000040);
EricLew 0:80ee8f3b695e 622 WRITE_REG(Device->PMEM, 0xFCFCFCFC);
EricLew 0:80ee8f3b695e 623 WRITE_REG(Device->PATT, 0xFCFCFCFC);
EricLew 0:80ee8f3b695e 624
EricLew 0:80ee8f3b695e 625 return HAL_OK;
EricLew 0:80ee8f3b695e 626 }
EricLew 0:80ee8f3b695e 627
EricLew 0:80ee8f3b695e 628 /**
EricLew 0:80ee8f3b695e 629 * @}
EricLew 0:80ee8f3b695e 630 */
EricLew 0:80ee8f3b695e 631
EricLew 0:80ee8f3b695e 632
EricLew 0:80ee8f3b695e 633 /** @defgroup FMC_LL_NAND_Exported_Functions_Group2 FMC Low Layer Peripheral Control functions
EricLew 0:80ee8f3b695e 634 * @brief management functions
EricLew 0:80ee8f3b695e 635 *
EricLew 0:80ee8f3b695e 636 @verbatim
EricLew 0:80ee8f3b695e 637 ==============================================================================
EricLew 0:80ee8f3b695e 638 ##### FMC_NAND Control functions #####
EricLew 0:80ee8f3b695e 639 ==============================================================================
EricLew 0:80ee8f3b695e 640 [..]
EricLew 0:80ee8f3b695e 641 This subsection provides a set of functions allowing to control dynamically
EricLew 0:80ee8f3b695e 642 the FMC NAND interface.
EricLew 0:80ee8f3b695e 643
EricLew 0:80ee8f3b695e 644 @endverbatim
EricLew 0:80ee8f3b695e 645 * @{
EricLew 0:80ee8f3b695e 646 */
EricLew 0:80ee8f3b695e 647
EricLew 0:80ee8f3b695e 648
EricLew 0:80ee8f3b695e 649 /**
EricLew 0:80ee8f3b695e 650 * @brief Enables dynamically FMC_NAND ECC feature.
EricLew 0:80ee8f3b695e 651 * @param Device: Pointer to NAND device instance
EricLew 0:80ee8f3b695e 652 * @param Bank: NAND bank number
EricLew 0:80ee8f3b695e 653 * @retval HAL status
EricLew 0:80ee8f3b695e 654 */
EricLew 0:80ee8f3b695e 655 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
EricLew 0:80ee8f3b695e 656 {
EricLew 0:80ee8f3b695e 657 /* Check the parameters */
EricLew 0:80ee8f3b695e 658 assert_param(IS_FMC_NAND_DEVICE(Device));
EricLew 0:80ee8f3b695e 659 assert_param(IS_FMC_NAND_BANK(Bank));
EricLew 0:80ee8f3b695e 660
EricLew 0:80ee8f3b695e 661 /* Enable ECC feature */
EricLew 0:80ee8f3b695e 662 SET_BIT(Device->PCR, FMC_PCR_ECCEN);
EricLew 0:80ee8f3b695e 663
EricLew 0:80ee8f3b695e 664 return HAL_OK;
EricLew 0:80ee8f3b695e 665 }
EricLew 0:80ee8f3b695e 666
EricLew 0:80ee8f3b695e 667
EricLew 0:80ee8f3b695e 668 /**
EricLew 0:80ee8f3b695e 669 * @brief Disables dynamically FMC_NAND ECC feature.
EricLew 0:80ee8f3b695e 670 * @param Device: Pointer to NAND device instance
EricLew 0:80ee8f3b695e 671 * @param Bank: NAND bank number
EricLew 0:80ee8f3b695e 672 * @retval HAL status
EricLew 0:80ee8f3b695e 673 */
EricLew 0:80ee8f3b695e 674 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
EricLew 0:80ee8f3b695e 675 {
EricLew 0:80ee8f3b695e 676 /* Check the parameters */
EricLew 0:80ee8f3b695e 677 assert_param(IS_FMC_NAND_DEVICE(Device));
EricLew 0:80ee8f3b695e 678 assert_param(IS_FMC_NAND_BANK(Bank));
EricLew 0:80ee8f3b695e 679
EricLew 0:80ee8f3b695e 680 /* Disable ECC feature */
EricLew 0:80ee8f3b695e 681 CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN);
EricLew 0:80ee8f3b695e 682
EricLew 0:80ee8f3b695e 683 return HAL_OK;
EricLew 0:80ee8f3b695e 684 }
EricLew 0:80ee8f3b695e 685
EricLew 0:80ee8f3b695e 686 /**
EricLew 0:80ee8f3b695e 687 * @brief Disables dynamically FMC_NAND ECC feature.
EricLew 0:80ee8f3b695e 688 * @param Device: Pointer to NAND device instance
EricLew 0:80ee8f3b695e 689 * @param ECCval: Pointer to ECC value
EricLew 0:80ee8f3b695e 690 * @param Bank: NAND bank number
EricLew 0:80ee8f3b695e 691 * @param Timeout: Timeout wait value
EricLew 0:80ee8f3b695e 692 * @retval HAL status
EricLew 0:80ee8f3b695e 693 */
EricLew 0:80ee8f3b695e 694 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
EricLew 0:80ee8f3b695e 695 {
EricLew 0:80ee8f3b695e 696 uint32_t tickstart = 0;
EricLew 0:80ee8f3b695e 697
EricLew 0:80ee8f3b695e 698 /* Check the parameters */
EricLew 0:80ee8f3b695e 699 assert_param(IS_FMC_NAND_DEVICE(Device));
EricLew 0:80ee8f3b695e 700 assert_param(IS_FMC_NAND_BANK(Bank));
EricLew 0:80ee8f3b695e 701
EricLew 0:80ee8f3b695e 702 /* Get tick */
EricLew 0:80ee8f3b695e 703 tickstart = HAL_GetTick();
EricLew 0:80ee8f3b695e 704
EricLew 0:80ee8f3b695e 705 /* Wait until FIFO is empty */
EricLew 0:80ee8f3b695e 706 while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
EricLew 0:80ee8f3b695e 707 {
EricLew 0:80ee8f3b695e 708 /* Check for the Timeout */
EricLew 0:80ee8f3b695e 709 if(Timeout != HAL_MAX_DELAY)
EricLew 0:80ee8f3b695e 710 {
EricLew 0:80ee8f3b695e 711 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
EricLew 0:80ee8f3b695e 712 {
EricLew 0:80ee8f3b695e 713 return HAL_TIMEOUT;
EricLew 0:80ee8f3b695e 714 }
EricLew 0:80ee8f3b695e 715 }
EricLew 0:80ee8f3b695e 716 }
EricLew 0:80ee8f3b695e 717
EricLew 0:80ee8f3b695e 718 /* Get the ECCR register value */
EricLew 0:80ee8f3b695e 719 *ECCval = (uint32_t)Device->ECCR;
EricLew 0:80ee8f3b695e 720
EricLew 0:80ee8f3b695e 721 return HAL_OK;
EricLew 0:80ee8f3b695e 722 }
EricLew 0:80ee8f3b695e 723
EricLew 0:80ee8f3b695e 724 /**
EricLew 0:80ee8f3b695e 725 * @}
EricLew 0:80ee8f3b695e 726 */
EricLew 0:80ee8f3b695e 727
EricLew 0:80ee8f3b695e 728 /**
EricLew 0:80ee8f3b695e 729 * @}
EricLew 0:80ee8f3b695e 730 */
EricLew 0:80ee8f3b695e 731
EricLew 0:80ee8f3b695e 732 /**
EricLew 0:80ee8f3b695e 733 * @}
EricLew 0:80ee8f3b695e 734 */
EricLew 0:80ee8f3b695e 735
EricLew 0:80ee8f3b695e 736 /**
EricLew 0:80ee8f3b695e 737 * @}
EricLew 0:80ee8f3b695e 738 */
EricLew 0:80ee8f3b695e 739
EricLew 0:80ee8f3b695e 740 /**
EricLew 0:80ee8f3b695e 741 * @}
EricLew 0:80ee8f3b695e 742 */
EricLew 0:80ee8f3b695e 743
EricLew 0:80ee8f3b695e 744 #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED */
EricLew 0:80ee8f3b695e 745
EricLew 0:80ee8f3b695e 746 /**
EricLew 0:80ee8f3b695e 747 * @}
EricLew 0:80ee8f3b695e 748 */
EricLew 0:80ee8f3b695e 749
EricLew 0:80ee8f3b695e 750 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
EricLew 0:80ee8f3b695e 751