STM32L4xx_HAL_Driver - Hal Drivers for L4

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Hal Drivers for L4

Dependents: BSP OneHopeOnePrayer FINAL_AUDIO_RECORD AudioDemo

Fork of STM32L4xx_HAL_Driver by Senior Design: Sound Monitor

Src/stm32l4xx_hal_rcc.c@0:80ee8f3b695e, 2015-11-02 (annotated)

Committer:: EricLew
Date:: Mon Nov 02 19:37:23 2015 +0000
Revision:: 0:80ee8f3b695e

Errors are with definitions of LCD and QSPI functions. I believe all .h and .c files are  uploaded, but there may need to be certain functions called.

Who changed what in which revision?

User	Revision	Line number	New contents of line
EricLew	0:80ee8f3b695e	1	/**
EricLew	0:80ee8f3b695e	2	******************************************************************************
EricLew	0:80ee8f3b695e	3	* @file stm32l4xx_hal_rcc.c
EricLew	0:80ee8f3b695e	4	* @author MCD Application Team
EricLew	0:80ee8f3b695e	5	* @version V1.1.0
EricLew	0:80ee8f3b695e	6	* @date 16-September-2015
EricLew	0:80ee8f3b695e	7	* @brief RCC HAL module driver.
EricLew	0:80ee8f3b695e	8	* This file provides firmware functions to manage the following
EricLew	0:80ee8f3b695e	9	* functionalities of the Reset and Clock Control (RCC) peripheral:
EricLew	0:80ee8f3b695e	10	* + Initialization and de-initialization functions
EricLew	0:80ee8f3b695e	11	* + Peripheral Control functions
EricLew	0:80ee8f3b695e	12	*
EricLew	0:80ee8f3b695e	13	@verbatim
EricLew	0:80ee8f3b695e	14	==============================================================================
EricLew	0:80ee8f3b695e	15	##### RCC specific features #####
EricLew	0:80ee8f3b695e	16	==============================================================================
EricLew	0:80ee8f3b695e	17	[..]
EricLew	0:80ee8f3b695e	18	After reset the device is running from Multiple Speed Internal oscillator
EricLew	0:80ee8f3b695e	19	(4 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache
EricLew	0:80ee8f3b695e	20	and I-Cache are disabled, and all peripherals are off except internal
EricLew	0:80ee8f3b695e	21	SRAM, Flash and JTAG.
EricLew	0:80ee8f3b695e	22
EricLew	0:80ee8f3b695e	23	(+) There is no prescaler on High speed (AHBs) and Low speed (APBs) busses:
EricLew	0:80ee8f3b695e	24	all peripherals mapped on these busses are running at MSI speed.
EricLew	0:80ee8f3b695e	25	(+) The clock for all peripherals is switched off, except the SRAM and FLASH.
EricLew	0:80ee8f3b695e	26	(+) All GPIOs are in analog mode, except the JTAG pins which
EricLew	0:80ee8f3b695e	27	are assigned to be used for debug purpose.
EricLew	0:80ee8f3b695e	28
EricLew	0:80ee8f3b695e	29	[..]
EricLew	0:80ee8f3b695e	30	Once the device started from reset, the user application has to:
EricLew	0:80ee8f3b695e	31	(+) Configure the clock source to be used to drive the System clock
EricLew	0:80ee8f3b695e	32	(if the application needs higher frequency/performance)
EricLew	0:80ee8f3b695e	33	(+) Configure the System clock frequency and Flash settings
EricLew	0:80ee8f3b695e	34	(+) Configure the AHB and APB busses prescalers
EricLew	0:80ee8f3b695e	35	(+) Enable the clock for the peripheral(s) to be used
EricLew	0:80ee8f3b695e	36	(+) Configure the clock source(s) for peripherals which clocks are not
EricLew	0:80ee8f3b695e	37	derived from the System clock (SAIx, RTC, ADC, USB OTG FS/SDMMC1/RNG)
EricLew	0:80ee8f3b695e	38
EricLew	0:80ee8f3b695e	39	@endverbatim
EricLew	0:80ee8f3b695e	40	******************************************************************************
EricLew	0:80ee8f3b695e	41	* @attention
EricLew	0:80ee8f3b695e	42	*
EricLew	0:80ee8f3b695e	43	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
EricLew	0:80ee8f3b695e	44	*
EricLew	0:80ee8f3b695e	45	* Redistribution and use in source and binary forms, with or without modification,
EricLew	0:80ee8f3b695e	46	* are permitted provided that the following conditions are met:
EricLew	0:80ee8f3b695e	47	* 1. Redistributions of source code must retain the above copyright notice,
EricLew	0:80ee8f3b695e	48	* this list of conditions and the following disclaimer.
EricLew	0:80ee8f3b695e	49	* 2. Redistributions in binary form must reproduce the above copyright notice,
EricLew	0:80ee8f3b695e	50	* this list of conditions and the following disclaimer in the documentation
EricLew	0:80ee8f3b695e	51	* and/or other materials provided with the distribution.
EricLew	0:80ee8f3b695e	52	* 3. Neither the name of STMicroelectronics nor the names of its contributors
EricLew	0:80ee8f3b695e	53	* may be used to endorse or promote products derived from this software
EricLew	0:80ee8f3b695e	54	* without specific prior written permission.
EricLew	0:80ee8f3b695e	55	*
EricLew	0:80ee8f3b695e	56	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew	0:80ee8f3b695e	57	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew	0:80ee8f3b695e	58	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
EricLew	0:80ee8f3b695e	59	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
EricLew	0:80ee8f3b695e	60	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
EricLew	0:80ee8f3b695e	61	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
EricLew	0:80ee8f3b695e	62	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
EricLew	0:80ee8f3b695e	63	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
EricLew	0:80ee8f3b695e	64	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
EricLew	0:80ee8f3b695e	65	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
EricLew	0:80ee8f3b695e	66	*
EricLew	0:80ee8f3b695e	67	******************************************************************************
EricLew	0:80ee8f3b695e	68	*/
EricLew	0:80ee8f3b695e	69
EricLew	0:80ee8f3b695e	70	/* Includes ------------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	71	#include "stm32l4xx_hal.h"
EricLew	0:80ee8f3b695e	72
EricLew	0:80ee8f3b695e	73	/** @addtogroup STM32L4xx_HAL_Driver
EricLew	0:80ee8f3b695e	74	* @{
EricLew	0:80ee8f3b695e	75	*/
EricLew	0:80ee8f3b695e	76
EricLew	0:80ee8f3b695e	77	/** @defgroup RCC RCC
EricLew	0:80ee8f3b695e	78	* @brief RCC HAL module driver
EricLew	0:80ee8f3b695e	79	* @{
EricLew	0:80ee8f3b695e	80	*/
EricLew	0:80ee8f3b695e	81
EricLew	0:80ee8f3b695e	82	#ifdef HAL_RCC_MODULE_ENABLED
EricLew	0:80ee8f3b695e	83
EricLew	0:80ee8f3b695e	84	/* Private typedef -----------------------------------------------------------*/
EricLew	0:80ee8f3b695e	85	/* Private define ------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	86	/** @defgroup RCC_Private_Constants RCC Private Constants
EricLew	0:80ee8f3b695e	87	* @{
EricLew	0:80ee8f3b695e	88	*/
EricLew	0:80ee8f3b695e	89	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
EricLew	0:80ee8f3b695e	90	#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
EricLew	0:80ee8f3b695e	91	#define MSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
EricLew	0:80ee8f3b695e	92	#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
EricLew	0:80ee8f3b695e	93	#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
EricLew	0:80ee8f3b695e	94	#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
EricLew	0:80ee8f3b695e	95
EricLew	0:80ee8f3b695e	96	#define PLLSOURCE_NONE ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	97	/**
EricLew	0:80ee8f3b695e	98	* @}
EricLew	0:80ee8f3b695e	99	*/
EricLew	0:80ee8f3b695e	100
EricLew	0:80ee8f3b695e	101	/* Private macro -------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	102	/** @defgroup RCC_Private_Macros RCC Private Macros
EricLew	0:80ee8f3b695e	103	* @{
EricLew	0:80ee8f3b695e	104	*/
EricLew	0:80ee8f3b695e	105	#define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
EricLew	0:80ee8f3b695e	106	#define MCO1_GPIO_PORT GPIOA
EricLew	0:80ee8f3b695e	107	#define MCO1_PIN GPIO_PIN_8
EricLew	0:80ee8f3b695e	108
EricLew	0:80ee8f3b695e	109	#define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \
EricLew	0:80ee8f3b695e	110	(MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__)))
EricLew	0:80ee8f3b695e	111	/**
EricLew	0:80ee8f3b695e	112	* @}
EricLew	0:80ee8f3b695e	113	*/
EricLew	0:80ee8f3b695e	114
EricLew	0:80ee8f3b695e	115	/* Private variables ---------------------------------------------------------*/
EricLew	0:80ee8f3b695e	116	/** @defgroup RCC_Private_Variables RCC Private Variables
EricLew	0:80ee8f3b695e	117	* @{
EricLew	0:80ee8f3b695e	118	*/
EricLew	0:80ee8f3b695e	119	const uint8_t APBAHBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
EricLew	0:80ee8f3b695e	120
EricLew	0:80ee8f3b695e	121	extern const uint32_t MSIRangeTable[]; /* Defined in CMSIS (system_stm32l4xx.c)*/
EricLew	0:80ee8f3b695e	122	/**
EricLew	0:80ee8f3b695e	123	* @}
EricLew	0:80ee8f3b695e	124	*/
EricLew	0:80ee8f3b695e	125
EricLew	0:80ee8f3b695e	126	/* Private function prototypes -----------------------------------------------*/
EricLew	0:80ee8f3b695e	127	/** @defgroup RCC_Private_Functions RCC Private Functions
EricLew	0:80ee8f3b695e	128	* @{
EricLew	0:80ee8f3b695e	129	*/
EricLew	0:80ee8f3b695e	130	static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange);
EricLew	0:80ee8f3b695e	131	/**
EricLew	0:80ee8f3b695e	132	* @}
EricLew	0:80ee8f3b695e	133	*/
EricLew	0:80ee8f3b695e	134
EricLew	0:80ee8f3b695e	135	/* Exported functions --------------------------------------------------------*/
EricLew	0:80ee8f3b695e	136
EricLew	0:80ee8f3b695e	137	/** @defgroup RCC_Exported_Functions RCC Exported Functions
EricLew	0:80ee8f3b695e	138	* @{
EricLew	0:80ee8f3b695e	139	*/
EricLew	0:80ee8f3b695e	140
EricLew	0:80ee8f3b695e	141	/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
EricLew	0:80ee8f3b695e	142	* @brief Initialization and Configuration functions
EricLew	0:80ee8f3b695e	143	*
EricLew	0:80ee8f3b695e	144	@verbatim
EricLew	0:80ee8f3b695e	145	===============================================================================
EricLew	0:80ee8f3b695e	146	##### Initialization and de-initialization functions #####
EricLew	0:80ee8f3b695e	147	===============================================================================
EricLew	0:80ee8f3b695e	148	[..]
EricLew	0:80ee8f3b695e	149	This section provides functions allowing to configure the internal and external oscillators
EricLew	0:80ee8f3b695e	150	(HSE, HSI, LSE, MSI, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
EricLew	0:80ee8f3b695e	151	and APB2).
EricLew	0:80ee8f3b695e	152
EricLew	0:80ee8f3b695e	153	[..] Internal/external clock and PLL configuration
EricLew	0:80ee8f3b695e	154	(+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through
EricLew	0:80ee8f3b695e	155	the PLL as System clock source.
EricLew	0:80ee8f3b695e	156
EricLew	0:80ee8f3b695e	157	(+) MSI (Mutiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ.
EricLew	0:80ee8f3b695e	158	It can be used to generate the clock for the USB OTG FS (48 MHz).
EricLew	0:80ee8f3b695e	159	The number of flash wait states is automatically adjusted when MSI range is updated with
EricLew	0:80ee8f3b695e	160	HAL_RCC_OscConfig() and the MSI is used as System clock source.
EricLew	0:80ee8f3b695e	161
EricLew	0:80ee8f3b695e	162	(+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC
EricLew	0:80ee8f3b695e	163	clock source.
EricLew	0:80ee8f3b695e	164
EricLew	0:80ee8f3b695e	165	(+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or
EricLew	0:80ee8f3b695e	166	through the PLL as System clock source. Can be used also optionally as RTC clock source.
EricLew	0:80ee8f3b695e	167
EricLew	0:80ee8f3b695e	168	(+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source.
EricLew	0:80ee8f3b695e	169
EricLew	0:80ee8f3b695e	170	(+) PLL (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
EricLew	0:80ee8f3b695e	171	(++) The first output is used to generate the high speed system clock (up to 80MHz).
EricLew	0:80ee8f3b695e	172	(++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
EricLew	0:80ee8f3b695e	173	the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
EricLew	0:80ee8f3b695e	174	(++) The third output is used to generate an accurate clock to achieve
EricLew	0:80ee8f3b695e	175	high-quality audio performance on SAI interface.
EricLew	0:80ee8f3b695e	176
EricLew	0:80ee8f3b695e	177	(+) PLLSAI1 (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
EricLew	0:80ee8f3b695e	178	(++) The first output is used to generate SAR ADC1 clock.
EricLew	0:80ee8f3b695e	179	(++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
EricLew	0:80ee8f3b695e	180	the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
EricLew	0:80ee8f3b695e	181	(++) The Third output is used to generate an accurate clock to achieve
EricLew	0:80ee8f3b695e	182	high-quality audio performance on SAI interface.
EricLew	0:80ee8f3b695e	183
EricLew	0:80ee8f3b695e	184	(+) PLLSAI2 (clocked by HSI , HSE or MSI) providing up to two independent output clocks:
EricLew	0:80ee8f3b695e	185	(++) The first output is used to generate SAR ADC2 clock.
EricLew	0:80ee8f3b695e	186	(++) The second output is used to generate an accurate clock to achieve
EricLew	0:80ee8f3b695e	187	high-quality audio performance on SAI interface.
EricLew	0:80ee8f3b695e	188
EricLew	0:80ee8f3b695e	189	(+) CSS (Clock security system): once enabled, if a HSE clock failure occurs
EricLew	0:80ee8f3b695e	190	(HSE used directly or through PLL as System clock source), the System clock
EricLew	0:80ee8f3b695e	191	is automatically switched to HSI and an interrupt is generated if enabled.
EricLew	0:80ee8f3b695e	192	The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
EricLew	0:80ee8f3b695e	193	exception vector.
EricLew	0:80ee8f3b695e	194
EricLew	0:80ee8f3b695e	195	(+) MCO (microcontroller clock output): used to output MSI, LSI, HSI, LSE, HSE or
EricLew	0:80ee8f3b695e	196	main PLL clock (through a configurable prescaler) on PA8 pin.
EricLew	0:80ee8f3b695e	197
EricLew	0:80ee8f3b695e	198	[..] System, AHB and APB busses clocks configuration
EricLew	0:80ee8f3b695e	199	(+) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,
EricLew	0:80ee8f3b695e	200	HSE and main PLL.
EricLew	0:80ee8f3b695e	201	The AHB clock (HCLK) is derived from System clock through configurable
EricLew	0:80ee8f3b695e	202	prescaler and used to clock the CPU, memory and peripherals mapped
EricLew	0:80ee8f3b695e	203	on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
EricLew	0:80ee8f3b695e	204	from AHB clock through configurable prescalers and used to clock
EricLew	0:80ee8f3b695e	205	the peripherals mapped on these busses. You can use
EricLew	0:80ee8f3b695e	206	"HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
EricLew	0:80ee8f3b695e	207
EricLew	0:80ee8f3b695e	208	-@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
EricLew	0:80ee8f3b695e	209
EricLew	0:80ee8f3b695e	210	(+@) SAI: the SAI clock can be derived either from a specific PLL (PLLSAI1) or (PLLSAI2) or
EricLew	0:80ee8f3b695e	211	from an external clock mapped on the SAI_CKIN pin.
EricLew	0:80ee8f3b695e	212	You have to use HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
EricLew	0:80ee8f3b695e	213	(+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
EricLew	0:80ee8f3b695e	214	divided by 2 to 31.
EricLew	0:80ee8f3b695e	215	You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function
EricLew	0:80ee8f3b695e	216	to configure this clock.
EricLew	0:80ee8f3b695e	217	(+@) USB OTG FS, SDMMC1 and RNG: USB OTG FS requires a frequency equal to 48 MHz
EricLew	0:80ee8f3b695e	218	to work correctly, while the SDMMC1 and RNG peripherals require a frequency
EricLew	0:80ee8f3b695e	219	equal or lower than to 48 MHz. This clock is derived of the main PLL or PLLSAI1
EricLew	0:80ee8f3b695e	220	through PLLQ divider. You have to enable the peripheral clock and use
EricLew	0:80ee8f3b695e	221	HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
EricLew	0:80ee8f3b695e	222	(+@) IWDG clock which is always the LSI clock.
EricLew	0:80ee8f3b695e	223
EricLew	0:80ee8f3b695e	224
EricLew	0:80ee8f3b695e	225	(+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 80 MHz.
EricLew	0:80ee8f3b695e	226	Depending on the device voltage range, the maximum frequency should be
EricLew	0:80ee8f3b695e	227	adapted accordingly:
EricLew	0:80ee8f3b695e	228
EricLew	0:80ee8f3b695e	229	(++) Table 1. HCLK clock frequency.
EricLew	0:80ee8f3b695e	230	(++) +-------------------------------------------------------+
EricLew	0:80ee8f3b695e	231	(++) \| Latency \| HCLK clock frequency (MHz) \|
EricLew	0:80ee8f3b695e	232	(++) \| \|-------------------------------------\|
EricLew	0:80ee8f3b695e	233	(++) \| \| voltage range 1 \| voltage range 2 \|
EricLew	0:80ee8f3b695e	234	(++) \| \| 1.2 V \| 1.0 V \|
EricLew	0:80ee8f3b695e	235	(++) \|-----------------\|------------------\|------------------\|
EricLew	0:80ee8f3b695e	236	(++) \|0WS(1 CPU cycles)\| 0 < HCLK <= 16 \| 0 < HCLK <= 6 \|
EricLew	0:80ee8f3b695e	237	(++) \|-----------------\|------------------\|------------------\|
EricLew	0:80ee8f3b695e	238	(++) \|1WS(2 CPU cycles)\| 16 < HCLK <= 32 \| 6 < HCLK <= 12 \|
EricLew	0:80ee8f3b695e	239	(++) \|-----------------\|------------------\|------------------\|
EricLew	0:80ee8f3b695e	240	(++) \|2WS(3 CPU cycles)\| 32 < HCLK <= 48 \| 12 < HCLK <= 18 \|
EricLew	0:80ee8f3b695e	241	(++) \|-----------------\|------------------\|------------------\|
EricLew	0:80ee8f3b695e	242	(++) \|3WS(4 CPU cycles)\| 48 < HCLK <= 64 \| 18 < HCLK <= 26 \|
EricLew	0:80ee8f3b695e	243	(++) \|-----------------\|------------------\|------------------\|
EricLew	0:80ee8f3b695e	244	(++) \|4WS(5 CPU cycles)\| 64 < HCLK <= 80 \| 18 < HCLK <= 26 \|
EricLew	0:80ee8f3b695e	245	(++) +-------------------------------------------------------+
EricLew	0:80ee8f3b695e	246
EricLew	0:80ee8f3b695e	247	@endverbatim
EricLew	0:80ee8f3b695e	248	* @{
EricLew	0:80ee8f3b695e	249	*/
EricLew	0:80ee8f3b695e	250
EricLew	0:80ee8f3b695e	251	/**
EricLew	0:80ee8f3b695e	252	* @brief Reset the RCC clock configuration to the default reset state.
EricLew	0:80ee8f3b695e	253	* @note The default reset state of the clock configuration is given below:
EricLew	0:80ee8f3b695e	254	* - MSI ON and used as system clock source
EricLew	0:80ee8f3b695e	255	* - HSE, HSI, PLL, PLLSAI1 and PLLISAI2 OFF
EricLew	0:80ee8f3b695e	256	* - AHB, APB1 and APB2 prescaler set to 1.
EricLew	0:80ee8f3b695e	257	* - CSS, MCO1 OFF
EricLew	0:80ee8f3b695e	258	* - All interrupts disabled
EricLew	0:80ee8f3b695e	259	* @note This function doesn't modify the configuration of the
EricLew	0:80ee8f3b695e	260	* - Peripheral clocks
EricLew	0:80ee8f3b695e	261	* - LSI, LSE and RTC clocks
EricLew	0:80ee8f3b695e	262	* @retval None
EricLew	0:80ee8f3b695e	263	*/
EricLew	0:80ee8f3b695e	264	void HAL_RCC_DeInit(void)
EricLew	0:80ee8f3b695e	265	{
EricLew	0:80ee8f3b695e	266	/* Set MSION bit */
EricLew	0:80ee8f3b695e	267	SET_BIT(RCC->CR, RCC_CR_MSION);
EricLew	0:80ee8f3b695e	268
EricLew	0:80ee8f3b695e	269	/* Insure MSIRDY bit is set before writing default MSIRANGE value */
EricLew	0:80ee8f3b695e	270	while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) { __NOP(); }
EricLew	0:80ee8f3b695e	271
EricLew	0:80ee8f3b695e	272	/* Set MSIRANGE default value */
EricLew	0:80ee8f3b695e	273	MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, RCC_MSIRANGE_6);
EricLew	0:80ee8f3b695e	274
EricLew	0:80ee8f3b695e	275	/* Reset CFGR register (MSI is selected as system clock source) */
EricLew	0:80ee8f3b695e	276	CLEAR_REG(RCC->CFGR);
EricLew	0:80ee8f3b695e	277
EricLew	0:80ee8f3b695e	278	/* Reset HSION, HSIKERON, HSIASFS, HSEON, HSECSSON, PLLON, PLLSAIxON bits */
EricLew	0:80ee8f3b695e	279	CLEAR_BIT(RCC->CR, RCC_CR_HSEON \| RCC_CR_HSION \| RCC_CR_HSIKERON\| RCC_CR_HSIASFS \| RCC_CR_CSSON \| RCC_CR_PLLON \| RCC_CR_PLLSAI1ON \| RCC_CR_PLLSAI2ON);
EricLew	0:80ee8f3b695e	280
EricLew	0:80ee8f3b695e	281	/* Reset PLLCFGR register */
EricLew	0:80ee8f3b695e	282	CLEAR_REG(RCC->PLLCFGR);
EricLew	0:80ee8f3b695e	283	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN_4 );
EricLew	0:80ee8f3b695e	284
EricLew	0:80ee8f3b695e	285	/* Reset PLLSAI1CFGR register */
EricLew	0:80ee8f3b695e	286	CLEAR_REG(RCC->PLLSAI1CFGR);
EricLew	0:80ee8f3b695e	287	SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N_4 );
EricLew	0:80ee8f3b695e	288
EricLew	0:80ee8f3b695e	289	/* Reset PLLSAI2CFGR register */
EricLew	0:80ee8f3b695e	290	CLEAR_REG(RCC->PLLSAI2CFGR);
EricLew	0:80ee8f3b695e	291	SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N_4 );
EricLew	0:80ee8f3b695e	292
EricLew	0:80ee8f3b695e	293	/* Reset HSEBYP bit */
EricLew	0:80ee8f3b695e	294	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
EricLew	0:80ee8f3b695e	295
EricLew	0:80ee8f3b695e	296	/* Disable all interrupts */
EricLew	0:80ee8f3b695e	297	CLEAR_REG(RCC->CIER);
EricLew	0:80ee8f3b695e	298	}
EricLew	0:80ee8f3b695e	299
EricLew	0:80ee8f3b695e	300	/**
EricLew	0:80ee8f3b695e	301	* @brief Initialize the RCC Oscillators according to the specified parameters in the
EricLew	0:80ee8f3b695e	302	* RCC_OscInitTypeDef.
EricLew	0:80ee8f3b695e	303	* @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
EricLew	0:80ee8f3b695e	304	* contains the configuration information for the RCC Oscillators.
EricLew	0:80ee8f3b695e	305	* @note The PLL is not disabled when used as system clock.
EricLew	0:80ee8f3b695e	306	* @retval HAL status
EricLew	0:80ee8f3b695e	307	*/
EricLew	0:80ee8f3b695e	308	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
EricLew	0:80ee8f3b695e	309	{
EricLew	0:80ee8f3b695e	310	uint32_t tickstart = 0;
EricLew	0:80ee8f3b695e	311
EricLew	0:80ee8f3b695e	312	/* Check the parameters */
EricLew	0:80ee8f3b695e	313	assert_param(RCC_OscInitStruct != NULL);
EricLew	0:80ee8f3b695e	314	assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
EricLew	0:80ee8f3b695e	315
EricLew	0:80ee8f3b695e	316	/----------------------------- MSI Configuration --------------------------/
EricLew	0:80ee8f3b695e	317	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
EricLew	0:80ee8f3b695e	318	{
EricLew	0:80ee8f3b695e	319	/* Check the parameters */
EricLew	0:80ee8f3b695e	320	assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
EricLew	0:80ee8f3b695e	321	assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
EricLew	0:80ee8f3b695e	322	assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
EricLew	0:80ee8f3b695e	323
EricLew	0:80ee8f3b695e	324	/* When the MSI is used as system clock it will not be disabled */
EricLew	0:80ee8f3b695e	325	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) )
EricLew	0:80ee8f3b695e	326	{
EricLew	0:80ee8f3b695e	327	if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != RESET) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
EricLew	0:80ee8f3b695e	328	{
EricLew	0:80ee8f3b695e	329	return HAL_ERROR;
EricLew	0:80ee8f3b695e	330	}
EricLew	0:80ee8f3b695e	331
EricLew	0:80ee8f3b695e	332	/* Otherwise, just the calibration and MSI range change are allowed */
EricLew	0:80ee8f3b695e	333	else
EricLew	0:80ee8f3b695e	334	{
EricLew	0:80ee8f3b695e	335	/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
EricLew	0:80ee8f3b695e	336	must be correctly programmed according to the frequency of the CPU clock
EricLew	0:80ee8f3b695e	337	(HCLK) and the supply voltage of the device. */
EricLew	0:80ee8f3b695e	338	if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
EricLew	0:80ee8f3b695e	339	{
EricLew	0:80ee8f3b695e	340	/* First increase number of wait states update if necessary */
EricLew	0:80ee8f3b695e	341	if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
EricLew	0:80ee8f3b695e	342	{
EricLew	0:80ee8f3b695e	343	return HAL_ERROR;
EricLew	0:80ee8f3b695e	344	}
EricLew	0:80ee8f3b695e	345
EricLew	0:80ee8f3b695e	346	/* Selects the Multiple Speed oscillator (MSI) clock range .*/
EricLew	0:80ee8f3b695e	347	__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
EricLew	0:80ee8f3b695e	348	/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
EricLew	0:80ee8f3b695e	349	__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
EricLew	0:80ee8f3b695e	350	}
EricLew	0:80ee8f3b695e	351	else
EricLew	0:80ee8f3b695e	352	{
EricLew	0:80ee8f3b695e	353	/* Else, keep current flash latency while decreasing applies */
EricLew	0:80ee8f3b695e	354	/* Selects the Multiple Speed oscillator (MSI) clock range .*/
EricLew	0:80ee8f3b695e	355	__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
EricLew	0:80ee8f3b695e	356	/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
EricLew	0:80ee8f3b695e	357	__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
EricLew	0:80ee8f3b695e	358
EricLew	0:80ee8f3b695e	359	/* Decrease number of wait states update if necessary */
EricLew	0:80ee8f3b695e	360	if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
EricLew	0:80ee8f3b695e	361	{
EricLew	0:80ee8f3b695e	362	return HAL_ERROR;
EricLew	0:80ee8f3b695e	363	}
EricLew	0:80ee8f3b695e	364	}
EricLew	0:80ee8f3b695e	365
EricLew	0:80ee8f3b695e	366	/* Configure the source of time base considering new system clocks settings*/
EricLew	0:80ee8f3b695e	367	HAL_InitTick (TICK_INT_PRIORITY);
EricLew	0:80ee8f3b695e	368	}
EricLew	0:80ee8f3b695e	369	}
EricLew	0:80ee8f3b695e	370	else
EricLew	0:80ee8f3b695e	371	{
EricLew	0:80ee8f3b695e	372	/* Check the MSI State */
EricLew	0:80ee8f3b695e	373	if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
EricLew	0:80ee8f3b695e	374	{
EricLew	0:80ee8f3b695e	375	/* Enable the Internal High Speed oscillator (MSI). */
EricLew	0:80ee8f3b695e	376	__HAL_RCC_MSI_ENABLE();
EricLew	0:80ee8f3b695e	377
EricLew	0:80ee8f3b695e	378	/* Get timeout */
EricLew	0:80ee8f3b695e	379	tickstart = HAL_GetTick();
EricLew	0:80ee8f3b695e	380
EricLew	0:80ee8f3b695e	381	/* Wait till MSI is ready */
EricLew	0:80ee8f3b695e	382	while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET)
EricLew	0:80ee8f3b695e	383	{
EricLew	0:80ee8f3b695e	384	if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
EricLew	0:80ee8f3b695e	385	{
EricLew	0:80ee8f3b695e	386	return HAL_TIMEOUT;
EricLew	0:80ee8f3b695e	387	}
EricLew	0:80ee8f3b695e	388	}
EricLew	0:80ee8f3b695e	389	/* Selects the Multiple Speed oscillator (MSI) clock range .*/
EricLew	0:80ee8f3b695e	390	__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
EricLew	0:80ee8f3b695e	391	/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
EricLew	0:80ee8f3b695e	392	__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
EricLew	0:80ee8f3b695e	393
EricLew	0:80ee8f3b695e	394	}
EricLew	0:80ee8f3b695e	395	else
EricLew	0:80ee8f3b695e	396	{
EricLew	0:80ee8f3b695e	397	/* Disable the Internal High Speed oscillator (MSI). */
EricLew	0:80ee8f3b695e	398	__HAL_RCC_MSI_DISABLE();
EricLew	0:80ee8f3b695e	399
EricLew	0:80ee8f3b695e	400	/* Get timeout */
EricLew	0:80ee8f3b695e	401	tickstart = HAL_GetTick();
EricLew	0:80ee8f3b695e	402
EricLew	0:80ee8f3b695e	403	/* Wait till MSI is ready */
EricLew	0:80ee8f3b695e	404	while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != RESET)
EricLew	0:80ee8f3b695e	405	{
EricLew	0:80ee8f3b695e	406	if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
EricLew	0:80ee8f3b695e	407	{
EricLew	0:80ee8f3b695e	408	return HAL_TIMEOUT;
EricLew	0:80ee8f3b695e	409	}
EricLew	0:80ee8f3b695e	410	}
EricLew	0:80ee8f3b695e	411	}
EricLew	0:80ee8f3b695e	412	}
EricLew	0:80ee8f3b695e	413	}
EricLew	0:80ee8f3b695e	414	/------------------------------- HSE Configuration ------------------------/
EricLew	0:80ee8f3b695e	415	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
EricLew	0:80ee8f3b695e	416	{
EricLew	0:80ee8f3b695e	417	/* Check the parameters */
EricLew	0:80ee8f3b695e	418	assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
EricLew	0:80ee8f3b695e	419
EricLew	0:80ee8f3b695e	420	/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
EricLew	0:80ee8f3b695e	421	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) \|\|
EricLew	0:80ee8f3b695e	422	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
EricLew	0:80ee8f3b695e	423	{
EricLew	0:80ee8f3b695e	424	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
EricLew	0:80ee8f3b695e	425	{
EricLew	0:80ee8f3b695e	426	return HAL_ERROR;
EricLew	0:80ee8f3b695e	427	}
EricLew	0:80ee8f3b695e	428	}
EricLew	0:80ee8f3b695e	429	else
EricLew	0:80ee8f3b695e	430	{
EricLew	0:80ee8f3b695e	431	/* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
EricLew	0:80ee8f3b695e	432	__HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
EricLew	0:80ee8f3b695e	433
EricLew	0:80ee8f3b695e	434	/* Get Start Tick*/
EricLew	0:80ee8f3b695e	435	tickstart = HAL_GetTick();
EricLew	0:80ee8f3b695e	436
EricLew	0:80ee8f3b695e	437	/* Wait till HSE is disabled */
EricLew	0:80ee8f3b695e	438	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
EricLew	0:80ee8f3b695e	439	{
EricLew	0:80ee8f3b695e	440	if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
EricLew	0:80ee8f3b695e	441	{
EricLew	0:80ee8f3b695e	442	return HAL_TIMEOUT;
EricLew	0:80ee8f3b695e	443	}
EricLew	0:80ee8f3b695e	444	}
EricLew	0:80ee8f3b695e	445
EricLew	0:80ee8f3b695e	446	/* Set the new HSE configuration ---------------------------------------*/
EricLew	0:80ee8f3b695e	447	__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
EricLew	0:80ee8f3b695e	448
EricLew	0:80ee8f3b695e	449	/* Check the HSE State */
EricLew	0:80ee8f3b695e	450	if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
EricLew	0:80ee8f3b695e	451	{
EricLew	0:80ee8f3b695e	452	/* Get Start Tick*/
EricLew	0:80ee8f3b695e	453	tickstart = HAL_GetTick();
EricLew	0:80ee8f3b695e	454
EricLew	0:80ee8f3b695e	455	/* Wait till HSE is ready */
EricLew	0:80ee8f3b695e	456	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
EricLew	0:80ee8f3b695e	457	{
EricLew	0:80ee8f3b695e	458	if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
EricLew	0:80ee8f3b695e	459	{
EricLew	0:80ee8f3b695e	460	return HAL_TIMEOUT;
EricLew	0:80ee8f3b695e	461	}
EricLew	0:80ee8f3b695e	462	}
EricLew	0:80ee8f3b695e	463	}
EricLew	0:80ee8f3b695e	464	else
EricLew	0:80ee8f3b695e	465	{
EricLew	0:80ee8f3b695e	466	/* Get Start Tick*/
EricLew	0:80ee8f3b695e	467	tickstart = HAL_GetTick();
EricLew	0:80ee8f3b695e	468
EricLew	0:80ee8f3b695e	469	/* Wait till HSE is disabled */
EricLew	0:80ee8f3b695e	470	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
EricLew	0:80ee8f3b695e	471	{
EricLew	0:80ee8f3b695e	472	if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
EricLew	0:80ee8f3b695e	473	{
EricLew	0:80ee8f3b695e	474	return HAL_TIMEOUT;
EricLew	0:80ee8f3b695e	475	}
EricLew	0:80ee8f3b695e	476	}
EricLew	0:80ee8f3b695e	477	}
EricLew	0:80ee8f3b695e	478	}
EricLew	0:80ee8f3b695e	479	}
EricLew	0:80ee8f3b695e	480	/----------------------------- HSI Configuration --------------------------/
EricLew	0:80ee8f3b695e	481	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
EricLew	0:80ee8f3b695e	482	{
EricLew	0:80ee8f3b695e	483	/* Check the parameters */
EricLew	0:80ee8f3b695e	484	assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
EricLew	0:80ee8f3b695e	485	assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
EricLew	0:80ee8f3b695e	486
EricLew	0:80ee8f3b695e	487	/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
EricLew	0:80ee8f3b695e	488	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) \|\|
EricLew	0:80ee8f3b695e	489	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
EricLew	0:80ee8f3b695e	490	{
EricLew	0:80ee8f3b695e	491	/* When HSI is used as system clock it will not be disabled */
EricLew	0:80ee8f3b695e	492	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
EricLew	0:80ee8f3b695e	493	{
EricLew	0:80ee8f3b695e	494	return HAL_ERROR;
EricLew	0:80ee8f3b695e	495	}
EricLew	0:80ee8f3b695e	496	/* Otherwise, just the calibration is allowed */
EricLew	0:80ee8f3b695e	497	else
EricLew	0:80ee8f3b695e	498	{
EricLew	0:80ee8f3b695e	499	/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
EricLew	0:80ee8f3b695e	500	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
EricLew	0:80ee8f3b695e	501	}
EricLew	0:80ee8f3b695e	502	}
EricLew	0:80ee8f3b695e	503	else
EricLew	0:80ee8f3b695e	504	{
EricLew	0:80ee8f3b695e	505	/* Check the HSI State */
EricLew	0:80ee8f3b695e	506	if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
EricLew	0:80ee8f3b695e	507	{
EricLew	0:80ee8f3b695e	508	/* Enable the Internal High Speed oscillator (HSI). */
EricLew	0:80ee8f3b695e	509	__HAL_RCC_HSI_ENABLE();
EricLew	0:80ee8f3b695e	510
EricLew	0:80ee8f3b695e	511	/* Get Start Tick*/
EricLew	0:80ee8f3b695e	512	tickstart = HAL_GetTick();
EricLew	0:80ee8f3b695e	513
EricLew	0:80ee8f3b695e	514	/* Wait till HSI is ready */
EricLew	0:80ee8f3b695e	515	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
EricLew	0:80ee8f3b695e	516	{
EricLew	0:80ee8f3b695e	517	if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
EricLew	0:80ee8f3b695e	518	{
EricLew	0:80ee8f3b695e	519	return HAL_TIMEOUT;
EricLew	0:80ee8f3b695e	520	}
EricLew	0:80ee8f3b695e	521	}
EricLew	0:80ee8f3b695e	522
EricLew	0:80ee8f3b695e	523	/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
EricLew	0:80ee8f3b695e	524	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
EricLew	0:80ee8f3b695e	525	}
EricLew	0:80ee8f3b695e	526	else
EricLew	0:80ee8f3b695e	527	{
EricLew	0:80ee8f3b695e	528	/* Disable the Internal High Speed oscillator (HSI). */
EricLew	0:80ee8f3b695e	529	__HAL_RCC_HSI_DISABLE();
EricLew	0:80ee8f3b695e	530
EricLew	0:80ee8f3b695e	531	/* Get Start Tick*/
EricLew	0:80ee8f3b695e	532	tickstart = HAL_GetTick();
EricLew	0:80ee8f3b695e	533
EricLew	0:80ee8f3b695e	534	/* Wait till HSI is disabled */
EricLew	0:80ee8f3b695e	535	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
EricLew	0:80ee8f3b695e	536	{
EricLew	0:80ee8f3b695e	537	if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
EricLew	0:80ee8f3b695e	538	{
EricLew	0:80ee8f3b695e	539	return HAL_TIMEOUT;
EricLew	0:80ee8f3b695e	540	}
EricLew	0:80ee8f3b695e	541	}
EricLew	0:80ee8f3b695e	542	}
EricLew	0:80ee8f3b695e	543	}
EricLew	0:80ee8f3b695e	544	}
EricLew	0:80ee8f3b695e	545	/------------------------------ LSI Configuration -------------------------/
EricLew	0:80ee8f3b695e	546	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
EricLew	0:80ee8f3b695e	547	{
EricLew	0:80ee8f3b695e	548	/* Check the parameters */
EricLew	0:80ee8f3b695e	549	assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
EricLew	0:80ee8f3b695e	550
EricLew	0:80ee8f3b695e	551	/* Check the LSI State */
EricLew	0:80ee8f3b695e	552	if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
EricLew	0:80ee8f3b695e	553	{
EricLew	0:80ee8f3b695e	554	/* Enable the Internal Low Speed oscillator (LSI). */
EricLew	0:80ee8f3b695e	555	__HAL_RCC_LSI_ENABLE();
EricLew	0:80ee8f3b695e	556
EricLew	0:80ee8f3b695e	557	/* Get Start Tick*/
EricLew	0:80ee8f3b695e	558	tickstart = HAL_GetTick();
EricLew	0:80ee8f3b695e	559
EricLew	0:80ee8f3b695e	560	/* Wait till LSI is ready */
EricLew	0:80ee8f3b695e	561	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
EricLew	0:80ee8f3b695e	562	{
EricLew	0:80ee8f3b695e	563	if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
EricLew	0:80ee8f3b695e	564	{
EricLew	0:80ee8f3b695e	565	return HAL_TIMEOUT;
EricLew	0:80ee8f3b695e	566	}
EricLew	0:80ee8f3b695e	567	}
EricLew	0:80ee8f3b695e	568	}
EricLew	0:80ee8f3b695e	569	else
EricLew	0:80ee8f3b695e	570	{
EricLew	0:80ee8f3b695e	571	/* Disable the Internal Low Speed oscillator (LSI). */
EricLew	0:80ee8f3b695e	572	__HAL_RCC_LSI_DISABLE();
EricLew	0:80ee8f3b695e	573
EricLew	0:80ee8f3b695e	574	/* Get Start Tick*/
EricLew	0:80ee8f3b695e	575	tickstart = HAL_GetTick();
EricLew	0:80ee8f3b695e	576
EricLew	0:80ee8f3b695e	577	/* Wait till LSI is disabled */
EricLew	0:80ee8f3b695e	578	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
EricLew	0:80ee8f3b695e	579	{
EricLew	0:80ee8f3b695e	580	if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
EricLew	0:80ee8f3b695e	581	{
EricLew	0:80ee8f3b695e	582	return HAL_TIMEOUT;
EricLew	0:80ee8f3b695e	583	}
EricLew	0:80ee8f3b695e	584	}
EricLew	0:80ee8f3b695e	585	}
EricLew	0:80ee8f3b695e	586	}
EricLew	0:80ee8f3b695e	587	/------------------------------ LSE Configuration -------------------------/
EricLew	0:80ee8f3b695e	588	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
EricLew	0:80ee8f3b695e	589	{
EricLew	0:80ee8f3b695e	590	FlagStatus pwrclkchanged = RESET;
EricLew	0:80ee8f3b695e	591
EricLew	0:80ee8f3b695e	592	/* Check the parameters */
EricLew	0:80ee8f3b695e	593	assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
EricLew	0:80ee8f3b695e	594
EricLew	0:80ee8f3b695e	595	/* Update LSE configuration in Backup Domain control register */
EricLew	0:80ee8f3b695e	596	/* Requires to enable write access to Backup Domain of necessary */
EricLew	0:80ee8f3b695e	597	if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN))
EricLew	0:80ee8f3b695e	598	{
EricLew	0:80ee8f3b695e	599	__HAL_RCC_PWR_CLK_ENABLE();
EricLew	0:80ee8f3b695e	600	pwrclkchanged = SET;
EricLew	0:80ee8f3b695e	601	}
EricLew	0:80ee8f3b695e	602
EricLew	0:80ee8f3b695e	603	if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
EricLew	0:80ee8f3b695e	604	{
EricLew	0:80ee8f3b695e	605	/* Enable write access to Backup domain */
EricLew	0:80ee8f3b695e	606	SET_BIT(PWR->CR1, PWR_CR1_DBP);
EricLew	0:80ee8f3b695e	607
EricLew	0:80ee8f3b695e	608	/* Wait for Backup domain Write protection disable */
EricLew	0:80ee8f3b695e	609	tickstart = HAL_GetTick();
EricLew	0:80ee8f3b695e	610
EricLew	0:80ee8f3b695e	611	while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
EricLew	0:80ee8f3b695e	612	{
EricLew	0:80ee8f3b695e	613	if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
EricLew	0:80ee8f3b695e	614	{
EricLew	0:80ee8f3b695e	615	return HAL_TIMEOUT;
EricLew	0:80ee8f3b695e	616	}
EricLew	0:80ee8f3b695e	617	}
EricLew	0:80ee8f3b695e	618	}
EricLew	0:80ee8f3b695e	619
EricLew	0:80ee8f3b695e	620	/* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
EricLew	0:80ee8f3b695e	621	__HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
EricLew	0:80ee8f3b695e	622
EricLew	0:80ee8f3b695e	623	/* Get Start Tick*/
EricLew	0:80ee8f3b695e	624	tickstart = HAL_GetTick();
EricLew	0:80ee8f3b695e	625
EricLew	0:80ee8f3b695e	626	/* Wait till LSE is ready */
EricLew	0:80ee8f3b695e	627	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
EricLew	0:80ee8f3b695e	628	{
EricLew	0:80ee8f3b695e	629	if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
EricLew	0:80ee8f3b695e	630	{
EricLew	0:80ee8f3b695e	631	return HAL_TIMEOUT;
EricLew	0:80ee8f3b695e	632	}
EricLew	0:80ee8f3b695e	633	}
EricLew	0:80ee8f3b695e	634
EricLew	0:80ee8f3b695e	635	/* Set the new LSE configuration -----------------------------------------*/
EricLew	0:80ee8f3b695e	636	__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
EricLew	0:80ee8f3b695e	637
EricLew	0:80ee8f3b695e	638	/* Check the LSE State */
EricLew	0:80ee8f3b695e	639	if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
EricLew	0:80ee8f3b695e	640	{
EricLew	0:80ee8f3b695e	641	/* Get Start Tick*/
EricLew	0:80ee8f3b695e	642	tickstart = HAL_GetTick();
EricLew	0:80ee8f3b695e	643
EricLew	0:80ee8f3b695e	644	/* Wait till LSE is ready */
EricLew	0:80ee8f3b695e	645	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
EricLew	0:80ee8f3b695e	646	{
EricLew	0:80ee8f3b695e	647	if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
EricLew	0:80ee8f3b695e	648	{
EricLew	0:80ee8f3b695e	649	return HAL_TIMEOUT;
EricLew	0:80ee8f3b695e	650	}
EricLew	0:80ee8f3b695e	651	}
EricLew	0:80ee8f3b695e	652	}
EricLew	0:80ee8f3b695e	653	else
EricLew	0:80ee8f3b695e	654	{
EricLew	0:80ee8f3b695e	655	/* Get Start Tick*/
EricLew	0:80ee8f3b695e	656	tickstart = HAL_GetTick();
EricLew	0:80ee8f3b695e	657
EricLew	0:80ee8f3b695e	658	/* Wait till LSE is disabled */
EricLew	0:80ee8f3b695e	659	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
EricLew	0:80ee8f3b695e	660	{
EricLew	0:80ee8f3b695e	661	if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
EricLew	0:80ee8f3b695e	662	{
EricLew	0:80ee8f3b695e	663	return HAL_TIMEOUT;
EricLew	0:80ee8f3b695e	664	}
EricLew	0:80ee8f3b695e	665	}
EricLew	0:80ee8f3b695e	666	}
EricLew	0:80ee8f3b695e	667
EricLew	0:80ee8f3b695e	668	/* Restore clock configuration if changed */
EricLew	0:80ee8f3b695e	669	if(pwrclkchanged == SET)
EricLew	0:80ee8f3b695e	670	{
EricLew	0:80ee8f3b695e	671	__HAL_RCC_PWR_CLK_DISABLE();
EricLew	0:80ee8f3b695e	672	}
EricLew	0:80ee8f3b695e	673	}
EricLew	0:80ee8f3b695e	674	/-------------------------------- PLL Configuration -----------------------/
EricLew	0:80ee8f3b695e	675	/* Check the parameters */
EricLew	0:80ee8f3b695e	676	assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
EricLew	0:80ee8f3b695e	677
EricLew	0:80ee8f3b695e	678	if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
EricLew	0:80ee8f3b695e	679	{
EricLew	0:80ee8f3b695e	680	/* Check if the PLL is used as system clock or not */
EricLew	0:80ee8f3b695e	681	if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
EricLew	0:80ee8f3b695e	682	{
EricLew	0:80ee8f3b695e	683	if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
EricLew	0:80ee8f3b695e	684	{
EricLew	0:80ee8f3b695e	685	/* Check the parameters */
EricLew	0:80ee8f3b695e	686	assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
EricLew	0:80ee8f3b695e	687	assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
EricLew	0:80ee8f3b695e	688	assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
EricLew	0:80ee8f3b695e	689	assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
EricLew	0:80ee8f3b695e	690	assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
EricLew	0:80ee8f3b695e	691	assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
EricLew	0:80ee8f3b695e	692
EricLew	0:80ee8f3b695e	693	/* Disable the main PLL. */
EricLew	0:80ee8f3b695e	694	__HAL_RCC_PLL_DISABLE();
EricLew	0:80ee8f3b695e	695
EricLew	0:80ee8f3b695e	696	/* Get Start Tick*/
EricLew	0:80ee8f3b695e	697	tickstart = HAL_GetTick();
EricLew	0:80ee8f3b695e	698
EricLew	0:80ee8f3b695e	699	/* Wait till PLL is ready */
EricLew	0:80ee8f3b695e	700	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
EricLew	0:80ee8f3b695e	701	{
EricLew	0:80ee8f3b695e	702	if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
EricLew	0:80ee8f3b695e	703	{
EricLew	0:80ee8f3b695e	704	return HAL_TIMEOUT;
EricLew	0:80ee8f3b695e	705	}
EricLew	0:80ee8f3b695e	706	}
EricLew	0:80ee8f3b695e	707
EricLew	0:80ee8f3b695e	708	/* Configure the main PLL clock source, multiplication and division factors. */
EricLew	0:80ee8f3b695e	709	__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
EricLew	0:80ee8f3b695e	710	RCC_OscInitStruct->PLL.PLLM,
EricLew	0:80ee8f3b695e	711	RCC_OscInitStruct->PLL.PLLN,
EricLew	0:80ee8f3b695e	712	RCC_OscInitStruct->PLL.PLLP,
EricLew	0:80ee8f3b695e	713	RCC_OscInitStruct->PLL.PLLQ,
EricLew	0:80ee8f3b695e	714	RCC_OscInitStruct->PLL.PLLR);
EricLew	0:80ee8f3b695e	715
EricLew	0:80ee8f3b695e	716	/* Enable the main PLL. */
EricLew	0:80ee8f3b695e	717	__HAL_RCC_PLL_ENABLE();
EricLew	0:80ee8f3b695e	718
EricLew	0:80ee8f3b695e	719	/* Enable PLL System Clock output. */
EricLew	0:80ee8f3b695e	720	__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
EricLew	0:80ee8f3b695e	721
EricLew	0:80ee8f3b695e	722	/* Get Start Tick*/
EricLew	0:80ee8f3b695e	723	tickstart = HAL_GetTick();
EricLew	0:80ee8f3b695e	724
EricLew	0:80ee8f3b695e	725	/* Wait till PLL is ready */
EricLew	0:80ee8f3b695e	726	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
EricLew	0:80ee8f3b695e	727	{
EricLew	0:80ee8f3b695e	728	if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
EricLew	0:80ee8f3b695e	729	{
EricLew	0:80ee8f3b695e	730	return HAL_TIMEOUT;
EricLew	0:80ee8f3b695e	731	}
EricLew	0:80ee8f3b695e	732	}
EricLew	0:80ee8f3b695e	733	}
EricLew	0:80ee8f3b695e	734	else
EricLew	0:80ee8f3b695e	735	{
EricLew	0:80ee8f3b695e	736	/* Disable the main PLL. */
EricLew	0:80ee8f3b695e	737	__HAL_RCC_PLL_DISABLE();
EricLew	0:80ee8f3b695e	738
EricLew	0:80ee8f3b695e	739	/* Disable all PLL outputs to save power */
EricLew	0:80ee8f3b695e	740	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSOURCE_NONE);
EricLew	0:80ee8f3b695e	741	__HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK \| RCC_PLL_48M1CLK \| RCC_PLL_SAI3CLK);
EricLew	0:80ee8f3b695e	742
EricLew	0:80ee8f3b695e	743	/* Get Start Tick*/
EricLew	0:80ee8f3b695e	744	tickstart = HAL_GetTick();
EricLew	0:80ee8f3b695e	745
EricLew	0:80ee8f3b695e	746	/* Wait till PLL is disabled */
EricLew	0:80ee8f3b695e	747	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
EricLew	0:80ee8f3b695e	748	{
EricLew	0:80ee8f3b695e	749	if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
EricLew	0:80ee8f3b695e	750	{
EricLew	0:80ee8f3b695e	751	return HAL_TIMEOUT;
EricLew	0:80ee8f3b695e	752	}
EricLew	0:80ee8f3b695e	753	}
EricLew	0:80ee8f3b695e	754	}
EricLew	0:80ee8f3b695e	755	}
EricLew	0:80ee8f3b695e	756	else
EricLew	0:80ee8f3b695e	757	{
EricLew	0:80ee8f3b695e	758	return HAL_ERROR;
EricLew	0:80ee8f3b695e	759	}
EricLew	0:80ee8f3b695e	760	}
EricLew	0:80ee8f3b695e	761	return HAL_OK;
EricLew	0:80ee8f3b695e	762	}
EricLew	0:80ee8f3b695e	763
EricLew	0:80ee8f3b695e	764	/**
EricLew	0:80ee8f3b695e	765	* @brief Initialize the CPU, AHB and APB busses clocks according to the specified
EricLew	0:80ee8f3b695e	766	* parameters in the RCC_ClkInitStruct.
EricLew	0:80ee8f3b695e	767	* @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
EricLew	0:80ee8f3b695e	768	* contains the configuration information for the RCC peripheral.
EricLew	0:80ee8f3b695e	769	* @param FLatency FLASH Latency
EricLew	0:80ee8f3b695e	770	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	771	* @arg FLASH_LATENCY_0 FLASH 0 Latency cycle
EricLew	0:80ee8f3b695e	772	* @arg FLASH_LATENCY_1 FLASH 1 Latency cycle
EricLew	0:80ee8f3b695e	773	* @arg FLASH_LATENCY_2 FLASH 2 Latency cycle
EricLew	0:80ee8f3b695e	774	* @arg FLASH_LATENCY_3 FLASH 3 Latency cycle
EricLew	0:80ee8f3b695e	775	* @arg FLASH_LATENCY_4 FLASH 4 Latency cycle
EricLew	0:80ee8f3b695e	776	*
EricLew	0:80ee8f3b695e	777	* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
EricLew	0:80ee8f3b695e	778	* and updated by HAL_RCC_GetHCLKFreq() function called within this function
EricLew	0:80ee8f3b695e	779	*
EricLew	0:80ee8f3b695e	780	* @note The MSI is used by default as system clock source after
EricLew	0:80ee8f3b695e	781	* startup from Reset, wake-up from STANDBY mode. After restart from Reset,
EricLew	0:80ee8f3b695e	782	* the MSI frequency is set to its default value 4 MHz.
EricLew	0:80ee8f3b695e	783	*
EricLew	0:80ee8f3b695e	784	* @note The HSI can be selected as system clock source after
EricLew	0:80ee8f3b695e	785	* from STOP modes or in case of failure of the HSE used directly or indirectly
EricLew	0:80ee8f3b695e	786	* as system clock (if the Clock Security System CSS is enabled).
EricLew	0:80ee8f3b695e	787	*
EricLew	0:80ee8f3b695e	788	* @note A switch from one clock source to another occurs only if the target
EricLew	0:80ee8f3b695e	789	* clock source is ready (clock stable after startup delay or PLL locked).
EricLew	0:80ee8f3b695e	790	* If a clock source which is not yet ready is selected, the switch will
EricLew	0:80ee8f3b695e	791	* occur when the clock source is ready.
EricLew	0:80ee8f3b695e	792	*
EricLew	0:80ee8f3b695e	793	* @note You can use HAL_RCC_GetClockConfig() function to know which clock is
EricLew	0:80ee8f3b695e	794	* currently used as system clock source.
EricLew	0:80ee8f3b695e	795	*
EricLew	0:80ee8f3b695e	796	* @note Depending on the device voltage range, the software has to set correctly
EricLew	0:80ee8f3b695e	797	* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
EricLew	0:80ee8f3b695e	798	* (for more details refer to section above "Initialization/de-initialization functions")
EricLew	0:80ee8f3b695e	799	* @retval None
EricLew	0:80ee8f3b695e	800	*/
EricLew	0:80ee8f3b695e	801	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
EricLew	0:80ee8f3b695e	802	{
EricLew	0:80ee8f3b695e	803	uint32_t tickstart = 0;
EricLew	0:80ee8f3b695e	804
EricLew	0:80ee8f3b695e	805	/* Check the parameters */
EricLew	0:80ee8f3b695e	806	assert_param(RCC_ClkInitStruct != NULL);
EricLew	0:80ee8f3b695e	807	assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
EricLew	0:80ee8f3b695e	808	assert_param(IS_FLASH_LATENCY(FLatency));
EricLew	0:80ee8f3b695e	809
EricLew	0:80ee8f3b695e	810	/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
EricLew	0:80ee8f3b695e	811	must be correctly programmed according to the frequency of the CPU clock
EricLew	0:80ee8f3b695e	812	(HCLK) and the supply voltage of the device. */
EricLew	0:80ee8f3b695e	813
EricLew	0:80ee8f3b695e	814	/* Increasing the CPU frequency */
EricLew	0:80ee8f3b695e	815	if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
EricLew	0:80ee8f3b695e	816	{
EricLew	0:80ee8f3b695e	817	/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
EricLew	0:80ee8f3b695e	818	__HAL_FLASH_SET_LATENCY(FLatency);
EricLew	0:80ee8f3b695e	819
EricLew	0:80ee8f3b695e	820	/* Check that the new number of wait states is taken into account to access the Flash
EricLew	0:80ee8f3b695e	821	memory by reading the FLASH_ACR register */
EricLew	0:80ee8f3b695e	822	if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
EricLew	0:80ee8f3b695e	823	{
EricLew	0:80ee8f3b695e	824	return HAL_ERROR;
EricLew	0:80ee8f3b695e	825	}
EricLew	0:80ee8f3b695e	826
EricLew	0:80ee8f3b695e	827	/-------------------------- HCLK Configuration --------------------------/
EricLew	0:80ee8f3b695e	828	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
EricLew	0:80ee8f3b695e	829	{
EricLew	0:80ee8f3b695e	830	assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
EricLew	0:80ee8f3b695e	831	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
EricLew	0:80ee8f3b695e	832	}
EricLew	0:80ee8f3b695e	833
EricLew	0:80ee8f3b695e	834	/------------------------- SYSCLK Configuration ---------------------------/
EricLew	0:80ee8f3b695e	835	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
EricLew	0:80ee8f3b695e	836	{
EricLew	0:80ee8f3b695e	837	assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
EricLew	0:80ee8f3b695e	838
EricLew	0:80ee8f3b695e	839	/* HSE is selected as System Clock Source */
EricLew	0:80ee8f3b695e	840	if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
EricLew	0:80ee8f3b695e	841	{
EricLew	0:80ee8f3b695e	842	/* Check the HSE ready flag */
EricLew	0:80ee8f3b695e	843	if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
EricLew	0:80ee8f3b695e	844	{
EricLew	0:80ee8f3b695e	845	return HAL_ERROR;
EricLew	0:80ee8f3b695e	846	}
EricLew	0:80ee8f3b695e	847	}
EricLew	0:80ee8f3b695e	848	/* PLL is selected as System Clock Source */
EricLew	0:80ee8f3b695e	849	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
EricLew	0:80ee8f3b695e	850	{
EricLew	0:80ee8f3b695e	851	/* Check the PLL ready flag */
EricLew	0:80ee8f3b695e	852	if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
EricLew	0:80ee8f3b695e	853	{
EricLew	0:80ee8f3b695e	854	return HAL_ERROR;
EricLew	0:80ee8f3b695e	855	}
EricLew	0:80ee8f3b695e	856	}
EricLew	0:80ee8f3b695e	857	/* MSI is selected as System Clock Source */
EricLew	0:80ee8f3b695e	858	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
EricLew	0:80ee8f3b695e	859	{
EricLew	0:80ee8f3b695e	860	/* Check the MSI ready flag */
EricLew	0:80ee8f3b695e	861	if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET)
EricLew	0:80ee8f3b695e	862	{
EricLew	0:80ee8f3b695e	863	return HAL_ERROR;
EricLew	0:80ee8f3b695e	864	}
EricLew	0:80ee8f3b695e	865	}
EricLew	0:80ee8f3b695e	866	/* HSI is selected as System Clock Source */
EricLew	0:80ee8f3b695e	867	else
EricLew	0:80ee8f3b695e	868	{
EricLew	0:80ee8f3b695e	869	/* Check the HSI ready flag */
EricLew	0:80ee8f3b695e	870	if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
EricLew	0:80ee8f3b695e	871	{
EricLew	0:80ee8f3b695e	872	return HAL_ERROR;
EricLew	0:80ee8f3b695e	873	}
EricLew	0:80ee8f3b695e	874	}
EricLew	0:80ee8f3b695e	875	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
EricLew	0:80ee8f3b695e	876
EricLew	0:80ee8f3b695e	877	/* Get Start Tick*/
EricLew	0:80ee8f3b695e	878	tickstart = HAL_GetTick();
EricLew	0:80ee8f3b695e	879
EricLew	0:80ee8f3b695e	880	if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
EricLew	0:80ee8f3b695e	881	{
EricLew	0:80ee8f3b695e	882	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
EricLew	0:80ee8f3b695e	883	{
EricLew	0:80ee8f3b695e	884	if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
EricLew	0:80ee8f3b695e	885	{
EricLew	0:80ee8f3b695e	886	return HAL_TIMEOUT;
EricLew	0:80ee8f3b695e	887	}
EricLew	0:80ee8f3b695e	888	}
EricLew	0:80ee8f3b695e	889	}
EricLew	0:80ee8f3b695e	890	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
EricLew	0:80ee8f3b695e	891	{
EricLew	0:80ee8f3b695e	892	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
EricLew	0:80ee8f3b695e	893	{
EricLew	0:80ee8f3b695e	894	if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
EricLew	0:80ee8f3b695e	895	{
EricLew	0:80ee8f3b695e	896	return HAL_TIMEOUT;
EricLew	0:80ee8f3b695e	897	}
EricLew	0:80ee8f3b695e	898	}
EricLew	0:80ee8f3b695e	899	}
EricLew	0:80ee8f3b695e	900	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
EricLew	0:80ee8f3b695e	901	{
EricLew	0:80ee8f3b695e	902	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI)
EricLew	0:80ee8f3b695e	903	{
EricLew	0:80ee8f3b695e	904	if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
EricLew	0:80ee8f3b695e	905	{
EricLew	0:80ee8f3b695e	906	return HAL_TIMEOUT;
EricLew	0:80ee8f3b695e	907	}
EricLew	0:80ee8f3b695e	908	}
EricLew	0:80ee8f3b695e	909	}
EricLew	0:80ee8f3b695e	910	else
EricLew	0:80ee8f3b695e	911	{
EricLew	0:80ee8f3b695e	912	while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
EricLew	0:80ee8f3b695e	913	{
EricLew	0:80ee8f3b695e	914	if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
EricLew	0:80ee8f3b695e	915	{
EricLew	0:80ee8f3b695e	916	return HAL_TIMEOUT;
EricLew	0:80ee8f3b695e	917	}
EricLew	0:80ee8f3b695e	918	}
EricLew	0:80ee8f3b695e	919	}
EricLew	0:80ee8f3b695e	920	}
EricLew	0:80ee8f3b695e	921	}
EricLew	0:80ee8f3b695e	922	/* Decreasing the CPU frequency */
EricLew	0:80ee8f3b695e	923	else
EricLew	0:80ee8f3b695e	924	{
EricLew	0:80ee8f3b695e	925	/-------------------------- HCLK Configuration --------------------------/
EricLew	0:80ee8f3b695e	926	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
EricLew	0:80ee8f3b695e	927	{
EricLew	0:80ee8f3b695e	928	assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
EricLew	0:80ee8f3b695e	929	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
EricLew	0:80ee8f3b695e	930	}
EricLew	0:80ee8f3b695e	931
EricLew	0:80ee8f3b695e	932	/------------------------- SYSCLK Configuration -------------------------/
EricLew	0:80ee8f3b695e	933	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
EricLew	0:80ee8f3b695e	934	{
EricLew	0:80ee8f3b695e	935	assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
EricLew	0:80ee8f3b695e	936
EricLew	0:80ee8f3b695e	937	/* HSE is selected as System Clock Source */
EricLew	0:80ee8f3b695e	938	if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
EricLew	0:80ee8f3b695e	939	{
EricLew	0:80ee8f3b695e	940	/* Check the HSE ready flag */
EricLew	0:80ee8f3b695e	941	if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
EricLew	0:80ee8f3b695e	942	{
EricLew	0:80ee8f3b695e	943	return HAL_ERROR;
EricLew	0:80ee8f3b695e	944	}
EricLew	0:80ee8f3b695e	945	}
EricLew	0:80ee8f3b695e	946	/* MSI is selected as System Clock Source */
EricLew	0:80ee8f3b695e	947	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
EricLew	0:80ee8f3b695e	948	{
EricLew	0:80ee8f3b695e	949	/* Check the MSI ready flag */
EricLew	0:80ee8f3b695e	950	if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET)
EricLew	0:80ee8f3b695e	951	{
EricLew	0:80ee8f3b695e	952	return HAL_ERROR;
EricLew	0:80ee8f3b695e	953	}
EricLew	0:80ee8f3b695e	954	}
EricLew	0:80ee8f3b695e	955	/* PLL is selected as System Clock Source */
EricLew	0:80ee8f3b695e	956	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
EricLew	0:80ee8f3b695e	957	{
EricLew	0:80ee8f3b695e	958	/* Check the PLL ready flag */
EricLew	0:80ee8f3b695e	959	if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
EricLew	0:80ee8f3b695e	960	{
EricLew	0:80ee8f3b695e	961	return HAL_ERROR;
EricLew	0:80ee8f3b695e	962	}
EricLew	0:80ee8f3b695e	963	}
EricLew	0:80ee8f3b695e	964	/* HSI is selected as System Clock Source */
EricLew	0:80ee8f3b695e	965	else
EricLew	0:80ee8f3b695e	966	{
EricLew	0:80ee8f3b695e	967	/* Check the HSI ready flag */
EricLew	0:80ee8f3b695e	968	if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
EricLew	0:80ee8f3b695e	969	{
EricLew	0:80ee8f3b695e	970	return HAL_ERROR;
EricLew	0:80ee8f3b695e	971	}
EricLew	0:80ee8f3b695e	972	}
EricLew	0:80ee8f3b695e	973	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
EricLew	0:80ee8f3b695e	974
EricLew	0:80ee8f3b695e	975	/* Get Start Tick*/
EricLew	0:80ee8f3b695e	976	tickstart = HAL_GetTick();
EricLew	0:80ee8f3b695e	977
EricLew	0:80ee8f3b695e	978	if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
EricLew	0:80ee8f3b695e	979	{
EricLew	0:80ee8f3b695e	980	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
EricLew	0:80ee8f3b695e	981	{
EricLew	0:80ee8f3b695e	982	if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
EricLew	0:80ee8f3b695e	983	{
EricLew	0:80ee8f3b695e	984	return HAL_TIMEOUT;
EricLew	0:80ee8f3b695e	985	}
EricLew	0:80ee8f3b695e	986	}
EricLew	0:80ee8f3b695e	987	}
EricLew	0:80ee8f3b695e	988	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
EricLew	0:80ee8f3b695e	989	{
EricLew	0:80ee8f3b695e	990	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
EricLew	0:80ee8f3b695e	991	{
EricLew	0:80ee8f3b695e	992	if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
EricLew	0:80ee8f3b695e	993	{
EricLew	0:80ee8f3b695e	994	return HAL_TIMEOUT;
EricLew	0:80ee8f3b695e	995	}
EricLew	0:80ee8f3b695e	996	}
EricLew	0:80ee8f3b695e	997	}
EricLew	0:80ee8f3b695e	998	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
EricLew	0:80ee8f3b695e	999	{
EricLew	0:80ee8f3b695e	1000	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI)
EricLew	0:80ee8f3b695e	1001	{
EricLew	0:80ee8f3b695e	1002	if((HAL_GetTick() - tickstart) >= CLOCKSWITCH_TIMEOUT_VALUE)
EricLew	0:80ee8f3b695e	1003	{
EricLew	0:80ee8f3b695e	1004	return HAL_TIMEOUT;
EricLew	0:80ee8f3b695e	1005	}
EricLew	0:80ee8f3b695e	1006	}
EricLew	0:80ee8f3b695e	1007	}
EricLew	0:80ee8f3b695e	1008	else
EricLew	0:80ee8f3b695e	1009	{
EricLew	0:80ee8f3b695e	1010	while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
EricLew	0:80ee8f3b695e	1011	{
EricLew	0:80ee8f3b695e	1012	if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
EricLew	0:80ee8f3b695e	1013	{
EricLew	0:80ee8f3b695e	1014	return HAL_TIMEOUT;
EricLew	0:80ee8f3b695e	1015	}
EricLew	0:80ee8f3b695e	1016	}
EricLew	0:80ee8f3b695e	1017	}
EricLew	0:80ee8f3b695e	1018	}
EricLew	0:80ee8f3b695e	1019
EricLew	0:80ee8f3b695e	1020	/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
EricLew	0:80ee8f3b695e	1021	__HAL_FLASH_SET_LATENCY(FLatency);
EricLew	0:80ee8f3b695e	1022
EricLew	0:80ee8f3b695e	1023	/* Check that the new number of wait states is taken into account to access the Flash
EricLew	0:80ee8f3b695e	1024	memory by reading the FLASH_ACR register */
EricLew	0:80ee8f3b695e	1025	if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
EricLew	0:80ee8f3b695e	1026	{
EricLew	0:80ee8f3b695e	1027	return HAL_ERROR;
EricLew	0:80ee8f3b695e	1028	}
EricLew	0:80ee8f3b695e	1029	}
EricLew	0:80ee8f3b695e	1030
EricLew	0:80ee8f3b695e	1031	/-------------------------- PCLK1 Configuration ---------------------------/
EricLew	0:80ee8f3b695e	1032	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
EricLew	0:80ee8f3b695e	1033	{
EricLew	0:80ee8f3b695e	1034	assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
EricLew	0:80ee8f3b695e	1035	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
EricLew	0:80ee8f3b695e	1036	}
EricLew	0:80ee8f3b695e	1037
EricLew	0:80ee8f3b695e	1038	/-------------------------- PCLK2 Configuration ---------------------------/
EricLew	0:80ee8f3b695e	1039	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
EricLew	0:80ee8f3b695e	1040	{
EricLew	0:80ee8f3b695e	1041	assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
EricLew	0:80ee8f3b695e	1042	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
EricLew	0:80ee8f3b695e	1043	}
EricLew	0:80ee8f3b695e	1044
EricLew	0:80ee8f3b695e	1045	/* Configure the source of time base considering new system clocks settings*/
EricLew	0:80ee8f3b695e	1046	HAL_InitTick (TICK_INT_PRIORITY);
EricLew	0:80ee8f3b695e	1047
EricLew	0:80ee8f3b695e	1048	return HAL_OK;
EricLew	0:80ee8f3b695e	1049	}
EricLew	0:80ee8f3b695e	1050
EricLew	0:80ee8f3b695e	1051	/**
EricLew	0:80ee8f3b695e	1052	* @}
EricLew	0:80ee8f3b695e	1053	*/
EricLew	0:80ee8f3b695e	1054
EricLew	0:80ee8f3b695e	1055	/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
EricLew	0:80ee8f3b695e	1056	* @brief RCC clocks control functions
EricLew	0:80ee8f3b695e	1057	*
EricLew	0:80ee8f3b695e	1058	@verbatim
EricLew	0:80ee8f3b695e	1059	===============================================================================
EricLew	0:80ee8f3b695e	1060	##### Peripheral Control functions #####
EricLew	0:80ee8f3b695e	1061	===============================================================================
EricLew	0:80ee8f3b695e	1062	[..]
EricLew	0:80ee8f3b695e	1063	This subsection provides a set of functions allowing to:
EricLew	0:80ee8f3b695e	1064
EricLew	0:80ee8f3b695e	1065	(+) Ouput clock to MCO pin.
EricLew	0:80ee8f3b695e	1066	(+) Retrieve current clock frequencies.
EricLew	0:80ee8f3b695e	1067	(+) Enable the Clock Security System.
EricLew	0:80ee8f3b695e	1068
EricLew	0:80ee8f3b695e	1069	@endverbatim
EricLew	0:80ee8f3b695e	1070	* @{
EricLew	0:80ee8f3b695e	1071	*/
EricLew	0:80ee8f3b695e	1072
EricLew	0:80ee8f3b695e	1073	/**
EricLew	0:80ee8f3b695e	1074	* @brief Select the clock source to output on MCO pin(PA8).
EricLew	0:80ee8f3b695e	1075	* @note PA8 should be configured in alternate function mode.
EricLew	0:80ee8f3b695e	1076	* @param RCC_MCOx specifies the output direction for the clock source.
EricLew	0:80ee8f3b695e	1077	* For STM32L4xx family this parameter can have only one value:
EricLew	0:80ee8f3b695e	1078	* @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
EricLew	0:80ee8f3b695e	1079	* @param RCC_MCOSource specifies the clock source to output.
EricLew	0:80ee8f3b695e	1080	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1081	* @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on MCO
EricLew	0:80ee8f3b695e	1082	* @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source
EricLew	0:80ee8f3b695e	1083	* @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
EricLew	0:80ee8f3b695e	1084	* @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
EricLew	0:80ee8f3b695e	1085	* @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
EricLew	0:80ee8f3b695e	1086	* @arg @ref RCC_MCO1SOURCE_PLLCLK main PLL clock selected as MCO source
EricLew	0:80ee8f3b695e	1087	* @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
EricLew	0:80ee8f3b695e	1088	* @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
EricLew	0:80ee8f3b695e	1089	* @param RCC_MCODiv specifies the MCO prescaler.
EricLew	0:80ee8f3b695e	1090	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1091	* @arg @ref RCC_MCODIV_1 no division applied to MCO clock
EricLew	0:80ee8f3b695e	1092	* @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock
EricLew	0:80ee8f3b695e	1093	* @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock
EricLew	0:80ee8f3b695e	1094	* @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock
EricLew	0:80ee8f3b695e	1095	* @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock
EricLew	0:80ee8f3b695e	1096	* @retval None
EricLew	0:80ee8f3b695e	1097	*/
EricLew	0:80ee8f3b695e	1098	void HAL_RCC_MCOConfig( uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
EricLew	0:80ee8f3b695e	1099	{
EricLew	0:80ee8f3b695e	1100	GPIO_InitTypeDef GPIO_InitStruct;
EricLew	0:80ee8f3b695e	1101	/* Check the parameters */
EricLew	0:80ee8f3b695e	1102	assert_param(IS_RCC_MCO(RCC_MCOx));
EricLew	0:80ee8f3b695e	1103	assert_param(IS_RCC_MCODIV(RCC_MCODiv));
EricLew	0:80ee8f3b695e	1104	assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
EricLew	0:80ee8f3b695e	1105
EricLew	0:80ee8f3b695e	1106	/* MCO Clock Enable */
EricLew	0:80ee8f3b695e	1107	__MCO1_CLK_ENABLE();
EricLew	0:80ee8f3b695e	1108
EricLew	0:80ee8f3b695e	1109	/* Configue the MCO1 pin in alternate function mode */
EricLew	0:80ee8f3b695e	1110	GPIO_InitStruct.Pin = MCO1_PIN;
EricLew	0:80ee8f3b695e	1111	GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
EricLew	0:80ee8f3b695e	1112	GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
EricLew	0:80ee8f3b695e	1113	GPIO_InitStruct.Pull = GPIO_NOPULL;
EricLew	0:80ee8f3b695e	1114	GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
EricLew	0:80ee8f3b695e	1115	HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
EricLew	0:80ee8f3b695e	1116
EricLew	0:80ee8f3b695e	1117	/* Mask MCOSEL[] and MCOPRE[] bits then set MCO1 clock source and prescaler */
EricLew	0:80ee8f3b695e	1118	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL \| RCC_CFGR_MCO_PRE), (RCC_MCOSource \| RCC_MCODiv ));
EricLew	0:80ee8f3b695e	1119	}
EricLew	0:80ee8f3b695e	1120
EricLew	0:80ee8f3b695e	1121	/**
EricLew	0:80ee8f3b695e	1122	* @brief Return the SYSCLK frequency.
EricLew	0:80ee8f3b695e	1123	*
EricLew	0:80ee8f3b695e	1124	* @note The system frequency computed by this function is not the real
EricLew	0:80ee8f3b695e	1125	* frequency in the chip. It is calculated based on the predefined
EricLew	0:80ee8f3b695e	1126	* constant and the selected clock source:
EricLew	0:80ee8f3b695e	1127	* @note If SYSCLK source is MSI, function returns values based on MSI
EricLew	0:80ee8f3b695e	1128	* Value as defined by the MSI range.
EricLew	0:80ee8f3b695e	1129	* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
EricLew	0:80ee8f3b695e	1130	* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
EricLew	0:80ee8f3b695e	1131	* @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**),
EricLew	0:80ee8f3b695e	1132	* HSI_VALUE(*) or MSI Value multiplied/divided by the PLL factors.
EricLew	0:80ee8f3b695e	1133	* @note (*) HSI_VALUE is a constant defined in stm32l4xx_hal_conf.h file (default value
EricLew	0:80ee8f3b695e	1134	* 16 MHz) but the real value may vary depending on the variations
EricLew	0:80ee8f3b695e	1135	* in voltage and temperature.
EricLew	0:80ee8f3b695e	1136	* @note (**) HSE_VALUE is a constant defined in stm32l4xx_hal_conf.h file (default value
EricLew	0:80ee8f3b695e	1137	* 8 MHz), user has to ensure that HSE_VALUE is same as the real
EricLew	0:80ee8f3b695e	1138	* frequency of the crystal used. Otherwise, this function may
EricLew	0:80ee8f3b695e	1139	* have wrong result.
EricLew	0:80ee8f3b695e	1140	*
EricLew	0:80ee8f3b695e	1141	* @note The result of this function could be not correct when using fractional
EricLew	0:80ee8f3b695e	1142	* value for HSE crystal.
EricLew	0:80ee8f3b695e	1143	*
EricLew	0:80ee8f3b695e	1144	* @note This function can be used by the user application to compute the
EricLew	0:80ee8f3b695e	1145	* baudrate for the communication peripherals or configure other parameters.
EricLew	0:80ee8f3b695e	1146	*
EricLew	0:80ee8f3b695e	1147	* @note Each time SYSCLK changes, this function must be called to update the
EricLew	0:80ee8f3b695e	1148	* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
EricLew	0:80ee8f3b695e	1149	*
EricLew	0:80ee8f3b695e	1150	*
EricLew	0:80ee8f3b695e	1151	* @retval SYSCLK frequency
EricLew	0:80ee8f3b695e	1152	*/
EricLew	0:80ee8f3b695e	1153	uint32_t HAL_RCC_GetSysClockFreq(void)
EricLew	0:80ee8f3b695e	1154	{
EricLew	0:80ee8f3b695e	1155	uint32_t msirange = 0, pllvco = 0, pllr = 2, pllsource = 0, pllm = 2;
EricLew	0:80ee8f3b695e	1156	uint32_t sysclockfreq = 0;
EricLew	0:80ee8f3b695e	1157
EricLew	0:80ee8f3b695e	1158	if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
EricLew	0:80ee8f3b695e	1159	{
EricLew	0:80ee8f3b695e	1160	/* HSI used as system clock source */
EricLew	0:80ee8f3b695e	1161	sysclockfreq = HSI_VALUE;
EricLew	0:80ee8f3b695e	1162	}
EricLew	0:80ee8f3b695e	1163	else if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
EricLew	0:80ee8f3b695e	1164	{
EricLew	0:80ee8f3b695e	1165	/* HSE used as system clock source */
EricLew	0:80ee8f3b695e	1166	sysclockfreq = HSE_VALUE;
EricLew	0:80ee8f3b695e	1167	}
EricLew	0:80ee8f3b695e	1168	else if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) \|\|
EricLew	0:80ee8f3b695e	1169	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI)))
EricLew	0:80ee8f3b695e	1170	{
EricLew	0:80ee8f3b695e	1171	/* MSI or PLL with MSI source used as system clock source */
EricLew	0:80ee8f3b695e	1172
EricLew	0:80ee8f3b695e	1173	/* Get SYSCLK source */
EricLew	0:80ee8f3b695e	1174	if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == RESET)
EricLew	0:80ee8f3b695e	1175	{ /* MSISRANGE from RCC_CSR applies */
EricLew	0:80ee8f3b695e	1176	msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8;
EricLew	0:80ee8f3b695e	1177	}
EricLew	0:80ee8f3b695e	1178	else
EricLew	0:80ee8f3b695e	1179	{ /* MSIRANGE from RCC_CR applies */
EricLew	0:80ee8f3b695e	1180	msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4;
EricLew	0:80ee8f3b695e	1181	}
EricLew	0:80ee8f3b695e	1182	/MSI frequency range in HZ/
EricLew	0:80ee8f3b695e	1183	msirange = MSIRangeTable[msirange];
EricLew	0:80ee8f3b695e	1184
EricLew	0:80ee8f3b695e	1185	if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI)
EricLew	0:80ee8f3b695e	1186	{
EricLew	0:80ee8f3b695e	1187	/* MSI used as system clock source */
EricLew	0:80ee8f3b695e	1188	sysclockfreq = msirange;
EricLew	0:80ee8f3b695e	1189	}
EricLew	0:80ee8f3b695e	1190	}
EricLew	0:80ee8f3b695e	1191
EricLew	0:80ee8f3b695e	1192	if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL)
EricLew	0:80ee8f3b695e	1193	{
EricLew	0:80ee8f3b695e	1194	/* PLL used as system clock source */
EricLew	0:80ee8f3b695e	1195
EricLew	0:80ee8f3b695e	1196	/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
EricLew	0:80ee8f3b695e	1197	SYSCLK = PLL_VCO / PLLR
EricLew	0:80ee8f3b695e	1198	*/
EricLew	0:80ee8f3b695e	1199	pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
EricLew	0:80ee8f3b695e	1200	pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM)>> 4) + 1 ;
EricLew	0:80ee8f3b695e	1201
EricLew	0:80ee8f3b695e	1202	switch (pllsource)
EricLew	0:80ee8f3b695e	1203	{
EricLew	0:80ee8f3b695e	1204	case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
EricLew	0:80ee8f3b695e	1205	pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
EricLew	0:80ee8f3b695e	1206	break;
EricLew	0:80ee8f3b695e	1207
EricLew	0:80ee8f3b695e	1208	case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
EricLew	0:80ee8f3b695e	1209	pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
EricLew	0:80ee8f3b695e	1210	break;
EricLew	0:80ee8f3b695e	1211
EricLew	0:80ee8f3b695e	1212	case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
EricLew	0:80ee8f3b695e	1213	default:
EricLew	0:80ee8f3b695e	1214	pllvco = (msirange / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
EricLew	0:80ee8f3b695e	1215	break;
EricLew	0:80ee8f3b695e	1216	}
EricLew	0:80ee8f3b695e	1217	pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >>25) + 1 ) *2;
EricLew	0:80ee8f3b695e	1218	sysclockfreq = pllvco/pllr;
EricLew	0:80ee8f3b695e	1219	}
EricLew	0:80ee8f3b695e	1220
EricLew	0:80ee8f3b695e	1221	return sysclockfreq;
EricLew	0:80ee8f3b695e	1222	}
EricLew	0:80ee8f3b695e	1223
EricLew	0:80ee8f3b695e	1224	/**
EricLew	0:80ee8f3b695e	1225	* @brief Return the HCLK frequency.
EricLew	0:80ee8f3b695e	1226	* @note Each time HCLK changes, this function must be called to update the
EricLew	0:80ee8f3b695e	1227	* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
EricLew	0:80ee8f3b695e	1228	*
EricLew	0:80ee8f3b695e	1229	* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
EricLew	0:80ee8f3b695e	1230	* and updated within this function
EricLew	0:80ee8f3b695e	1231	* @retval HCLK frequency
EricLew	0:80ee8f3b695e	1232	*/
EricLew	0:80ee8f3b695e	1233	uint32_t HAL_RCC_GetHCLKFreq(void)
EricLew	0:80ee8f3b695e	1234	{
EricLew	0:80ee8f3b695e	1235	SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
EricLew	0:80ee8f3b695e	1236	return SystemCoreClock;
EricLew	0:80ee8f3b695e	1237	}
EricLew	0:80ee8f3b695e	1238
EricLew	0:80ee8f3b695e	1239	/**
EricLew	0:80ee8f3b695e	1240	* @brief Return the PCLK1 frequency.
EricLew	0:80ee8f3b695e	1241	* @note Each time PCLK1 changes, this function must be called to update the
EricLew	0:80ee8f3b695e	1242	* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
EricLew	0:80ee8f3b695e	1243	* @retval PCLK1 frequency
EricLew	0:80ee8f3b695e	1244	*/
EricLew	0:80ee8f3b695e	1245	uint32_t HAL_RCC_GetPCLK1Freq(void)
EricLew	0:80ee8f3b695e	1246	{
EricLew	0:80ee8f3b695e	1247	/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
EricLew	0:80ee8f3b695e	1248	return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
EricLew	0:80ee8f3b695e	1249	}
EricLew	0:80ee8f3b695e	1250
EricLew	0:80ee8f3b695e	1251	/**
EricLew	0:80ee8f3b695e	1252	* @brief Return the PCLK2 frequency.
EricLew	0:80ee8f3b695e	1253	* @note Each time PCLK2 changes, this function must be called to update the
EricLew	0:80ee8f3b695e	1254	* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
EricLew	0:80ee8f3b695e	1255	* @retval PCLK2 frequency
EricLew	0:80ee8f3b695e	1256	*/
EricLew	0:80ee8f3b695e	1257	uint32_t HAL_RCC_GetPCLK2Freq(void)
EricLew	0:80ee8f3b695e	1258	{
EricLew	0:80ee8f3b695e	1259	/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
EricLew	0:80ee8f3b695e	1260	return (HAL_RCC_GetHCLKFreq()>> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
EricLew	0:80ee8f3b695e	1261	}
EricLew	0:80ee8f3b695e	1262
EricLew	0:80ee8f3b695e	1263	/**
EricLew	0:80ee8f3b695e	1264	* @brief Configure the RCC_OscInitStruct according to the internal
EricLew	0:80ee8f3b695e	1265	* RCC configuration registers.
EricLew	0:80ee8f3b695e	1266	* @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
EricLew	0:80ee8f3b695e	1267	* will be configured.
EricLew	0:80ee8f3b695e	1268	* @retval None
EricLew	0:80ee8f3b695e	1269	*/
EricLew	0:80ee8f3b695e	1270	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
EricLew	0:80ee8f3b695e	1271	{
EricLew	0:80ee8f3b695e	1272	/* Check the parameters */
EricLew	0:80ee8f3b695e	1273	assert_param(RCC_OscInitStruct != NULL);
EricLew	0:80ee8f3b695e	1274	/* Set all possible values for the Oscillator type parameter ---------------*/
EricLew	0:80ee8f3b695e	1275	RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE \| RCC_OSCILLATORTYPE_HSI \| RCC_OSCILLATORTYPE_MSI \| \
EricLew	0:80ee8f3b695e	1276	RCC_OSCILLATORTYPE_LSE \| RCC_OSCILLATORTYPE_LSI;
EricLew	0:80ee8f3b695e	1277
EricLew	0:80ee8f3b695e	1278	/* Get the HSE configuration -----------------------------------------------*/
EricLew	0:80ee8f3b695e	1279	if((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
EricLew	0:80ee8f3b695e	1280	{
EricLew	0:80ee8f3b695e	1281	RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
EricLew	0:80ee8f3b695e	1282	}
EricLew	0:80ee8f3b695e	1283	else if((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
EricLew	0:80ee8f3b695e	1284	{
EricLew	0:80ee8f3b695e	1285	RCC_OscInitStruct->HSEState = RCC_HSE_ON;
EricLew	0:80ee8f3b695e	1286	}
EricLew	0:80ee8f3b695e	1287	else
EricLew	0:80ee8f3b695e	1288	{
EricLew	0:80ee8f3b695e	1289	RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
EricLew	0:80ee8f3b695e	1290	}
EricLew	0:80ee8f3b695e	1291
EricLew	0:80ee8f3b695e	1292	/* Get the MSI configuration -----------------------------------------------*/
EricLew	0:80ee8f3b695e	1293	if((RCC->CR & RCC_CR_MSION) == RCC_CR_MSION)
EricLew	0:80ee8f3b695e	1294	{
EricLew	0:80ee8f3b695e	1295	RCC_OscInitStruct->MSIState = RCC_MSI_ON;
EricLew	0:80ee8f3b695e	1296	}
EricLew	0:80ee8f3b695e	1297	else
EricLew	0:80ee8f3b695e	1298	{
EricLew	0:80ee8f3b695e	1299	RCC_OscInitStruct->MSIState = RCC_MSI_OFF;
EricLew	0:80ee8f3b695e	1300	}
EricLew	0:80ee8f3b695e	1301
EricLew	0:80ee8f3b695e	1302	RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->CR & RCC_ICSCR_MSITRIM) >> POSITION_VAL(RCC_ICSCR_MSITRIM));
EricLew	0:80ee8f3b695e	1303	RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->CR & RCC_CR_MSIRANGE) );
EricLew	0:80ee8f3b695e	1304
EricLew	0:80ee8f3b695e	1305	/* Get the HSI configuration -----------------------------------------------*/
EricLew	0:80ee8f3b695e	1306	if((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
EricLew	0:80ee8f3b695e	1307	{
EricLew	0:80ee8f3b695e	1308	RCC_OscInitStruct->HSIState = RCC_HSI_ON;
EricLew	0:80ee8f3b695e	1309	}
EricLew	0:80ee8f3b695e	1310	else
EricLew	0:80ee8f3b695e	1311	{
EricLew	0:80ee8f3b695e	1312	RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
EricLew	0:80ee8f3b695e	1313	}
EricLew	0:80ee8f3b695e	1314
EricLew	0:80ee8f3b695e	1315	RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> POSITION_VAL(RCC_ICSCR_HSITRIM));
EricLew	0:80ee8f3b695e	1316
EricLew	0:80ee8f3b695e	1317	/* Get the LSE configuration -----------------------------------------------*/
EricLew	0:80ee8f3b695e	1318	if((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
EricLew	0:80ee8f3b695e	1319	{
EricLew	0:80ee8f3b695e	1320	RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
EricLew	0:80ee8f3b695e	1321	}
EricLew	0:80ee8f3b695e	1322	else if((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
EricLew	0:80ee8f3b695e	1323	{
EricLew	0:80ee8f3b695e	1324	RCC_OscInitStruct->LSEState = RCC_LSE_ON;
EricLew	0:80ee8f3b695e	1325	}
EricLew	0:80ee8f3b695e	1326	else
EricLew	0:80ee8f3b695e	1327	{
EricLew	0:80ee8f3b695e	1328	RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
EricLew	0:80ee8f3b695e	1329	}
EricLew	0:80ee8f3b695e	1330
EricLew	0:80ee8f3b695e	1331	/* Get the LSI configuration -----------------------------------------------*/
EricLew	0:80ee8f3b695e	1332	if((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION)
EricLew	0:80ee8f3b695e	1333	{
EricLew	0:80ee8f3b695e	1334	RCC_OscInitStruct->LSIState = RCC_LSI_ON;
EricLew	0:80ee8f3b695e	1335	}
EricLew	0:80ee8f3b695e	1336	else
EricLew	0:80ee8f3b695e	1337	{
EricLew	0:80ee8f3b695e	1338	RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
EricLew	0:80ee8f3b695e	1339	}
EricLew	0:80ee8f3b695e	1340
EricLew	0:80ee8f3b695e	1341	/* Get the PLL configuration -----------------------------------------------*/
EricLew	0:80ee8f3b695e	1342	if((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
EricLew	0:80ee8f3b695e	1343	{
EricLew	0:80ee8f3b695e	1344	RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
EricLew	0:80ee8f3b695e	1345	}
EricLew	0:80ee8f3b695e	1346	else
EricLew	0:80ee8f3b695e	1347	{
EricLew	0:80ee8f3b695e	1348	RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
EricLew	0:80ee8f3b695e	1349	}
EricLew	0:80ee8f3b695e	1350	RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
EricLew	0:80ee8f3b695e	1351	RCC_OscInitStruct->PLL.PLLM = (uint32_t)(((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1);
EricLew	0:80ee8f3b695e	1352	RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
EricLew	0:80ee8f3b695e	1353	RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ)) + 1) << 1U);
EricLew	0:80ee8f3b695e	1354	RCC_OscInitStruct->PLL.PLLR = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR)) + 1) << 1U);
EricLew	0:80ee8f3b695e	1355	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) != RESET)
EricLew	0:80ee8f3b695e	1356	{
EricLew	0:80ee8f3b695e	1357	RCC_OscInitStruct->PLL.PLLP = RCC_PLLP_DIV17;
EricLew	0:80ee8f3b695e	1358	}
EricLew	0:80ee8f3b695e	1359	else
EricLew	0:80ee8f3b695e	1360	{
EricLew	0:80ee8f3b695e	1361	RCC_OscInitStruct->PLL.PLLP = RCC_PLLP_DIV7;
EricLew	0:80ee8f3b695e	1362	}
EricLew	0:80ee8f3b695e	1363	}
EricLew	0:80ee8f3b695e	1364
EricLew	0:80ee8f3b695e	1365	/**
EricLew	0:80ee8f3b695e	1366	* @brief Configure the RCC_ClkInitStruct according to the internal
EricLew	0:80ee8f3b695e	1367	* RCC configuration registers.
EricLew	0:80ee8f3b695e	1368	* @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
EricLew	0:80ee8f3b695e	1369	* will be configured.
EricLew	0:80ee8f3b695e	1370	* @param pFLatency Pointer on the Flash Latency.
EricLew	0:80ee8f3b695e	1371	* @retval None
EricLew	0:80ee8f3b695e	1372	*/
EricLew	0:80ee8f3b695e	1373	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency)
EricLew	0:80ee8f3b695e	1374	{
EricLew	0:80ee8f3b695e	1375	/* Check the parameters */
EricLew	0:80ee8f3b695e	1376	assert_param(RCC_ClkInitStruct != NULL);
EricLew	0:80ee8f3b695e	1377	assert_param(pFLatency != NULL);
EricLew	0:80ee8f3b695e	1378
EricLew	0:80ee8f3b695e	1379	/* Set all possible values for the Clock type parameter --------------------*/
EricLew	0:80ee8f3b695e	1380	RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK \| RCC_CLOCKTYPE_HCLK \| RCC_CLOCKTYPE_PCLK1 \| RCC_CLOCKTYPE_PCLK2;
EricLew	0:80ee8f3b695e	1381
EricLew	0:80ee8f3b695e	1382	/* Get the SYSCLK configuration --------------------------------------------*/
EricLew	0:80ee8f3b695e	1383	RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
EricLew	0:80ee8f3b695e	1384
EricLew	0:80ee8f3b695e	1385	/* Get the HCLK configuration ----------------------------------------------*/
EricLew	0:80ee8f3b695e	1386	RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
EricLew	0:80ee8f3b695e	1387
EricLew	0:80ee8f3b695e	1388	/* Get the APB1 configuration ----------------------------------------------*/
EricLew	0:80ee8f3b695e	1389	RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
EricLew	0:80ee8f3b695e	1390
EricLew	0:80ee8f3b695e	1391	/* Get the APB2 configuration ----------------------------------------------*/
EricLew	0:80ee8f3b695e	1392	RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
EricLew	0:80ee8f3b695e	1393
EricLew	0:80ee8f3b695e	1394	/* Get the Flash Wait State (Latency) configuration ------------------------*/
EricLew	0:80ee8f3b695e	1395	*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
EricLew	0:80ee8f3b695e	1396	}
EricLew	0:80ee8f3b695e	1397
EricLew	0:80ee8f3b695e	1398	/**
EricLew	0:80ee8f3b695e	1399	* @brief Enable the Clock Security System.
EricLew	0:80ee8f3b695e	1400	* @note If a failure is detected on the HSE oscillator clock, this oscillator
EricLew	0:80ee8f3b695e	1401	* is automatically disabled and an interrupt is generated to inform the
EricLew	0:80ee8f3b695e	1402	* software about the failure (Clock Security System Interrupt, CSSI),
EricLew	0:80ee8f3b695e	1403	* allowing the MCU to perform rescue operations. The CSSI is linked to
EricLew	0:80ee8f3b695e	1404	* the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
EricLew	0:80ee8f3b695e	1405	* @note The Clock Security System can only be cleared by reset.
EricLew	0:80ee8f3b695e	1406	* @retval None
EricLew	0:80ee8f3b695e	1407	*/
EricLew	0:80ee8f3b695e	1408	void HAL_RCC_EnableCSS(void)
EricLew	0:80ee8f3b695e	1409	{
EricLew	0:80ee8f3b695e	1410	SET_BIT(RCC->CR, RCC_CR_CSSON) ;
EricLew	0:80ee8f3b695e	1411	}
EricLew	0:80ee8f3b695e	1412
EricLew	0:80ee8f3b695e	1413	/**
EricLew	0:80ee8f3b695e	1414	* @brief Handle the RCC Clock Security System interrupt request.
EricLew	0:80ee8f3b695e	1415	* @note This API should be called under the NMI_Handler().
EricLew	0:80ee8f3b695e	1416	* @retval None
EricLew	0:80ee8f3b695e	1417	*/
EricLew	0:80ee8f3b695e	1418	void HAL_RCC_NMI_IRQHandler(void)
EricLew	0:80ee8f3b695e	1419	{
EricLew	0:80ee8f3b695e	1420	/* Check RCC CSSF interrupt flag */
EricLew	0:80ee8f3b695e	1421	if(__HAL_RCC_GET_IT(RCC_IT_CSS))
EricLew	0:80ee8f3b695e	1422	{
EricLew	0:80ee8f3b695e	1423	/* RCC Clock Security System interrupt user callback */
EricLew	0:80ee8f3b695e	1424	HAL_RCC_CSSCallback();
EricLew	0:80ee8f3b695e	1425
EricLew	0:80ee8f3b695e	1426	/* Clear RCC CSS pending bit */
EricLew	0:80ee8f3b695e	1427	__HAL_RCC_CLEAR_IT(RCC_IT_CSS);
EricLew	0:80ee8f3b695e	1428	}
EricLew	0:80ee8f3b695e	1429	}
EricLew	0:80ee8f3b695e	1430
EricLew	0:80ee8f3b695e	1431	/**
EricLew	0:80ee8f3b695e	1432	* @brief RCC Clock Security System interrupt callback.
EricLew	0:80ee8f3b695e	1433	* @retval none
EricLew	0:80ee8f3b695e	1434	*/
EricLew	0:80ee8f3b695e	1435	__weak void HAL_RCC_CSSCallback(void)
EricLew	0:80ee8f3b695e	1436	{
EricLew	0:80ee8f3b695e	1437	/* NOTE : This function should not be modified, when the callback is needed,
EricLew	0:80ee8f3b695e	1438	the HAL_RCC_CSSCallback should be implemented in the user file
EricLew	0:80ee8f3b695e	1439	*/
EricLew	0:80ee8f3b695e	1440	}
EricLew	0:80ee8f3b695e	1441
EricLew	0:80ee8f3b695e	1442	/**
EricLew	0:80ee8f3b695e	1443	* @}
EricLew	0:80ee8f3b695e	1444	*/
EricLew	0:80ee8f3b695e	1445
EricLew	0:80ee8f3b695e	1446	/**
EricLew	0:80ee8f3b695e	1447	* @}
EricLew	0:80ee8f3b695e	1448	*/
EricLew	0:80ee8f3b695e	1449
EricLew	0:80ee8f3b695e	1450	/* Private function prototypes -----------------------------------------------*/
EricLew	0:80ee8f3b695e	1451	/** @addtogroup RCC_Private_Functions
EricLew	0:80ee8f3b695e	1452	* @{
EricLew	0:80ee8f3b695e	1453	*/
EricLew	0:80ee8f3b695e	1454	/**
EricLew	0:80ee8f3b695e	1455	* @brief Update number of Flash wait states in line with MSI range and current
EricLew	0:80ee8f3b695e	1456	voltage range.
EricLew	0:80ee8f3b695e	1457	* @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11
EricLew	0:80ee8f3b695e	1458	* @retval HAL status
EricLew	0:80ee8f3b695e	1459	*/
EricLew	0:80ee8f3b695e	1460	static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
EricLew	0:80ee8f3b695e	1461	{
EricLew	0:80ee8f3b695e	1462	uint32_t vos = 0;
EricLew	0:80ee8f3b695e	1463	uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
EricLew	0:80ee8f3b695e	1464
EricLew	0:80ee8f3b695e	1465	if(__HAL_RCC_PWR_IS_CLK_ENABLED())
EricLew	0:80ee8f3b695e	1466	{
EricLew	0:80ee8f3b695e	1467	vos = HAL_PWREx_GetVoltageRange();
EricLew	0:80ee8f3b695e	1468	}
EricLew	0:80ee8f3b695e	1469	else
EricLew	0:80ee8f3b695e	1470	{
EricLew	0:80ee8f3b695e	1471	__HAL_RCC_PWR_CLK_ENABLE();
EricLew	0:80ee8f3b695e	1472	vos = HAL_PWREx_GetVoltageRange();
EricLew	0:80ee8f3b695e	1473	__HAL_RCC_PWR_CLK_DISABLE();
EricLew	0:80ee8f3b695e	1474	}
EricLew	0:80ee8f3b695e	1475
EricLew	0:80ee8f3b695e	1476	if(vos == PWR_REGULATOR_VOLTAGE_SCALE1)
EricLew	0:80ee8f3b695e	1477	{
EricLew	0:80ee8f3b695e	1478	if(msirange > RCC_MSIRANGE_8)
EricLew	0:80ee8f3b695e	1479	{
EricLew	0:80ee8f3b695e	1480	/* MSI > 16Mhz */
EricLew	0:80ee8f3b695e	1481	if(msirange > RCC_MSIRANGE_10)
EricLew	0:80ee8f3b695e	1482	{
EricLew	0:80ee8f3b695e	1483	/* MSI 48Mhz */
EricLew	0:80ee8f3b695e	1484	latency = FLASH_LATENCY_2; /* 2WS */
EricLew	0:80ee8f3b695e	1485	}
EricLew	0:80ee8f3b695e	1486	else
EricLew	0:80ee8f3b695e	1487	{
EricLew	0:80ee8f3b695e	1488	/* MSI 24Mhz or 32Mhz */
EricLew	0:80ee8f3b695e	1489	latency = FLASH_LATENCY_1; /* 1WS */
EricLew	0:80ee8f3b695e	1490	}
EricLew	0:80ee8f3b695e	1491	}
EricLew	0:80ee8f3b695e	1492	/* else MSI <= 16Mhz default FLASH_LATENCY_0 0WS */
EricLew	0:80ee8f3b695e	1493	}
EricLew	0:80ee8f3b695e	1494	else
EricLew	0:80ee8f3b695e	1495	{
EricLew	0:80ee8f3b695e	1496	if(msirange > RCC_MSIRANGE_8)
EricLew	0:80ee8f3b695e	1497	{
EricLew	0:80ee8f3b695e	1498	/* MSI > 16Mhz */
EricLew	0:80ee8f3b695e	1499	latency = FLASH_LATENCY_3; /* 3WS */
EricLew	0:80ee8f3b695e	1500	}
EricLew	0:80ee8f3b695e	1501	else
EricLew	0:80ee8f3b695e	1502	{
EricLew	0:80ee8f3b695e	1503	if(msirange == RCC_MSIRANGE_8)
EricLew	0:80ee8f3b695e	1504	{
EricLew	0:80ee8f3b695e	1505	/* MSI 16Mhz */
EricLew	0:80ee8f3b695e	1506	latency = FLASH_LATENCY_2; /* 2WS */
EricLew	0:80ee8f3b695e	1507	}
EricLew	0:80ee8f3b695e	1508	else if(msirange == RCC_MSIRANGE_7)
EricLew	0:80ee8f3b695e	1509	{
EricLew	0:80ee8f3b695e	1510	/* MSI 8Mhz */
EricLew	0:80ee8f3b695e	1511	latency = FLASH_LATENCY_1; /* 1WS */
EricLew	0:80ee8f3b695e	1512	}
EricLew	0:80ee8f3b695e	1513	/* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
EricLew	0:80ee8f3b695e	1514	}
EricLew	0:80ee8f3b695e	1515	}
EricLew	0:80ee8f3b695e	1516
EricLew	0:80ee8f3b695e	1517	__HAL_FLASH_SET_LATENCY(latency);
EricLew	0:80ee8f3b695e	1518
EricLew	0:80ee8f3b695e	1519	/* Check that the new number of wait states is taken into account to access the Flash
EricLew	0:80ee8f3b695e	1520	memory by reading the FLASH_ACR register */
EricLew	0:80ee8f3b695e	1521	if((FLASH->ACR & FLASH_ACR_LATENCY) != latency)
EricLew	0:80ee8f3b695e	1522	{
EricLew	0:80ee8f3b695e	1523	return HAL_ERROR;
EricLew	0:80ee8f3b695e	1524	}
EricLew	0:80ee8f3b695e	1525
EricLew	0:80ee8f3b695e	1526	return HAL_OK;
EricLew	0:80ee8f3b695e	1527	}
EricLew	0:80ee8f3b695e	1528
EricLew	0:80ee8f3b695e	1529	/**
EricLew	0:80ee8f3b695e	1530	* @}
EricLew	0:80ee8f3b695e	1531	*/
EricLew	0:80ee8f3b695e	1532
EricLew	0:80ee8f3b695e	1533	#endif /* HAL_RCC_MODULE_ENABLED */
EricLew	0:80ee8f3b695e	1534	/**
EricLew	0:80ee8f3b695e	1535	* @}
EricLew	0:80ee8f3b695e	1536	*/
EricLew	0:80ee8f3b695e	1537
EricLew	0:80ee8f3b695e	1538	/**
EricLew	0:80ee8f3b695e	1539	* @}
EricLew	0:80ee8f3b695e	1540	*/
EricLew	0:80ee8f3b695e	1541
EricLew	0:80ee8f3b695e	1542	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
EricLew	0:80ee8f3b695e	1543

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Type:	Library
Created:	12 Nov 2015
Imports:	198
Forks:	0
Commits:	3
Dependents:	4
Dependencies:	0
Followers:	14

Src/stm32l4xx_hal_rcc.c@0:80ee8f3b695e, 2015-11-02 (annotated)

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