Eric Lewiston / STM32L4xx_HAL_Driver

Hal Drivers for L4

Dependents:   BSP OneHopeOnePrayer FINAL_AUDIO_RECORD AudioDemo

Fork of STM32L4xx_HAL_Driver by Senior Design: Sound Monitor

Src/stm32l4xx_hal_dma.c@0:80ee8f3b695e, 2015-11-02 (annotated)

Committer:
EricLew
Date:
Mon Nov 02 19:37:23 2015 +0000
Revision:
0:80ee8f3b695e
Errors are with definitions of LCD and QSPI functions. I believe all .h and .c files are  uploaded, but there may need to be certain functions called.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
EricLew 0:80ee8f3b695e 1 /**
EricLew 0:80ee8f3b695e 2 ******************************************************************************
EricLew 0:80ee8f3b695e 3 * @file stm32l4xx_hal_dma.c
EricLew 0:80ee8f3b695e 4 * @author MCD Application Team
EricLew 0:80ee8f3b695e 5 * @version V1.1.0
EricLew 0:80ee8f3b695e 6 * @date 16-September-2015
EricLew 0:80ee8f3b695e 7 * @brief DMA HAL module driver.
EricLew 0:80ee8f3b695e 8 *
EricLew 0:80ee8f3b695e 9 * This file provides firmware functions to manage the following
EricLew 0:80ee8f3b695e 10 * functionalities of the Direct Memory Access (DMA) peripheral:
EricLew 0:80ee8f3b695e 11 * + Initialization and de-initialization functions
EricLew 0:80ee8f3b695e 12 * + IO operation functions
EricLew 0:80ee8f3b695e 13 * + Peripheral State and errors functions
EricLew 0:80ee8f3b695e 14 @verbatim
EricLew 0:80ee8f3b695e 15 ==============================================================================
EricLew 0:80ee8f3b695e 16 ##### How to use this driver #####
EricLew 0:80ee8f3b695e 17 ==============================================================================
EricLew 0:80ee8f3b695e 18 [..]
EricLew 0:80ee8f3b695e 19 (#) Enable and configure the peripheral to be connected to the DMA Channel
EricLew 0:80ee8f3b695e 20 (except for internal SRAM / FLASH memories: no initialization is
EricLew 0:80ee8f3b695e 21 necessary). Please refer to the Reference manual for connection between peripherals
EricLew 0:80ee8f3b695e 22 and DMA requests.
EricLew 0:80ee8f3b695e 23
EricLew 0:80ee8f3b695e 24 (#) For a given Channel, program the required configuration through the following parameters:
EricLew 0:80ee8f3b695e 25 Channel request, Transfer Direction, Source and Destination data formats,
EricLew 0:80ee8f3b695e 26 Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
EricLew 0:80ee8f3b695e 27 using HAL_DMA_Init() function.
EricLew 0:80ee8f3b695e 28
EricLew 0:80ee8f3b695e 29 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
EricLew 0:80ee8f3b695e 30 detection.
EricLew 0:80ee8f3b695e 31
EricLew 0:80ee8f3b695e 32 (#) Use HAL_DMA_Abort() function to abort the current transfer
EricLew 0:80ee8f3b695e 33
EricLew 0:80ee8f3b695e 34 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
EricLew 0:80ee8f3b695e 35 *** Polling mode IO operation ***
EricLew 0:80ee8f3b695e 36 =================================
EricLew 0:80ee8f3b695e 37 [..]
EricLew 0:80ee8f3b695e 38 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
EricLew 0:80ee8f3b695e 39 address and destination address and the Length of data to be transferred
EricLew 0:80ee8f3b695e 40 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
EricLew 0:80ee8f3b695e 41 case a fixed Timeout can be configured by User depending from his application.
EricLew 0:80ee8f3b695e 42
EricLew 0:80ee8f3b695e 43 *** Interrupt mode IO operation ***
EricLew 0:80ee8f3b695e 44 ===================================
EricLew 0:80ee8f3b695e 45 [..]
EricLew 0:80ee8f3b695e 46 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
EricLew 0:80ee8f3b695e 47 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
EricLew 0:80ee8f3b695e 48 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
EricLew 0:80ee8f3b695e 49 Source address and destination address and the Length of data to be transferred.
EricLew 0:80ee8f3b695e 50 In this case the DMA interrupt is configured
EricLew 0:80ee8f3b695e 51 (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
EricLew 0:80ee8f3b695e 52 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
EricLew 0:80ee8f3b695e 53 add his own function by customization of function pointer XferCpltCallback and
EricLew 0:80ee8f3b695e 54 XferErrorCallback (i.e. a member of DMA handle structure).
EricLew 0:80ee8f3b695e 55
EricLew 0:80ee8f3b695e 56 *** DMA HAL driver macros list ***
EricLew 0:80ee8f3b695e 57 =============================================
EricLew 0:80ee8f3b695e 58 [..]
EricLew 0:80ee8f3b695e 59 Below the list of most used macros in DMA HAL driver.
EricLew 0:80ee8f3b695e 60
EricLew 0:80ee8f3b695e 61 (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
EricLew 0:80ee8f3b695e 62 (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
EricLew 0:80ee8f3b695e 63 (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
EricLew 0:80ee8f3b695e 64 (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
EricLew 0:80ee8f3b695e 65 (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
EricLew 0:80ee8f3b695e 66 (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
EricLew 0:80ee8f3b695e 67 (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
EricLew 0:80ee8f3b695e 68
EricLew 0:80ee8f3b695e 69 [..]
EricLew 0:80ee8f3b695e 70 (@) You can refer to the DMA HAL driver header file for more useful macros
EricLew 0:80ee8f3b695e 71
EricLew 0:80ee8f3b695e 72 @endverbatim
EricLew 0:80ee8f3b695e 73 ******************************************************************************
EricLew 0:80ee8f3b695e 74 * @attention
EricLew 0:80ee8f3b695e 75 *
EricLew 0:80ee8f3b695e 76 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
EricLew 0:80ee8f3b695e 77 *
EricLew 0:80ee8f3b695e 78 * Redistribution and use in source and binary forms, with or without modification,
EricLew 0:80ee8f3b695e 79 * are permitted provided that the following conditions are met:
EricLew 0:80ee8f3b695e 80 * 1. Redistributions of source code must retain the above copyright notice,
EricLew 0:80ee8f3b695e 81 * this list of conditions and the following disclaimer.
EricLew 0:80ee8f3b695e 82 * 2. Redistributions in binary form must reproduce the above copyright notice,
EricLew 0:80ee8f3b695e 83 * this list of conditions and the following disclaimer in the documentation
EricLew 0:80ee8f3b695e 84 * and/or other materials provided with the distribution.
EricLew 0:80ee8f3b695e 85 * 3. Neither the name of STMicroelectronics nor the names of its contributors
EricLew 0:80ee8f3b695e 86 * may be used to endorse or promote products derived from this software
EricLew 0:80ee8f3b695e 87 * without specific prior written permission.
EricLew 0:80ee8f3b695e 88 *
EricLew 0:80ee8f3b695e 89 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew 0:80ee8f3b695e 90 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew 0:80ee8f3b695e 91 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
EricLew 0:80ee8f3b695e 92 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
EricLew 0:80ee8f3b695e 93 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
EricLew 0:80ee8f3b695e 94 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
EricLew 0:80ee8f3b695e 95 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
EricLew 0:80ee8f3b695e 96 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
EricLew 0:80ee8f3b695e 97 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
EricLew 0:80ee8f3b695e 98 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
EricLew 0:80ee8f3b695e 99 *
EricLew 0:80ee8f3b695e 100 ******************************************************************************
EricLew 0:80ee8f3b695e 101 */
EricLew 0:80ee8f3b695e 102
EricLew 0:80ee8f3b695e 103 /* Includes ------------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 104 #include "stm32l4xx_hal.h"
EricLew 0:80ee8f3b695e 105
EricLew 0:80ee8f3b695e 106 /** @addtogroup STM32L4xx_HAL_Driver
EricLew 0:80ee8f3b695e 107 * @{
EricLew 0:80ee8f3b695e 108 */
EricLew 0:80ee8f3b695e 109
EricLew 0:80ee8f3b695e 110 /** @defgroup DMA DMA
EricLew 0:80ee8f3b695e 111 * @brief DMA HAL module driver
EricLew 0:80ee8f3b695e 112 * @{
EricLew 0:80ee8f3b695e 113 */
EricLew 0:80ee8f3b695e 114
EricLew 0:80ee8f3b695e 115 #ifdef HAL_DMA_MODULE_ENABLED
EricLew 0:80ee8f3b695e 116
EricLew 0:80ee8f3b695e 117 /* Private typedef -----------------------------------------------------------*/
EricLew 0:80ee8f3b695e 118 /* Private define ------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 119 /** @defgroup DMA_Private_Constants DMA Private Constants
EricLew 0:80ee8f3b695e 120 * @{
EricLew 0:80ee8f3b695e 121 */
EricLew 0:80ee8f3b695e 122 #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
EricLew 0:80ee8f3b695e 123 /**
EricLew 0:80ee8f3b695e 124 * @}
EricLew 0:80ee8f3b695e 125 */
EricLew 0:80ee8f3b695e 126
EricLew 0:80ee8f3b695e 127 /* Private macro -------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 128 /* Private variables ---------------------------------------------------------*/
EricLew 0:80ee8f3b695e 129 /* Private function prototypes -----------------------------------------------*/
EricLew 0:80ee8f3b695e 130 /** @defgroup DMA_Private_Functions DMA Private Functions
EricLew 0:80ee8f3b695e 131 * @{
EricLew 0:80ee8f3b695e 132 */
EricLew 0:80ee8f3b695e 133 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
EricLew 0:80ee8f3b695e 134 /**
EricLew 0:80ee8f3b695e 135 * @}
EricLew 0:80ee8f3b695e 136 */
EricLew 0:80ee8f3b695e 137
EricLew 0:80ee8f3b695e 138 /* Exported functions ---------------------------------------------------------*/
EricLew 0:80ee8f3b695e 139
EricLew 0:80ee8f3b695e 140 /** @defgroup DMA_Exported_Functions DMA Exported Functions
EricLew 0:80ee8f3b695e 141 * @{
EricLew 0:80ee8f3b695e 142 */
EricLew 0:80ee8f3b695e 143
EricLew 0:80ee8f3b695e 144 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
EricLew 0:80ee8f3b695e 145 * @brief Initialization and de-initialization functions
EricLew 0:80ee8f3b695e 146 *
EricLew 0:80ee8f3b695e 147 @verbatim
EricLew 0:80ee8f3b695e 148 ===============================================================================
EricLew 0:80ee8f3b695e 149 ##### Initialization and de-initialization functions #####
EricLew 0:80ee8f3b695e 150 ===============================================================================
EricLew 0:80ee8f3b695e 151 [..]
EricLew 0:80ee8f3b695e 152 This section provides functions allowing to initialize the DMA Channel source
EricLew 0:80ee8f3b695e 153 and destination addresses, incrementation and data sizes, transfer direction,
EricLew 0:80ee8f3b695e 154 circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
EricLew 0:80ee8f3b695e 155 [..]
EricLew 0:80ee8f3b695e 156 The HAL_DMA_Init() function follows the DMA configuration procedures as described in
EricLew 0:80ee8f3b695e 157 reference manual.
EricLew 0:80ee8f3b695e 158
EricLew 0:80ee8f3b695e 159 @endverbatim
EricLew 0:80ee8f3b695e 160 * @{
EricLew 0:80ee8f3b695e 161 */
EricLew 0:80ee8f3b695e 162
EricLew 0:80ee8f3b695e 163 /**
EricLew 0:80ee8f3b695e 164 * @brief Initialize the DMA according to the specified
EricLew 0:80ee8f3b695e 165 * parameters in the DMA_InitTypeDef and initialize the associated handle.
EricLew 0:80ee8f3b695e 166 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 167 * the configuration information for the specified DMA Channel.
EricLew 0:80ee8f3b695e 168 * @retval HAL status
EricLew 0:80ee8f3b695e 169 */
EricLew 0:80ee8f3b695e 170 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
EricLew 0:80ee8f3b695e 171 {
EricLew 0:80ee8f3b695e 172 uint32_t tmp = 0;
EricLew 0:80ee8f3b695e 173
EricLew 0:80ee8f3b695e 174 /* Check the DMA handle allocation */
EricLew 0:80ee8f3b695e 175 if(hdma == NULL)
EricLew 0:80ee8f3b695e 176 {
EricLew 0:80ee8f3b695e 177 return HAL_ERROR;
EricLew 0:80ee8f3b695e 178 }
EricLew 0:80ee8f3b695e 179
EricLew 0:80ee8f3b695e 180 /* Check the parameters */
EricLew 0:80ee8f3b695e 181 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
EricLew 0:80ee8f3b695e 182 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
EricLew 0:80ee8f3b695e 183 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
EricLew 0:80ee8f3b695e 184 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
EricLew 0:80ee8f3b695e 185 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
EricLew 0:80ee8f3b695e 186 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
EricLew 0:80ee8f3b695e 187 assert_param(IS_DMA_MODE(hdma->Init.Mode));
EricLew 0:80ee8f3b695e 188 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
EricLew 0:80ee8f3b695e 189 if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
EricLew 0:80ee8f3b695e 190 {
EricLew 0:80ee8f3b695e 191 assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
EricLew 0:80ee8f3b695e 192 }
EricLew 0:80ee8f3b695e 193
EricLew 0:80ee8f3b695e 194 if(hdma->State == HAL_DMA_STATE_RESET)
EricLew 0:80ee8f3b695e 195 {
EricLew 0:80ee8f3b695e 196 /* Allocate lock resource and initialize it */
EricLew 0:80ee8f3b695e 197 hdma->Lock = HAL_UNLOCKED;
EricLew 0:80ee8f3b695e 198 }
EricLew 0:80ee8f3b695e 199
EricLew 0:80ee8f3b695e 200 /* Change DMA peripheral state */
EricLew 0:80ee8f3b695e 201 hdma->State = HAL_DMA_STATE_BUSY;
EricLew 0:80ee8f3b695e 202
EricLew 0:80ee8f3b695e 203 /* Get the CR register value */
EricLew 0:80ee8f3b695e 204 tmp = hdma->Instance->CCR;
EricLew 0:80ee8f3b695e 205
EricLew 0:80ee8f3b695e 206 /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
EricLew 0:80ee8f3b695e 207 tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
EricLew 0:80ee8f3b695e 208 DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
EricLew 0:80ee8f3b695e 209 DMA_CCR_DIR));
EricLew 0:80ee8f3b695e 210
EricLew 0:80ee8f3b695e 211 /* Prepare the DMA Channel configuration */
EricLew 0:80ee8f3b695e 212 tmp |= hdma->Init.Direction |
EricLew 0:80ee8f3b695e 213 hdma->Init.PeriphInc | hdma->Init.MemInc |
EricLew 0:80ee8f3b695e 214 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
EricLew 0:80ee8f3b695e 215 hdma->Init.Mode | hdma->Init.Priority;
EricLew 0:80ee8f3b695e 216
EricLew 0:80ee8f3b695e 217 /* Write to DMA Channel CR register */
EricLew 0:80ee8f3b695e 218 hdma->Instance->CCR = tmp;
EricLew 0:80ee8f3b695e 219
EricLew 0:80ee8f3b695e 220 /* Set request selection */
EricLew 0:80ee8f3b695e 221 if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
EricLew 0:80ee8f3b695e 222 {
EricLew 0:80ee8f3b695e 223 /* Write to DMA channel selection register */
EricLew 0:80ee8f3b695e 224 if (hdma->Instance == DMA1_Channel1)
EricLew 0:80ee8f3b695e 225 {
EricLew 0:80ee8f3b695e 226 /*Reset request selection for DMA1 Channel1*/
EricLew 0:80ee8f3b695e 227 DMA1_CSELR->CSELR &= ~DMA_CSELR_C1S;
EricLew 0:80ee8f3b695e 228
EricLew 0:80ee8f3b695e 229 /* Configure request selection for DMA1 Channel1 */
EricLew 0:80ee8f3b695e 230 DMA1_CSELR->CSELR |= hdma->Init.Request;
EricLew 0:80ee8f3b695e 231 }
EricLew 0:80ee8f3b695e 232 else if (hdma->Instance == DMA1_Channel2)
EricLew 0:80ee8f3b695e 233 {
EricLew 0:80ee8f3b695e 234 /*Reset request selection for DMA1 Channel2*/
EricLew 0:80ee8f3b695e 235 DMA1_CSELR->CSELR &= ~DMA_CSELR_C2S;
EricLew 0:80ee8f3b695e 236
EricLew 0:80ee8f3b695e 237 /* Configure request selection for DMA1 Channel2 */
EricLew 0:80ee8f3b695e 238 DMA1_CSELR->CSELR |= (uint32_t)(hdma->Init.Request << 4);
EricLew 0:80ee8f3b695e 239 }
EricLew 0:80ee8f3b695e 240 else if (hdma->Instance == DMA1_Channel3)
EricLew 0:80ee8f3b695e 241 {
EricLew 0:80ee8f3b695e 242 /*Reset request selection for DMA1 Channel3*/
EricLew 0:80ee8f3b695e 243 DMA1_CSELR->CSELR &= ~DMA_CSELR_C3S;
EricLew 0:80ee8f3b695e 244
EricLew 0:80ee8f3b695e 245 /* Configure request selection for DMA1 Channel3 */
EricLew 0:80ee8f3b695e 246 DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 8);
EricLew 0:80ee8f3b695e 247 }
EricLew 0:80ee8f3b695e 248 else if (hdma->Instance == DMA1_Channel4)
EricLew 0:80ee8f3b695e 249 {
EricLew 0:80ee8f3b695e 250 /*Reset request selection for DMA1 Channel4*/
EricLew 0:80ee8f3b695e 251 DMA1_CSELR->CSELR &= ~DMA_CSELR_C4S;
EricLew 0:80ee8f3b695e 252
EricLew 0:80ee8f3b695e 253 /* Configure request selection for DMA1 Channel4 */
EricLew 0:80ee8f3b695e 254 DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 12);
EricLew 0:80ee8f3b695e 255 }
EricLew 0:80ee8f3b695e 256 else if (hdma->Instance == DMA1_Channel5)
EricLew 0:80ee8f3b695e 257 {
EricLew 0:80ee8f3b695e 258 /*Reset request selection for DMA1 Channel5*/
EricLew 0:80ee8f3b695e 259 DMA1_CSELR->CSELR &= ~DMA_CSELR_C5S;
EricLew 0:80ee8f3b695e 260
EricLew 0:80ee8f3b695e 261 /* Configure request selection for DMA1 Channel5 */
EricLew 0:80ee8f3b695e 262 DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 16);
EricLew 0:80ee8f3b695e 263 }
EricLew 0:80ee8f3b695e 264 else if (hdma->Instance == DMA1_Channel6)
EricLew 0:80ee8f3b695e 265 {
EricLew 0:80ee8f3b695e 266 /*Reset request selection for DMA1 Channel6*/
EricLew 0:80ee8f3b695e 267 DMA1_CSELR->CSELR &= ~DMA_CSELR_C6S;
EricLew 0:80ee8f3b695e 268
EricLew 0:80ee8f3b695e 269 /* Configure request selection for DMA1 Channel6 */
EricLew 0:80ee8f3b695e 270 DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 20);
EricLew 0:80ee8f3b695e 271 }
EricLew 0:80ee8f3b695e 272 else if (hdma->Instance == DMA1_Channel7)
EricLew 0:80ee8f3b695e 273 {
EricLew 0:80ee8f3b695e 274 /*Reset request selection for DMA1 Channel7*/
EricLew 0:80ee8f3b695e 275 DMA1_CSELR->CSELR &= ~DMA_CSELR_C7S;
EricLew 0:80ee8f3b695e 276
EricLew 0:80ee8f3b695e 277 /* Configure request selection for DMA1 Channel7 */
EricLew 0:80ee8f3b695e 278 DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 24);
EricLew 0:80ee8f3b695e 279 }
EricLew 0:80ee8f3b695e 280 else if (hdma->Instance == DMA2_Channel1)
EricLew 0:80ee8f3b695e 281 {
EricLew 0:80ee8f3b695e 282 /*Reset request selection for DMA2 Channel1*/
EricLew 0:80ee8f3b695e 283 DMA2_CSELR->CSELR &= ~DMA_CSELR_C1S;
EricLew 0:80ee8f3b695e 284
EricLew 0:80ee8f3b695e 285 /* Configure request selection for DMA2 Channel1 */
EricLew 0:80ee8f3b695e 286 DMA2_CSELR->CSELR |= hdma->Init.Request;
EricLew 0:80ee8f3b695e 287 }
EricLew 0:80ee8f3b695e 288 else if (hdma->Instance == DMA2_Channel2)
EricLew 0:80ee8f3b695e 289 {
EricLew 0:80ee8f3b695e 290 /*Reset request selection for DMA2 Channel2*/
EricLew 0:80ee8f3b695e 291 DMA2_CSELR->CSELR &= ~DMA_CSELR_C2S;
EricLew 0:80ee8f3b695e 292
EricLew 0:80ee8f3b695e 293 /* Configure request selection for DMA2 Channel2 */
EricLew 0:80ee8f3b695e 294 DMA2_CSELR->CSELR |= (uint32_t)(hdma->Init.Request << 4);
EricLew 0:80ee8f3b695e 295 }
EricLew 0:80ee8f3b695e 296 else if (hdma->Instance == DMA2_Channel3)
EricLew 0:80ee8f3b695e 297 {
EricLew 0:80ee8f3b695e 298 /*Reset request selection for DMA2 Channel3*/
EricLew 0:80ee8f3b695e 299 DMA2_CSELR->CSELR &= ~DMA_CSELR_C3S;
EricLew 0:80ee8f3b695e 300
EricLew 0:80ee8f3b695e 301 /* Configure request selection for DMA2 Channel3 */
EricLew 0:80ee8f3b695e 302 DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 8);
EricLew 0:80ee8f3b695e 303 }
EricLew 0:80ee8f3b695e 304 else if (hdma->Instance == DMA2_Channel4)
EricLew 0:80ee8f3b695e 305 {
EricLew 0:80ee8f3b695e 306 /*Reset request selection for DMA2 Channel4*/
EricLew 0:80ee8f3b695e 307 DMA2_CSELR->CSELR &= ~DMA_CSELR_C4S;
EricLew 0:80ee8f3b695e 308
EricLew 0:80ee8f3b695e 309 /* Configure request selection for DMA2 Channel4 */
EricLew 0:80ee8f3b695e 310 DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 12);
EricLew 0:80ee8f3b695e 311 }
EricLew 0:80ee8f3b695e 312 else if (hdma->Instance == DMA2_Channel5)
EricLew 0:80ee8f3b695e 313 {
EricLew 0:80ee8f3b695e 314 /*Reset request selection for DMA2 Channel5*/
EricLew 0:80ee8f3b695e 315 DMA2_CSELR->CSELR &= ~DMA_CSELR_C5S;
EricLew 0:80ee8f3b695e 316
EricLew 0:80ee8f3b695e 317 /* Configure request selection for DMA2 Channel5 */
EricLew 0:80ee8f3b695e 318 DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 16);
EricLew 0:80ee8f3b695e 319 }
EricLew 0:80ee8f3b695e 320 else if (hdma->Instance == DMA2_Channel6)
EricLew 0:80ee8f3b695e 321 {
EricLew 0:80ee8f3b695e 322 /*Reset request selection for DMA2 Channel6*/
EricLew 0:80ee8f3b695e 323 DMA2_CSELR->CSELR &= ~DMA_CSELR_C6S;
EricLew 0:80ee8f3b695e 324
EricLew 0:80ee8f3b695e 325 /* Configure request selection for DMA2 Channel6 */
EricLew 0:80ee8f3b695e 326 DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 20);
EricLew 0:80ee8f3b695e 327 }
EricLew 0:80ee8f3b695e 328 else if (hdma->Instance == DMA2_Channel7)
EricLew 0:80ee8f3b695e 329 {
EricLew 0:80ee8f3b695e 330 /*Reset request selection for DMA2 Channel7*/
EricLew 0:80ee8f3b695e 331 DMA2_CSELR->CSELR &= ~DMA_CSELR_C7S;
EricLew 0:80ee8f3b695e 332
EricLew 0:80ee8f3b695e 333 /* Configure request selection for DMA2 Channel7 */
EricLew 0:80ee8f3b695e 334 DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 24);
EricLew 0:80ee8f3b695e 335 }
EricLew 0:80ee8f3b695e 336 }
EricLew 0:80ee8f3b695e 337
EricLew 0:80ee8f3b695e 338 /* Initialize the error code */
EricLew 0:80ee8f3b695e 339 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
EricLew 0:80ee8f3b695e 340
EricLew 0:80ee8f3b695e 341 /* Initialize the DMA state*/
EricLew 0:80ee8f3b695e 342 hdma->State = HAL_DMA_STATE_READY;
EricLew 0:80ee8f3b695e 343
EricLew 0:80ee8f3b695e 344 return HAL_OK;
EricLew 0:80ee8f3b695e 345 }
EricLew 0:80ee8f3b695e 346
EricLew 0:80ee8f3b695e 347 /**
EricLew 0:80ee8f3b695e 348 * @brief DeInitialize the DMA peripheral.
EricLew 0:80ee8f3b695e 349 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 350 * the configuration information for the specified DMA Channel.
EricLew 0:80ee8f3b695e 351 * @retval HAL status
EricLew 0:80ee8f3b695e 352 */
EricLew 0:80ee8f3b695e 353 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
EricLew 0:80ee8f3b695e 354 {
EricLew 0:80ee8f3b695e 355 /* Check the DMA handle allocation */
EricLew 0:80ee8f3b695e 356 if(hdma == NULL)
EricLew 0:80ee8f3b695e 357 {
EricLew 0:80ee8f3b695e 358 return HAL_ERROR;
EricLew 0:80ee8f3b695e 359 }
EricLew 0:80ee8f3b695e 360
EricLew 0:80ee8f3b695e 361 /* Check the parameters */
EricLew 0:80ee8f3b695e 362 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
EricLew 0:80ee8f3b695e 363
EricLew 0:80ee8f3b695e 364 /* Check the DMA peripheral state */
EricLew 0:80ee8f3b695e 365 if(hdma->State == HAL_DMA_STATE_BUSY)
EricLew 0:80ee8f3b695e 366 {
EricLew 0:80ee8f3b695e 367 return HAL_ERROR;
EricLew 0:80ee8f3b695e 368 }
EricLew 0:80ee8f3b695e 369
EricLew 0:80ee8f3b695e 370 /* Disable the selected DMA Channelx */
EricLew 0:80ee8f3b695e 371 __HAL_DMA_DISABLE(hdma);
EricLew 0:80ee8f3b695e 372
EricLew 0:80ee8f3b695e 373 /* Reset DMA Channel control register */
EricLew 0:80ee8f3b695e 374 hdma->Instance->CCR = 0;
EricLew 0:80ee8f3b695e 375
EricLew 0:80ee8f3b695e 376 /* Reset DMA Channel Number of Data to Transfer register */
EricLew 0:80ee8f3b695e 377 hdma->Instance->CNDTR = 0;
EricLew 0:80ee8f3b695e 378
EricLew 0:80ee8f3b695e 379 /* Reset DMA Channel peripheral address register */
EricLew 0:80ee8f3b695e 380 hdma->Instance->CPAR = 0;
EricLew 0:80ee8f3b695e 381
EricLew 0:80ee8f3b695e 382 /* Reset DMA Channel memory address register */
EricLew 0:80ee8f3b695e 383 hdma->Instance->CMAR = 0;
EricLew 0:80ee8f3b695e 384
EricLew 0:80ee8f3b695e 385 /* Clear all flags */
EricLew 0:80ee8f3b695e 386 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
EricLew 0:80ee8f3b695e 387 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
EricLew 0:80ee8f3b695e 388 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
EricLew 0:80ee8f3b695e 389 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
EricLew 0:80ee8f3b695e 390
EricLew 0:80ee8f3b695e 391 /* Reset DMA channel selection register */
EricLew 0:80ee8f3b695e 392 if (hdma->Instance == DMA1_Channel1)
EricLew 0:80ee8f3b695e 393 {
EricLew 0:80ee8f3b695e 394 /*Reset DMA request*/
EricLew 0:80ee8f3b695e 395 DMA1_CSELR->CSELR &= ~DMA_CSELR_C1S;
EricLew 0:80ee8f3b695e 396 }
EricLew 0:80ee8f3b695e 397 else if (hdma->Instance == DMA1_Channel2)
EricLew 0:80ee8f3b695e 398 {
EricLew 0:80ee8f3b695e 399 /*Reset DMA request*/
EricLew 0:80ee8f3b695e 400 DMA1_CSELR->CSELR &= ~DMA_CSELR_C2S;
EricLew 0:80ee8f3b695e 401 }
EricLew 0:80ee8f3b695e 402 else if (hdma->Instance == DMA1_Channel3)
EricLew 0:80ee8f3b695e 403 {
EricLew 0:80ee8f3b695e 404 /*Reset DMA request*/
EricLew 0:80ee8f3b695e 405 DMA1_CSELR->CSELR &= ~DMA_CSELR_C3S;
EricLew 0:80ee8f3b695e 406 }
EricLew 0:80ee8f3b695e 407 else if (hdma->Instance == DMA1_Channel4)
EricLew 0:80ee8f3b695e 408 {
EricLew 0:80ee8f3b695e 409 /*Reset DMA request*/
EricLew 0:80ee8f3b695e 410 DMA1_CSELR->CSELR &= ~DMA_CSELR_C4S;
EricLew 0:80ee8f3b695e 411 }
EricLew 0:80ee8f3b695e 412 else if (hdma->Instance == DMA1_Channel5)
EricLew 0:80ee8f3b695e 413 {
EricLew 0:80ee8f3b695e 414 /*Reset DMA request*/
EricLew 0:80ee8f3b695e 415 DMA1_CSELR->CSELR &= ~DMA_CSELR_C5S;
EricLew 0:80ee8f3b695e 416 }
EricLew 0:80ee8f3b695e 417 else if (hdma->Instance == DMA1_Channel6)
EricLew 0:80ee8f3b695e 418 {
EricLew 0:80ee8f3b695e 419 /*Reset DMA request*/
EricLew 0:80ee8f3b695e 420 DMA1_CSELR->CSELR &= ~DMA_CSELR_C6S;
EricLew 0:80ee8f3b695e 421 }
EricLew 0:80ee8f3b695e 422 else if (hdma->Instance == DMA1_Channel7)
EricLew 0:80ee8f3b695e 423 {
EricLew 0:80ee8f3b695e 424 /*Reset DMA request*/
EricLew 0:80ee8f3b695e 425 DMA1_CSELR->CSELR &= ~DMA_CSELR_C7S;
EricLew 0:80ee8f3b695e 426 }
EricLew 0:80ee8f3b695e 427 else if (hdma->Instance == DMA2_Channel1)
EricLew 0:80ee8f3b695e 428 {
EricLew 0:80ee8f3b695e 429 /*Reset DMA request*/
EricLew 0:80ee8f3b695e 430 DMA2_CSELR->CSELR &= ~DMA_CSELR_C1S;
EricLew 0:80ee8f3b695e 431 }
EricLew 0:80ee8f3b695e 432 else if (hdma->Instance == DMA2_Channel2)
EricLew 0:80ee8f3b695e 433 {
EricLew 0:80ee8f3b695e 434 /*Reset DMA request*/
EricLew 0:80ee8f3b695e 435 DMA2_CSELR->CSELR &= ~DMA_CSELR_C2S;
EricLew 0:80ee8f3b695e 436 }
EricLew 0:80ee8f3b695e 437 else if (hdma->Instance == DMA2_Channel3)
EricLew 0:80ee8f3b695e 438 {
EricLew 0:80ee8f3b695e 439 /*Reset DMA request*/
EricLew 0:80ee8f3b695e 440 DMA2_CSELR->CSELR &= ~DMA_CSELR_C3S;
EricLew 0:80ee8f3b695e 441 }
EricLew 0:80ee8f3b695e 442 else if (hdma->Instance == DMA2_Channel4)
EricLew 0:80ee8f3b695e 443 {
EricLew 0:80ee8f3b695e 444 /*Reset DMA request*/
EricLew 0:80ee8f3b695e 445 DMA2_CSELR->CSELR &= ~DMA_CSELR_C4S;
EricLew 0:80ee8f3b695e 446 }
EricLew 0:80ee8f3b695e 447 else if (hdma->Instance == DMA2_Channel5)
EricLew 0:80ee8f3b695e 448 {
EricLew 0:80ee8f3b695e 449 /*Reset DMA request*/
EricLew 0:80ee8f3b695e 450 DMA2_CSELR->CSELR &= ~DMA_CSELR_C5S;
EricLew 0:80ee8f3b695e 451 }
EricLew 0:80ee8f3b695e 452 else if (hdma->Instance == DMA2_Channel6)
EricLew 0:80ee8f3b695e 453 {
EricLew 0:80ee8f3b695e 454 /*Reset DMA request*/
EricLew 0:80ee8f3b695e 455 DMA2_CSELR->CSELR &= ~DMA_CSELR_C6S;
EricLew 0:80ee8f3b695e 456 }
EricLew 0:80ee8f3b695e 457 else if (hdma->Instance == DMA2_Channel7)
EricLew 0:80ee8f3b695e 458 {
EricLew 0:80ee8f3b695e 459 /*Reset DMA request*/
EricLew 0:80ee8f3b695e 460 DMA2_CSELR->CSELR &= ~DMA_CSELR_C7S;
EricLew 0:80ee8f3b695e 461 }
EricLew 0:80ee8f3b695e 462
EricLew 0:80ee8f3b695e 463 /* Initialize the error code */
EricLew 0:80ee8f3b695e 464 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
EricLew 0:80ee8f3b695e 465
EricLew 0:80ee8f3b695e 466 /* Initialize the DMA state */
EricLew 0:80ee8f3b695e 467 hdma->State = HAL_DMA_STATE_RESET;
EricLew 0:80ee8f3b695e 468
EricLew 0:80ee8f3b695e 469 /* Release Lock */
EricLew 0:80ee8f3b695e 470 __HAL_UNLOCK(hdma);
EricLew 0:80ee8f3b695e 471
EricLew 0:80ee8f3b695e 472 return HAL_OK;
EricLew 0:80ee8f3b695e 473 }
EricLew 0:80ee8f3b695e 474
EricLew 0:80ee8f3b695e 475 /**
EricLew 0:80ee8f3b695e 476 * @}
EricLew 0:80ee8f3b695e 477 */
EricLew 0:80ee8f3b695e 478
EricLew 0:80ee8f3b695e 479 /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
EricLew 0:80ee8f3b695e 480 * @brief Input and Output operation functions
EricLew 0:80ee8f3b695e 481 *
EricLew 0:80ee8f3b695e 482 @verbatim
EricLew 0:80ee8f3b695e 483 ===============================================================================
EricLew 0:80ee8f3b695e 484 ##### IO operation functions #####
EricLew 0:80ee8f3b695e 485 ===============================================================================
EricLew 0:80ee8f3b695e 486 [..] This section provides functions allowing to:
EricLew 0:80ee8f3b695e 487 (+) Configure the source, destination address and data length and Start DMA transfer
EricLew 0:80ee8f3b695e 488 (+) Configure the source, destination address and data length and
EricLew 0:80ee8f3b695e 489 Start DMA transfer with interrupt
EricLew 0:80ee8f3b695e 490 (+) Abort DMA transfer
EricLew 0:80ee8f3b695e 491 (+) Poll for transfer complete
EricLew 0:80ee8f3b695e 492 (+) Handle DMA interrupt request
EricLew 0:80ee8f3b695e 493
EricLew 0:80ee8f3b695e 494 @endverbatim
EricLew 0:80ee8f3b695e 495 * @{
EricLew 0:80ee8f3b695e 496 */
EricLew 0:80ee8f3b695e 497
EricLew 0:80ee8f3b695e 498 /**
EricLew 0:80ee8f3b695e 499 * @brief Start the DMA Transfer.
EricLew 0:80ee8f3b695e 500 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 501 * the configuration information for the specified DMA Channel.
EricLew 0:80ee8f3b695e 502 * @param SrcAddress: The source memory Buffer address
EricLew 0:80ee8f3b695e 503 * @param DstAddress: The destination memory Buffer address
EricLew 0:80ee8f3b695e 504 * @param DataLength: The length of data to be transferred from source to destination
EricLew 0:80ee8f3b695e 505 * @retval HAL status
EricLew 0:80ee8f3b695e 506 */
EricLew 0:80ee8f3b695e 507 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
EricLew 0:80ee8f3b695e 508 {
EricLew 0:80ee8f3b695e 509 /* Process locked */
EricLew 0:80ee8f3b695e 510 __HAL_LOCK(hdma);
EricLew 0:80ee8f3b695e 511
EricLew 0:80ee8f3b695e 512 /* Change DMA peripheral state */
EricLew 0:80ee8f3b695e 513 hdma->State = HAL_DMA_STATE_BUSY;
EricLew 0:80ee8f3b695e 514
EricLew 0:80ee8f3b695e 515 /* Check the parameters */
EricLew 0:80ee8f3b695e 516 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
EricLew 0:80ee8f3b695e 517
EricLew 0:80ee8f3b695e 518 /* Disable the peripheral */
EricLew 0:80ee8f3b695e 519 __HAL_DMA_DISABLE(hdma);
EricLew 0:80ee8f3b695e 520
EricLew 0:80ee8f3b695e 521 /* Configure the source, destination address and the data length */
EricLew 0:80ee8f3b695e 522 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
EricLew 0:80ee8f3b695e 523
EricLew 0:80ee8f3b695e 524 /* Enable the Peripheral */
EricLew 0:80ee8f3b695e 525 __HAL_DMA_ENABLE(hdma);
EricLew 0:80ee8f3b695e 526
EricLew 0:80ee8f3b695e 527 return HAL_OK;
EricLew 0:80ee8f3b695e 528 }
EricLew 0:80ee8f3b695e 529
EricLew 0:80ee8f3b695e 530 /**
EricLew 0:80ee8f3b695e 531 * @brief Start the DMA Transfer with interrupt enabled.
EricLew 0:80ee8f3b695e 532 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 533 * the configuration information for the specified DMA Channel.
EricLew 0:80ee8f3b695e 534 * @param SrcAddress: The source memory Buffer address
EricLew 0:80ee8f3b695e 535 * @param DstAddress: The destination memory Buffer address
EricLew 0:80ee8f3b695e 536 * @param DataLength: The length of data to be transferred from source to destination
EricLew 0:80ee8f3b695e 537 * @retval HAL status
EricLew 0:80ee8f3b695e 538 */
EricLew 0:80ee8f3b695e 539 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
EricLew 0:80ee8f3b695e 540 {
EricLew 0:80ee8f3b695e 541 /* Process locked */
EricLew 0:80ee8f3b695e 542 __HAL_LOCK(hdma);
EricLew 0:80ee8f3b695e 543
EricLew 0:80ee8f3b695e 544 /* Change DMA peripheral state */
EricLew 0:80ee8f3b695e 545 hdma->State = HAL_DMA_STATE_BUSY;
EricLew 0:80ee8f3b695e 546
EricLew 0:80ee8f3b695e 547 /* Check the parameters */
EricLew 0:80ee8f3b695e 548 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
EricLew 0:80ee8f3b695e 549
EricLew 0:80ee8f3b695e 550 /* Disable the peripheral */
EricLew 0:80ee8f3b695e 551 __HAL_DMA_DISABLE(hdma);
EricLew 0:80ee8f3b695e 552
EricLew 0:80ee8f3b695e 553 /* Configure the source, destination address and the data length */
EricLew 0:80ee8f3b695e 554 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
EricLew 0:80ee8f3b695e 555
EricLew 0:80ee8f3b695e 556 /* Enable the transfer complete interrupt */
EricLew 0:80ee8f3b695e 557 /* Enable the Half transfer complete interrupt */
EricLew 0:80ee8f3b695e 558 /* Enable the transfer Error interrupt */
EricLew 0:80ee8f3b695e 559 __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
EricLew 0:80ee8f3b695e 560
EricLew 0:80ee8f3b695e 561 /* Enable the Peripheral */
EricLew 0:80ee8f3b695e 562 __HAL_DMA_ENABLE(hdma);
EricLew 0:80ee8f3b695e 563
EricLew 0:80ee8f3b695e 564 return HAL_OK;
EricLew 0:80ee8f3b695e 565 }
EricLew 0:80ee8f3b695e 566
EricLew 0:80ee8f3b695e 567 /**
EricLew 0:80ee8f3b695e 568 * @brief Abort the DMA Transfer.
EricLew 0:80ee8f3b695e 569 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 570 * the configuration information for the specified DMA Channel.
EricLew 0:80ee8f3b695e 571 *
EricLew 0:80ee8f3b695e 572 * @note After disabling a DMA Channel, a check for wait until the DMA Channel is
EricLew 0:80ee8f3b695e 573 * effectively disabled is added. If a Channel is disabled
EricLew 0:80ee8f3b695e 574 * while a data transfer is ongoing, the current data will be transferred
EricLew 0:80ee8f3b695e 575 * and the Channel will be effectively disabled only after the transfer of
EricLew 0:80ee8f3b695e 576 * this single data is finished.
EricLew 0:80ee8f3b695e 577 * @retval HAL status
EricLew 0:80ee8f3b695e 578 */
EricLew 0:80ee8f3b695e 579 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
EricLew 0:80ee8f3b695e 580 {
EricLew 0:80ee8f3b695e 581 uint32_t tickstart = 0;
EricLew 0:80ee8f3b695e 582
EricLew 0:80ee8f3b695e 583 /* Disable the channel */
EricLew 0:80ee8f3b695e 584 __HAL_DMA_DISABLE(hdma);
EricLew 0:80ee8f3b695e 585
EricLew 0:80ee8f3b695e 586 /* Get tick */
EricLew 0:80ee8f3b695e 587 tickstart = HAL_GetTick();
EricLew 0:80ee8f3b695e 588
EricLew 0:80ee8f3b695e 589 /* Check if the DMA Channel is effectively disabled */
EricLew 0:80ee8f3b695e 590 while((hdma->Instance->CCR & DMA_CCR_EN) != 0)
EricLew 0:80ee8f3b695e 591 {
EricLew 0:80ee8f3b695e 592 /* Check for the Timeout */
EricLew 0:80ee8f3b695e 593 if((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
EricLew 0:80ee8f3b695e 594 {
EricLew 0:80ee8f3b695e 595 /* Update error code */
EricLew 0:80ee8f3b695e 596 hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
EricLew 0:80ee8f3b695e 597
EricLew 0:80ee8f3b695e 598 /* Change the DMA state */
EricLew 0:80ee8f3b695e 599 hdma->State = HAL_DMA_STATE_TIMEOUT;
EricLew 0:80ee8f3b695e 600
EricLew 0:80ee8f3b695e 601 /* Process Unlocked */
EricLew 0:80ee8f3b695e 602 __HAL_UNLOCK(hdma);
EricLew 0:80ee8f3b695e 603
EricLew 0:80ee8f3b695e 604 return HAL_TIMEOUT;
EricLew 0:80ee8f3b695e 605 }
EricLew 0:80ee8f3b695e 606 }
EricLew 0:80ee8f3b695e 607 /* Change the DMA state */
EricLew 0:80ee8f3b695e 608 hdma->State = HAL_DMA_STATE_READY;
EricLew 0:80ee8f3b695e 609
EricLew 0:80ee8f3b695e 610 /* Process Unlocked */
EricLew 0:80ee8f3b695e 611 __HAL_UNLOCK(hdma);
EricLew 0:80ee8f3b695e 612
EricLew 0:80ee8f3b695e 613 return HAL_OK;
EricLew 0:80ee8f3b695e 614 }
EricLew 0:80ee8f3b695e 615
EricLew 0:80ee8f3b695e 616 /**
EricLew 0:80ee8f3b695e 617 * @brief Polling for transfer complete.
EricLew 0:80ee8f3b695e 618 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 619 * the configuration information for the specified DMA Channel.
EricLew 0:80ee8f3b695e 620 * @param CompleteLevel: Specifies the DMA level complete.
EricLew 0:80ee8f3b695e 621 * @param Timeout: Timeout duration.
EricLew 0:80ee8f3b695e 622 * @retval HAL status
EricLew 0:80ee8f3b695e 623 */
EricLew 0:80ee8f3b695e 624 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
EricLew 0:80ee8f3b695e 625 {
EricLew 0:80ee8f3b695e 626 uint32_t temp;
EricLew 0:80ee8f3b695e 627 uint32_t tickstart = 0;
EricLew 0:80ee8f3b695e 628
EricLew 0:80ee8f3b695e 629 /* Get the level transfer complete flag */
EricLew 0:80ee8f3b695e 630 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
EricLew 0:80ee8f3b695e 631 {
EricLew 0:80ee8f3b695e 632 /* Transfer Complete flag */
EricLew 0:80ee8f3b695e 633 temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
EricLew 0:80ee8f3b695e 634 }
EricLew 0:80ee8f3b695e 635 else
EricLew 0:80ee8f3b695e 636 {
EricLew 0:80ee8f3b695e 637 /* Half Transfer Complete flag */
EricLew 0:80ee8f3b695e 638 temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
EricLew 0:80ee8f3b695e 639 }
EricLew 0:80ee8f3b695e 640
EricLew 0:80ee8f3b695e 641 /* Get tick */
EricLew 0:80ee8f3b695e 642 tickstart = HAL_GetTick();
EricLew 0:80ee8f3b695e 643
EricLew 0:80ee8f3b695e 644 while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
EricLew 0:80ee8f3b695e 645 {
EricLew 0:80ee8f3b695e 646 if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET))
EricLew 0:80ee8f3b695e 647 {
EricLew 0:80ee8f3b695e 648 /* Clear the transfer error flags */
EricLew 0:80ee8f3b695e 649 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
EricLew 0:80ee8f3b695e 650
EricLew 0:80ee8f3b695e 651 /* Update error code */
EricLew 0:80ee8f3b695e 652 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
EricLew 0:80ee8f3b695e 653
EricLew 0:80ee8f3b695e 654 /* Change the DMA state */
EricLew 0:80ee8f3b695e 655 hdma->State= HAL_DMA_STATE_ERROR;
EricLew 0:80ee8f3b695e 656
EricLew 0:80ee8f3b695e 657 /* Process Unlocked */
EricLew 0:80ee8f3b695e 658 __HAL_UNLOCK(hdma);
EricLew 0:80ee8f3b695e 659
EricLew 0:80ee8f3b695e 660 return HAL_ERROR;
EricLew 0:80ee8f3b695e 661 }
EricLew 0:80ee8f3b695e 662 /* Check for the Timeout */
EricLew 0:80ee8f3b695e 663 if(Timeout != HAL_MAX_DELAY)
EricLew 0:80ee8f3b695e 664 {
EricLew 0:80ee8f3b695e 665 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
EricLew 0:80ee8f3b695e 666 {
EricLew 0:80ee8f3b695e 667 /* Update error code */
EricLew 0:80ee8f3b695e 668 hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
EricLew 0:80ee8f3b695e 669
EricLew 0:80ee8f3b695e 670 /* Change the DMA state */
EricLew 0:80ee8f3b695e 671 hdma->State = HAL_DMA_STATE_TIMEOUT;
EricLew 0:80ee8f3b695e 672
EricLew 0:80ee8f3b695e 673 /* Process Unlocked */
EricLew 0:80ee8f3b695e 674 __HAL_UNLOCK(hdma);
EricLew 0:80ee8f3b695e 675
EricLew 0:80ee8f3b695e 676 return HAL_TIMEOUT;
EricLew 0:80ee8f3b695e 677 }
EricLew 0:80ee8f3b695e 678 }
EricLew 0:80ee8f3b695e 679 }
EricLew 0:80ee8f3b695e 680
EricLew 0:80ee8f3b695e 681 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
EricLew 0:80ee8f3b695e 682 {
EricLew 0:80ee8f3b695e 683 /* Clear the transfer complete flag */
EricLew 0:80ee8f3b695e 684 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
EricLew 0:80ee8f3b695e 685
EricLew 0:80ee8f3b695e 686 /* The selected Channelx EN bit is cleared (DMA is disabled and
EricLew 0:80ee8f3b695e 687 all transfers are complete) */
EricLew 0:80ee8f3b695e 688 hdma->State = HAL_DMA_STATE_READY;
EricLew 0:80ee8f3b695e 689
EricLew 0:80ee8f3b695e 690 }
EricLew 0:80ee8f3b695e 691 else
EricLew 0:80ee8f3b695e 692 {
EricLew 0:80ee8f3b695e 693 /* Clear the half transfer complete flag */
EricLew 0:80ee8f3b695e 694 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
EricLew 0:80ee8f3b695e 695
EricLew 0:80ee8f3b695e 696 hdma->State = HAL_DMA_STATE_READY_HALF;
EricLew 0:80ee8f3b695e 697 }
EricLew 0:80ee8f3b695e 698
EricLew 0:80ee8f3b695e 699 /* Process unlocked */
EricLew 0:80ee8f3b695e 700 __HAL_UNLOCK(hdma);
EricLew 0:80ee8f3b695e 701
EricLew 0:80ee8f3b695e 702 return HAL_OK;
EricLew 0:80ee8f3b695e 703 }
EricLew 0:80ee8f3b695e 704
EricLew 0:80ee8f3b695e 705 /**
EricLew 0:80ee8f3b695e 706 * @brief Handle DMA interrupt request.
EricLew 0:80ee8f3b695e 707 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 708 * the configuration information for the specified DMA Channel.
EricLew 0:80ee8f3b695e 709 * @retval None
EricLew 0:80ee8f3b695e 710 */
EricLew 0:80ee8f3b695e 711 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
EricLew 0:80ee8f3b695e 712 {
EricLew 0:80ee8f3b695e 713 /* Transfer Error Interrupt management ***************************************/
EricLew 0:80ee8f3b695e 714 if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)
EricLew 0:80ee8f3b695e 715 {
EricLew 0:80ee8f3b695e 716 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
EricLew 0:80ee8f3b695e 717 {
EricLew 0:80ee8f3b695e 718 /* Disable the transfer error interrupt */
EricLew 0:80ee8f3b695e 719 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
EricLew 0:80ee8f3b695e 720
EricLew 0:80ee8f3b695e 721 /* Clear the transfer error flag */
EricLew 0:80ee8f3b695e 722 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
EricLew 0:80ee8f3b695e 723
EricLew 0:80ee8f3b695e 724 /* Update error code */
EricLew 0:80ee8f3b695e 725 hdma->ErrorCode |= HAL_DMA_ERROR_TE;
EricLew 0:80ee8f3b695e 726
EricLew 0:80ee8f3b695e 727 /* Change the DMA state */
EricLew 0:80ee8f3b695e 728 hdma->State = HAL_DMA_STATE_ERROR;
EricLew 0:80ee8f3b695e 729
EricLew 0:80ee8f3b695e 730 /* Process Unlocked */
EricLew 0:80ee8f3b695e 731 __HAL_UNLOCK(hdma);
EricLew 0:80ee8f3b695e 732
EricLew 0:80ee8f3b695e 733 if (hdma->XferErrorCallback != NULL)
EricLew 0:80ee8f3b695e 734 {
EricLew 0:80ee8f3b695e 735 /* Transfer error callback */
EricLew 0:80ee8f3b695e 736 hdma->XferErrorCallback(hdma);
EricLew 0:80ee8f3b695e 737 }
EricLew 0:80ee8f3b695e 738 }
EricLew 0:80ee8f3b695e 739 }
EricLew 0:80ee8f3b695e 740
EricLew 0:80ee8f3b695e 741 /* Half Transfer Complete Interrupt management ******************************/
EricLew 0:80ee8f3b695e 742 if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)
EricLew 0:80ee8f3b695e 743 {
EricLew 0:80ee8f3b695e 744 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
EricLew 0:80ee8f3b695e 745 {
EricLew 0:80ee8f3b695e 746 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
EricLew 0:80ee8f3b695e 747 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
EricLew 0:80ee8f3b695e 748 {
EricLew 0:80ee8f3b695e 749 /* Disable the half transfer interrupt */
EricLew 0:80ee8f3b695e 750 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
EricLew 0:80ee8f3b695e 751 }
EricLew 0:80ee8f3b695e 752 /* Clear the half transfer complete flag */
EricLew 0:80ee8f3b695e 753 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
EricLew 0:80ee8f3b695e 754
EricLew 0:80ee8f3b695e 755 /* Change DMA peripheral state */
EricLew 0:80ee8f3b695e 756 hdma->State = HAL_DMA_STATE_READY_HALF;
EricLew 0:80ee8f3b695e 757
EricLew 0:80ee8f3b695e 758 if(hdma->XferHalfCpltCallback != NULL)
EricLew 0:80ee8f3b695e 759 {
EricLew 0:80ee8f3b695e 760 /* Half transfer callback */
EricLew 0:80ee8f3b695e 761 hdma->XferHalfCpltCallback(hdma);
EricLew 0:80ee8f3b695e 762 }
EricLew 0:80ee8f3b695e 763 }
EricLew 0:80ee8f3b695e 764 }
EricLew 0:80ee8f3b695e 765
EricLew 0:80ee8f3b695e 766 /* Transfer Complete Interrupt management ***********************************/
EricLew 0:80ee8f3b695e 767 if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)
EricLew 0:80ee8f3b695e 768 {
EricLew 0:80ee8f3b695e 769 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
EricLew 0:80ee8f3b695e 770 {
EricLew 0:80ee8f3b695e 771 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
EricLew 0:80ee8f3b695e 772 {
EricLew 0:80ee8f3b695e 773 /* Disable the transfer complete interrupt */
EricLew 0:80ee8f3b695e 774 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
EricLew 0:80ee8f3b695e 775 }
EricLew 0:80ee8f3b695e 776 /* Clear the transfer complete flag */
EricLew 0:80ee8f3b695e 777 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
EricLew 0:80ee8f3b695e 778
EricLew 0:80ee8f3b695e 779 /* Update error code */
EricLew 0:80ee8f3b695e 780 hdma->ErrorCode |= HAL_DMA_ERROR_NONE;
EricLew 0:80ee8f3b695e 781
EricLew 0:80ee8f3b695e 782 /* Change the DMA state */
EricLew 0:80ee8f3b695e 783 hdma->State = HAL_DMA_STATE_READY;
EricLew 0:80ee8f3b695e 784
EricLew 0:80ee8f3b695e 785 /* Process Unlocked */
EricLew 0:80ee8f3b695e 786 __HAL_UNLOCK(hdma);
EricLew 0:80ee8f3b695e 787
EricLew 0:80ee8f3b695e 788 if(hdma->XferCpltCallback != NULL)
EricLew 0:80ee8f3b695e 789 {
EricLew 0:80ee8f3b695e 790 /* Transfer complete callback */
EricLew 0:80ee8f3b695e 791 hdma->XferCpltCallback(hdma);
EricLew 0:80ee8f3b695e 792 }
EricLew 0:80ee8f3b695e 793 }
EricLew 0:80ee8f3b695e 794 }
EricLew 0:80ee8f3b695e 795 }
EricLew 0:80ee8f3b695e 796
EricLew 0:80ee8f3b695e 797 /**
EricLew 0:80ee8f3b695e 798 * @}
EricLew 0:80ee8f3b695e 799 */
EricLew 0:80ee8f3b695e 800
EricLew 0:80ee8f3b695e 801 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
EricLew 0:80ee8f3b695e 802 * @brief Peripheral State and Errors functions
EricLew 0:80ee8f3b695e 803 *
EricLew 0:80ee8f3b695e 804 @verbatim
EricLew 0:80ee8f3b695e 805 ===============================================================================
EricLew 0:80ee8f3b695e 806 ##### Peripheral State and Errors functions #####
EricLew 0:80ee8f3b695e 807 ===============================================================================
EricLew 0:80ee8f3b695e 808 [..]
EricLew 0:80ee8f3b695e 809 This subsection provides functions allowing to
EricLew 0:80ee8f3b695e 810 (+) Check the DMA state
EricLew 0:80ee8f3b695e 811 (+) Get error code
EricLew 0:80ee8f3b695e 812
EricLew 0:80ee8f3b695e 813 @endverbatim
EricLew 0:80ee8f3b695e 814 * @{
EricLew 0:80ee8f3b695e 815 */
EricLew 0:80ee8f3b695e 816
EricLew 0:80ee8f3b695e 817 /**
EricLew 0:80ee8f3b695e 818 * @brief Return the DMA hande state.
EricLew 0:80ee8f3b695e 819 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 820 * the configuration information for the specified DMA Channel.
EricLew 0:80ee8f3b695e 821 * @retval HAL state
EricLew 0:80ee8f3b695e 822 */
EricLew 0:80ee8f3b695e 823 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
EricLew 0:80ee8f3b695e 824 {
EricLew 0:80ee8f3b695e 825 /* Return DMA handle state */
EricLew 0:80ee8f3b695e 826 return hdma->State;
EricLew 0:80ee8f3b695e 827 }
EricLew 0:80ee8f3b695e 828
EricLew 0:80ee8f3b695e 829 /**
EricLew 0:80ee8f3b695e 830 * @brief Return the DMA error code.
EricLew 0:80ee8f3b695e 831 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 832 * the configuration information for the specified DMA Channel.
EricLew 0:80ee8f3b695e 833 * @retval DMA Error Code
EricLew 0:80ee8f3b695e 834 */
EricLew 0:80ee8f3b695e 835 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
EricLew 0:80ee8f3b695e 836 {
EricLew 0:80ee8f3b695e 837 return hdma->ErrorCode;
EricLew 0:80ee8f3b695e 838 }
EricLew 0:80ee8f3b695e 839
EricLew 0:80ee8f3b695e 840 /**
EricLew 0:80ee8f3b695e 841 * @}
EricLew 0:80ee8f3b695e 842 */
EricLew 0:80ee8f3b695e 843
EricLew 0:80ee8f3b695e 844 /**
EricLew 0:80ee8f3b695e 845 * @}
EricLew 0:80ee8f3b695e 846 */
EricLew 0:80ee8f3b695e 847
EricLew 0:80ee8f3b695e 848 /** @addtogroup DMA_Private_Functions
EricLew 0:80ee8f3b695e 849 * @{
EricLew 0:80ee8f3b695e 850 */
EricLew 0:80ee8f3b695e 851
EricLew 0:80ee8f3b695e 852 /**
EricLew 0:80ee8f3b695e 853 * @brief Sets the DMA Transfer parameter.
EricLew 0:80ee8f3b695e 854 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 855 * the configuration information for the specified DMA Channel.
EricLew 0:80ee8f3b695e 856 * @param SrcAddress: The source memory Buffer address
EricLew 0:80ee8f3b695e 857 * @param DstAddress: The destination memory Buffer address
EricLew 0:80ee8f3b695e 858 * @param DataLength: The length of data to be transferred from source to destination
EricLew 0:80ee8f3b695e 859 * @retval HAL status
EricLew 0:80ee8f3b695e 860 */
EricLew 0:80ee8f3b695e 861 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
EricLew 0:80ee8f3b695e 862 {
EricLew 0:80ee8f3b695e 863 /* Configure DMA Channel data length */
EricLew 0:80ee8f3b695e 864 hdma->Instance->CNDTR = DataLength;
EricLew 0:80ee8f3b695e 865
EricLew 0:80ee8f3b695e 866 /* Peripheral to Memory */
EricLew 0:80ee8f3b695e 867 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
EricLew 0:80ee8f3b695e 868 {
EricLew 0:80ee8f3b695e 869 /* Configure DMA Channel destination address */
EricLew 0:80ee8f3b695e 870 hdma->Instance->CPAR = DstAddress;
EricLew 0:80ee8f3b695e 871
EricLew 0:80ee8f3b695e 872 /* Configure DMA Channel source address */
EricLew 0:80ee8f3b695e 873 hdma->Instance->CMAR = SrcAddress;
EricLew 0:80ee8f3b695e 874 }
EricLew 0:80ee8f3b695e 875 /* Memory to Peripheral */
EricLew 0:80ee8f3b695e 876 else
EricLew 0:80ee8f3b695e 877 {
EricLew 0:80ee8f3b695e 878 /* Configure DMA Channel source address */
EricLew 0:80ee8f3b695e 879 hdma->Instance->CPAR = SrcAddress;
EricLew 0:80ee8f3b695e 880
EricLew 0:80ee8f3b695e 881 /* Configure DMA Channel destination address */
EricLew 0:80ee8f3b695e 882 hdma->Instance->CMAR = DstAddress;
EricLew 0:80ee8f3b695e 883 }
EricLew 0:80ee8f3b695e 884 }
EricLew 0:80ee8f3b695e 885
EricLew 0:80ee8f3b695e 886 /**
EricLew 0:80ee8f3b695e 887 * @}
EricLew 0:80ee8f3b695e 888 */
EricLew 0:80ee8f3b695e 889
EricLew 0:80ee8f3b695e 890 #endif /* HAL_DMA_MODULE_ENABLED */
EricLew 0:80ee8f3b695e 891 /**
EricLew 0:80ee8f3b695e 892 * @}
EricLew 0:80ee8f3b695e 893 */
EricLew 0:80ee8f3b695e 894
EricLew 0:80ee8f3b695e 895 /**
EricLew 0:80ee8f3b695e 896 * @}
EricLew 0:80ee8f3b695e 897 */
EricLew 0:80ee8f3b695e 898
EricLew 0:80ee8f3b695e 899 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
EricLew 0:80ee8f3b695e 900