Eric Lewiston / STM32L4xx_HAL_Driver

Hal Drivers for L4

Dependents:   BSP OneHopeOnePrayer FINAL_AUDIO_RECORD AudioDemo

Fork of STM32L4xx_HAL_Driver by Senior Design: Sound Monitor

Src/stm32l4xx_hal_pwr_ex.c@2:7aef7655b0a8, 2015-11-25 (annotated)

Committer:
EricLew
Date:
Wed Nov 25 17:30:43 2015 +0000
Revision:
2:7aef7655b0a8
Parent:
0:80ee8f3b695e 
commit;

Who changed what in which revision?

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EricLew 0:80ee8f3b695e 1 /**
EricLew 0:80ee8f3b695e 2 ******************************************************************************
EricLew 0:80ee8f3b695e 3 * @file stm32l4xx_hal_pwr_ex.c
EricLew 0:80ee8f3b695e 4 * @author MCD Application Team
EricLew 0:80ee8f3b695e 5 * @version V1.1.0
EricLew 0:80ee8f3b695e 6 * @date 16-September-2015
EricLew 0:80ee8f3b695e 7 * @brief Extended PWR HAL module driver.
EricLew 0:80ee8f3b695e 8 * This file provides firmware functions to manage the following
EricLew 0:80ee8f3b695e 9 * functionalities of the Power Controller (PWR) peripheral:
EricLew 0:80ee8f3b695e 10 * + Extended Initialization and de-initialization functions
EricLew 0:80ee8f3b695e 11 * + Extended Peripheral Control functions
EricLew 0:80ee8f3b695e 12 *
EricLew 0:80ee8f3b695e 13 ******************************************************************************
EricLew 0:80ee8f3b695e 14 * @attention
EricLew 0:80ee8f3b695e 15 *
EricLew 0:80ee8f3b695e 16 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
EricLew 0:80ee8f3b695e 17 *
EricLew 0:80ee8f3b695e 18 * Redistribution and use in source and binary forms, with or without modification,
EricLew 0:80ee8f3b695e 19 * are permitted provided that the following conditions are met:
EricLew 0:80ee8f3b695e 20 * 1. Redistributions of source code must retain the above copyright notice,
EricLew 0:80ee8f3b695e 21 * this list of conditions and the following disclaimer.
EricLew 0:80ee8f3b695e 22 * 2. Redistributions in binary form must reproduce the above copyright notice,
EricLew 0:80ee8f3b695e 23 * this list of conditions and the following disclaimer in the documentation
EricLew 0:80ee8f3b695e 24 * and/or other materials provided with the distribution.
EricLew 0:80ee8f3b695e 25 * 3. Neither the name of STMicroelectronics nor the names of its contributors
EricLew 0:80ee8f3b695e 26 * may be used to endorse or promote products derived from this software
EricLew 0:80ee8f3b695e 27 * without specific prior written permission.
EricLew 0:80ee8f3b695e 28 *
EricLew 0:80ee8f3b695e 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew 0:80ee8f3b695e 30 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew 0:80ee8f3b695e 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
EricLew 0:80ee8f3b695e 32 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
EricLew 0:80ee8f3b695e 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
EricLew 0:80ee8f3b695e 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
EricLew 0:80ee8f3b695e 35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
EricLew 0:80ee8f3b695e 36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
EricLew 0:80ee8f3b695e 37 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
EricLew 0:80ee8f3b695e 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
EricLew 0:80ee8f3b695e 39 *
EricLew 0:80ee8f3b695e 40 ******************************************************************************
EricLew 0:80ee8f3b695e 41 */
EricLew 0:80ee8f3b695e 42
EricLew 0:80ee8f3b695e 43 /* Includes ------------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 44 #include "stm32l4xx_hal.h"
EricLew 0:80ee8f3b695e 45
EricLew 0:80ee8f3b695e 46 /** @addtogroup STM32L4xx_HAL_Driver
EricLew 0:80ee8f3b695e 47 * @{
EricLew 0:80ee8f3b695e 48 */
EricLew 0:80ee8f3b695e 49
EricLew 0:80ee8f3b695e 50 /** @defgroup PWREx PWREx
EricLew 0:80ee8f3b695e 51 * @brief PWR Extended HAL module driver
EricLew 0:80ee8f3b695e 52 * @{
EricLew 0:80ee8f3b695e 53 */
EricLew 0:80ee8f3b695e 54
EricLew 0:80ee8f3b695e 55 #ifdef HAL_PWR_MODULE_ENABLED
EricLew 0:80ee8f3b695e 56
EricLew 0:80ee8f3b695e 57 /* Private typedef -----------------------------------------------------------*/
EricLew 0:80ee8f3b695e 58 /* Private define ------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 59 #define PWR_PORTH_AVAILABLE_PINS (PWR_GPIO_BIT_0|PWR_GPIO_BIT_1)
EricLew 0:80ee8f3b695e 60
EricLew 0:80ee8f3b695e 61
EricLew 0:80ee8f3b695e 62 /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
EricLew 0:80ee8f3b695e 63 * @{
EricLew 0:80ee8f3b695e 64 */
EricLew 0:80ee8f3b695e 65
EricLew 0:80ee8f3b695e 66 /** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask
EricLew 0:80ee8f3b695e 67 * @{
EricLew 0:80ee8f3b695e 68 */
EricLew 0:80ee8f3b695e 69 #define PVM_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVM threshold crossing */
EricLew 0:80ee8f3b695e 70 #define PVM_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVM threshold crossing */
EricLew 0:80ee8f3b695e 71 #define PVM_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVM trigger */
EricLew 0:80ee8f3b695e 72 #define PVM_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVM trigger */
EricLew 0:80ee8f3b695e 73 /**
EricLew 0:80ee8f3b695e 74 * @}
EricLew 0:80ee8f3b695e 75 */
EricLew 0:80ee8f3b695e 76
EricLew 0:80ee8f3b695e 77 /** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value
EricLew 0:80ee8f3b695e 78 * @{
EricLew 0:80ee8f3b695e 79 */
EricLew 0:80ee8f3b695e 80 #define PWR_FLAG_SETTING_DELAY_US 50 /*!< Time out value for REGLPF and VOSF flags setting */
EricLew 0:80ee8f3b695e 81 /**
EricLew 0:80ee8f3b695e 82 * @}
EricLew 0:80ee8f3b695e 83 */
EricLew 0:80ee8f3b695e 84
EricLew 0:80ee8f3b695e 85
EricLew 0:80ee8f3b695e 86
EricLew 0:80ee8f3b695e 87 /**
EricLew 0:80ee8f3b695e 88 * @}
EricLew 0:80ee8f3b695e 89 */
EricLew 0:80ee8f3b695e 90
EricLew 0:80ee8f3b695e 91
EricLew 0:80ee8f3b695e 92
EricLew 0:80ee8f3b695e 93 /* Private macro -------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 94 /* Private variables ---------------------------------------------------------*/
EricLew 0:80ee8f3b695e 95 /* Private function prototypes -----------------------------------------------*/
EricLew 0:80ee8f3b695e 96 /* Exported functions --------------------------------------------------------*/
EricLew 0:80ee8f3b695e 97
EricLew 0:80ee8f3b695e 98 /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
EricLew 0:80ee8f3b695e 99 * @{
EricLew 0:80ee8f3b695e 100 */
EricLew 0:80ee8f3b695e 101
EricLew 0:80ee8f3b695e 102 /** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
EricLew 0:80ee8f3b695e 103 * @brief Extended Peripheral Control functions
EricLew 0:80ee8f3b695e 104 *
EricLew 0:80ee8f3b695e 105 @verbatim
EricLew 0:80ee8f3b695e 106 ===============================================================================
EricLew 0:80ee8f3b695e 107 ##### Extended Peripheral Initialization and de-initialization functions #####
EricLew 0:80ee8f3b695e 108 ===============================================================================
EricLew 0:80ee8f3b695e 109 [..]
EricLew 0:80ee8f3b695e 110
EricLew 0:80ee8f3b695e 111 @endverbatim
EricLew 0:80ee8f3b695e 112 * @{
EricLew 0:80ee8f3b695e 113 */
EricLew 0:80ee8f3b695e 114
EricLew 0:80ee8f3b695e 115
EricLew 0:80ee8f3b695e 116 /**
EricLew 0:80ee8f3b695e 117 * @brief Return Voltage Scaling Range.
EricLew 0:80ee8f3b695e 118 * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2)
EricLew 0:80ee8f3b695e 119 */
EricLew 0:80ee8f3b695e 120 uint32_t HAL_PWREx_GetVoltageRange(void)
EricLew 0:80ee8f3b695e 121 {
EricLew 0:80ee8f3b695e 122 return (PWR->CR1 & PWR_CR1_VOS);
EricLew 0:80ee8f3b695e 123 }
EricLew 0:80ee8f3b695e 124
EricLew 0:80ee8f3b695e 125
EricLew 0:80ee8f3b695e 126
EricLew 0:80ee8f3b695e 127 /**
EricLew 0:80ee8f3b695e 128 * @brief Configure the main internal regulator output voltage.
EricLew 0:80ee8f3b695e 129 * @param VoltageScaling: specifies the regulator output voltage to achieve
EricLew 0:80ee8f3b695e 130 * a tradeoff between performance and power consumption.
EricLew 0:80ee8f3b695e 131 * This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 132 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
EricLew 0:80ee8f3b695e 133 * typical output voltage at 1.2 V,
EricLew 0:80ee8f3b695e 134 * system frequency up to 80 MHz.
EricLew 0:80ee8f3b695e 135 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
EricLew 0:80ee8f3b695e 136 * typical output voltage at 1.0 V,
EricLew 0:80ee8f3b695e 137 * system frequency up to 26 MHz.
EricLew 0:80ee8f3b695e 138 * @note When moving from Range 1 to Range 2, the system frequency must be decreased to
EricLew 0:80ee8f3b695e 139 * a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API.
EricLew 0:80ee8f3b695e 140 * When moving from Range 2 to Range 1, the system frequency can be increased to
EricLew 0:80ee8f3b695e 141 * a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API.
EricLew 0:80ee8f3b695e 142 * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be
EricLew 0:80ee8f3b695e 143 * cleared before returning the status. If the flag is not cleared within
EricLew 0:80ee8f3b695e 144 * 50 microseconds, HAL_TIMEOUT status is reported.
EricLew 0:80ee8f3b695e 145 * @retval HAL Status
EricLew 0:80ee8f3b695e 146 */
EricLew 0:80ee8f3b695e 147 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
EricLew 0:80ee8f3b695e 148 {
EricLew 0:80ee8f3b695e 149 uint32_t wait_loop_index = 0;
EricLew 0:80ee8f3b695e 150
EricLew 0:80ee8f3b695e 151 assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
EricLew 0:80ee8f3b695e 152
EricLew 0:80ee8f3b695e 153 /* If Set Range 1 */
EricLew 0:80ee8f3b695e 154 if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
EricLew 0:80ee8f3b695e 155 {
EricLew 0:80ee8f3b695e 156 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
EricLew 0:80ee8f3b695e 157 {
EricLew 0:80ee8f3b695e 158 /* Set Range 1 */
EricLew 0:80ee8f3b695e 159 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
EricLew 0:80ee8f3b695e 160
EricLew 0:80ee8f3b695e 161 /* Wait until VOSF is cleared */
EricLew 0:80ee8f3b695e 162 wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000));
EricLew 0:80ee8f3b695e 163 while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)))
EricLew 0:80ee8f3b695e 164 {
EricLew 0:80ee8f3b695e 165 wait_loop_index--;
EricLew 0:80ee8f3b695e 166 }
EricLew 0:80ee8f3b695e 167 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
EricLew 0:80ee8f3b695e 168 {
EricLew 0:80ee8f3b695e 169 return HAL_TIMEOUT;
EricLew 0:80ee8f3b695e 170 }
EricLew 0:80ee8f3b695e 171 }
EricLew 0:80ee8f3b695e 172 }
EricLew 0:80ee8f3b695e 173 else
EricLew 0:80ee8f3b695e 174 {
EricLew 0:80ee8f3b695e 175 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
EricLew 0:80ee8f3b695e 176 {
EricLew 0:80ee8f3b695e 177 /* Set Range 2 */
EricLew 0:80ee8f3b695e 178 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
EricLew 0:80ee8f3b695e 179 /* No need to wait for VOSF to be cleared for this transition */
EricLew 0:80ee8f3b695e 180 }
EricLew 0:80ee8f3b695e 181 }
EricLew 0:80ee8f3b695e 182
EricLew 0:80ee8f3b695e 183 return HAL_OK;
EricLew 0:80ee8f3b695e 184 }
EricLew 0:80ee8f3b695e 185
EricLew 0:80ee8f3b695e 186
EricLew 0:80ee8f3b695e 187 /**
EricLew 0:80ee8f3b695e 188 * @brief Enable battery charging.
EricLew 0:80ee8f3b695e 189 * When VDD is present, charge the external battery on VBAT thru an internal resistor.
EricLew 0:80ee8f3b695e 190 * @param ResistorSelection: specifies the resistor impedance.
EricLew 0:80ee8f3b695e 191 * This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 192 * @arg PWR_BATTERY_CHARGING_RESISTOR_5: 5 kOhms resistor
EricLew 0:80ee8f3b695e 193 * @arg PWR_BATTERY_CHARGING_RESISTOR_1_5: 1.5 kOhms resistor
EricLew 0:80ee8f3b695e 194 * @retval None
EricLew 0:80ee8f3b695e 195 */
EricLew 0:80ee8f3b695e 196 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)
EricLew 0:80ee8f3b695e 197 {
EricLew 0:80ee8f3b695e 198 assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection));
EricLew 0:80ee8f3b695e 199
EricLew 0:80ee8f3b695e 200 /* Specify resistor selection */
EricLew 0:80ee8f3b695e 201 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection);
EricLew 0:80ee8f3b695e 202
EricLew 0:80ee8f3b695e 203 /* Enable battery charging */
EricLew 0:80ee8f3b695e 204 SET_BIT(PWR->CR4, PWR_CR4_VBE);
EricLew 0:80ee8f3b695e 205 }
EricLew 0:80ee8f3b695e 206
EricLew 0:80ee8f3b695e 207
EricLew 0:80ee8f3b695e 208 /**
EricLew 0:80ee8f3b695e 209 * @brief Disable battery charging.
EricLew 0:80ee8f3b695e 210 * @retval None
EricLew 0:80ee8f3b695e 211 */
EricLew 0:80ee8f3b695e 212 void HAL_PWREx_DisableBatteryCharging(void)
EricLew 0:80ee8f3b695e 213 {
EricLew 0:80ee8f3b695e 214 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
EricLew 0:80ee8f3b695e 215 }
EricLew 0:80ee8f3b695e 216
EricLew 0:80ee8f3b695e 217
EricLew 0:80ee8f3b695e 218 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
EricLew 0:80ee8f3b695e 219 /**
EricLew 0:80ee8f3b695e 220 * @brief Enable VDDUSB supply.
EricLew 0:80ee8f3b695e 221 * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.
EricLew 0:80ee8f3b695e 222 * @retval None
EricLew 0:80ee8f3b695e 223 */
EricLew 0:80ee8f3b695e 224 void HAL_PWREx_EnableVddUSB(void)
EricLew 0:80ee8f3b695e 225 {
EricLew 0:80ee8f3b695e 226 SET_BIT(PWR->CR2, PWR_CR2_USV);
EricLew 0:80ee8f3b695e 227 }
EricLew 0:80ee8f3b695e 228
EricLew 0:80ee8f3b695e 229
EricLew 0:80ee8f3b695e 230 /**
EricLew 0:80ee8f3b695e 231 * @brief Disable VDDUSB supply.
EricLew 0:80ee8f3b695e 232 * @retval None
EricLew 0:80ee8f3b695e 233 */
EricLew 0:80ee8f3b695e 234 void HAL_PWREx_DisableVddUSB(void)
EricLew 0:80ee8f3b695e 235 {
EricLew 0:80ee8f3b695e 236 CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
EricLew 0:80ee8f3b695e 237 }
EricLew 0:80ee8f3b695e 238 #endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
EricLew 0:80ee8f3b695e 239
EricLew 0:80ee8f3b695e 240 /**
EricLew 0:80ee8f3b695e 241 * @brief Enable VDDIO2 supply.
EricLew 0:80ee8f3b695e 242 * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present.
EricLew 0:80ee8f3b695e 243 * @retval None
EricLew 0:80ee8f3b695e 244 */
EricLew 0:80ee8f3b695e 245 void HAL_PWREx_EnableVddIO2(void)
EricLew 0:80ee8f3b695e 246 {
EricLew 0:80ee8f3b695e 247 SET_BIT(PWR->CR2, PWR_CR2_IOSV);
EricLew 0:80ee8f3b695e 248 }
EricLew 0:80ee8f3b695e 249
EricLew 0:80ee8f3b695e 250
EricLew 0:80ee8f3b695e 251 /**
EricLew 0:80ee8f3b695e 252 * @brief Disable VDDIO2 supply.
EricLew 0:80ee8f3b695e 253 * @retval None
EricLew 0:80ee8f3b695e 254 */
EricLew 0:80ee8f3b695e 255 void HAL_PWREx_DisableVddIO2(void)
EricLew 0:80ee8f3b695e 256 {
EricLew 0:80ee8f3b695e 257 CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
EricLew 0:80ee8f3b695e 258 }
EricLew 0:80ee8f3b695e 259
EricLew 0:80ee8f3b695e 260
EricLew 0:80ee8f3b695e 261 /**
EricLew 0:80ee8f3b695e 262 * @brief Enable Internal Wake-up Line.
EricLew 0:80ee8f3b695e 263 * @retval None
EricLew 0:80ee8f3b695e 264 */
EricLew 0:80ee8f3b695e 265 void HAL_PWREx_EnableInternalWakeUpLine(void)
EricLew 0:80ee8f3b695e 266 {
EricLew 0:80ee8f3b695e 267 SET_BIT(PWR->CR3, PWR_CR3_EIWF);
EricLew 0:80ee8f3b695e 268 }
EricLew 0:80ee8f3b695e 269
EricLew 0:80ee8f3b695e 270
EricLew 0:80ee8f3b695e 271 /**
EricLew 0:80ee8f3b695e 272 * @brief Disable Internal Wake-up Line.
EricLew 0:80ee8f3b695e 273 * @retval None
EricLew 0:80ee8f3b695e 274 */
EricLew 0:80ee8f3b695e 275 void HAL_PWREx_DisableInternalWakeUpLine(void)
EricLew 0:80ee8f3b695e 276 {
EricLew 0:80ee8f3b695e 277 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
EricLew 0:80ee8f3b695e 278 }
EricLew 0:80ee8f3b695e 279
EricLew 0:80ee8f3b695e 280
EricLew 0:80ee8f3b695e 281
EricLew 0:80ee8f3b695e 282 /**
EricLew 0:80ee8f3b695e 283 * @brief Enable GPIO pull-up state in Standby and Shutdown modes.
EricLew 0:80ee8f3b695e 284 * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in
EricLew 0:80ee8f3b695e 285 * pull-up state in Standby and Shutdown modes.
EricLew 0:80ee8f3b695e 286 * @note This state is effective in Standby and Shutdown modes only if APC bit
EricLew 0:80ee8f3b695e 287 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
EricLew 0:80ee8f3b695e 288 * @note The configuration is lost when exiting the Shutdown mode due to the
EricLew 0:80ee8f3b695e 289 * power-on reset, maintained when exiting the Standby mode.
EricLew 0:80ee8f3b695e 290 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding
EricLew 0:80ee8f3b695e 291 * PDy bit of PWR_PDCRx register is cleared unless it is reserved.
EricLew 0:80ee8f3b695e 292 * @note Even if a PUy bit to set is reserved, the other PUy bits entered as input
EricLew 0:80ee8f3b695e 293 * parameter at the same time are set.
EricLew 0:80ee8f3b695e 294 * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
EricLew 0:80ee8f3b695e 295 * to select the GPIO peripheral.
EricLew 0:80ee8f3b695e 296 * @param GPIONumber: Specify the I/O pins numbers.
EricLew 0:80ee8f3b695e 297 * This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 298 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less
EricLew 0:80ee8f3b695e 299 * I/O pins are available) or the logical OR of several of them to set
EricLew 0:80ee8f3b695e 300 * several bits for a given port in a single API call.
EricLew 0:80ee8f3b695e 301 * @retval HAL Status
EricLew 0:80ee8f3b695e 302 */
EricLew 0:80ee8f3b695e 303 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
EricLew 0:80ee8f3b695e 304 {
EricLew 0:80ee8f3b695e 305 assert_param(IS_PWR_GPIO(GPIO));
EricLew 0:80ee8f3b695e 306 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
EricLew 0:80ee8f3b695e 307
EricLew 0:80ee8f3b695e 308 switch (GPIO)
EricLew 0:80ee8f3b695e 309 {
EricLew 0:80ee8f3b695e 310 case PWR_GPIO_A:
EricLew 0:80ee8f3b695e 311 SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
EricLew 0:80ee8f3b695e 312 CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
EricLew 0:80ee8f3b695e 313 break;
EricLew 0:80ee8f3b695e 314 case PWR_GPIO_B:
EricLew 0:80ee8f3b695e 315 SET_BIT(PWR->PUCRB, GPIONumber);
EricLew 0:80ee8f3b695e 316 CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
EricLew 0:80ee8f3b695e 317 break;
EricLew 0:80ee8f3b695e 318 case PWR_GPIO_C:
EricLew 0:80ee8f3b695e 319 SET_BIT(PWR->PUCRC, GPIONumber);
EricLew 0:80ee8f3b695e 320 CLEAR_BIT(PWR->PDCRC, GPIONumber);
EricLew 0:80ee8f3b695e 321 break;
EricLew 0:80ee8f3b695e 322 case PWR_GPIO_D:
EricLew 0:80ee8f3b695e 323 SET_BIT(PWR->PUCRD, GPIONumber);
EricLew 0:80ee8f3b695e 324 CLEAR_BIT(PWR->PDCRD, GPIONumber);
EricLew 0:80ee8f3b695e 325 break;
EricLew 0:80ee8f3b695e 326 case PWR_GPIO_E:
EricLew 0:80ee8f3b695e 327 SET_BIT(PWR->PUCRE, GPIONumber);
EricLew 0:80ee8f3b695e 328 CLEAR_BIT(PWR->PDCRE, GPIONumber);
EricLew 0:80ee8f3b695e 329 break;
EricLew 0:80ee8f3b695e 330 case PWR_GPIO_F:
EricLew 0:80ee8f3b695e 331 SET_BIT(PWR->PUCRF, GPIONumber);
EricLew 0:80ee8f3b695e 332 CLEAR_BIT(PWR->PDCRF, GPIONumber);
EricLew 0:80ee8f3b695e 333 break;
EricLew 0:80ee8f3b695e 334 case PWR_GPIO_G:
EricLew 0:80ee8f3b695e 335 SET_BIT(PWR->PUCRG, GPIONumber);
EricLew 0:80ee8f3b695e 336 CLEAR_BIT(PWR->PDCRG, GPIONumber);
EricLew 0:80ee8f3b695e 337 break;
EricLew 0:80ee8f3b695e 338 case PWR_GPIO_H:
EricLew 0:80ee8f3b695e 339 SET_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
EricLew 0:80ee8f3b695e 340 CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
EricLew 0:80ee8f3b695e 341 break;
EricLew 0:80ee8f3b695e 342 default:
EricLew 0:80ee8f3b695e 343 return HAL_ERROR;
EricLew 0:80ee8f3b695e 344 }
EricLew 0:80ee8f3b695e 345
EricLew 0:80ee8f3b695e 346 return HAL_OK;
EricLew 0:80ee8f3b695e 347 }
EricLew 0:80ee8f3b695e 348
EricLew 0:80ee8f3b695e 349
EricLew 0:80ee8f3b695e 350 /**
EricLew 0:80ee8f3b695e 351 * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.
EricLew 0:80ee8f3b695e 352 * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O
EricLew 0:80ee8f3b695e 353 * in pull-up state in Standby and Shutdown modes.
EricLew 0:80ee8f3b695e 354 * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input
EricLew 0:80ee8f3b695e 355 * parameter at the same time are reset.
EricLew 0:80ee8f3b695e 356 * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
EricLew 0:80ee8f3b695e 357 * to select the GPIO peripheral.
EricLew 0:80ee8f3b695e 358 * @param GPIONumber: Specify the I/O pins numbers.
EricLew 0:80ee8f3b695e 359 * This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 360 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less
EricLew 0:80ee8f3b695e 361 * I/O pins are available) or the logical OR of several of them to reset
EricLew 0:80ee8f3b695e 362 * several bits for a given port in a single API call.
EricLew 0:80ee8f3b695e 363 * @retval HAL Status
EricLew 0:80ee8f3b695e 364 */
EricLew 0:80ee8f3b695e 365 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
EricLew 0:80ee8f3b695e 366 {
EricLew 0:80ee8f3b695e 367 assert_param(IS_PWR_GPIO(GPIO));
EricLew 0:80ee8f3b695e 368 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
EricLew 0:80ee8f3b695e 369
EricLew 0:80ee8f3b695e 370 switch (GPIO)
EricLew 0:80ee8f3b695e 371 {
EricLew 0:80ee8f3b695e 372 case PWR_GPIO_A:
EricLew 0:80ee8f3b695e 373 CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
EricLew 0:80ee8f3b695e 374 break;
EricLew 0:80ee8f3b695e 375 case PWR_GPIO_B:
EricLew 0:80ee8f3b695e 376 CLEAR_BIT(PWR->PUCRB, GPIONumber);
EricLew 0:80ee8f3b695e 377 break;
EricLew 0:80ee8f3b695e 378 case PWR_GPIO_C:
EricLew 0:80ee8f3b695e 379 CLEAR_BIT(PWR->PUCRC, GPIONumber);
EricLew 0:80ee8f3b695e 380 break;
EricLew 0:80ee8f3b695e 381 case PWR_GPIO_D:
EricLew 0:80ee8f3b695e 382 CLEAR_BIT(PWR->PUCRD, GPIONumber);
EricLew 0:80ee8f3b695e 383 break;
EricLew 0:80ee8f3b695e 384 case PWR_GPIO_E:
EricLew 0:80ee8f3b695e 385 CLEAR_BIT(PWR->PUCRE, GPIONumber);
EricLew 0:80ee8f3b695e 386 break;
EricLew 0:80ee8f3b695e 387 case PWR_GPIO_F:
EricLew 0:80ee8f3b695e 388 CLEAR_BIT(PWR->PUCRF, GPIONumber);
EricLew 0:80ee8f3b695e 389 break;
EricLew 0:80ee8f3b695e 390 case PWR_GPIO_G:
EricLew 0:80ee8f3b695e 391 CLEAR_BIT(PWR->PUCRG, GPIONumber);
EricLew 0:80ee8f3b695e 392 break;
EricLew 0:80ee8f3b695e 393 case PWR_GPIO_H:
EricLew 0:80ee8f3b695e 394 CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
EricLew 0:80ee8f3b695e 395 break;
EricLew 0:80ee8f3b695e 396 default:
EricLew 0:80ee8f3b695e 397 return HAL_ERROR;
EricLew 0:80ee8f3b695e 398 }
EricLew 0:80ee8f3b695e 399
EricLew 0:80ee8f3b695e 400 return HAL_OK;
EricLew 0:80ee8f3b695e 401 }
EricLew 0:80ee8f3b695e 402
EricLew 0:80ee8f3b695e 403
EricLew 0:80ee8f3b695e 404
EricLew 0:80ee8f3b695e 405 /**
EricLew 0:80ee8f3b695e 406 * @brief Enable GPIO pull-down state in Standby and Shutdown modes.
EricLew 0:80ee8f3b695e 407 * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in
EricLew 0:80ee8f3b695e 408 * pull-down state in Standby and Shutdown modes.
EricLew 0:80ee8f3b695e 409 * @note This state is effective in Standby and Shutdown modes only if APC bit
EricLew 0:80ee8f3b695e 410 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
EricLew 0:80ee8f3b695e 411 * @note The configuration is lost when exiting the Shutdown mode due to the
EricLew 0:80ee8f3b695e 412 * power-on reset, maintained when exiting the Standby mode.
EricLew 0:80ee8f3b695e 413 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding
EricLew 0:80ee8f3b695e 414 * PUy bit of PWR_PUCRx register is cleared unless it is reserved.
EricLew 0:80ee8f3b695e 415 * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input
EricLew 0:80ee8f3b695e 416 * parameter at the same time are set.
EricLew 0:80ee8f3b695e 417 * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
EricLew 0:80ee8f3b695e 418 * to select the GPIO peripheral.
EricLew 0:80ee8f3b695e 419 * @param GPIONumber: Specify the I/O pins numbers.
EricLew 0:80ee8f3b695e 420 * This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 421 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less
EricLew 0:80ee8f3b695e 422 * I/O pins are available) or the logical OR of several of them to set
EricLew 0:80ee8f3b695e 423 * several bits for a given port in a single API call.
EricLew 0:80ee8f3b695e 424 * @retval HAL Status
EricLew 0:80ee8f3b695e 425 */
EricLew 0:80ee8f3b695e 426 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
EricLew 0:80ee8f3b695e 427 {
EricLew 0:80ee8f3b695e 428 assert_param(IS_PWR_GPIO(GPIO));
EricLew 0:80ee8f3b695e 429 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
EricLew 0:80ee8f3b695e 430
EricLew 0:80ee8f3b695e 431 switch (GPIO)
EricLew 0:80ee8f3b695e 432 {
EricLew 0:80ee8f3b695e 433 case PWR_GPIO_A:
EricLew 0:80ee8f3b695e 434 SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
EricLew 0:80ee8f3b695e 435 CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
EricLew 0:80ee8f3b695e 436 break;
EricLew 0:80ee8f3b695e 437 case PWR_GPIO_B:
EricLew 0:80ee8f3b695e 438 SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
EricLew 0:80ee8f3b695e 439 CLEAR_BIT(PWR->PUCRB, GPIONumber);
EricLew 0:80ee8f3b695e 440 break;
EricLew 0:80ee8f3b695e 441 case PWR_GPIO_C:
EricLew 0:80ee8f3b695e 442 SET_BIT(PWR->PDCRC, GPIONumber);
EricLew 0:80ee8f3b695e 443 CLEAR_BIT(PWR->PUCRC, GPIONumber);
EricLew 0:80ee8f3b695e 444 break;
EricLew 0:80ee8f3b695e 445 case PWR_GPIO_D:
EricLew 0:80ee8f3b695e 446 SET_BIT(PWR->PDCRD, GPIONumber);
EricLew 0:80ee8f3b695e 447 CLEAR_BIT(PWR->PUCRD, GPIONumber);
EricLew 0:80ee8f3b695e 448 break;
EricLew 0:80ee8f3b695e 449 case PWR_GPIO_E:
EricLew 0:80ee8f3b695e 450 SET_BIT(PWR->PDCRE, GPIONumber);
EricLew 0:80ee8f3b695e 451 CLEAR_BIT(PWR->PUCRE, GPIONumber);
EricLew 0:80ee8f3b695e 452 break;
EricLew 0:80ee8f3b695e 453 case PWR_GPIO_F:
EricLew 0:80ee8f3b695e 454 SET_BIT(PWR->PDCRF, GPIONumber);
EricLew 0:80ee8f3b695e 455 CLEAR_BIT(PWR->PUCRF, GPIONumber);
EricLew 0:80ee8f3b695e 456 break;
EricLew 0:80ee8f3b695e 457 case PWR_GPIO_G:
EricLew 0:80ee8f3b695e 458 SET_BIT(PWR->PDCRG, GPIONumber);
EricLew 0:80ee8f3b695e 459 CLEAR_BIT(PWR->PUCRG, GPIONumber);
EricLew 0:80ee8f3b695e 460 break;
EricLew 0:80ee8f3b695e 461 case PWR_GPIO_H:
EricLew 0:80ee8f3b695e 462 SET_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
EricLew 0:80ee8f3b695e 463 CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
EricLew 0:80ee8f3b695e 464 break;
EricLew 0:80ee8f3b695e 465 default:
EricLew 0:80ee8f3b695e 466 return HAL_ERROR;
EricLew 0:80ee8f3b695e 467 }
EricLew 0:80ee8f3b695e 468
EricLew 0:80ee8f3b695e 469 return HAL_OK;
EricLew 0:80ee8f3b695e 470 }
EricLew 0:80ee8f3b695e 471
EricLew 0:80ee8f3b695e 472
EricLew 0:80ee8f3b695e 473 /**
EricLew 0:80ee8f3b695e 474 * @brief Disable GPIO pull-down state in Standby and Shutdown modes.
EricLew 0:80ee8f3b695e 475 * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O
EricLew 0:80ee8f3b695e 476 * in pull-down state in Standby and Shutdown modes.
EricLew 0:80ee8f3b695e 477 * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input
EricLew 0:80ee8f3b695e 478 * parameter at the same time are reset.
EricLew 0:80ee8f3b695e 479 * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
EricLew 0:80ee8f3b695e 480 * to select the GPIO peripheral.
EricLew 0:80ee8f3b695e 481 * @param GPIONumber: Specify the I/O pins numbers.
EricLew 0:80ee8f3b695e 482 * This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 483 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less
EricLew 0:80ee8f3b695e 484 * I/O pins are available) or the logical OR of several of them to reset
EricLew 0:80ee8f3b695e 485 * several bits for a given port in a single API call.
EricLew 0:80ee8f3b695e 486 * @retval HAL Status
EricLew 0:80ee8f3b695e 487 */
EricLew 0:80ee8f3b695e 488 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
EricLew 0:80ee8f3b695e 489 {
EricLew 0:80ee8f3b695e 490 assert_param(IS_PWR_GPIO(GPIO));
EricLew 0:80ee8f3b695e 491 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
EricLew 0:80ee8f3b695e 492
EricLew 0:80ee8f3b695e 493 switch (GPIO)
EricLew 0:80ee8f3b695e 494 {
EricLew 0:80ee8f3b695e 495 case PWR_GPIO_A:
EricLew 0:80ee8f3b695e 496 CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
EricLew 0:80ee8f3b695e 497 break;
EricLew 0:80ee8f3b695e 498 case PWR_GPIO_B:
EricLew 0:80ee8f3b695e 499 CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
EricLew 0:80ee8f3b695e 500 break;
EricLew 0:80ee8f3b695e 501 case PWR_GPIO_C:
EricLew 0:80ee8f3b695e 502 CLEAR_BIT(PWR->PDCRC, GPIONumber);
EricLew 0:80ee8f3b695e 503 break;
EricLew 0:80ee8f3b695e 504 case PWR_GPIO_D:
EricLew 0:80ee8f3b695e 505 CLEAR_BIT(PWR->PDCRD, GPIONumber);
EricLew 0:80ee8f3b695e 506 break;
EricLew 0:80ee8f3b695e 507 case PWR_GPIO_E:
EricLew 0:80ee8f3b695e 508 CLEAR_BIT(PWR->PDCRE, GPIONumber);
EricLew 0:80ee8f3b695e 509 break;
EricLew 0:80ee8f3b695e 510 case PWR_GPIO_F:
EricLew 0:80ee8f3b695e 511 CLEAR_BIT(PWR->PDCRF, GPIONumber);
EricLew 0:80ee8f3b695e 512 break;
EricLew 0:80ee8f3b695e 513 case PWR_GPIO_G:
EricLew 0:80ee8f3b695e 514 CLEAR_BIT(PWR->PDCRG, GPIONumber);
EricLew 0:80ee8f3b695e 515 break;
EricLew 0:80ee8f3b695e 516 case PWR_GPIO_H:
EricLew 0:80ee8f3b695e 517 CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
EricLew 0:80ee8f3b695e 518 break;
EricLew 0:80ee8f3b695e 519 default:
EricLew 0:80ee8f3b695e 520 return HAL_ERROR;
EricLew 0:80ee8f3b695e 521 }
EricLew 0:80ee8f3b695e 522
EricLew 0:80ee8f3b695e 523 return HAL_OK;
EricLew 0:80ee8f3b695e 524 }
EricLew 0:80ee8f3b695e 525
EricLew 0:80ee8f3b695e 526
EricLew 0:80ee8f3b695e 527
EricLew 0:80ee8f3b695e 528 /**
EricLew 0:80ee8f3b695e 529 * @brief Enable pull-up and pull-down configuration.
EricLew 0:80ee8f3b695e 530 * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in
EricLew 0:80ee8f3b695e 531 * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes.
EricLew 0:80ee8f3b695e 532 * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding
EricLew 0:80ee8f3b695e 533 * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher).
EricLew 0:80ee8f3b695e 534 * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there
EricLew 0:80ee8f3b695e 535 * is no conflict when setting PUy or PDy bit.
EricLew 0:80ee8f3b695e 536 * @retval None
EricLew 0:80ee8f3b695e 537 */
EricLew 0:80ee8f3b695e 538 void HAL_PWREx_EnablePullUpPullDownConfig(void)
EricLew 0:80ee8f3b695e 539 {
EricLew 0:80ee8f3b695e 540 SET_BIT(PWR->CR3, PWR_CR3_APC);
EricLew 0:80ee8f3b695e 541 }
EricLew 0:80ee8f3b695e 542
EricLew 0:80ee8f3b695e 543
EricLew 0:80ee8f3b695e 544 /**
EricLew 0:80ee8f3b695e 545 * @brief Disable pull-up and pull-down configuration.
EricLew 0:80ee8f3b695e 546 * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in
EricLew 0:80ee8f3b695e 547 * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.
EricLew 0:80ee8f3b695e 548 * @retval None
EricLew 0:80ee8f3b695e 549 */
EricLew 0:80ee8f3b695e 550 void HAL_PWREx_DisablePullUpPullDownConfig(void)
EricLew 0:80ee8f3b695e 551 {
EricLew 0:80ee8f3b695e 552 CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
EricLew 0:80ee8f3b695e 553 }
EricLew 0:80ee8f3b695e 554
EricLew 0:80ee8f3b695e 555
EricLew 0:80ee8f3b695e 556
EricLew 0:80ee8f3b695e 557 /**
EricLew 0:80ee8f3b695e 558 * @brief Enable SRAM2 content retention in Standby mode.
EricLew 0:80ee8f3b695e 559 * @note When RRS bit is set, SRAM2 is powered by the low-power regulator in
EricLew 0:80ee8f3b695e 560 * Standby mode and its content is kept.
EricLew 0:80ee8f3b695e 561 * @retval None
EricLew 0:80ee8f3b695e 562 */
EricLew 0:80ee8f3b695e 563 void HAL_PWREx_EnableSRAM2ContentRetention(void)
EricLew 0:80ee8f3b695e 564 {
EricLew 0:80ee8f3b695e 565 SET_BIT(PWR->CR3, PWR_CR3_RRS);
EricLew 0:80ee8f3b695e 566 }
EricLew 0:80ee8f3b695e 567
EricLew 0:80ee8f3b695e 568
EricLew 0:80ee8f3b695e 569 /**
EricLew 0:80ee8f3b695e 570 * @brief Disable SRAM2 content retention in Standby mode.
EricLew 0:80ee8f3b695e 571 * @note When RRS bit is reset, SRAM2 is powered off in Standby mode
EricLew 0:80ee8f3b695e 572 * and its content is lost.
EricLew 0:80ee8f3b695e 573 * @retval None
EricLew 0:80ee8f3b695e 574 */
EricLew 0:80ee8f3b695e 575 void HAL_PWREx_DisableSRAM2ContentRetention(void)
EricLew 0:80ee8f3b695e 576 {
EricLew 0:80ee8f3b695e 577 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
EricLew 0:80ee8f3b695e 578 }
EricLew 0:80ee8f3b695e 579
EricLew 0:80ee8f3b695e 580
EricLew 0:80ee8f3b695e 581
EricLew 0:80ee8f3b695e 582
EricLew 0:80ee8f3b695e 583 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
EricLew 0:80ee8f3b695e 584 /**
EricLew 0:80ee8f3b695e 585 * @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
EricLew 0:80ee8f3b695e 586 * @retval None
EricLew 0:80ee8f3b695e 587 */
EricLew 0:80ee8f3b695e 588 void HAL_PWREx_EnablePVM1(void)
EricLew 0:80ee8f3b695e 589 {
EricLew 0:80ee8f3b695e 590 SET_BIT(PWR->CR2, PWR_PVM_1);
EricLew 0:80ee8f3b695e 591 }
EricLew 0:80ee8f3b695e 592
EricLew 0:80ee8f3b695e 593 /**
EricLew 0:80ee8f3b695e 594 * @brief Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
EricLew 0:80ee8f3b695e 595 * @retval None
EricLew 0:80ee8f3b695e 596 */
EricLew 0:80ee8f3b695e 597 void HAL_PWREx_DisablePVM1(void)
EricLew 0:80ee8f3b695e 598 {
EricLew 0:80ee8f3b695e 599 CLEAR_BIT(PWR->CR2, PWR_PVM_1);
EricLew 0:80ee8f3b695e 600 }
EricLew 0:80ee8f3b695e 601 #endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
EricLew 0:80ee8f3b695e 602
EricLew 0:80ee8f3b695e 603 /**
EricLew 0:80ee8f3b695e 604 * @brief Enable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
EricLew 0:80ee8f3b695e 605 * @retval None
EricLew 0:80ee8f3b695e 606 */
EricLew 0:80ee8f3b695e 607 void HAL_PWREx_EnablePVM2(void)
EricLew 0:80ee8f3b695e 608 {
EricLew 0:80ee8f3b695e 609 SET_BIT(PWR->CR2, PWR_PVM_2);
EricLew 0:80ee8f3b695e 610 }
EricLew 0:80ee8f3b695e 611
EricLew 0:80ee8f3b695e 612 /**
EricLew 0:80ee8f3b695e 613 * @brief Disable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
EricLew 0:80ee8f3b695e 614 * @retval None
EricLew 0:80ee8f3b695e 615 */
EricLew 0:80ee8f3b695e 616 void HAL_PWREx_DisablePVM2(void)
EricLew 0:80ee8f3b695e 617 {
EricLew 0:80ee8f3b695e 618 CLEAR_BIT(PWR->CR2, PWR_PVM_2);
EricLew 0:80ee8f3b695e 619 }
EricLew 0:80ee8f3b695e 620
EricLew 0:80ee8f3b695e 621
EricLew 0:80ee8f3b695e 622 /**
EricLew 0:80ee8f3b695e 623 * @brief Enable the Power Voltage Monitoring 3: VDDA versus 1.62V.
EricLew 0:80ee8f3b695e 624 * @retval None
EricLew 0:80ee8f3b695e 625 */
EricLew 0:80ee8f3b695e 626 void HAL_PWREx_EnablePVM3(void)
EricLew 0:80ee8f3b695e 627 {
EricLew 0:80ee8f3b695e 628 SET_BIT(PWR->CR2, PWR_PVM_3);
EricLew 0:80ee8f3b695e 629 }
EricLew 0:80ee8f3b695e 630
EricLew 0:80ee8f3b695e 631 /**
EricLew 0:80ee8f3b695e 632 * @brief Disable the Power Voltage Monitoring 3: VDDA versus 1.62V.
EricLew 0:80ee8f3b695e 633 * @retval None
EricLew 0:80ee8f3b695e 634 */
EricLew 0:80ee8f3b695e 635 void HAL_PWREx_DisablePVM3(void)
EricLew 0:80ee8f3b695e 636 {
EricLew 0:80ee8f3b695e 637 CLEAR_BIT(PWR->CR2, PWR_PVM_3);
EricLew 0:80ee8f3b695e 638 }
EricLew 0:80ee8f3b695e 639
EricLew 0:80ee8f3b695e 640
EricLew 0:80ee8f3b695e 641 /**
EricLew 0:80ee8f3b695e 642 * @brief Enable the Power Voltage Monitoring 4: VDDA versus 2.2V.
EricLew 0:80ee8f3b695e 643 * @retval None
EricLew 0:80ee8f3b695e 644 */
EricLew 0:80ee8f3b695e 645 void HAL_PWREx_EnablePVM4(void)
EricLew 0:80ee8f3b695e 646 {
EricLew 0:80ee8f3b695e 647 SET_BIT(PWR->CR2, PWR_PVM_4);
EricLew 0:80ee8f3b695e 648 }
EricLew 0:80ee8f3b695e 649
EricLew 0:80ee8f3b695e 650 /**
EricLew 0:80ee8f3b695e 651 * @brief Disable the Power Voltage Monitoring 4: VDDA versus 2.2V.
EricLew 0:80ee8f3b695e 652 * @retval None
EricLew 0:80ee8f3b695e 653 */
EricLew 0:80ee8f3b695e 654 void HAL_PWREx_DisablePVM4(void)
EricLew 0:80ee8f3b695e 655 {
EricLew 0:80ee8f3b695e 656 CLEAR_BIT(PWR->CR2, PWR_PVM_4);
EricLew 0:80ee8f3b695e 657 }
EricLew 0:80ee8f3b695e 658
EricLew 0:80ee8f3b695e 659
EricLew 0:80ee8f3b695e 660
EricLew 0:80ee8f3b695e 661
EricLew 0:80ee8f3b695e 662 /**
EricLew 0:80ee8f3b695e 663 * @brief Configure the Peripheral Voltage Monitoring (PVM).
EricLew 0:80ee8f3b695e 664 * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the
EricLew 0:80ee8f3b695e 665 * PVM configuration information.
EricLew 0:80ee8f3b695e 666 * @note The API configures a single PVM according to the information contained
EricLew 0:80ee8f3b695e 667 * in the input structure. To configure several PVMs, the API must be singly
EricLew 0:80ee8f3b695e 668 * called for each PVM used.
EricLew 0:80ee8f3b695e 669 * @note Refer to the electrical characteristics of your device datasheet for
EricLew 0:80ee8f3b695e 670 * more details about the voltage thresholds corresponding to each
EricLew 0:80ee8f3b695e 671 * detection level and to each monitored supply.
EricLew 0:80ee8f3b695e 672 * @retval HAL status
EricLew 0:80ee8f3b695e 673 */
EricLew 0:80ee8f3b695e 674 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
EricLew 0:80ee8f3b695e 675 {
EricLew 0:80ee8f3b695e 676 /* Check the parameters */
EricLew 0:80ee8f3b695e 677 assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType));
EricLew 0:80ee8f3b695e 678 assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode));
EricLew 0:80ee8f3b695e 679
EricLew 0:80ee8f3b695e 680
EricLew 0:80ee8f3b695e 681 /* Configure EXTI 35 to 38 interrupts if so required:
EricLew 0:80ee8f3b695e 682 scan thru PVMType to detect which PVMx is set and
EricLew 0:80ee8f3b695e 683 configure the corresponding EXTI line accordingly. */
EricLew 0:80ee8f3b695e 684 switch (sConfigPVM->PVMType)
EricLew 0:80ee8f3b695e 685 {
EricLew 0:80ee8f3b695e 686 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
EricLew 0:80ee8f3b695e 687 case PWR_PVM_1:
EricLew 0:80ee8f3b695e 688 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
EricLew 0:80ee8f3b695e 689 __HAL_PWR_PVM1_EXTI_DISABLE_EVENT();
EricLew 0:80ee8f3b695e 690 __HAL_PWR_PVM1_EXTI_DISABLE_IT();
EricLew 0:80ee8f3b695e 691 __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();
EricLew 0:80ee8f3b695e 692 __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();
EricLew 0:80ee8f3b695e 693
EricLew 0:80ee8f3b695e 694 /* Configure interrupt mode */
EricLew 0:80ee8f3b695e 695 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
EricLew 0:80ee8f3b695e 696 {
EricLew 0:80ee8f3b695e 697 __HAL_PWR_PVM1_EXTI_ENABLE_IT();
EricLew 0:80ee8f3b695e 698 }
EricLew 0:80ee8f3b695e 699
EricLew 0:80ee8f3b695e 700 /* Configure event mode */
EricLew 0:80ee8f3b695e 701 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
EricLew 0:80ee8f3b695e 702 {
EricLew 0:80ee8f3b695e 703 __HAL_PWR_PVM1_EXTI_ENABLE_EVENT();
EricLew 0:80ee8f3b695e 704 }
EricLew 0:80ee8f3b695e 705
EricLew 0:80ee8f3b695e 706 /* Configure the edge */
EricLew 0:80ee8f3b695e 707 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
EricLew 0:80ee8f3b695e 708 {
EricLew 0:80ee8f3b695e 709 __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();
EricLew 0:80ee8f3b695e 710 }
EricLew 0:80ee8f3b695e 711
EricLew 0:80ee8f3b695e 712 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
EricLew 0:80ee8f3b695e 713 {
EricLew 0:80ee8f3b695e 714 __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();
EricLew 0:80ee8f3b695e 715 }
EricLew 0:80ee8f3b695e 716 break;
EricLew 0:80ee8f3b695e 717 #endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
EricLew 0:80ee8f3b695e 718
EricLew 0:80ee8f3b695e 719 case PWR_PVM_2:
EricLew 0:80ee8f3b695e 720 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
EricLew 0:80ee8f3b695e 721 __HAL_PWR_PVM2_EXTI_DISABLE_EVENT();
EricLew 0:80ee8f3b695e 722 __HAL_PWR_PVM2_EXTI_DISABLE_IT();
EricLew 0:80ee8f3b695e 723 __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();
EricLew 0:80ee8f3b695e 724 __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();
EricLew 0:80ee8f3b695e 725
EricLew 0:80ee8f3b695e 726 /* Configure interrupt mode */
EricLew 0:80ee8f3b695e 727 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
EricLew 0:80ee8f3b695e 728 {
EricLew 0:80ee8f3b695e 729 __HAL_PWR_PVM2_EXTI_ENABLE_IT();
EricLew 0:80ee8f3b695e 730 }
EricLew 0:80ee8f3b695e 731
EricLew 0:80ee8f3b695e 732 /* Configure event mode */
EricLew 0:80ee8f3b695e 733 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
EricLew 0:80ee8f3b695e 734 {
EricLew 0:80ee8f3b695e 735 __HAL_PWR_PVM2_EXTI_ENABLE_EVENT();
EricLew 0:80ee8f3b695e 736 }
EricLew 0:80ee8f3b695e 737
EricLew 0:80ee8f3b695e 738 /* Configure the edge */
EricLew 0:80ee8f3b695e 739 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
EricLew 0:80ee8f3b695e 740 {
EricLew 0:80ee8f3b695e 741 __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();
EricLew 0:80ee8f3b695e 742 }
EricLew 0:80ee8f3b695e 743
EricLew 0:80ee8f3b695e 744 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
EricLew 0:80ee8f3b695e 745 {
EricLew 0:80ee8f3b695e 746 __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();
EricLew 0:80ee8f3b695e 747 }
EricLew 0:80ee8f3b695e 748 break;
EricLew 0:80ee8f3b695e 749
EricLew 0:80ee8f3b695e 750 case PWR_PVM_3:
EricLew 0:80ee8f3b695e 751 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
EricLew 0:80ee8f3b695e 752 __HAL_PWR_PVM3_EXTI_DISABLE_EVENT();
EricLew 0:80ee8f3b695e 753 __HAL_PWR_PVM3_EXTI_DISABLE_IT();
EricLew 0:80ee8f3b695e 754 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();
EricLew 0:80ee8f3b695e 755 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();
EricLew 0:80ee8f3b695e 756
EricLew 0:80ee8f3b695e 757 /* Configure interrupt mode */
EricLew 0:80ee8f3b695e 758 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
EricLew 0:80ee8f3b695e 759 {
EricLew 0:80ee8f3b695e 760 __HAL_PWR_PVM3_EXTI_ENABLE_IT();
EricLew 0:80ee8f3b695e 761 }
EricLew 0:80ee8f3b695e 762
EricLew 0:80ee8f3b695e 763 /* Configure event mode */
EricLew 0:80ee8f3b695e 764 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
EricLew 0:80ee8f3b695e 765 {
EricLew 0:80ee8f3b695e 766 __HAL_PWR_PVM3_EXTI_ENABLE_EVENT();
EricLew 0:80ee8f3b695e 767 }
EricLew 0:80ee8f3b695e 768
EricLew 0:80ee8f3b695e 769 /* Configure the edge */
EricLew 0:80ee8f3b695e 770 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
EricLew 0:80ee8f3b695e 771 {
EricLew 0:80ee8f3b695e 772 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();
EricLew 0:80ee8f3b695e 773 }
EricLew 0:80ee8f3b695e 774
EricLew 0:80ee8f3b695e 775 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
EricLew 0:80ee8f3b695e 776 {
EricLew 0:80ee8f3b695e 777 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();
EricLew 0:80ee8f3b695e 778 }
EricLew 0:80ee8f3b695e 779 break;
EricLew 0:80ee8f3b695e 780
EricLew 0:80ee8f3b695e 781 case PWR_PVM_4:
EricLew 0:80ee8f3b695e 782 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
EricLew 0:80ee8f3b695e 783 __HAL_PWR_PVM4_EXTI_DISABLE_EVENT();
EricLew 0:80ee8f3b695e 784 __HAL_PWR_PVM4_EXTI_DISABLE_IT();
EricLew 0:80ee8f3b695e 785 __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();
EricLew 0:80ee8f3b695e 786 __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();
EricLew 0:80ee8f3b695e 787
EricLew 0:80ee8f3b695e 788 /* Configure interrupt mode */
EricLew 0:80ee8f3b695e 789 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
EricLew 0:80ee8f3b695e 790 {
EricLew 0:80ee8f3b695e 791 __HAL_PWR_PVM4_EXTI_ENABLE_IT();
EricLew 0:80ee8f3b695e 792 }
EricLew 0:80ee8f3b695e 793
EricLew 0:80ee8f3b695e 794 /* Configure event mode */
EricLew 0:80ee8f3b695e 795 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
EricLew 0:80ee8f3b695e 796 {
EricLew 0:80ee8f3b695e 797 __HAL_PWR_PVM4_EXTI_ENABLE_EVENT();
EricLew 0:80ee8f3b695e 798 }
EricLew 0:80ee8f3b695e 799
EricLew 0:80ee8f3b695e 800 /* Configure the edge */
EricLew 0:80ee8f3b695e 801 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
EricLew 0:80ee8f3b695e 802 {
EricLew 0:80ee8f3b695e 803 __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();
EricLew 0:80ee8f3b695e 804 }
EricLew 0:80ee8f3b695e 805
EricLew 0:80ee8f3b695e 806 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
EricLew 0:80ee8f3b695e 807 {
EricLew 0:80ee8f3b695e 808 __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();
EricLew 0:80ee8f3b695e 809 }
EricLew 0:80ee8f3b695e 810 break;
EricLew 0:80ee8f3b695e 811
EricLew 0:80ee8f3b695e 812 default:
EricLew 0:80ee8f3b695e 813 return HAL_ERROR;
EricLew 0:80ee8f3b695e 814
EricLew 0:80ee8f3b695e 815 }
EricLew 0:80ee8f3b695e 816
EricLew 0:80ee8f3b695e 817
EricLew 0:80ee8f3b695e 818 return HAL_OK;
EricLew 0:80ee8f3b695e 819 }
EricLew 0:80ee8f3b695e 820
EricLew 0:80ee8f3b695e 821
EricLew 0:80ee8f3b695e 822
EricLew 0:80ee8f3b695e 823 /**
EricLew 0:80ee8f3b695e 824 * @brief Enter Low-power Run mode
EricLew 0:80ee8f3b695e 825 * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode.
EricLew 0:80ee8f3b695e 826 * @note When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
EricLew 0:80ee8f3b695e 827 * Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register.
EricLew 0:80ee8f3b695e 828 * Additionally, the clock frequency must be reduced below 2 MHz.
EricLew 0:80ee8f3b695e 829 * Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must
EricLew 0:80ee8f3b695e 830 * be done before calling HAL_PWREx_EnableLowPowerRunMode() API.
EricLew 0:80ee8f3b695e 831 * @retval None
EricLew 0:80ee8f3b695e 832 */
EricLew 0:80ee8f3b695e 833 void HAL_PWREx_EnableLowPowerRunMode(void)
EricLew 0:80ee8f3b695e 834 {
EricLew 0:80ee8f3b695e 835 /* Set Regulator parameter */
EricLew 0:80ee8f3b695e 836 SET_BIT(PWR->CR1, PWR_CR1_LPR);
EricLew 0:80ee8f3b695e 837 }
EricLew 0:80ee8f3b695e 838
EricLew 0:80ee8f3b695e 839
EricLew 0:80ee8f3b695e 840 /**
EricLew 0:80ee8f3b695e 841 * @brief Exit Low-power Run mode.
EricLew 0:80ee8f3b695e 842 * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that
EricLew 0:80ee8f3b695e 843 * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode
EricLew 0:80ee8f3b695e 844 * returns HAL_TIMEOUT status). The system clock frequency can then be
EricLew 0:80ee8f3b695e 845 * increased above 2 MHz.
EricLew 0:80ee8f3b695e 846 * @retval HAL Status
EricLew 0:80ee8f3b695e 847 */
EricLew 0:80ee8f3b695e 848 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
EricLew 0:80ee8f3b695e 849 {
EricLew 0:80ee8f3b695e 850 uint32_t wait_loop_index = 0;
EricLew 0:80ee8f3b695e 851
EricLew 0:80ee8f3b695e 852 /* Clear LPR bit */
EricLew 0:80ee8f3b695e 853 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
EricLew 0:80ee8f3b695e 854
EricLew 0:80ee8f3b695e 855 /* Wait until REGLPF is reset */
EricLew 0:80ee8f3b695e 856 wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000));
EricLew 0:80ee8f3b695e 857 while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)))
EricLew 0:80ee8f3b695e 858 {
EricLew 0:80ee8f3b695e 859 wait_loop_index--;
EricLew 0:80ee8f3b695e 860 }
EricLew 0:80ee8f3b695e 861 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
EricLew 0:80ee8f3b695e 862 {
EricLew 0:80ee8f3b695e 863 return HAL_TIMEOUT;
EricLew 0:80ee8f3b695e 864 }
EricLew 0:80ee8f3b695e 865
EricLew 0:80ee8f3b695e 866 return HAL_OK;
EricLew 0:80ee8f3b695e 867 }
EricLew 0:80ee8f3b695e 868
EricLew 0:80ee8f3b695e 869
EricLew 0:80ee8f3b695e 870 /**
EricLew 0:80ee8f3b695e 871 * @brief Enter Stop 1 mode.
EricLew 0:80ee8f3b695e 872 * @note In Stop 1 mode, all I/O pins keep the same state as in Run mode.
EricLew 0:80ee8f3b695e 873 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
EricLew 0:80ee8f3b695e 874 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
EricLew 0:80ee8f3b695e 875 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
EricLew 0:80ee8f3b695e 876 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
EricLew 0:80ee8f3b695e 877 * only to the peripheral requesting it.
EricLew 0:80ee8f3b695e 878 * SRAM1, SRAM2 and register contents are preserved.
EricLew 0:80ee8f3b695e 879 * The BOR is available.
EricLew 0:80ee8f3b695e 880 * The voltage regulator can be configured either in normal or low-power mode.
EricLew 0:80ee8f3b695e 881 * @note When exiting Stop 1 mode by issuing an interrupt or a wakeup event,
EricLew 0:80ee8f3b695e 882 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
EricLew 0:80ee8f3b695e 883 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
EricLew 0:80ee8f3b695e 884 * @note When the voltage regulator operates in low power mode, an additional
EricLew 0:80ee8f3b695e 885 * startup delay is incurred when waking up from Stop 1 mode.
EricLew 0:80ee8f3b695e 886 * By keeping the internal regulator ON during Stop 1 mode, the consumption
EricLew 0:80ee8f3b695e 887 * is higher although the startup time is reduced.
EricLew 0:80ee8f3b695e 888 * @param Regulator: Specifies the regulator state in Stop 1 mode.
EricLew 0:80ee8f3b695e 889 * This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 890 * @arg PWR_MAINREGULATOR_ON: Stop 1 mode with regulator ON
EricLew 0:80ee8f3b695e 891 * @arg PWR_LOWPOWERREGULATOR_ON: Stop 1 mode with low power regulator ON
EricLew 0:80ee8f3b695e 892 * This parameter has no effect when entering stop mode 2.
EricLew 0:80ee8f3b695e 893 * @param STOPEntry: specifies if Stop mode in entered with WFI or WFE instruction.
EricLew 0:80ee8f3b695e 894 * This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 895 * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
EricLew 0:80ee8f3b695e 896 * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
EricLew 0:80ee8f3b695e 897 * @retval None
EricLew 0:80ee8f3b695e 898 */
EricLew 0:80ee8f3b695e 899 void HAL_PWREx_EnterSTOP1Mode(uint32_t Regulator, uint8_t STOPEntry)
EricLew 0:80ee8f3b695e 900 {
EricLew 0:80ee8f3b695e 901 /* Check the parameters */
EricLew 0:80ee8f3b695e 902 assert_param(IS_PWR_REGULATOR(Regulator));
EricLew 0:80ee8f3b695e 903 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
EricLew 0:80ee8f3b695e 904
EricLew 0:80ee8f3b695e 905 if (Regulator == PWR_MAINREGULATOR_ON)
EricLew 0:80ee8f3b695e 906 {
EricLew 0:80ee8f3b695e 907 /* Stop 1 mode with Main Regulator */
EricLew 0:80ee8f3b695e 908 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1MR);
EricLew 0:80ee8f3b695e 909 }
EricLew 0:80ee8f3b695e 910 else
EricLew 0:80ee8f3b695e 911 {
EricLew 0:80ee8f3b695e 912 /* Stop 1 mode with Low-Power Regulator */
EricLew 0:80ee8f3b695e 913 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1LPR);
EricLew 0:80ee8f3b695e 914 }
EricLew 0:80ee8f3b695e 915
EricLew 0:80ee8f3b695e 916 /* Set SLEEPDEEP bit of Cortex System Control Register */
EricLew 0:80ee8f3b695e 917 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
EricLew 0:80ee8f3b695e 918
EricLew 0:80ee8f3b695e 919 /* Select Stop mode entry --------------------------------------------------*/
EricLew 0:80ee8f3b695e 920 if(STOPEntry == PWR_STOPENTRY_WFI)
EricLew 0:80ee8f3b695e 921 {
EricLew 0:80ee8f3b695e 922 /* Request Wait For Interrupt */
EricLew 0:80ee8f3b695e 923 __WFI();
EricLew 0:80ee8f3b695e 924 }
EricLew 0:80ee8f3b695e 925 else
EricLew 0:80ee8f3b695e 926 {
EricLew 0:80ee8f3b695e 927 /* Request Wait For Event */
EricLew 0:80ee8f3b695e 928 __SEV();
EricLew 0:80ee8f3b695e 929 __WFE();
EricLew 0:80ee8f3b695e 930 __WFE();
EricLew 0:80ee8f3b695e 931 }
EricLew 0:80ee8f3b695e 932
EricLew 0:80ee8f3b695e 933 /* Reset SLEEPDEEP bit of Cortex System Control Register */
EricLew 0:80ee8f3b695e 934 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
EricLew 0:80ee8f3b695e 935 }
EricLew 0:80ee8f3b695e 936
EricLew 0:80ee8f3b695e 937
EricLew 0:80ee8f3b695e 938 /**
EricLew 0:80ee8f3b695e 939 * @brief Enter Stop 2 mode.
EricLew 0:80ee8f3b695e 940 * @note In Stop 2 mode, all I/O pins keep the same state as in Run mode.
EricLew 0:80ee8f3b695e 941 * @note All clocks in the VCORE domain are stopped, the PLL, the MSI,
EricLew 0:80ee8f3b695e 942 * the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability
EricLew 0:80ee8f3b695e 943 * (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after
EricLew 0:80ee8f3b695e 944 * receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only
EricLew 0:80ee8f3b695e 945 * to the peripheral requesting it.
EricLew 0:80ee8f3b695e 946 * SRAM1, SRAM2 and register contents are preserved.
EricLew 0:80ee8f3b695e 947 * The BOR is available.
EricLew 0:80ee8f3b695e 948 * The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode.
EricLew 0:80ee8f3b695e 949 * Otherwise, Stop 1 mode is entered.
EricLew 0:80ee8f3b695e 950 * @note When exiting Stop 2 mode by issuing an interrupt or a wakeup event,
EricLew 0:80ee8f3b695e 951 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
EricLew 0:80ee8f3b695e 952 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
EricLew 0:80ee8f3b695e 953 * @param STOPEntry: specifies if Stop mode in entered with WFI or WFE instruction.
EricLew 0:80ee8f3b695e 954 * This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 955 * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
EricLew 0:80ee8f3b695e 956 * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
EricLew 0:80ee8f3b695e 957 * @retval None
EricLew 0:80ee8f3b695e 958 */
EricLew 0:80ee8f3b695e 959 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)
EricLew 0:80ee8f3b695e 960 {
EricLew 0:80ee8f3b695e 961 /* Check the parameter */
EricLew 0:80ee8f3b695e 962 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
EricLew 0:80ee8f3b695e 963
EricLew 0:80ee8f3b695e 964 /* Set Stop mode 2 */
EricLew 0:80ee8f3b695e 965 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP2);
EricLew 0:80ee8f3b695e 966
EricLew 0:80ee8f3b695e 967
EricLew 0:80ee8f3b695e 968 /* Set SLEEPDEEP bit of Cortex System Control Register */
EricLew 0:80ee8f3b695e 969 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
EricLew 0:80ee8f3b695e 970
EricLew 0:80ee8f3b695e 971 /* Select Stop mode entry --------------------------------------------------*/
EricLew 0:80ee8f3b695e 972 if(STOPEntry == PWR_STOPENTRY_WFI)
EricLew 0:80ee8f3b695e 973 {
EricLew 0:80ee8f3b695e 974 /* Request Wait For Interrupt */
EricLew 0:80ee8f3b695e 975 __WFI();
EricLew 0:80ee8f3b695e 976 }
EricLew 0:80ee8f3b695e 977 else
EricLew 0:80ee8f3b695e 978 {
EricLew 0:80ee8f3b695e 979 /* Request Wait For Event */
EricLew 0:80ee8f3b695e 980 __SEV();
EricLew 0:80ee8f3b695e 981 __WFE();
EricLew 0:80ee8f3b695e 982 __WFE();
EricLew 0:80ee8f3b695e 983 }
EricLew 0:80ee8f3b695e 984
EricLew 0:80ee8f3b695e 985 /* Reset SLEEPDEEP bit of Cortex System Control Register */
EricLew 0:80ee8f3b695e 986 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
EricLew 0:80ee8f3b695e 987 }
EricLew 0:80ee8f3b695e 988
EricLew 0:80ee8f3b695e 989
EricLew 0:80ee8f3b695e 990
EricLew 0:80ee8f3b695e 991
EricLew 0:80ee8f3b695e 992
EricLew 0:80ee8f3b695e 993 /**
EricLew 0:80ee8f3b695e 994 * @brief Enter Shutdown mode.
EricLew 0:80ee8f3b695e 995 * @note In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched
EricLew 0:80ee8f3b695e 996 * off. The voltage regulator is disabled and Vcore domain is powered off.
EricLew 0:80ee8f3b695e 997 * SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain.
EricLew 0:80ee8f3b695e 998 * The BOR is not available.
EricLew 0:80ee8f3b695e 999 * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
EricLew 0:80ee8f3b695e 1000 * @retval None
EricLew 0:80ee8f3b695e 1001 */
EricLew 0:80ee8f3b695e 1002 void HAL_PWREx_EnterSHUTDOWNMode(void)
EricLew 0:80ee8f3b695e 1003 {
EricLew 0:80ee8f3b695e 1004
EricLew 0:80ee8f3b695e 1005 /* Set Shutdown mode */
EricLew 0:80ee8f3b695e 1006 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN);
EricLew 0:80ee8f3b695e 1007
EricLew 0:80ee8f3b695e 1008 /* Set SLEEPDEEP bit of Cortex System Control Register */
EricLew 0:80ee8f3b695e 1009 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
EricLew 0:80ee8f3b695e 1010
EricLew 0:80ee8f3b695e 1011 /* This option is used to ensure that store operations are completed */
EricLew 0:80ee8f3b695e 1012 #if defined ( __CC_ARM)
EricLew 0:80ee8f3b695e 1013 __force_stores();
EricLew 0:80ee8f3b695e 1014 #endif
EricLew 0:80ee8f3b695e 1015 /* Request Wait For Interrupt */
EricLew 0:80ee8f3b695e 1016 __WFI();
EricLew 0:80ee8f3b695e 1017 }
EricLew 0:80ee8f3b695e 1018
EricLew 0:80ee8f3b695e 1019
EricLew 0:80ee8f3b695e 1020
EricLew 0:80ee8f3b695e 1021
EricLew 0:80ee8f3b695e 1022 /**
EricLew 0:80ee8f3b695e 1023 * @brief This function handles the PWR PVD/PVMx interrupt request.
EricLew 0:80ee8f3b695e 1024 * @note This API should be called under the PVD_PVM_IRQHandler().
EricLew 0:80ee8f3b695e 1025 * @retval None
EricLew 0:80ee8f3b695e 1026 */
EricLew 0:80ee8f3b695e 1027 void HAL_PWREx_PVD_PVM_IRQHandler(void)
EricLew 0:80ee8f3b695e 1028 {
EricLew 0:80ee8f3b695e 1029 /* Check PWR exti flag */
EricLew 0:80ee8f3b695e 1030 if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
EricLew 0:80ee8f3b695e 1031 {
EricLew 0:80ee8f3b695e 1032 /* PWR PVD interrupt user callback */
EricLew 0:80ee8f3b695e 1033 HAL_PWR_PVDCallback();
EricLew 0:80ee8f3b695e 1034
EricLew 0:80ee8f3b695e 1035 /* Clear PVD exti pending bit */
EricLew 0:80ee8f3b695e 1036 __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
EricLew 0:80ee8f3b695e 1037 }
EricLew 0:80ee8f3b695e 1038 /* Next, successively check PVMx exti flags */
EricLew 0:80ee8f3b695e 1039 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
EricLew 0:80ee8f3b695e 1040 if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != RESET)
EricLew 0:80ee8f3b695e 1041 {
EricLew 0:80ee8f3b695e 1042 /* PWR PVM1 interrupt user callback */
EricLew 0:80ee8f3b695e 1043 HAL_PWREx_PVM1Callback();
EricLew 0:80ee8f3b695e 1044
EricLew 0:80ee8f3b695e 1045 /* Clear PVM1 exti pending bit */
EricLew 0:80ee8f3b695e 1046 __HAL_PWR_PVM1_EXTI_CLEAR_FLAG();
EricLew 0:80ee8f3b695e 1047 }
EricLew 0:80ee8f3b695e 1048 #endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
EricLew 0:80ee8f3b695e 1049 if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != RESET)
EricLew 0:80ee8f3b695e 1050 {
EricLew 0:80ee8f3b695e 1051 /* PWR PVM2 interrupt user callback */
EricLew 0:80ee8f3b695e 1052 HAL_PWREx_PVM2Callback();
EricLew 0:80ee8f3b695e 1053
EricLew 0:80ee8f3b695e 1054 /* Clear PVM2 exti pending bit */
EricLew 0:80ee8f3b695e 1055 __HAL_PWR_PVM2_EXTI_CLEAR_FLAG();
EricLew 0:80ee8f3b695e 1056 }
EricLew 0:80ee8f3b695e 1057 if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != RESET)
EricLew 0:80ee8f3b695e 1058 {
EricLew 0:80ee8f3b695e 1059 /* PWR PVM3 interrupt user callback */
EricLew 0:80ee8f3b695e 1060 HAL_PWREx_PVM3Callback();
EricLew 0:80ee8f3b695e 1061
EricLew 0:80ee8f3b695e 1062 /* Clear PVM3 exti pending bit */
EricLew 0:80ee8f3b695e 1063 __HAL_PWR_PVM3_EXTI_CLEAR_FLAG();
EricLew 0:80ee8f3b695e 1064 }
EricLew 0:80ee8f3b695e 1065 if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != RESET)
EricLew 0:80ee8f3b695e 1066 {
EricLew 0:80ee8f3b695e 1067 /* PWR PVM4 interrupt user callback */
EricLew 0:80ee8f3b695e 1068 HAL_PWREx_PVM4Callback();
EricLew 0:80ee8f3b695e 1069
EricLew 0:80ee8f3b695e 1070 /* Clear PVM4 exti pending bit */
EricLew 0:80ee8f3b695e 1071 __HAL_PWR_PVM4_EXTI_CLEAR_FLAG();
EricLew 0:80ee8f3b695e 1072 }
EricLew 0:80ee8f3b695e 1073 }
EricLew 0:80ee8f3b695e 1074
EricLew 0:80ee8f3b695e 1075
EricLew 0:80ee8f3b695e 1076 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
EricLew 0:80ee8f3b695e 1077 /**
EricLew 0:80ee8f3b695e 1078 * @brief PWR PVM1 interrupt callback
EricLew 0:80ee8f3b695e 1079 * @retval None
EricLew 0:80ee8f3b695e 1080 */
EricLew 0:80ee8f3b695e 1081 __weak void HAL_PWREx_PVM1Callback(void)
EricLew 0:80ee8f3b695e 1082 {
EricLew 0:80ee8f3b695e 1083 /* NOTE : This function should not be modified; when the callback is needed,
EricLew 0:80ee8f3b695e 1084 HAL_PWREx_PVM1Callback() API can be implemented in the user file
EricLew 0:80ee8f3b695e 1085 */
EricLew 0:80ee8f3b695e 1086 }
EricLew 0:80ee8f3b695e 1087 #endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
EricLew 0:80ee8f3b695e 1088
EricLew 0:80ee8f3b695e 1089 /**
EricLew 0:80ee8f3b695e 1090 * @brief PWR PVM2 interrupt callback
EricLew 0:80ee8f3b695e 1091 * @retval None
EricLew 0:80ee8f3b695e 1092 */
EricLew 0:80ee8f3b695e 1093 __weak void HAL_PWREx_PVM2Callback(void)
EricLew 0:80ee8f3b695e 1094 {
EricLew 0:80ee8f3b695e 1095 /* NOTE : This function should not be modified; when the callback is needed,
EricLew 0:80ee8f3b695e 1096 HAL_PWREx_PVM2Callback() API can be implemented in the user file
EricLew 0:80ee8f3b695e 1097 */
EricLew 0:80ee8f3b695e 1098 }
EricLew 0:80ee8f3b695e 1099
EricLew 0:80ee8f3b695e 1100 /**
EricLew 0:80ee8f3b695e 1101 * @brief PWR PVM3 interrupt callback
EricLew 0:80ee8f3b695e 1102 * @retval None
EricLew 0:80ee8f3b695e 1103 */
EricLew 0:80ee8f3b695e 1104 __weak void HAL_PWREx_PVM3Callback(void)
EricLew 0:80ee8f3b695e 1105 {
EricLew 0:80ee8f3b695e 1106 /* NOTE : This function should not be modified; when the callback is needed,
EricLew 0:80ee8f3b695e 1107 HAL_PWREx_PVM3Callback() API can be implemented in the user file
EricLew 0:80ee8f3b695e 1108 */
EricLew 0:80ee8f3b695e 1109 }
EricLew 0:80ee8f3b695e 1110
EricLew 0:80ee8f3b695e 1111 /**
EricLew 0:80ee8f3b695e 1112 * @brief PWR PVM4 interrupt callback
EricLew 0:80ee8f3b695e 1113 * @retval None
EricLew 0:80ee8f3b695e 1114 */
EricLew 0:80ee8f3b695e 1115 __weak void HAL_PWREx_PVM4Callback(void)
EricLew 0:80ee8f3b695e 1116 {
EricLew 0:80ee8f3b695e 1117 /* NOTE : This function should not be modified; when the callback is needed,
EricLew 0:80ee8f3b695e 1118 HAL_PWREx_PVM4Callback() API can be implemented in the user file
EricLew 0:80ee8f3b695e 1119 */
EricLew 0:80ee8f3b695e 1120 }
EricLew 0:80ee8f3b695e 1121
EricLew 0:80ee8f3b695e 1122
EricLew 0:80ee8f3b695e 1123 /**
EricLew 0:80ee8f3b695e 1124 * @}
EricLew 0:80ee8f3b695e 1125 */
EricLew 0:80ee8f3b695e 1126
EricLew 0:80ee8f3b695e 1127 /**
EricLew 0:80ee8f3b695e 1128 * @}
EricLew 0:80ee8f3b695e 1129 */
EricLew 0:80ee8f3b695e 1130
EricLew 0:80ee8f3b695e 1131 #endif /* HAL_PWR_MODULE_ENABLED */
EricLew 0:80ee8f3b695e 1132 /**
EricLew 0:80ee8f3b695e 1133 * @}
EricLew 0:80ee8f3b695e 1134 */
EricLew 0:80ee8f3b695e 1135
EricLew 0:80ee8f3b695e 1136 /**
EricLew 0:80ee8f3b695e 1137 * @}
EricLew 0:80ee8f3b695e 1138 */
EricLew 0:80ee8f3b695e 1139
EricLew 0:80ee8f3b695e 1140 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
EricLew 0:80ee8f3b695e 1141