Enda Kilgarriff / AD5592R

Initial Commit

ad5592r-base.h@1:2ad195e1455b, 2020-06-15 (annotated)

Committer:
EndaKilgarriff
Date:
Mon Jun 15 13:58:03 2020 +0000
Revision:
1:2ad195e1455b
AD5592R Initial Commit

Who changed what in which revision?

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EndaKilgarriff 1:2ad195e1455b 1 /***************************************************************************//**
EndaKilgarriff 1:2ad195e1455b 2 * @file ad5592r-base.h
EndaKilgarriff 1:2ad195e1455b 3 * @brief Header file of AD5592R Base Driver.
EndaKilgarriff 1:2ad195e1455b 4 * @author Mircea Caprioru (mircea.caprioru@analog.com)
EndaKilgarriff 1:2ad195e1455b 5 ********************************************************************************
EndaKilgarriff 1:2ad195e1455b 6 * Copyright 2018, 2020(c) Analog Devices, Inc.
EndaKilgarriff 1:2ad195e1455b 7 *
EndaKilgarriff 1:2ad195e1455b 8 * All rights reserved.
EndaKilgarriff 1:2ad195e1455b 9 *
EndaKilgarriff 1:2ad195e1455b 10 * Redistribution and use in source and binary forms, with or without
EndaKilgarriff 1:2ad195e1455b 11 * modification, are permitted provided that the following conditions are met:
EndaKilgarriff 1:2ad195e1455b 12 * - Redistributions of source code must retain the above copyright
EndaKilgarriff 1:2ad195e1455b 13 * notice, this list of conditions and the following disclaimer.
EndaKilgarriff 1:2ad195e1455b 14 * - Redistributions in binary form must reproduce the above copyright
EndaKilgarriff 1:2ad195e1455b 15 * notice, this list of conditions and the following disclaimer in
EndaKilgarriff 1:2ad195e1455b 16 * the documentation and/or other materials provided with the
EndaKilgarriff 1:2ad195e1455b 17 * distribution.
EndaKilgarriff 1:2ad195e1455b 18 * - Neither the name of Analog Devices, Inc. nor the names of its
EndaKilgarriff 1:2ad195e1455b 19 * contributors may be used to endorse or promote products derived
EndaKilgarriff 1:2ad195e1455b 20 * from this software without specific prior written permission.
EndaKilgarriff 1:2ad195e1455b 21 * - The use of this software may or may not infringe the patent rights
EndaKilgarriff 1:2ad195e1455b 22 * of one or more patent holders. This license does not release you
EndaKilgarriff 1:2ad195e1455b 23 * from the requirement that you obtain separate licenses from these
EndaKilgarriff 1:2ad195e1455b 24 * patent holders to use this software.
EndaKilgarriff 1:2ad195e1455b 25 * - Use of the software either in source or binary form, must be run
EndaKilgarriff 1:2ad195e1455b 26 * on or directly connected to an Analog Devices Inc. component.
EndaKilgarriff 1:2ad195e1455b 27 *
EndaKilgarriff 1:2ad195e1455b 28 * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
EndaKilgarriff 1:2ad195e1455b 29 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
EndaKilgarriff 1:2ad195e1455b 30 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
EndaKilgarriff 1:2ad195e1455b 31 * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
EndaKilgarriff 1:2ad195e1455b 32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
EndaKilgarriff 1:2ad195e1455b 33 * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
EndaKilgarriff 1:2ad195e1455b 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
EndaKilgarriff 1:2ad195e1455b 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
EndaKilgarriff 1:2ad195e1455b 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
EndaKilgarriff 1:2ad195e1455b 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
EndaKilgarriff 1:2ad195e1455b 38 *******************************************************************************/
EndaKilgarriff 1:2ad195e1455b 39 #ifndef AD5592R_BASE_H_
EndaKilgarriff 1:2ad195e1455b 40 #define AD5592R_BASE_H_
EndaKilgarriff 1:2ad195e1455b 41
EndaKilgarriff 1:2ad195e1455b 42 #include "stdint.h"
EndaKilgarriff 1:2ad195e1455b 43 #include "platform_drivers.h"
EndaKilgarriff 1:2ad195e1455b 44
EndaKilgarriff 1:2ad195e1455b 45 #include <stdbool.h>
EndaKilgarriff 1:2ad195e1455b 46
EndaKilgarriff 1:2ad195e1455b 47 #define CH_MODE_UNUSED 0
EndaKilgarriff 1:2ad195e1455b 48 #define CH_MODE_ADC 1
EndaKilgarriff 1:2ad195e1455b 49 #define CH_MODE_DAC 2
EndaKilgarriff 1:2ad195e1455b 50 #define CH_MODE_DAC_AND_ADC 3
EndaKilgarriff 1:2ad195e1455b 51 #define CH_MODE_GPI 4
EndaKilgarriff 1:2ad195e1455b 52 #define CH_MODE_GPO 5
EndaKilgarriff 1:2ad195e1455b 53
EndaKilgarriff 1:2ad195e1455b 54 #define CH_OFFSTATE_PULLDOWN 0
EndaKilgarriff 1:2ad195e1455b 55 #define CH_OFFSTATE_OUT_LOW 1
EndaKilgarriff 1:2ad195e1455b 56 #define CH_OFFSTATE_OUT_HIGH 2
EndaKilgarriff 1:2ad195e1455b 57 #define CH_OFFSTATE_OUT_TRISTATE 3
EndaKilgarriff 1:2ad195e1455b 58
EndaKilgarriff 1:2ad195e1455b 59 enum ad5592r_registers {
EndaKilgarriff 1:2ad195e1455b 60 AD5592R_REG_NOOP = 0x0,
EndaKilgarriff 1:2ad195e1455b 61 AD5592R_REG_DAC_READBACK = 0x1,
EndaKilgarriff 1:2ad195e1455b 62 AD5592R_REG_ADC_SEQ = 0x2,
EndaKilgarriff 1:2ad195e1455b 63 AD5592R_REG_CTRL = 0x3,
EndaKilgarriff 1:2ad195e1455b 64 AD5592R_REG_ADC_EN = 0x4,
EndaKilgarriff 1:2ad195e1455b 65 AD5592R_REG_DAC_EN = 0x5,
EndaKilgarriff 1:2ad195e1455b 66 AD5592R_REG_PULLDOWN = 0x6,
EndaKilgarriff 1:2ad195e1455b 67 AD5592R_REG_LDAC = 0x7,
EndaKilgarriff 1:2ad195e1455b 68 AD5592R_REG_GPIO_OUT_EN = 0x8,
EndaKilgarriff 1:2ad195e1455b 69 AD5592R_REG_GPIO_SET = 0x9,
EndaKilgarriff 1:2ad195e1455b 70 AD5592R_REG_GPIO_IN_EN = 0xA,
EndaKilgarriff 1:2ad195e1455b 71 AD5592R_REG_PD = 0xB,
EndaKilgarriff 1:2ad195e1455b 72 AD5592R_REG_OPEN_DRAIN = 0xC,
EndaKilgarriff 1:2ad195e1455b 73 AD5592R_REG_TRISTATE = 0xD,
EndaKilgarriff 1:2ad195e1455b 74 AD5592R_REG_RESET = 0xF,
EndaKilgarriff 1:2ad195e1455b 75 };
EndaKilgarriff 1:2ad195e1455b 76
EndaKilgarriff 1:2ad195e1455b 77 #define AD5592R_REG_PD_PD_ALL BIT(10)
EndaKilgarriff 1:2ad195e1455b 78 #define AD5592R_REG_PD_EN_REF BIT(9)
EndaKilgarriff 1:2ad195e1455b 79
EndaKilgarriff 1:2ad195e1455b 80 #define AD5592R_REG_CTRL_ADC_PC_BUFF BIT(9)
EndaKilgarriff 1:2ad195e1455b 81 #define AD5592R_REG_CTRL_ADC_BUFF_EN BIT(8)
EndaKilgarriff 1:2ad195e1455b 82 #define AD5592R_REG_CTRL_CONFIG_LOCK BIT(7)
EndaKilgarriff 1:2ad195e1455b 83 #define AD5592R_REG_CTRL_W_ALL_DACS BIT(6)
EndaKilgarriff 1:2ad195e1455b 84 #define AD5592R_REG_CTRL_ADC_RANGE BIT(5)
EndaKilgarriff 1:2ad195e1455b 85 #define AD5592R_REG_CTRL_DAC_RANGE BIT(4)
EndaKilgarriff 1:2ad195e1455b 86
EndaKilgarriff 1:2ad195e1455b 87 #define AD5592R_REG_ADC_SEQ_REP BIT(9)
EndaKilgarriff 1:2ad195e1455b 88 #define AD5592R_REG_ADC_SEQ_TEMP_READBACK BIT(8)
EndaKilgarriff 1:2ad195e1455b 89 #define AD5592R_REG_ADC_SEQ_CODE_MSK(x) ((x) & 0x0FFF)
EndaKilgarriff 1:2ad195e1455b 90
EndaKilgarriff 1:2ad195e1455b 91 #define AD5592R_REG_GPIO_OUT_EN_ADC_NOT_BUSY BIT(8)
EndaKilgarriff 1:2ad195e1455b 92
EndaKilgarriff 1:2ad195e1455b 93 #define AD5592R_REG_LDAC_IMMEDIATE_OUT 0x00
EndaKilgarriff 1:2ad195e1455b 94 #define AD5592R_REG_LDAC_INPUT_REG_ONLY 0x01
EndaKilgarriff 1:2ad195e1455b 95 #define AD5592R_REG_LDAC_INPUT_REG_OUT 0x02
EndaKilgarriff 1:2ad195e1455b 96
EndaKilgarriff 1:2ad195e1455b 97 #define INTERNAL_VREF_VOLTAGE 2.5
EndaKilgarriff 1:2ad195e1455b 98
EndaKilgarriff 1:2ad195e1455b 99 struct ad5592r_dev;
EndaKilgarriff 1:2ad195e1455b 100
EndaKilgarriff 1:2ad195e1455b 101 struct ad5592r_rw_ops {
EndaKilgarriff 1:2ad195e1455b 102 int32_t (*write_dac)(struct ad5592r_dev *dev, uint8_t chan,
EndaKilgarriff 1:2ad195e1455b 103 uint16_t value);
EndaKilgarriff 1:2ad195e1455b 104 int32_t (*read_adc)(struct ad5592r_dev *dev, uint8_t chan,
EndaKilgarriff 1:2ad195e1455b 105 uint16_t *value);
EndaKilgarriff 1:2ad195e1455b 106 int32_t(*multi_read_adc)(struct ad5592r_dev *dev,
EndaKilgarriff 1:2ad195e1455b 107 uint16_t chans, uint16_t *value);
EndaKilgarriff 1:2ad195e1455b 108 int32_t (*reg_write)(struct ad5592r_dev *dev, uint8_t reg,
EndaKilgarriff 1:2ad195e1455b 109 uint16_t value);
EndaKilgarriff 1:2ad195e1455b 110 int32_t (*reg_read)(struct ad5592r_dev *dev, uint8_t reg,
EndaKilgarriff 1:2ad195e1455b 111 uint16_t *value);
EndaKilgarriff 1:2ad195e1455b 112 int32_t (*gpio_read)(struct ad5592r_dev *dev, uint8_t *value);
EndaKilgarriff 1:2ad195e1455b 113 };
EndaKilgarriff 1:2ad195e1455b 114
EndaKilgarriff 1:2ad195e1455b 115 struct ad5592r_init_param {
EndaKilgarriff 1:2ad195e1455b 116 bool int_ref;
EndaKilgarriff 1:2ad195e1455b 117 };
EndaKilgarriff 1:2ad195e1455b 118
EndaKilgarriff 1:2ad195e1455b 119 struct ad5592r_dev {
EndaKilgarriff 1:2ad195e1455b 120 const struct ad5592r_rw_ops *ops;
EndaKilgarriff 1:2ad195e1455b 121 i2c_desc *i2c;
EndaKilgarriff 1:2ad195e1455b 122 spi_desc *spi;
EndaKilgarriff 1:2ad195e1455b 123 uint16_t spi_msg;
EndaKilgarriff 1:2ad195e1455b 124 uint8_t num_channels;
EndaKilgarriff 1:2ad195e1455b 125 uint16_t cached_dac[8];
EndaKilgarriff 1:2ad195e1455b 126 uint16_t cached_gp_ctrl;
EndaKilgarriff 1:2ad195e1455b 127 uint8_t channel_modes[8];
EndaKilgarriff 1:2ad195e1455b 128 uint8_t channel_offstate[8];
EndaKilgarriff 1:2ad195e1455b 129 uint8_t gpio_out;
EndaKilgarriff 1:2ad195e1455b 130 uint8_t gpio_in;
EndaKilgarriff 1:2ad195e1455b 131 uint8_t gpio_val;
EndaKilgarriff 1:2ad195e1455b 132 uint8_t ldac_mode;
EndaKilgarriff 1:2ad195e1455b 133 };
EndaKilgarriff 1:2ad195e1455b 134
EndaKilgarriff 1:2ad195e1455b 135 int32_t ad5592r_base_reg_write(struct ad5592r_dev *dev, uint8_t reg,
EndaKilgarriff 1:2ad195e1455b 136 uint16_t value);
EndaKilgarriff 1:2ad195e1455b 137 int32_t ad5592r_base_reg_read(struct ad5592r_dev *dev, uint8_t reg,
EndaKilgarriff 1:2ad195e1455b 138 uint16_t *value);
EndaKilgarriff 1:2ad195e1455b 139 int32_t ad5592r_gpio_get(struct ad5592r_dev *dev, uint8_t offset);
EndaKilgarriff 1:2ad195e1455b 140 int32_t ad5592r_gpio_set(struct ad5592r_dev *dev, uint8_t offset,
EndaKilgarriff 1:2ad195e1455b 141 int32_t value);
EndaKilgarriff 1:2ad195e1455b 142 int32_t ad5592r_gpio_direction_input(struct ad5592r_dev *dev, uint8_t offset);
EndaKilgarriff 1:2ad195e1455b 143 int32_t ad5592r_gpio_direction_output(struct ad5592r_dev *dev,
EndaKilgarriff 1:2ad195e1455b 144 uint8_t offset, int32_t value);
EndaKilgarriff 1:2ad195e1455b 145 int32_t ad5592r_software_reset(struct ad5592r_dev *dev);
EndaKilgarriff 1:2ad195e1455b 146 int32_t ad5592r_set_channel_modes(struct ad5592r_dev *dev);
EndaKilgarriff 1:2ad195e1455b 147 int32_t ad5592r_reset_channel_modes(struct ad5592r_dev *dev);
EndaKilgarriff 1:2ad195e1455b 148
EndaKilgarriff 1:2ad195e1455b 149 #endif /* AD5592R_BASE_H_ */