Krzysztof Sitko / mbed-dev-STM32F031K6

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targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_dma.h@50:a417edff4437, 2016-01-15 (annotated)

Committer:
mbed_official
Date:
Fri Jan 15 07:45:16 2016 +0000
Revision:
50:a417edff4437
Parent:
0:9b334a45a8ff 
Synchronized with git revision 6010f32619bfcbb01cc73747d4ff9040863482d9



Full URL: https://github.com/mbedmicro/mbed/commit/6010f32619bfcbb01cc73747d4ff9040863482d9/



Remove doubling of buffer size in realiseEndpoint()

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 2 * @file efm32hg_dma.h
bogdanm 0:9b334a45a8ff 3 * @brief EFM32HG_DMA register and bit field definitions
mbed_official 50:a417edff4437 4 * @version 4.2.0
bogdanm 0:9b334a45a8ff 5 ******************************************************************************
bogdanm 0:9b334a45a8ff 6 * @section License
mbed_official 50:a417edff4437 7 * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
bogdanm 0:9b334a45a8ff 8 ******************************************************************************
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Permission is granted to anyone to use this software for any purpose,
bogdanm 0:9b334a45a8ff 11 * including commercial applications, and to alter it and redistribute it
bogdanm 0:9b334a45a8ff 12 * freely, subject to the following restrictions:
bogdanm 0:9b334a45a8ff 13 *
bogdanm 0:9b334a45a8ff 14 * 1. The origin of this software must not be misrepresented; you must not
bogdanm 0:9b334a45a8ff 15 * claim that you wrote the original software.@n
bogdanm 0:9b334a45a8ff 16 * 2. Altered source versions must be plainly marked as such, and must not be
bogdanm 0:9b334a45a8ff 17 * misrepresented as being the original software.@n
bogdanm 0:9b334a45a8ff 18 * 3. This notice may not be removed or altered from any source distribution.
bogdanm 0:9b334a45a8ff 19 *
bogdanm 0:9b334a45a8ff 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
bogdanm 0:9b334a45a8ff 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
bogdanm 0:9b334a45a8ff 22 * providing the Software "AS IS", with no express or implied warranties of any
bogdanm 0:9b334a45a8ff 23 * kind, including, but not limited to, any implied warranties of
bogdanm 0:9b334a45a8ff 24 * merchantability or fitness for any particular purpose or warranties against
bogdanm 0:9b334a45a8ff 25 * infringement of any proprietary rights of a third party.
bogdanm 0:9b334a45a8ff 26 *
bogdanm 0:9b334a45a8ff 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
bogdanm 0:9b334a45a8ff 28 * incidental, or special damages, or any other relief, or for any claim by
bogdanm 0:9b334a45a8ff 29 * any third party, arising from your use of this Software.
bogdanm 0:9b334a45a8ff 30 *
bogdanm 0:9b334a45a8ff 31 *****************************************************************************/
bogdanm 0:9b334a45a8ff 32 /**************************************************************************//**
mbed_official 50:a417edff4437 33 * @addtogroup Parts
mbed_official 50:a417edff4437 34 * @{
mbed_official 50:a417edff4437 35 ******************************************************************************/
mbed_official 50:a417edff4437 36 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 37 * @defgroup EFM32HG_DMA
bogdanm 0:9b334a45a8ff 38 * @{
bogdanm 0:9b334a45a8ff 39 * @brief EFM32HG_DMA Register Declaration
bogdanm 0:9b334a45a8ff 40 *****************************************************************************/
bogdanm 0:9b334a45a8ff 41 typedef struct
bogdanm 0:9b334a45a8ff 42 {
bogdanm 0:9b334a45a8ff 43 __I uint32_t STATUS; /**< DMA Status Registers */
bogdanm 0:9b334a45a8ff 44 __O uint32_t CONFIG; /**< DMA Configuration Register */
bogdanm 0:9b334a45a8ff 45 __IO uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */
bogdanm 0:9b334a45a8ff 46 __I uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */
bogdanm 0:9b334a45a8ff 47 __I uint32_t CHWAITSTATUS; /**< Channel Wait on Request Status Register */
bogdanm 0:9b334a45a8ff 48 __O uint32_t CHSWREQ; /**< Channel Software Request Register */
bogdanm 0:9b334a45a8ff 49 __IO uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */
bogdanm 0:9b334a45a8ff 50 __O uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */
bogdanm 0:9b334a45a8ff 51 __IO uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */
bogdanm 0:9b334a45a8ff 52 __O uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */
bogdanm 0:9b334a45a8ff 53 __IO uint32_t CHENS; /**< Channel Enable Set Register */
bogdanm 0:9b334a45a8ff 54 __O uint32_t CHENC; /**< Channel Enable Clear Register */
bogdanm 0:9b334a45a8ff 55 __IO uint32_t CHALTS; /**< Channel Alternate Set Register */
bogdanm 0:9b334a45a8ff 56 __O uint32_t CHALTC; /**< Channel Alternate Clear Register */
bogdanm 0:9b334a45a8ff 57 __IO uint32_t CHPRIS; /**< Channel Priority Set Register */
bogdanm 0:9b334a45a8ff 58 __O uint32_t CHPRIC; /**< Channel Priority Clear Register */
bogdanm 0:9b334a45a8ff 59 uint32_t RESERVED0[3]; /**< Reserved for future use **/
bogdanm 0:9b334a45a8ff 60 __IO uint32_t ERRORC; /**< Bus Error Clear Register */
bogdanm 0:9b334a45a8ff 61
bogdanm 0:9b334a45a8ff 62 uint32_t RESERVED1[880]; /**< Reserved for future use **/
bogdanm 0:9b334a45a8ff 63 __I uint32_t CHREQSTATUS; /**< Channel Request Status */
bogdanm 0:9b334a45a8ff 64 uint32_t RESERVED2[1]; /**< Reserved for future use **/
bogdanm 0:9b334a45a8ff 65 __I uint32_t CHSREQSTATUS; /**< Channel Single Request Status */
bogdanm 0:9b334a45a8ff 66
bogdanm 0:9b334a45a8ff 67 uint32_t RESERVED3[121]; /**< Reserved for future use **/
bogdanm 0:9b334a45a8ff 68 __I uint32_t IF; /**< Interrupt Flag Register */
bogdanm 0:9b334a45a8ff 69 __IO uint32_t IFS; /**< Interrupt Flag Set Register */
bogdanm 0:9b334a45a8ff 70 __IO uint32_t IFC; /**< Interrupt Flag Clear Register */
bogdanm 0:9b334a45a8ff 71 __IO uint32_t IEN; /**< Interrupt Enable register */
bogdanm 0:9b334a45a8ff 72
bogdanm 0:9b334a45a8ff 73 uint32_t RESERVED4[60]; /**< Reserved registers */
bogdanm 0:9b334a45a8ff 74 DMA_CH_TypeDef CH[6]; /**< Channel registers */
bogdanm 0:9b334a45a8ff 75 } DMA_TypeDef; /** @} */
bogdanm 0:9b334a45a8ff 76
bogdanm 0:9b334a45a8ff 77 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 78 * @defgroup EFM32HG_DMA_BitFields
bogdanm 0:9b334a45a8ff 79 * @{
bogdanm 0:9b334a45a8ff 80 *****************************************************************************/
bogdanm 0:9b334a45a8ff 81
bogdanm 0:9b334a45a8ff 82 /* Bit fields for DMA STATUS */
bogdanm 0:9b334a45a8ff 83 #define _DMA_STATUS_RESETVALUE 0x10050000UL /**< Default value for DMA_STATUS */
bogdanm 0:9b334a45a8ff 84 #define _DMA_STATUS_MASK 0x001F00F1UL /**< Mask for DMA_STATUS */
bogdanm 0:9b334a45a8ff 85 #define DMA_STATUS_EN (0x1UL << 0) /**< DMA Enable Status */
bogdanm 0:9b334a45a8ff 86 #define _DMA_STATUS_EN_SHIFT 0 /**< Shift value for DMA_EN */
bogdanm 0:9b334a45a8ff 87 #define _DMA_STATUS_EN_MASK 0x1UL /**< Bit mask for DMA_EN */
bogdanm 0:9b334a45a8ff 88 #define _DMA_STATUS_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */
bogdanm 0:9b334a45a8ff 89 #define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_STATUS */
bogdanm 0:9b334a45a8ff 90 #define _DMA_STATUS_STATE_SHIFT 4 /**< Shift value for DMA_STATE */
bogdanm 0:9b334a45a8ff 91 #define _DMA_STATUS_STATE_MASK 0xF0UL /**< Bit mask for DMA_STATE */
bogdanm 0:9b334a45a8ff 92 #define _DMA_STATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */
bogdanm 0:9b334a45a8ff 93 #define _DMA_STATUS_STATE_IDLE 0x00000000UL /**< Mode IDLE for DMA_STATUS */
bogdanm 0:9b334a45a8ff 94 #define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL /**< Mode RDCHCTRLDATA for DMA_STATUS */
bogdanm 0:9b334a45a8ff 95 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< Mode RDSRCENDPTR for DMA_STATUS */
bogdanm 0:9b334a45a8ff 96 #define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL /**< Mode RDDSTENDPTR for DMA_STATUS */
bogdanm 0:9b334a45a8ff 97 #define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL /**< Mode RDSRCDATA for DMA_STATUS */
bogdanm 0:9b334a45a8ff 98 #define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL /**< Mode WRDSTDATA for DMA_STATUS */
bogdanm 0:9b334a45a8ff 99 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< Mode WAITREQCLR for DMA_STATUS */
bogdanm 0:9b334a45a8ff 100 #define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL /**< Mode WRCHCTRLDATA for DMA_STATUS */
bogdanm 0:9b334a45a8ff 101 #define _DMA_STATUS_STATE_STALLED 0x00000008UL /**< Mode STALLED for DMA_STATUS */
bogdanm 0:9b334a45a8ff 102 #define _DMA_STATUS_STATE_DONE 0x00000009UL /**< Mode DONE for DMA_STATUS */
bogdanm 0:9b334a45a8ff 103 #define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL /**< Mode PERSCATTRANS for DMA_STATUS */
bogdanm 0:9b334a45a8ff 104 #define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_STATUS */
bogdanm 0:9b334a45a8ff 105 #define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4) /**< Shifted mode IDLE for DMA_STATUS */
bogdanm 0:9b334a45a8ff 106 #define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) /**< Shifted mode RDCHCTRLDATA for DMA_STATUS */
bogdanm 0:9b334a45a8ff 107 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< Shifted mode RDSRCENDPTR for DMA_STATUS */
bogdanm 0:9b334a45a8ff 108 #define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4) /**< Shifted mode RDDSTENDPTR for DMA_STATUS */
bogdanm 0:9b334a45a8ff 109 #define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4) /**< Shifted mode RDSRCDATA for DMA_STATUS */
bogdanm 0:9b334a45a8ff 110 #define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4) /**< Shifted mode WRDSTDATA for DMA_STATUS */
bogdanm 0:9b334a45a8ff 111 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< Shifted mode WAITREQCLR for DMA_STATUS */
bogdanm 0:9b334a45a8ff 112 #define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) /**< Shifted mode WRCHCTRLDATA for DMA_STATUS */
bogdanm 0:9b334a45a8ff 113 #define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4) /**< Shifted mode STALLED for DMA_STATUS */
bogdanm 0:9b334a45a8ff 114 #define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4) /**< Shifted mode DONE for DMA_STATUS */
bogdanm 0:9b334a45a8ff 115 #define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4) /**< Shifted mode PERSCATTRANS for DMA_STATUS */
bogdanm 0:9b334a45a8ff 116 #define _DMA_STATUS_CHNUM_SHIFT 16 /**< Shift value for DMA_CHNUM */
bogdanm 0:9b334a45a8ff 117 #define _DMA_STATUS_CHNUM_MASK 0x1F0000UL /**< Bit mask for DMA_CHNUM */
bogdanm 0:9b334a45a8ff 118 #define _DMA_STATUS_CHNUM_DEFAULT 0x00000005UL /**< Mode DEFAULT for DMA_STATUS */
bogdanm 0:9b334a45a8ff 119 #define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_STATUS */
bogdanm 0:9b334a45a8ff 120
bogdanm 0:9b334a45a8ff 121 /* Bit fields for DMA CONFIG */
bogdanm 0:9b334a45a8ff 122 #define _DMA_CONFIG_RESETVALUE 0x00000000UL /**< Default value for DMA_CONFIG */
bogdanm 0:9b334a45a8ff 123 #define _DMA_CONFIG_MASK 0x00000021UL /**< Mask for DMA_CONFIG */
bogdanm 0:9b334a45a8ff 124 #define DMA_CONFIG_EN (0x1UL << 0) /**< Enable DMA */
bogdanm 0:9b334a45a8ff 125 #define _DMA_CONFIG_EN_SHIFT 0 /**< Shift value for DMA_EN */
bogdanm 0:9b334a45a8ff 126 #define _DMA_CONFIG_EN_MASK 0x1UL /**< Bit mask for DMA_EN */
bogdanm 0:9b334a45a8ff 127 #define _DMA_CONFIG_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */
bogdanm 0:9b334a45a8ff 128 #define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CONFIG */
bogdanm 0:9b334a45a8ff 129 #define DMA_CONFIG_CHPROT (0x1UL << 5) /**< Channel Protection Control */
bogdanm 0:9b334a45a8ff 130 #define _DMA_CONFIG_CHPROT_SHIFT 5 /**< Shift value for DMA_CHPROT */
bogdanm 0:9b334a45a8ff 131 #define _DMA_CONFIG_CHPROT_MASK 0x20UL /**< Bit mask for DMA_CHPROT */
bogdanm 0:9b334a45a8ff 132 #define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */
bogdanm 0:9b334a45a8ff 133 #define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CONFIG */
bogdanm 0:9b334a45a8ff 134
bogdanm 0:9b334a45a8ff 135 /* Bit fields for DMA CTRLBASE */
bogdanm 0:9b334a45a8ff 136 #define _DMA_CTRLBASE_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRLBASE */
bogdanm 0:9b334a45a8ff 137 #define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_CTRLBASE */
bogdanm 0:9b334a45a8ff 138 #define _DMA_CTRLBASE_CTRLBASE_SHIFT 0 /**< Shift value for DMA_CTRLBASE */
bogdanm 0:9b334a45a8ff 139 #define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_CTRLBASE */
bogdanm 0:9b334a45a8ff 140 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRLBASE */
bogdanm 0:9b334a45a8ff 141 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRLBASE */
bogdanm 0:9b334a45a8ff 142
bogdanm 0:9b334a45a8ff 143 /* Bit fields for DMA ALTCTRLBASE */
bogdanm 0:9b334a45a8ff 144 #define _DMA_ALTCTRLBASE_RESETVALUE 0x00000080UL /**< Default value for DMA_ALTCTRLBASE */
bogdanm 0:9b334a45a8ff 145 #define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_ALTCTRLBASE */
bogdanm 0:9b334a45a8ff 146 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0 /**< Shift value for DMA_ALTCTRLBASE */
bogdanm 0:9b334a45a8ff 147 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_ALTCTRLBASE */
bogdanm 0:9b334a45a8ff 148 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000080UL /**< Mode DEFAULT for DMA_ALTCTRLBASE */
bogdanm 0:9b334a45a8ff 149 #define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ALTCTRLBASE */
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151 /* Bit fields for DMA CHWAITSTATUS */
bogdanm 0:9b334a45a8ff 152 #define _DMA_CHWAITSTATUS_RESETVALUE 0x0000003FUL /**< Default value for DMA_CHWAITSTATUS */
bogdanm 0:9b334a45a8ff 153 #define _DMA_CHWAITSTATUS_MASK 0x0000003FUL /**< Mask for DMA_CHWAITSTATUS */
bogdanm 0:9b334a45a8ff 154 #define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0) /**< Channel 0 Wait on Request Status */
bogdanm 0:9b334a45a8ff 155 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0 /**< Shift value for DMA_CH0WAITSTATUS */
bogdanm 0:9b334a45a8ff 156 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0WAITSTATUS */
bogdanm 0:9b334a45a8ff 157 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
bogdanm 0:9b334a45a8ff 158 #define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
bogdanm 0:9b334a45a8ff 159 #define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1) /**< Channel 1 Wait on Request Status */
bogdanm 0:9b334a45a8ff 160 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1 /**< Shift value for DMA_CH1WAITSTATUS */
bogdanm 0:9b334a45a8ff 161 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1WAITSTATUS */
bogdanm 0:9b334a45a8ff 162 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
bogdanm 0:9b334a45a8ff 163 #define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
bogdanm 0:9b334a45a8ff 164 #define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2) /**< Channel 2 Wait on Request Status */
bogdanm 0:9b334a45a8ff 165 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2 /**< Shift value for DMA_CH2WAITSTATUS */
bogdanm 0:9b334a45a8ff 166 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2WAITSTATUS */
bogdanm 0:9b334a45a8ff 167 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
bogdanm 0:9b334a45a8ff 168 #define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
bogdanm 0:9b334a45a8ff 169 #define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3) /**< Channel 3 Wait on Request Status */
bogdanm 0:9b334a45a8ff 170 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3 /**< Shift value for DMA_CH3WAITSTATUS */
bogdanm 0:9b334a45a8ff 171 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3WAITSTATUS */
bogdanm 0:9b334a45a8ff 172 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
bogdanm 0:9b334a45a8ff 173 #define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
bogdanm 0:9b334a45a8ff 174 #define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4) /**< Channel 4 Wait on Request Status */
bogdanm 0:9b334a45a8ff 175 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4 /**< Shift value for DMA_CH4WAITSTATUS */
bogdanm 0:9b334a45a8ff 176 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4WAITSTATUS */
bogdanm 0:9b334a45a8ff 177 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
bogdanm 0:9b334a45a8ff 178 #define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
bogdanm 0:9b334a45a8ff 179 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) /**< Channel 5 Wait on Request Status */
bogdanm 0:9b334a45a8ff 180 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5 /**< Shift value for DMA_CH5WAITSTATUS */
bogdanm 0:9b334a45a8ff 181 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5WAITSTATUS */
bogdanm 0:9b334a45a8ff 182 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
bogdanm 0:9b334a45a8ff 183 #define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
bogdanm 0:9b334a45a8ff 184
bogdanm 0:9b334a45a8ff 185 /* Bit fields for DMA CHSWREQ */
bogdanm 0:9b334a45a8ff 186 #define _DMA_CHSWREQ_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSWREQ */
bogdanm 0:9b334a45a8ff 187 #define _DMA_CHSWREQ_MASK 0x0000003FUL /**< Mask for DMA_CHSWREQ */
bogdanm 0:9b334a45a8ff 188 #define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0) /**< Channel 0 Software Request */
bogdanm 0:9b334a45a8ff 189 #define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0 /**< Shift value for DMA_CH0SWREQ */
bogdanm 0:9b334a45a8ff 190 #define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL /**< Bit mask for DMA_CH0SWREQ */
bogdanm 0:9b334a45a8ff 191 #define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
bogdanm 0:9b334a45a8ff 192 #define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
bogdanm 0:9b334a45a8ff 193 #define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1) /**< Channel 1 Software Request */
bogdanm 0:9b334a45a8ff 194 #define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1 /**< Shift value for DMA_CH1SWREQ */
bogdanm 0:9b334a45a8ff 195 #define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL /**< Bit mask for DMA_CH1SWREQ */
bogdanm 0:9b334a45a8ff 196 #define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
bogdanm 0:9b334a45a8ff 197 #define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
bogdanm 0:9b334a45a8ff 198 #define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2) /**< Channel 2 Software Request */
bogdanm 0:9b334a45a8ff 199 #define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2 /**< Shift value for DMA_CH2SWREQ */
bogdanm 0:9b334a45a8ff 200 #define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL /**< Bit mask for DMA_CH2SWREQ */
bogdanm 0:9b334a45a8ff 201 #define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
bogdanm 0:9b334a45a8ff 202 #define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
bogdanm 0:9b334a45a8ff 203 #define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3) /**< Channel 3 Software Request */
bogdanm 0:9b334a45a8ff 204 #define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3 /**< Shift value for DMA_CH3SWREQ */
bogdanm 0:9b334a45a8ff 205 #define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL /**< Bit mask for DMA_CH3SWREQ */
bogdanm 0:9b334a45a8ff 206 #define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
bogdanm 0:9b334a45a8ff 207 #define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
bogdanm 0:9b334a45a8ff 208 #define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4) /**< Channel 4 Software Request */
bogdanm 0:9b334a45a8ff 209 #define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4 /**< Shift value for DMA_CH4SWREQ */
bogdanm 0:9b334a45a8ff 210 #define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL /**< Bit mask for DMA_CH4SWREQ */
bogdanm 0:9b334a45a8ff 211 #define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
bogdanm 0:9b334a45a8ff 212 #define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
bogdanm 0:9b334a45a8ff 213 #define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5) /**< Channel 5 Software Request */
bogdanm 0:9b334a45a8ff 214 #define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5 /**< Shift value for DMA_CH5SWREQ */
bogdanm 0:9b334a45a8ff 215 #define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL /**< Bit mask for DMA_CH5SWREQ */
bogdanm 0:9b334a45a8ff 216 #define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
bogdanm 0:9b334a45a8ff 217 #define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
bogdanm 0:9b334a45a8ff 218
bogdanm 0:9b334a45a8ff 219 /* Bit fields for DMA CHUSEBURSTS */
bogdanm 0:9b334a45a8ff 220 #define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTS */
bogdanm 0:9b334a45a8ff 221 #define _DMA_CHUSEBURSTS_MASK 0x0000003FUL /**< Mask for DMA_CHUSEBURSTS */
bogdanm 0:9b334a45a8ff 222 #define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0) /**< Channel 0 Useburst Set */
bogdanm 0:9b334a45a8ff 223 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTS */
bogdanm 0:9b334a45a8ff 224 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTS */
bogdanm 0:9b334a45a8ff 225 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
bogdanm 0:9b334a45a8ff 226 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL /**< Mode SINGLEANDBURST for DMA_CHUSEBURSTS */
bogdanm 0:9b334a45a8ff 227 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL /**< Mode BURSTONLY for DMA_CHUSEBURSTS */
bogdanm 0:9b334a45a8ff 228 #define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
bogdanm 0:9b334a45a8ff 229 #define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) /**< Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS */
bogdanm 0:9b334a45a8ff 230 #define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0) /**< Shifted mode BURSTONLY for DMA_CHUSEBURSTS */
bogdanm 0:9b334a45a8ff 231 #define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1) /**< Channel 1 Useburst Set */
bogdanm 0:9b334a45a8ff 232 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTS */
bogdanm 0:9b334a45a8ff 233 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTS */
bogdanm 0:9b334a45a8ff 234 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
bogdanm 0:9b334a45a8ff 235 #define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
bogdanm 0:9b334a45a8ff 236 #define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2) /**< Channel 2 Useburst Set */
bogdanm 0:9b334a45a8ff 237 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTS */
bogdanm 0:9b334a45a8ff 238 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTS */
bogdanm 0:9b334a45a8ff 239 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
bogdanm 0:9b334a45a8ff 240 #define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
bogdanm 0:9b334a45a8ff 241 #define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3) /**< Channel 3 Useburst Set */
bogdanm 0:9b334a45a8ff 242 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTS */
bogdanm 0:9b334a45a8ff 243 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTS */
bogdanm 0:9b334a45a8ff 244 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
bogdanm 0:9b334a45a8ff 245 #define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
bogdanm 0:9b334a45a8ff 246 #define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4) /**< Channel 4 Useburst Set */
bogdanm 0:9b334a45a8ff 247 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTS */
bogdanm 0:9b334a45a8ff 248 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTS */
bogdanm 0:9b334a45a8ff 249 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
bogdanm 0:9b334a45a8ff 250 #define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
bogdanm 0:9b334a45a8ff 251 #define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5) /**< Channel 5 Useburst Set */
bogdanm 0:9b334a45a8ff 252 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTS */
bogdanm 0:9b334a45a8ff 253 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTS */
bogdanm 0:9b334a45a8ff 254 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
bogdanm 0:9b334a45a8ff 255 #define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
bogdanm 0:9b334a45a8ff 256
bogdanm 0:9b334a45a8ff 257 /* Bit fields for DMA CHUSEBURSTC */
bogdanm 0:9b334a45a8ff 258 #define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTC */
bogdanm 0:9b334a45a8ff 259 #define _DMA_CHUSEBURSTC_MASK 0x0000003FUL /**< Mask for DMA_CHUSEBURSTC */
bogdanm 0:9b334a45a8ff 260 #define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0) /**< Channel 0 Useburst Clear */
bogdanm 0:9b334a45a8ff 261 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTC */
bogdanm 0:9b334a45a8ff 262 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTC */
bogdanm 0:9b334a45a8ff 263 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
bogdanm 0:9b334a45a8ff 264 #define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
bogdanm 0:9b334a45a8ff 265 #define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1) /**< Channel 1 Useburst Clear */
bogdanm 0:9b334a45a8ff 266 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTC */
bogdanm 0:9b334a45a8ff 267 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTC */
bogdanm 0:9b334a45a8ff 268 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
bogdanm 0:9b334a45a8ff 269 #define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
bogdanm 0:9b334a45a8ff 270 #define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2) /**< Channel 2 Useburst Clear */
bogdanm 0:9b334a45a8ff 271 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTC */
bogdanm 0:9b334a45a8ff 272 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTC */
bogdanm 0:9b334a45a8ff 273 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
bogdanm 0:9b334a45a8ff 274 #define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
bogdanm 0:9b334a45a8ff 275 #define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3) /**< Channel 3 Useburst Clear */
bogdanm 0:9b334a45a8ff 276 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTC */
bogdanm 0:9b334a45a8ff 277 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTC */
bogdanm 0:9b334a45a8ff 278 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
bogdanm 0:9b334a45a8ff 279 #define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
bogdanm 0:9b334a45a8ff 280 #define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4) /**< Channel 4 Useburst Clear */
bogdanm 0:9b334a45a8ff 281 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTC */
bogdanm 0:9b334a45a8ff 282 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTC */
bogdanm 0:9b334a45a8ff 283 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
bogdanm 0:9b334a45a8ff 284 #define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
bogdanm 0:9b334a45a8ff 285 #define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5) /**< Channel 5 Useburst Clear */
bogdanm 0:9b334a45a8ff 286 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTC */
bogdanm 0:9b334a45a8ff 287 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTC */
bogdanm 0:9b334a45a8ff 288 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
bogdanm 0:9b334a45a8ff 289 #define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
bogdanm 0:9b334a45a8ff 290
bogdanm 0:9b334a45a8ff 291 /* Bit fields for DMA CHREQMASKS */
bogdanm 0:9b334a45a8ff 292 #define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKS */
bogdanm 0:9b334a45a8ff 293 #define _DMA_CHREQMASKS_MASK 0x0000003FUL /**< Mask for DMA_CHREQMASKS */
bogdanm 0:9b334a45a8ff 294 #define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0) /**< Channel 0 Request Mask Set */
bogdanm 0:9b334a45a8ff 295 #define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0 /**< Shift value for DMA_CH0REQMASKS */
bogdanm 0:9b334a45a8ff 296 #define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKS */
bogdanm 0:9b334a45a8ff 297 #define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
bogdanm 0:9b334a45a8ff 298 #define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
bogdanm 0:9b334a45a8ff 299 #define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1) /**< Channel 1 Request Mask Set */
bogdanm 0:9b334a45a8ff 300 #define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1 /**< Shift value for DMA_CH1REQMASKS */
bogdanm 0:9b334a45a8ff 301 #define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKS */
bogdanm 0:9b334a45a8ff 302 #define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
bogdanm 0:9b334a45a8ff 303 #define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
bogdanm 0:9b334a45a8ff 304 #define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2) /**< Channel 2 Request Mask Set */
bogdanm 0:9b334a45a8ff 305 #define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2 /**< Shift value for DMA_CH2REQMASKS */
bogdanm 0:9b334a45a8ff 306 #define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKS */
bogdanm 0:9b334a45a8ff 307 #define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
bogdanm 0:9b334a45a8ff 308 #define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
bogdanm 0:9b334a45a8ff 309 #define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3) /**< Channel 3 Request Mask Set */
bogdanm 0:9b334a45a8ff 310 #define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3 /**< Shift value for DMA_CH3REQMASKS */
bogdanm 0:9b334a45a8ff 311 #define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKS */
bogdanm 0:9b334a45a8ff 312 #define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
bogdanm 0:9b334a45a8ff 313 #define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
bogdanm 0:9b334a45a8ff 314 #define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4) /**< Channel 4 Request Mask Set */
bogdanm 0:9b334a45a8ff 315 #define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4 /**< Shift value for DMA_CH4REQMASKS */
bogdanm 0:9b334a45a8ff 316 #define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKS */
bogdanm 0:9b334a45a8ff 317 #define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
bogdanm 0:9b334a45a8ff 318 #define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
bogdanm 0:9b334a45a8ff 319 #define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5) /**< Channel 5 Request Mask Set */
bogdanm 0:9b334a45a8ff 320 #define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5 /**< Shift value for DMA_CH5REQMASKS */
bogdanm 0:9b334a45a8ff 321 #define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKS */
bogdanm 0:9b334a45a8ff 322 #define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
bogdanm 0:9b334a45a8ff 323 #define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
bogdanm 0:9b334a45a8ff 324
bogdanm 0:9b334a45a8ff 325 /* Bit fields for DMA CHREQMASKC */
bogdanm 0:9b334a45a8ff 326 #define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKC */
bogdanm 0:9b334a45a8ff 327 #define _DMA_CHREQMASKC_MASK 0x0000003FUL /**< Mask for DMA_CHREQMASKC */
bogdanm 0:9b334a45a8ff 328 #define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0) /**< Channel 0 Request Mask Clear */
bogdanm 0:9b334a45a8ff 329 #define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0 /**< Shift value for DMA_CH0REQMASKC */
bogdanm 0:9b334a45a8ff 330 #define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKC */
bogdanm 0:9b334a45a8ff 331 #define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
bogdanm 0:9b334a45a8ff 332 #define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
bogdanm 0:9b334a45a8ff 333 #define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1) /**< Channel 1 Request Mask Clear */
bogdanm 0:9b334a45a8ff 334 #define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1 /**< Shift value for DMA_CH1REQMASKC */
bogdanm 0:9b334a45a8ff 335 #define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKC */
bogdanm 0:9b334a45a8ff 336 #define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
bogdanm 0:9b334a45a8ff 337 #define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
bogdanm 0:9b334a45a8ff 338 #define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2) /**< Channel 2 Request Mask Clear */
bogdanm 0:9b334a45a8ff 339 #define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2 /**< Shift value for DMA_CH2REQMASKC */
bogdanm 0:9b334a45a8ff 340 #define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKC */
bogdanm 0:9b334a45a8ff 341 #define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
bogdanm 0:9b334a45a8ff 342 #define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
bogdanm 0:9b334a45a8ff 343 #define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3) /**< Channel 3 Request Mask Clear */
bogdanm 0:9b334a45a8ff 344 #define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3 /**< Shift value for DMA_CH3REQMASKC */
bogdanm 0:9b334a45a8ff 345 #define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKC */
bogdanm 0:9b334a45a8ff 346 #define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
bogdanm 0:9b334a45a8ff 347 #define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
bogdanm 0:9b334a45a8ff 348 #define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4) /**< Channel 4 Request Mask Clear */
bogdanm 0:9b334a45a8ff 349 #define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4 /**< Shift value for DMA_CH4REQMASKC */
bogdanm 0:9b334a45a8ff 350 #define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKC */
bogdanm 0:9b334a45a8ff 351 #define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
bogdanm 0:9b334a45a8ff 352 #define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
bogdanm 0:9b334a45a8ff 353 #define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5) /**< Channel 5 Request Mask Clear */
bogdanm 0:9b334a45a8ff 354 #define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5 /**< Shift value for DMA_CH5REQMASKC */
bogdanm 0:9b334a45a8ff 355 #define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKC */
bogdanm 0:9b334a45a8ff 356 #define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
bogdanm 0:9b334a45a8ff 357 #define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
bogdanm 0:9b334a45a8ff 358
bogdanm 0:9b334a45a8ff 359 /* Bit fields for DMA CHENS */
bogdanm 0:9b334a45a8ff 360 #define _DMA_CHENS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENS */
bogdanm 0:9b334a45a8ff 361 #define _DMA_CHENS_MASK 0x0000003FUL /**< Mask for DMA_CHENS */
bogdanm 0:9b334a45a8ff 362 #define DMA_CHENS_CH0ENS (0x1UL << 0) /**< Channel 0 Enable Set */
bogdanm 0:9b334a45a8ff 363 #define _DMA_CHENS_CH0ENS_SHIFT 0 /**< Shift value for DMA_CH0ENS */
bogdanm 0:9b334a45a8ff 364 #define _DMA_CHENS_CH0ENS_MASK 0x1UL /**< Bit mask for DMA_CH0ENS */
bogdanm 0:9b334a45a8ff 365 #define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
bogdanm 0:9b334a45a8ff 366 #define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENS */
bogdanm 0:9b334a45a8ff 367 #define DMA_CHENS_CH1ENS (0x1UL << 1) /**< Channel 1 Enable Set */
bogdanm 0:9b334a45a8ff 368 #define _DMA_CHENS_CH1ENS_SHIFT 1 /**< Shift value for DMA_CH1ENS */
bogdanm 0:9b334a45a8ff 369 #define _DMA_CHENS_CH1ENS_MASK 0x2UL /**< Bit mask for DMA_CH1ENS */
bogdanm 0:9b334a45a8ff 370 #define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
bogdanm 0:9b334a45a8ff 371 #define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENS */
bogdanm 0:9b334a45a8ff 372 #define DMA_CHENS_CH2ENS (0x1UL << 2) /**< Channel 2 Enable Set */
bogdanm 0:9b334a45a8ff 373 #define _DMA_CHENS_CH2ENS_SHIFT 2 /**< Shift value for DMA_CH2ENS */
bogdanm 0:9b334a45a8ff 374 #define _DMA_CHENS_CH2ENS_MASK 0x4UL /**< Bit mask for DMA_CH2ENS */
bogdanm 0:9b334a45a8ff 375 #define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
bogdanm 0:9b334a45a8ff 376 #define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENS */
bogdanm 0:9b334a45a8ff 377 #define DMA_CHENS_CH3ENS (0x1UL << 3) /**< Channel 3 Enable Set */
bogdanm 0:9b334a45a8ff 378 #define _DMA_CHENS_CH3ENS_SHIFT 3 /**< Shift value for DMA_CH3ENS */
bogdanm 0:9b334a45a8ff 379 #define _DMA_CHENS_CH3ENS_MASK 0x8UL /**< Bit mask for DMA_CH3ENS */
bogdanm 0:9b334a45a8ff 380 #define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
bogdanm 0:9b334a45a8ff 381 #define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENS */
bogdanm 0:9b334a45a8ff 382 #define DMA_CHENS_CH4ENS (0x1UL << 4) /**< Channel 4 Enable Set */
bogdanm 0:9b334a45a8ff 383 #define _DMA_CHENS_CH4ENS_SHIFT 4 /**< Shift value for DMA_CH4ENS */
bogdanm 0:9b334a45a8ff 384 #define _DMA_CHENS_CH4ENS_MASK 0x10UL /**< Bit mask for DMA_CH4ENS */
bogdanm 0:9b334a45a8ff 385 #define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
bogdanm 0:9b334a45a8ff 386 #define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENS */
bogdanm 0:9b334a45a8ff 387 #define DMA_CHENS_CH5ENS (0x1UL << 5) /**< Channel 5 Enable Set */
bogdanm 0:9b334a45a8ff 388 #define _DMA_CHENS_CH5ENS_SHIFT 5 /**< Shift value for DMA_CH5ENS */
bogdanm 0:9b334a45a8ff 389 #define _DMA_CHENS_CH5ENS_MASK 0x20UL /**< Bit mask for DMA_CH5ENS */
bogdanm 0:9b334a45a8ff 390 #define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
bogdanm 0:9b334a45a8ff 391 #define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENS */
bogdanm 0:9b334a45a8ff 392
bogdanm 0:9b334a45a8ff 393 /* Bit fields for DMA CHENC */
bogdanm 0:9b334a45a8ff 394 #define _DMA_CHENC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENC */
bogdanm 0:9b334a45a8ff 395 #define _DMA_CHENC_MASK 0x0000003FUL /**< Mask for DMA_CHENC */
bogdanm 0:9b334a45a8ff 396 #define DMA_CHENC_CH0ENC (0x1UL << 0) /**< Channel 0 Enable Clear */
bogdanm 0:9b334a45a8ff 397 #define _DMA_CHENC_CH0ENC_SHIFT 0 /**< Shift value for DMA_CH0ENC */
bogdanm 0:9b334a45a8ff 398 #define _DMA_CHENC_CH0ENC_MASK 0x1UL /**< Bit mask for DMA_CH0ENC */
bogdanm 0:9b334a45a8ff 399 #define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
bogdanm 0:9b334a45a8ff 400 #define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENC */
bogdanm 0:9b334a45a8ff 401 #define DMA_CHENC_CH1ENC (0x1UL << 1) /**< Channel 1 Enable Clear */
bogdanm 0:9b334a45a8ff 402 #define _DMA_CHENC_CH1ENC_SHIFT 1 /**< Shift value for DMA_CH1ENC */
bogdanm 0:9b334a45a8ff 403 #define _DMA_CHENC_CH1ENC_MASK 0x2UL /**< Bit mask for DMA_CH1ENC */
bogdanm 0:9b334a45a8ff 404 #define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
bogdanm 0:9b334a45a8ff 405 #define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENC */
bogdanm 0:9b334a45a8ff 406 #define DMA_CHENC_CH2ENC (0x1UL << 2) /**< Channel 2 Enable Clear */
bogdanm 0:9b334a45a8ff 407 #define _DMA_CHENC_CH2ENC_SHIFT 2 /**< Shift value for DMA_CH2ENC */
bogdanm 0:9b334a45a8ff 408 #define _DMA_CHENC_CH2ENC_MASK 0x4UL /**< Bit mask for DMA_CH2ENC */
bogdanm 0:9b334a45a8ff 409 #define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
bogdanm 0:9b334a45a8ff 410 #define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENC */
bogdanm 0:9b334a45a8ff 411 #define DMA_CHENC_CH3ENC (0x1UL << 3) /**< Channel 3 Enable Clear */
bogdanm 0:9b334a45a8ff 412 #define _DMA_CHENC_CH3ENC_SHIFT 3 /**< Shift value for DMA_CH3ENC */
bogdanm 0:9b334a45a8ff 413 #define _DMA_CHENC_CH3ENC_MASK 0x8UL /**< Bit mask for DMA_CH3ENC */
bogdanm 0:9b334a45a8ff 414 #define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
bogdanm 0:9b334a45a8ff 415 #define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENC */
bogdanm 0:9b334a45a8ff 416 #define DMA_CHENC_CH4ENC (0x1UL << 4) /**< Channel 4 Enable Clear */
bogdanm 0:9b334a45a8ff 417 #define _DMA_CHENC_CH4ENC_SHIFT 4 /**< Shift value for DMA_CH4ENC */
bogdanm 0:9b334a45a8ff 418 #define _DMA_CHENC_CH4ENC_MASK 0x10UL /**< Bit mask for DMA_CH4ENC */
bogdanm 0:9b334a45a8ff 419 #define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
bogdanm 0:9b334a45a8ff 420 #define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENC */
bogdanm 0:9b334a45a8ff 421 #define DMA_CHENC_CH5ENC (0x1UL << 5) /**< Channel 5 Enable Clear */
bogdanm 0:9b334a45a8ff 422 #define _DMA_CHENC_CH5ENC_SHIFT 5 /**< Shift value for DMA_CH5ENC */
bogdanm 0:9b334a45a8ff 423 #define _DMA_CHENC_CH5ENC_MASK 0x20UL /**< Bit mask for DMA_CH5ENC */
bogdanm 0:9b334a45a8ff 424 #define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
bogdanm 0:9b334a45a8ff 425 #define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENC */
bogdanm 0:9b334a45a8ff 426
bogdanm 0:9b334a45a8ff 427 /* Bit fields for DMA CHALTS */
bogdanm 0:9b334a45a8ff 428 #define _DMA_CHALTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTS */
bogdanm 0:9b334a45a8ff 429 #define _DMA_CHALTS_MASK 0x0000003FUL /**< Mask for DMA_CHALTS */
bogdanm 0:9b334a45a8ff 430 #define DMA_CHALTS_CH0ALTS (0x1UL << 0) /**< Channel 0 Alternate Structure Set */
bogdanm 0:9b334a45a8ff 431 #define _DMA_CHALTS_CH0ALTS_SHIFT 0 /**< Shift value for DMA_CH0ALTS */
bogdanm 0:9b334a45a8ff 432 #define _DMA_CHALTS_CH0ALTS_MASK 0x1UL /**< Bit mask for DMA_CH0ALTS */
bogdanm 0:9b334a45a8ff 433 #define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
bogdanm 0:9b334a45a8ff 434 #define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTS */
bogdanm 0:9b334a45a8ff 435 #define DMA_CHALTS_CH1ALTS (0x1UL << 1) /**< Channel 1 Alternate Structure Set */
bogdanm 0:9b334a45a8ff 436 #define _DMA_CHALTS_CH1ALTS_SHIFT 1 /**< Shift value for DMA_CH1ALTS */
bogdanm 0:9b334a45a8ff 437 #define _DMA_CHALTS_CH1ALTS_MASK 0x2UL /**< Bit mask for DMA_CH1ALTS */
bogdanm 0:9b334a45a8ff 438 #define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
bogdanm 0:9b334a45a8ff 439 #define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTS */
bogdanm 0:9b334a45a8ff 440 #define DMA_CHALTS_CH2ALTS (0x1UL << 2) /**< Channel 2 Alternate Structure Set */
bogdanm 0:9b334a45a8ff 441 #define _DMA_CHALTS_CH2ALTS_SHIFT 2 /**< Shift value for DMA_CH2ALTS */
bogdanm 0:9b334a45a8ff 442 #define _DMA_CHALTS_CH2ALTS_MASK 0x4UL /**< Bit mask for DMA_CH2ALTS */
bogdanm 0:9b334a45a8ff 443 #define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
bogdanm 0:9b334a45a8ff 444 #define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTS */
bogdanm 0:9b334a45a8ff 445 #define DMA_CHALTS_CH3ALTS (0x1UL << 3) /**< Channel 3 Alternate Structure Set */
bogdanm 0:9b334a45a8ff 446 #define _DMA_CHALTS_CH3ALTS_SHIFT 3 /**< Shift value for DMA_CH3ALTS */
bogdanm 0:9b334a45a8ff 447 #define _DMA_CHALTS_CH3ALTS_MASK 0x8UL /**< Bit mask for DMA_CH3ALTS */
bogdanm 0:9b334a45a8ff 448 #define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
bogdanm 0:9b334a45a8ff 449 #define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTS */
bogdanm 0:9b334a45a8ff 450 #define DMA_CHALTS_CH4ALTS (0x1UL << 4) /**< Channel 4 Alternate Structure Set */
bogdanm 0:9b334a45a8ff 451 #define _DMA_CHALTS_CH4ALTS_SHIFT 4 /**< Shift value for DMA_CH4ALTS */
bogdanm 0:9b334a45a8ff 452 #define _DMA_CHALTS_CH4ALTS_MASK 0x10UL /**< Bit mask for DMA_CH4ALTS */
bogdanm 0:9b334a45a8ff 453 #define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
bogdanm 0:9b334a45a8ff 454 #define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTS */
bogdanm 0:9b334a45a8ff 455 #define DMA_CHALTS_CH5ALTS (0x1UL << 5) /**< Channel 5 Alternate Structure Set */
bogdanm 0:9b334a45a8ff 456 #define _DMA_CHALTS_CH5ALTS_SHIFT 5 /**< Shift value for DMA_CH5ALTS */
bogdanm 0:9b334a45a8ff 457 #define _DMA_CHALTS_CH5ALTS_MASK 0x20UL /**< Bit mask for DMA_CH5ALTS */
bogdanm 0:9b334a45a8ff 458 #define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
bogdanm 0:9b334a45a8ff 459 #define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTS */
bogdanm 0:9b334a45a8ff 460
bogdanm 0:9b334a45a8ff 461 /* Bit fields for DMA CHALTC */
bogdanm 0:9b334a45a8ff 462 #define _DMA_CHALTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTC */
bogdanm 0:9b334a45a8ff 463 #define _DMA_CHALTC_MASK 0x0000003FUL /**< Mask for DMA_CHALTC */
bogdanm 0:9b334a45a8ff 464 #define DMA_CHALTC_CH0ALTC (0x1UL << 0) /**< Channel 0 Alternate Clear */
bogdanm 0:9b334a45a8ff 465 #define _DMA_CHALTC_CH0ALTC_SHIFT 0 /**< Shift value for DMA_CH0ALTC */
bogdanm 0:9b334a45a8ff 466 #define _DMA_CHALTC_CH0ALTC_MASK 0x1UL /**< Bit mask for DMA_CH0ALTC */
bogdanm 0:9b334a45a8ff 467 #define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
bogdanm 0:9b334a45a8ff 468 #define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTC */
bogdanm 0:9b334a45a8ff 469 #define DMA_CHALTC_CH1ALTC (0x1UL << 1) /**< Channel 1 Alternate Clear */
bogdanm 0:9b334a45a8ff 470 #define _DMA_CHALTC_CH1ALTC_SHIFT 1 /**< Shift value for DMA_CH1ALTC */
bogdanm 0:9b334a45a8ff 471 #define _DMA_CHALTC_CH1ALTC_MASK 0x2UL /**< Bit mask for DMA_CH1ALTC */
bogdanm 0:9b334a45a8ff 472 #define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
bogdanm 0:9b334a45a8ff 473 #define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTC */
bogdanm 0:9b334a45a8ff 474 #define DMA_CHALTC_CH2ALTC (0x1UL << 2) /**< Channel 2 Alternate Clear */
bogdanm 0:9b334a45a8ff 475 #define _DMA_CHALTC_CH2ALTC_SHIFT 2 /**< Shift value for DMA_CH2ALTC */
bogdanm 0:9b334a45a8ff 476 #define _DMA_CHALTC_CH2ALTC_MASK 0x4UL /**< Bit mask for DMA_CH2ALTC */
bogdanm 0:9b334a45a8ff 477 #define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
bogdanm 0:9b334a45a8ff 478 #define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTC */
bogdanm 0:9b334a45a8ff 479 #define DMA_CHALTC_CH3ALTC (0x1UL << 3) /**< Channel 3 Alternate Clear */
bogdanm 0:9b334a45a8ff 480 #define _DMA_CHALTC_CH3ALTC_SHIFT 3 /**< Shift value for DMA_CH3ALTC */
bogdanm 0:9b334a45a8ff 481 #define _DMA_CHALTC_CH3ALTC_MASK 0x8UL /**< Bit mask for DMA_CH3ALTC */
bogdanm 0:9b334a45a8ff 482 #define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
bogdanm 0:9b334a45a8ff 483 #define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTC */
bogdanm 0:9b334a45a8ff 484 #define DMA_CHALTC_CH4ALTC (0x1UL << 4) /**< Channel 4 Alternate Clear */
bogdanm 0:9b334a45a8ff 485 #define _DMA_CHALTC_CH4ALTC_SHIFT 4 /**< Shift value for DMA_CH4ALTC */
bogdanm 0:9b334a45a8ff 486 #define _DMA_CHALTC_CH4ALTC_MASK 0x10UL /**< Bit mask for DMA_CH4ALTC */
bogdanm 0:9b334a45a8ff 487 #define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
bogdanm 0:9b334a45a8ff 488 #define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTC */
bogdanm 0:9b334a45a8ff 489 #define DMA_CHALTC_CH5ALTC (0x1UL << 5) /**< Channel 5 Alternate Clear */
bogdanm 0:9b334a45a8ff 490 #define _DMA_CHALTC_CH5ALTC_SHIFT 5 /**< Shift value for DMA_CH5ALTC */
bogdanm 0:9b334a45a8ff 491 #define _DMA_CHALTC_CH5ALTC_MASK 0x20UL /**< Bit mask for DMA_CH5ALTC */
bogdanm 0:9b334a45a8ff 492 #define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
bogdanm 0:9b334a45a8ff 493 #define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTC */
bogdanm 0:9b334a45a8ff 494
bogdanm 0:9b334a45a8ff 495 /* Bit fields for DMA CHPRIS */
bogdanm 0:9b334a45a8ff 496 #define _DMA_CHPRIS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIS */
bogdanm 0:9b334a45a8ff 497 #define _DMA_CHPRIS_MASK 0x0000003FUL /**< Mask for DMA_CHPRIS */
bogdanm 0:9b334a45a8ff 498 #define DMA_CHPRIS_CH0PRIS (0x1UL << 0) /**< Channel 0 High Priority Set */
bogdanm 0:9b334a45a8ff 499 #define _DMA_CHPRIS_CH0PRIS_SHIFT 0 /**< Shift value for DMA_CH0PRIS */
bogdanm 0:9b334a45a8ff 500 #define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL /**< Bit mask for DMA_CH0PRIS */
bogdanm 0:9b334a45a8ff 501 #define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
bogdanm 0:9b334a45a8ff 502 #define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIS */
bogdanm 0:9b334a45a8ff 503 #define DMA_CHPRIS_CH1PRIS (0x1UL << 1) /**< Channel 1 High Priority Set */
bogdanm 0:9b334a45a8ff 504 #define _DMA_CHPRIS_CH1PRIS_SHIFT 1 /**< Shift value for DMA_CH1PRIS */
bogdanm 0:9b334a45a8ff 505 #define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL /**< Bit mask for DMA_CH1PRIS */
bogdanm 0:9b334a45a8ff 506 #define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
bogdanm 0:9b334a45a8ff 507 #define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIS */
bogdanm 0:9b334a45a8ff 508 #define DMA_CHPRIS_CH2PRIS (0x1UL << 2) /**< Channel 2 High Priority Set */
bogdanm 0:9b334a45a8ff 509 #define _DMA_CHPRIS_CH2PRIS_SHIFT 2 /**< Shift value for DMA_CH2PRIS */
bogdanm 0:9b334a45a8ff 510 #define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL /**< Bit mask for DMA_CH2PRIS */
bogdanm 0:9b334a45a8ff 511 #define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
bogdanm 0:9b334a45a8ff 512 #define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIS */
bogdanm 0:9b334a45a8ff 513 #define DMA_CHPRIS_CH3PRIS (0x1UL << 3) /**< Channel 3 High Priority Set */
bogdanm 0:9b334a45a8ff 514 #define _DMA_CHPRIS_CH3PRIS_SHIFT 3 /**< Shift value for DMA_CH3PRIS */
bogdanm 0:9b334a45a8ff 515 #define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL /**< Bit mask for DMA_CH3PRIS */
bogdanm 0:9b334a45a8ff 516 #define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
bogdanm 0:9b334a45a8ff 517 #define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIS */
bogdanm 0:9b334a45a8ff 518 #define DMA_CHPRIS_CH4PRIS (0x1UL << 4) /**< Channel 4 High Priority Set */
bogdanm 0:9b334a45a8ff 519 #define _DMA_CHPRIS_CH4PRIS_SHIFT 4 /**< Shift value for DMA_CH4PRIS */
bogdanm 0:9b334a45a8ff 520 #define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL /**< Bit mask for DMA_CH4PRIS */
bogdanm 0:9b334a45a8ff 521 #define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
bogdanm 0:9b334a45a8ff 522 #define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIS */
bogdanm 0:9b334a45a8ff 523 #define DMA_CHPRIS_CH5PRIS (0x1UL << 5) /**< Channel 5 High Priority Set */
bogdanm 0:9b334a45a8ff 524 #define _DMA_CHPRIS_CH5PRIS_SHIFT 5 /**< Shift value for DMA_CH5PRIS */
bogdanm 0:9b334a45a8ff 525 #define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL /**< Bit mask for DMA_CH5PRIS */
bogdanm 0:9b334a45a8ff 526 #define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
bogdanm 0:9b334a45a8ff 527 #define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIS */
bogdanm 0:9b334a45a8ff 528
bogdanm 0:9b334a45a8ff 529 /* Bit fields for DMA CHPRIC */
bogdanm 0:9b334a45a8ff 530 #define _DMA_CHPRIC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIC */
bogdanm 0:9b334a45a8ff 531 #define _DMA_CHPRIC_MASK 0x0000003FUL /**< Mask for DMA_CHPRIC */
bogdanm 0:9b334a45a8ff 532 #define DMA_CHPRIC_CH0PRIC (0x1UL << 0) /**< Channel 0 High Priority Clear */
bogdanm 0:9b334a45a8ff 533 #define _DMA_CHPRIC_CH0PRIC_SHIFT 0 /**< Shift value for DMA_CH0PRIC */
bogdanm 0:9b334a45a8ff 534 #define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL /**< Bit mask for DMA_CH0PRIC */
bogdanm 0:9b334a45a8ff 535 #define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
bogdanm 0:9b334a45a8ff 536 #define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIC */
bogdanm 0:9b334a45a8ff 537 #define DMA_CHPRIC_CH1PRIC (0x1UL << 1) /**< Channel 1 High Priority Clear */
bogdanm 0:9b334a45a8ff 538 #define _DMA_CHPRIC_CH1PRIC_SHIFT 1 /**< Shift value for DMA_CH1PRIC */
bogdanm 0:9b334a45a8ff 539 #define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL /**< Bit mask for DMA_CH1PRIC */
bogdanm 0:9b334a45a8ff 540 #define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
bogdanm 0:9b334a45a8ff 541 #define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIC */
bogdanm 0:9b334a45a8ff 542 #define DMA_CHPRIC_CH2PRIC (0x1UL << 2) /**< Channel 2 High Priority Clear */
bogdanm 0:9b334a45a8ff 543 #define _DMA_CHPRIC_CH2PRIC_SHIFT 2 /**< Shift value for DMA_CH2PRIC */
bogdanm 0:9b334a45a8ff 544 #define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL /**< Bit mask for DMA_CH2PRIC */
bogdanm 0:9b334a45a8ff 545 #define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
bogdanm 0:9b334a45a8ff 546 #define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIC */
bogdanm 0:9b334a45a8ff 547 #define DMA_CHPRIC_CH3PRIC (0x1UL << 3) /**< Channel 3 High Priority Clear */
bogdanm 0:9b334a45a8ff 548 #define _DMA_CHPRIC_CH3PRIC_SHIFT 3 /**< Shift value for DMA_CH3PRIC */
bogdanm 0:9b334a45a8ff 549 #define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL /**< Bit mask for DMA_CH3PRIC */
bogdanm 0:9b334a45a8ff 550 #define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
bogdanm 0:9b334a45a8ff 551 #define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIC */
bogdanm 0:9b334a45a8ff 552 #define DMA_CHPRIC_CH4PRIC (0x1UL << 4) /**< Channel 4 High Priority Clear */
bogdanm 0:9b334a45a8ff 553 #define _DMA_CHPRIC_CH4PRIC_SHIFT 4 /**< Shift value for DMA_CH4PRIC */
bogdanm 0:9b334a45a8ff 554 #define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL /**< Bit mask for DMA_CH4PRIC */
bogdanm 0:9b334a45a8ff 555 #define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
bogdanm 0:9b334a45a8ff 556 #define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIC */
bogdanm 0:9b334a45a8ff 557 #define DMA_CHPRIC_CH5PRIC (0x1UL << 5) /**< Channel 5 High Priority Clear */
bogdanm 0:9b334a45a8ff 558 #define _DMA_CHPRIC_CH5PRIC_SHIFT 5 /**< Shift value for DMA_CH5PRIC */
bogdanm 0:9b334a45a8ff 559 #define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL /**< Bit mask for DMA_CH5PRIC */
bogdanm 0:9b334a45a8ff 560 #define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
bogdanm 0:9b334a45a8ff 561 #define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIC */
bogdanm 0:9b334a45a8ff 562
bogdanm 0:9b334a45a8ff 563 /* Bit fields for DMA ERRORC */
bogdanm 0:9b334a45a8ff 564 #define _DMA_ERRORC_RESETVALUE 0x00000000UL /**< Default value for DMA_ERRORC */
bogdanm 0:9b334a45a8ff 565 #define _DMA_ERRORC_MASK 0x00000001UL /**< Mask for DMA_ERRORC */
bogdanm 0:9b334a45a8ff 566 #define DMA_ERRORC_ERRORC (0x1UL << 0) /**< Bus Error Clear */
bogdanm 0:9b334a45a8ff 567 #define _DMA_ERRORC_ERRORC_SHIFT 0 /**< Shift value for DMA_ERRORC */
bogdanm 0:9b334a45a8ff 568 #define _DMA_ERRORC_ERRORC_MASK 0x1UL /**< Bit mask for DMA_ERRORC */
bogdanm 0:9b334a45a8ff 569 #define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_ERRORC */
bogdanm 0:9b334a45a8ff 570 #define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ERRORC */
bogdanm 0:9b334a45a8ff 571
bogdanm 0:9b334a45a8ff 572 /* Bit fields for DMA CHREQSTATUS */
bogdanm 0:9b334a45a8ff 573 #define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQSTATUS */
bogdanm 0:9b334a45a8ff 574 #define _DMA_CHREQSTATUS_MASK 0x0000003FUL /**< Mask for DMA_CHREQSTATUS */
bogdanm 0:9b334a45a8ff 575 #define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0) /**< Channel 0 Request Status */
bogdanm 0:9b334a45a8ff 576 #define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0REQSTATUS */
bogdanm 0:9b334a45a8ff 577 #define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0REQSTATUS */
bogdanm 0:9b334a45a8ff 578 #define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
bogdanm 0:9b334a45a8ff 579 #define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
bogdanm 0:9b334a45a8ff 580 #define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1) /**< Channel 1 Request Status */
bogdanm 0:9b334a45a8ff 581 #define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1REQSTATUS */
bogdanm 0:9b334a45a8ff 582 #define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1REQSTATUS */
bogdanm 0:9b334a45a8ff 583 #define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
bogdanm 0:9b334a45a8ff 584 #define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
bogdanm 0:9b334a45a8ff 585 #define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2) /**< Channel 2 Request Status */
bogdanm 0:9b334a45a8ff 586 #define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2REQSTATUS */
bogdanm 0:9b334a45a8ff 587 #define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2REQSTATUS */
bogdanm 0:9b334a45a8ff 588 #define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
bogdanm 0:9b334a45a8ff 589 #define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
bogdanm 0:9b334a45a8ff 590 #define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3) /**< Channel 3 Request Status */
bogdanm 0:9b334a45a8ff 591 #define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3REQSTATUS */
bogdanm 0:9b334a45a8ff 592 #define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3REQSTATUS */
bogdanm 0:9b334a45a8ff 593 #define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
bogdanm 0:9b334a45a8ff 594 #define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
bogdanm 0:9b334a45a8ff 595 #define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4) /**< Channel 4 Request Status */
bogdanm 0:9b334a45a8ff 596 #define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4REQSTATUS */
bogdanm 0:9b334a45a8ff 597 #define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4REQSTATUS */
bogdanm 0:9b334a45a8ff 598 #define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
bogdanm 0:9b334a45a8ff 599 #define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
bogdanm 0:9b334a45a8ff 600 #define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5) /**< Channel 5 Request Status */
bogdanm 0:9b334a45a8ff 601 #define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5REQSTATUS */
bogdanm 0:9b334a45a8ff 602 #define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5REQSTATUS */
bogdanm 0:9b334a45a8ff 603 #define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
bogdanm 0:9b334a45a8ff 604 #define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
bogdanm 0:9b334a45a8ff 605
bogdanm 0:9b334a45a8ff 606 /* Bit fields for DMA CHSREQSTATUS */
bogdanm 0:9b334a45a8ff 607 #define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSREQSTATUS */
bogdanm 0:9b334a45a8ff 608 #define _DMA_CHSREQSTATUS_MASK 0x0000003FUL /**< Mask for DMA_CHSREQSTATUS */
bogdanm 0:9b334a45a8ff 609 #define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0) /**< Channel 0 Single Request Status */
bogdanm 0:9b334a45a8ff 610 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0SREQSTATUS */
bogdanm 0:9b334a45a8ff 611 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0SREQSTATUS */
bogdanm 0:9b334a45a8ff 612 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
bogdanm 0:9b334a45a8ff 613 #define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
bogdanm 0:9b334a45a8ff 614 #define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1) /**< Channel 1 Single Request Status */
bogdanm 0:9b334a45a8ff 615 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1SREQSTATUS */
bogdanm 0:9b334a45a8ff 616 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1SREQSTATUS */
bogdanm 0:9b334a45a8ff 617 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
bogdanm 0:9b334a45a8ff 618 #define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
bogdanm 0:9b334a45a8ff 619 #define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2) /**< Channel 2 Single Request Status */
bogdanm 0:9b334a45a8ff 620 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2SREQSTATUS */
bogdanm 0:9b334a45a8ff 621 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2SREQSTATUS */
bogdanm 0:9b334a45a8ff 622 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
bogdanm 0:9b334a45a8ff 623 #define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
bogdanm 0:9b334a45a8ff 624 #define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3) /**< Channel 3 Single Request Status */
bogdanm 0:9b334a45a8ff 625 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3SREQSTATUS */
bogdanm 0:9b334a45a8ff 626 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3SREQSTATUS */
bogdanm 0:9b334a45a8ff 627 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
bogdanm 0:9b334a45a8ff 628 #define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
bogdanm 0:9b334a45a8ff 629 #define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4) /**< Channel 4 Single Request Status */
bogdanm 0:9b334a45a8ff 630 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4SREQSTATUS */
bogdanm 0:9b334a45a8ff 631 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4SREQSTATUS */
bogdanm 0:9b334a45a8ff 632 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
bogdanm 0:9b334a45a8ff 633 #define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
bogdanm 0:9b334a45a8ff 634 #define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5) /**< Channel 5 Single Request Status */
bogdanm 0:9b334a45a8ff 635 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5SREQSTATUS */
bogdanm 0:9b334a45a8ff 636 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5SREQSTATUS */
bogdanm 0:9b334a45a8ff 637 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
bogdanm 0:9b334a45a8ff 638 #define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
bogdanm 0:9b334a45a8ff 639
bogdanm 0:9b334a45a8ff 640 /* Bit fields for DMA IF */
bogdanm 0:9b334a45a8ff 641 #define _DMA_IF_RESETVALUE 0x00000000UL /**< Default value for DMA_IF */
bogdanm 0:9b334a45a8ff 642 #define _DMA_IF_MASK 0x8000003FUL /**< Mask for DMA_IF */
bogdanm 0:9b334a45a8ff 643 #define DMA_IF_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag */
bogdanm 0:9b334a45a8ff 644 #define _DMA_IF_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
bogdanm 0:9b334a45a8ff 645 #define _DMA_IF_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
bogdanm 0:9b334a45a8ff 646 #define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
bogdanm 0:9b334a45a8ff 647 #define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IF */
bogdanm 0:9b334a45a8ff 648 #define DMA_IF_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag */
bogdanm 0:9b334a45a8ff 649 #define _DMA_IF_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
bogdanm 0:9b334a45a8ff 650 #define _DMA_IF_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
bogdanm 0:9b334a45a8ff 651 #define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
bogdanm 0:9b334a45a8ff 652 #define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IF */
bogdanm 0:9b334a45a8ff 653 #define DMA_IF_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag */
bogdanm 0:9b334a45a8ff 654 #define _DMA_IF_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
bogdanm 0:9b334a45a8ff 655 #define _DMA_IF_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
bogdanm 0:9b334a45a8ff 656 #define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
bogdanm 0:9b334a45a8ff 657 #define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IF */
bogdanm 0:9b334a45a8ff 658 #define DMA_IF_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag */
bogdanm 0:9b334a45a8ff 659 #define _DMA_IF_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
bogdanm 0:9b334a45a8ff 660 #define _DMA_IF_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
bogdanm 0:9b334a45a8ff 661 #define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
bogdanm 0:9b334a45a8ff 662 #define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IF */
bogdanm 0:9b334a45a8ff 663 #define DMA_IF_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag */
bogdanm 0:9b334a45a8ff 664 #define _DMA_IF_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
bogdanm 0:9b334a45a8ff 665 #define _DMA_IF_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
bogdanm 0:9b334a45a8ff 666 #define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
bogdanm 0:9b334a45a8ff 667 #define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IF */
bogdanm 0:9b334a45a8ff 668 #define DMA_IF_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag */
bogdanm 0:9b334a45a8ff 669 #define _DMA_IF_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
bogdanm 0:9b334a45a8ff 670 #define _DMA_IF_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
bogdanm 0:9b334a45a8ff 671 #define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
bogdanm 0:9b334a45a8ff 672 #define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IF */
bogdanm 0:9b334a45a8ff 673 #define DMA_IF_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag */
bogdanm 0:9b334a45a8ff 674 #define _DMA_IF_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
bogdanm 0:9b334a45a8ff 675 #define _DMA_IF_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
bogdanm 0:9b334a45a8ff 676 #define _DMA_IF_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
bogdanm 0:9b334a45a8ff 677 #define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IF */
bogdanm 0:9b334a45a8ff 678
bogdanm 0:9b334a45a8ff 679 /* Bit fields for DMA IFS */
bogdanm 0:9b334a45a8ff 680 #define _DMA_IFS_RESETVALUE 0x00000000UL /**< Default value for DMA_IFS */
bogdanm 0:9b334a45a8ff 681 #define _DMA_IFS_MASK 0x8000003FUL /**< Mask for DMA_IFS */
bogdanm 0:9b334a45a8ff 682 #define DMA_IFS_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Set */
bogdanm 0:9b334a45a8ff 683 #define _DMA_IFS_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
bogdanm 0:9b334a45a8ff 684 #define _DMA_IFS_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
bogdanm 0:9b334a45a8ff 685 #define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
bogdanm 0:9b334a45a8ff 686 #define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFS */
bogdanm 0:9b334a45a8ff 687 #define DMA_IFS_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Set */
bogdanm 0:9b334a45a8ff 688 #define _DMA_IFS_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
bogdanm 0:9b334a45a8ff 689 #define _DMA_IFS_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
bogdanm 0:9b334a45a8ff 690 #define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
bogdanm 0:9b334a45a8ff 691 #define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFS */
bogdanm 0:9b334a45a8ff 692 #define DMA_IFS_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Set */
bogdanm 0:9b334a45a8ff 693 #define _DMA_IFS_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
bogdanm 0:9b334a45a8ff 694 #define _DMA_IFS_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
bogdanm 0:9b334a45a8ff 695 #define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
bogdanm 0:9b334a45a8ff 696 #define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFS */
bogdanm 0:9b334a45a8ff 697 #define DMA_IFS_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Set */
bogdanm 0:9b334a45a8ff 698 #define _DMA_IFS_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
bogdanm 0:9b334a45a8ff 699 #define _DMA_IFS_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
bogdanm 0:9b334a45a8ff 700 #define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
bogdanm 0:9b334a45a8ff 701 #define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFS */
bogdanm 0:9b334a45a8ff 702 #define DMA_IFS_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Set */
bogdanm 0:9b334a45a8ff 703 #define _DMA_IFS_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
bogdanm 0:9b334a45a8ff 704 #define _DMA_IFS_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
bogdanm 0:9b334a45a8ff 705 #define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
bogdanm 0:9b334a45a8ff 706 #define DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFS */
bogdanm 0:9b334a45a8ff 707 #define DMA_IFS_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Set */
bogdanm 0:9b334a45a8ff 708 #define _DMA_IFS_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
bogdanm 0:9b334a45a8ff 709 #define _DMA_IFS_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
bogdanm 0:9b334a45a8ff 710 #define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
bogdanm 0:9b334a45a8ff 711 #define DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFS */
bogdanm 0:9b334a45a8ff 712 #define DMA_IFS_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Set */
bogdanm 0:9b334a45a8ff 713 #define _DMA_IFS_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
bogdanm 0:9b334a45a8ff 714 #define _DMA_IFS_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
bogdanm 0:9b334a45a8ff 715 #define _DMA_IFS_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
bogdanm 0:9b334a45a8ff 716 #define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFS */
bogdanm 0:9b334a45a8ff 717
bogdanm 0:9b334a45a8ff 718 /* Bit fields for DMA IFC */
bogdanm 0:9b334a45a8ff 719 #define _DMA_IFC_RESETVALUE 0x00000000UL /**< Default value for DMA_IFC */
bogdanm 0:9b334a45a8ff 720 #define _DMA_IFC_MASK 0x8000003FUL /**< Mask for DMA_IFC */
bogdanm 0:9b334a45a8ff 721 #define DMA_IFC_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Clear */
bogdanm 0:9b334a45a8ff 722 #define _DMA_IFC_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
bogdanm 0:9b334a45a8ff 723 #define _DMA_IFC_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
bogdanm 0:9b334a45a8ff 724 #define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
bogdanm 0:9b334a45a8ff 725 #define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFC */
bogdanm 0:9b334a45a8ff 726 #define DMA_IFC_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Clear */
bogdanm 0:9b334a45a8ff 727 #define _DMA_IFC_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
bogdanm 0:9b334a45a8ff 728 #define _DMA_IFC_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
bogdanm 0:9b334a45a8ff 729 #define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
bogdanm 0:9b334a45a8ff 730 #define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFC */
bogdanm 0:9b334a45a8ff 731 #define DMA_IFC_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Clear */
bogdanm 0:9b334a45a8ff 732 #define _DMA_IFC_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
bogdanm 0:9b334a45a8ff 733 #define _DMA_IFC_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
bogdanm 0:9b334a45a8ff 734 #define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
bogdanm 0:9b334a45a8ff 735 #define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFC */
bogdanm 0:9b334a45a8ff 736 #define DMA_IFC_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Clear */
bogdanm 0:9b334a45a8ff 737 #define _DMA_IFC_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
bogdanm 0:9b334a45a8ff 738 #define _DMA_IFC_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
bogdanm 0:9b334a45a8ff 739 #define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
bogdanm 0:9b334a45a8ff 740 #define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFC */
bogdanm 0:9b334a45a8ff 741 #define DMA_IFC_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Clear */
bogdanm 0:9b334a45a8ff 742 #define _DMA_IFC_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
bogdanm 0:9b334a45a8ff 743 #define _DMA_IFC_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
bogdanm 0:9b334a45a8ff 744 #define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
bogdanm 0:9b334a45a8ff 745 #define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFC */
bogdanm 0:9b334a45a8ff 746 #define DMA_IFC_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Clear */
bogdanm 0:9b334a45a8ff 747 #define _DMA_IFC_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
bogdanm 0:9b334a45a8ff 748 #define _DMA_IFC_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
bogdanm 0:9b334a45a8ff 749 #define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
bogdanm 0:9b334a45a8ff 750 #define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFC */
bogdanm 0:9b334a45a8ff 751 #define DMA_IFC_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Clear */
bogdanm 0:9b334a45a8ff 752 #define _DMA_IFC_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
bogdanm 0:9b334a45a8ff 753 #define _DMA_IFC_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
bogdanm 0:9b334a45a8ff 754 #define _DMA_IFC_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
bogdanm 0:9b334a45a8ff 755 #define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFC */
bogdanm 0:9b334a45a8ff 756
bogdanm 0:9b334a45a8ff 757 /* Bit fields for DMA IEN */
bogdanm 0:9b334a45a8ff 758 #define _DMA_IEN_RESETVALUE 0x00000000UL /**< Default value for DMA_IEN */
bogdanm 0:9b334a45a8ff 759 #define _DMA_IEN_MASK 0x8000003FUL /**< Mask for DMA_IEN */
bogdanm 0:9b334a45a8ff 760 #define DMA_IEN_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Enable */
bogdanm 0:9b334a45a8ff 761 #define _DMA_IEN_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
bogdanm 0:9b334a45a8ff 762 #define _DMA_IEN_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
bogdanm 0:9b334a45a8ff 763 #define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
bogdanm 0:9b334a45a8ff 764 #define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IEN */
bogdanm 0:9b334a45a8ff 765 #define DMA_IEN_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Enable */
bogdanm 0:9b334a45a8ff 766 #define _DMA_IEN_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
bogdanm 0:9b334a45a8ff 767 #define _DMA_IEN_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
bogdanm 0:9b334a45a8ff 768 #define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
bogdanm 0:9b334a45a8ff 769 #define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IEN */
bogdanm 0:9b334a45a8ff 770 #define DMA_IEN_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Enable */
bogdanm 0:9b334a45a8ff 771 #define _DMA_IEN_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
bogdanm 0:9b334a45a8ff 772 #define _DMA_IEN_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
bogdanm 0:9b334a45a8ff 773 #define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
bogdanm 0:9b334a45a8ff 774 #define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IEN */
bogdanm 0:9b334a45a8ff 775 #define DMA_IEN_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Enable */
bogdanm 0:9b334a45a8ff 776 #define _DMA_IEN_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
bogdanm 0:9b334a45a8ff 777 #define _DMA_IEN_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
bogdanm 0:9b334a45a8ff 778 #define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
bogdanm 0:9b334a45a8ff 779 #define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IEN */
bogdanm 0:9b334a45a8ff 780 #define DMA_IEN_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Enable */
bogdanm 0:9b334a45a8ff 781 #define _DMA_IEN_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
bogdanm 0:9b334a45a8ff 782 #define _DMA_IEN_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
bogdanm 0:9b334a45a8ff 783 #define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
bogdanm 0:9b334a45a8ff 784 #define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IEN */
bogdanm 0:9b334a45a8ff 785 #define DMA_IEN_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Enable */
bogdanm 0:9b334a45a8ff 786 #define _DMA_IEN_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
bogdanm 0:9b334a45a8ff 787 #define _DMA_IEN_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
bogdanm 0:9b334a45a8ff 788 #define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
bogdanm 0:9b334a45a8ff 789 #define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IEN */
bogdanm 0:9b334a45a8ff 790 #define DMA_IEN_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Enable */
bogdanm 0:9b334a45a8ff 791 #define _DMA_IEN_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
bogdanm 0:9b334a45a8ff 792 #define _DMA_IEN_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
bogdanm 0:9b334a45a8ff 793 #define _DMA_IEN_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
bogdanm 0:9b334a45a8ff 794 #define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IEN */
bogdanm 0:9b334a45a8ff 795
bogdanm 0:9b334a45a8ff 796 /* Bit fields for DMA CH_CTRL */
bogdanm 0:9b334a45a8ff 797 #define _DMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 798 #define _DMA_CH_CTRL_MASK 0x003F000FUL /**< Mask for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 799 #define _DMA_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for DMA_SIGSEL */
bogdanm 0:9b334a45a8ff 800 #define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL /**< Bit mask for DMA_SIGSEL */
bogdanm 0:9b334a45a8ff 801 #define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 802 #define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 803 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 804 #define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 805 #define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 806 #define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 807 #define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 808 #define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 809 #define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 810 #define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL /**< Mode AESDATAWR for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 811 #define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 812 #define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 813 #define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 814 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 815 #define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 816 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 817 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 818 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 819 #define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL /**< Mode AESXORDATAWR for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 820 #define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 821 #define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 822 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 823 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 824 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 825 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 826 #define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL /**< Mode AESDATARD for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 827 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 828 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 829 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 830 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 831 #define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL /**< Mode AESKEYWR for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 832 #define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 833 #define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 834 #define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 835 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 836 #define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 837 #define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 838 #define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 839 #define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 840 #define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0) /**< Shifted mode TIMER2UFOF for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 841 #define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 842 #define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0) /**< Shifted mode AESDATAWR for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 843 #define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 844 #define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 845 #define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 846 #define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 847 #define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 848 #define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 849 #define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 850 #define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 851 #define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0) /**< Shifted mode AESXORDATAWR for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 852 #define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 853 #define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 854 #define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 855 #define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 856 #define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 857 #define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 858 #define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0) /**< Shifted mode AESDATARD for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 859 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 860 #define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 861 #define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 862 #define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 863 #define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0) /**< Shifted mode AESKEYWR for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 864 #define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 865 #define _DMA_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for DMA_SOURCESEL */
bogdanm 0:9b334a45a8ff 866 #define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for DMA_SOURCESEL */
bogdanm 0:9b334a45a8ff 867 #define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 868 #define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 869 #define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 870 #define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 871 #define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 872 #define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 873 #define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 874 #define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 875 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL /**< Mode TIMER2 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 876 #define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 877 #define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL /**< Mode AES for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 878 #define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 879 #define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 880 #define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 881 #define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 882 #define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 883 #define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 884 #define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 885 #define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 886 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 887 #define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 888 #define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16) /**< Shifted mode AES for DMA_CH_CTRL */
bogdanm 0:9b334a45a8ff 889
bogdanm 0:9b334a45a8ff 890 /** @} End of group EFM32HG_DMA */
mbed_official 50:a417edff4437 891 /** @} End of group Parts */
bogdanm 0:9b334a45a8ff 892